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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <cam@cs.ualberta.ca> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
0d1c9782 | 19 | #include "qemu/osdep.h" |
da34e65c | 20 | #include "qapi/error.h" |
f348b6d1 | 21 | #include "qemu/cutils.h" |
83c9f4ca | 22 | #include "hw/hw.h" |
83c9f4ca | 23 | #include "hw/pci/pci.h" |
660c97ee | 24 | #include "hw/pci/msi.h" |
83c9f4ca | 25 | #include "hw/pci/msix.h" |
9c17d615 | 26 | #include "sysemu/kvm.h" |
795c40b8 | 27 | #include "migration/blocker.h" |
d49b6836 | 28 | #include "qemu/error-report.h" |
1de7afc9 | 29 | #include "qemu/event_notifier.h" |
5503e285 | 30 | #include "qom/object_interfaces.h" |
4d43a603 | 31 | #include "chardev/char-fe.h" |
d9453c93 | 32 | #include "sysemu/hostmem.h" |
5400c02b | 33 | #include "sysemu/qtest.h" |
d9453c93 | 34 | #include "qapi/visitor.h" |
6cbf4c8c | 35 | |
5105b1d8 DM |
36 | #include "hw/misc/ivshmem.h" |
37 | ||
b8ef62a9 PB |
38 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
39 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
40 | ||
cd9953f7 | 41 | #define IVSHMEM_MAX_PEERS UINT16_MAX |
6cbf4c8c CM |
42 | #define IVSHMEM_IOEVENTFD 0 |
43 | #define IVSHMEM_MSI 1 | |
44 | ||
6cbf4c8c CM |
45 | #define IVSHMEM_REG_BAR_SIZE 0x100 |
46 | ||
a4fa93bf MA |
47 | #define IVSHMEM_DEBUG 0 |
48 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
49 | do { \ | |
50 | if (IVSHMEM_DEBUG) { \ | |
51 | printf("IVSHMEM: " fmt, ## __VA_ARGS__); \ | |
52 | } \ | |
53 | } while (0) | |
6cbf4c8c | 54 | |
5400c02b MA |
55 | #define TYPE_IVSHMEM_COMMON "ivshmem-common" |
56 | #define IVSHMEM_COMMON(obj) \ | |
57 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_COMMON) | |
58 | ||
59 | #define TYPE_IVSHMEM_PLAIN "ivshmem-plain" | |
60 | #define IVSHMEM_PLAIN(obj) \ | |
61 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_PLAIN) | |
62 | ||
63 | #define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell" | |
64 | #define IVSHMEM_DOORBELL(obj) \ | |
65 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_DOORBELL) | |
66 | ||
eb3fedf3 PC |
67 | #define TYPE_IVSHMEM "ivshmem" |
68 | #define IVSHMEM(obj) \ | |
69 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM) | |
70 | ||
6cbf4c8c CM |
71 | typedef struct Peer { |
72 | int nb_eventfds; | |
563027cc | 73 | EventNotifier *eventfds; |
6cbf4c8c CM |
74 | } Peer; |
75 | ||
0f57350e | 76 | typedef struct MSIVector { |
6cbf4c8c | 77 | PCIDevice *pdev; |
660c97ee | 78 | int virq; |
0f57350e | 79 | } MSIVector; |
6cbf4c8c CM |
80 | |
81 | typedef struct IVShmemState { | |
b7578eaa AF |
82 | /*< private >*/ |
83 | PCIDevice parent_obj; | |
84 | /*< public >*/ | |
85 | ||
ddc85284 MA |
86 | uint32_t features; |
87 | ||
88 | /* exactly one of these two may be set */ | |
89 | HostMemoryBackend *hostmem; /* with interrupts */ | |
becdfa00 | 90 | CharBackend server_chr; /* without interrupts */ |
ddc85284 MA |
91 | |
92 | /* registers */ | |
6cbf4c8c CM |
93 | uint32_t intrmask; |
94 | uint32_t intrstatus; | |
ddc85284 | 95 | int vm_id; |
6cbf4c8c | 96 | |
ddc85284 MA |
97 | /* BARs */ |
98 | MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */ | |
c2d8019c MA |
99 | MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */ |
100 | MemoryRegion server_bar2; /* used with server_chr */ | |
6cbf4c8c | 101 | |
ddc85284 | 102 | /* interrupt support */ |
6cbf4c8c | 103 | Peer *peers; |
cd9953f7 | 104 | int nb_peers; /* space in @peers[] */ |
6cbf4c8c | 105 | uint32_t vectors; |
0f57350e | 106 | MSIVector *msi_vectors; |
ee276391 MA |
107 | uint64_t msg_buf; /* buffer for receiving server messages */ |
108 | int msg_buffered_bytes; /* #bytes in @msg_buf */ | |
6cbf4c8c | 109 | |
ddc85284 | 110 | /* migration stuff */ |
2a845da7 | 111 | OnOffAuto master; |
38e0735e AL |
112 | Error *migration_blocker; |
113 | ||
5400c02b MA |
114 | /* legacy cruft */ |
115 | char *role; | |
116 | char *shmobj; | |
117 | char *sizearg; | |
118 | size_t legacy_size; | |
119 | uint32_t not_legacy_32bit; | |
6cbf4c8c CM |
120 | } IVShmemState; |
121 | ||
122 | /* registers for the Inter-VM shared memory device */ | |
123 | enum ivshmem_registers { | |
124 | INTRMASK = 0, | |
125 | INTRSTATUS = 4, | |
126 | IVPOSITION = 8, | |
127 | DOORBELL = 12, | |
128 | }; | |
129 | ||
130 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
131 | unsigned int feature) { | |
132 | return (ivs->features & (1 << feature)); | |
133 | } | |
134 | ||
2a845da7 MA |
135 | static inline bool ivshmem_is_master(IVShmemState *s) |
136 | { | |
137 | assert(s->master != ON_OFF_AUTO_AUTO); | |
138 | return s->master == ON_OFF_AUTO_ON; | |
139 | } | |
140 | ||
d8a5da07 | 141 | static void ivshmem_update_irq(IVShmemState *s) |
6cbf4c8c | 142 | { |
b7578eaa | 143 | PCIDevice *d = PCI_DEVICE(s); |
434ad76d | 144 | uint32_t isr = s->intrstatus & s->intrmask; |
6cbf4c8c | 145 | |
5400c02b MA |
146 | /* |
147 | * Do nothing unless the device actually uses INTx. Here's how | |
148 | * the device variants signal interrupts, what they put in PCI | |
149 | * config space: | |
150 | * Device variant Interrupt Interrupt Pin MSI-X cap. | |
151 | * ivshmem-plain none 0 no | |
152 | * ivshmem-doorbell MSI-X 1 yes(1) | |
153 | * ivshmem,msi=off INTx 1 no | |
154 | * ivshmem,msi=on MSI-X 1(2) yes(1) | |
155 | * (1) if guest enabled MSI-X | |
156 | * (2) the device lies | |
157 | * Leads to the condition for doing nothing: | |
158 | */ | |
159 | if (ivshmem_has_feature(s, IVSHMEM_MSI) | |
160 | || !d->config[PCI_INTERRUPT_PIN]) { | |
2d1d422d MA |
161 | return; |
162 | } | |
163 | ||
6cbf4c8c CM |
164 | /* don't print ISR resets */ |
165 | if (isr) { | |
166 | IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", | |
dbc464d4 | 167 | isr ? 1 : 0, s->intrstatus, s->intrmask); |
6cbf4c8c CM |
168 | } |
169 | ||
434ad76d | 170 | pci_set_irq(d, isr != 0); |
6cbf4c8c CM |
171 | } |
172 | ||
173 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) | |
174 | { | |
175 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
176 | ||
177 | s->intrmask = val; | |
d8a5da07 | 178 | ivshmem_update_irq(s); |
6cbf4c8c CM |
179 | } |
180 | ||
181 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
182 | { | |
183 | uint32_t ret = s->intrmask; | |
184 | ||
185 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
6cbf4c8c CM |
186 | return ret; |
187 | } | |
188 | ||
189 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
190 | { | |
191 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
192 | ||
193 | s->intrstatus = val; | |
d8a5da07 | 194 | ivshmem_update_irq(s); |
6cbf4c8c CM |
195 | } |
196 | ||
197 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
198 | { | |
199 | uint32_t ret = s->intrstatus; | |
200 | ||
201 | /* reading ISR clears all interrupts */ | |
202 | s->intrstatus = 0; | |
d8a5da07 | 203 | ivshmem_update_irq(s); |
6cbf4c8c CM |
204 | return ret; |
205 | } | |
206 | ||
a8170e5e | 207 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 208 | uint64_t val, unsigned size) |
6cbf4c8c CM |
209 | { |
210 | IVShmemState *s = opaque; | |
211 | ||
6cbf4c8c CM |
212 | uint16_t dest = val >> 16; |
213 | uint16_t vector = val & 0xff; | |
214 | ||
215 | addr &= 0xfc; | |
216 | ||
217 | IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); | |
218 | switch (addr) | |
219 | { | |
220 | case INTRMASK: | |
221 | ivshmem_IntrMask_write(s, val); | |
222 | break; | |
223 | ||
224 | case INTRSTATUS: | |
225 | ivshmem_IntrStatus_write(s, val); | |
226 | break; | |
227 | ||
228 | case DOORBELL: | |
229 | /* check that dest VM ID is reasonable */ | |
95c8425c | 230 | if (dest >= s->nb_peers) { |
6cbf4c8c CM |
231 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
232 | break; | |
233 | } | |
234 | ||
235 | /* check doorbell range */ | |
1b27d7a1 | 236 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
237 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
238 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
f59bb378 MAL |
239 | } else { |
240 | IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n", | |
241 | vector, dest); | |
6cbf4c8c CM |
242 | } |
243 | break; | |
244 | default: | |
f59bb378 | 245 | IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); |
6cbf4c8c CM |
246 | } |
247 | } | |
248 | ||
a8170e5e | 249 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 250 | unsigned size) |
6cbf4c8c CM |
251 | { |
252 | ||
253 | IVShmemState *s = opaque; | |
254 | uint32_t ret; | |
255 | ||
256 | switch (addr) | |
257 | { | |
258 | case INTRMASK: | |
259 | ret = ivshmem_IntrMask_read(s); | |
260 | break; | |
261 | ||
262 | case INTRSTATUS: | |
263 | ret = ivshmem_IntrStatus_read(s); | |
264 | break; | |
265 | ||
266 | case IVPOSITION: | |
1309cf44 | 267 | ret = s->vm_id; |
6cbf4c8c CM |
268 | break; |
269 | ||
270 | default: | |
271 | IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); | |
272 | ret = 0; | |
273 | } | |
274 | ||
275 | return ret; | |
276 | } | |
277 | ||
cb06608e AK |
278 | static const MemoryRegionOps ivshmem_mmio_ops = { |
279 | .read = ivshmem_io_read, | |
280 | .write = ivshmem_io_write, | |
281 | .endianness = DEVICE_NATIVE_ENDIAN, | |
282 | .impl = { | |
283 | .min_access_size = 4, | |
284 | .max_access_size = 4, | |
285 | }, | |
6cbf4c8c CM |
286 | }; |
287 | ||
9940c323 MAL |
288 | static void ivshmem_vector_notify(void *opaque) |
289 | { | |
0f57350e | 290 | MSIVector *entry = opaque; |
6cbf4c8c | 291 | PCIDevice *pdev = entry->pdev; |
5400c02b | 292 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
0f57350e | 293 | int vector = entry - s->msi_vectors; |
9940c323 MAL |
294 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
295 | ||
296 | if (!event_notifier_test_and_clear(n)) { | |
297 | return; | |
298 | } | |
6cbf4c8c | 299 | |
d160f3f7 | 300 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector); |
9940c323 | 301 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
082751e8 MA |
302 | if (msix_enabled(pdev)) { |
303 | msix_notify(pdev, vector); | |
304 | } | |
9940c323 MAL |
305 | } else { |
306 | ivshmem_IntrStatus_write(s, 1); | |
307 | } | |
6cbf4c8c CM |
308 | } |
309 | ||
660c97ee MAL |
310 | static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector, |
311 | MSIMessage msg) | |
312 | { | |
5400c02b | 313 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
314 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
315 | MSIVector *v = &s->msi_vectors[vector]; | |
316 | int ret; | |
317 | ||
318 | IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector); | |
319 | ||
320 | ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev); | |
321 | if (ret < 0) { | |
322 | return ret; | |
323 | } | |
3f1fea0f | 324 | kvm_irqchip_commit_routes(kvm_state); |
660c97ee MAL |
325 | |
326 | return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq); | |
327 | } | |
328 | ||
329 | static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector) | |
330 | { | |
5400c02b | 331 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
332 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
333 | int ret; | |
334 | ||
335 | IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector); | |
336 | ||
337 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, | |
338 | s->msi_vectors[vector].virq); | |
339 | if (ret != 0) { | |
340 | error_report("remove_irqfd_notifier_gsi failed"); | |
341 | } | |
342 | } | |
343 | ||
344 | static void ivshmem_vector_poll(PCIDevice *dev, | |
345 | unsigned int vector_start, | |
346 | unsigned int vector_end) | |
347 | { | |
5400c02b | 348 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
349 | unsigned int vector; |
350 | ||
351 | IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end); | |
352 | ||
353 | vector_end = MIN(vector_end, s->vectors); | |
354 | ||
355 | for (vector = vector_start; vector < vector_end; vector++) { | |
356 | EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector]; | |
357 | ||
358 | if (!msix_is_masked(dev, vector)) { | |
359 | continue; | |
360 | } | |
361 | ||
362 | if (event_notifier_test_and_clear(notifier)) { | |
363 | msix_set_pending(dev, vector); | |
364 | } | |
365 | } | |
366 | } | |
367 | ||
9940c323 MAL |
368 | static void watch_vector_notifier(IVShmemState *s, EventNotifier *n, |
369 | int vector) | |
6cbf4c8c | 370 | { |
563027cc | 371 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c | 372 | |
3c27969b | 373 | assert(!s->msi_vectors[vector].pdev); |
9940c323 | 374 | s->msi_vectors[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c | 375 | |
9940c323 MAL |
376 | qemu_set_fd_handler(eventfd, ivshmem_vector_notify, |
377 | NULL, &s->msi_vectors[vector]); | |
6cbf4c8c CM |
378 | } |
379 | ||
563027cc PB |
380 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
381 | { | |
382 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
383 | DOORBELL, | |
384 | 4, | |
385 | true, | |
386 | (posn << 16) | i, | |
753d5e14 | 387 | &s->peers[posn].eventfds[i]); |
563027cc PB |
388 | } |
389 | ||
390 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
391 | { | |
392 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
393 | DOORBELL, | |
394 | 4, | |
395 | true, | |
396 | (posn << 16) | i, | |
753d5e14 | 397 | &s->peers[posn].eventfds[i]); |
563027cc PB |
398 | } |
399 | ||
f456179f | 400 | static void close_peer_eventfds(IVShmemState *s, int posn) |
6cbf4c8c | 401 | { |
f456179f | 402 | int i, n; |
6cbf4c8c | 403 | |
9db51b4d | 404 | assert(posn >= 0 && posn < s->nb_peers); |
f456179f | 405 | n = s->peers[posn].nb_eventfds; |
6cbf4c8c | 406 | |
9db51b4d MA |
407 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
408 | memory_region_transaction_begin(); | |
409 | for (i = 0; i < n; i++) { | |
410 | ivshmem_del_eventfd(s, posn, i); | |
411 | } | |
412 | memory_region_transaction_commit(); | |
b6a1f3a5 | 413 | } |
9db51b4d | 414 | |
f456179f | 415 | for (i = 0; i < n; i++) { |
563027cc | 416 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
417 | } |
418 | ||
7267c094 | 419 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
420 | s->peers[posn].nb_eventfds = 0; |
421 | } | |
422 | ||
cd9953f7 | 423 | static void resize_peers(IVShmemState *s, int nb_peers) |
34bc07c5 | 424 | { |
cd9953f7 MA |
425 | int old_nb_peers = s->nb_peers; |
426 | int i; | |
6cbf4c8c | 427 | |
cd9953f7 MA |
428 | assert(nb_peers > old_nb_peers); |
429 | IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers); | |
6cbf4c8c | 430 | |
cd9953f7 MA |
431 | s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer)); |
432 | s->nb_peers = nb_peers; | |
1300b273 | 433 | |
cd9953f7 MA |
434 | for (i = old_nb_peers; i < nb_peers; i++) { |
435 | s->peers[i].eventfds = g_new0(EventNotifier, s->vectors); | |
436 | s->peers[i].nb_eventfds = 0; | |
6cbf4c8c CM |
437 | } |
438 | } | |
439 | ||
1309cf44 MA |
440 | static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector, |
441 | Error **errp) | |
660c97ee MAL |
442 | { |
443 | PCIDevice *pdev = PCI_DEVICE(s); | |
660c97ee MAL |
444 | int ret; |
445 | ||
446 | IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); | |
3c27969b | 447 | assert(!s->msi_vectors[vector].pdev); |
660c97ee | 448 | |
d1f6af6a | 449 | ret = kvm_irqchip_add_msi_route(kvm_state, vector, pdev); |
660c97ee | 450 | if (ret < 0) { |
1309cf44 MA |
451 | error_setg(errp, "kvm_irqchip_add_msi_route failed"); |
452 | return; | |
660c97ee MAL |
453 | } |
454 | ||
455 | s->msi_vectors[vector].virq = ret; | |
456 | s->msi_vectors[vector].pdev = pdev; | |
660c97ee MAL |
457 | } |
458 | ||
1309cf44 | 459 | static void setup_interrupt(IVShmemState *s, int vector, Error **errp) |
660c97ee MAL |
460 | { |
461 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
462 | bool with_irqfd = kvm_msi_via_irqfd_enabled() && | |
463 | ivshmem_has_feature(s, IVSHMEM_MSI); | |
464 | PCIDevice *pdev = PCI_DEVICE(s); | |
1309cf44 | 465 | Error *err = NULL; |
660c97ee MAL |
466 | |
467 | IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector); | |
468 | ||
469 | if (!with_irqfd) { | |
97553976 | 470 | IVSHMEM_DPRINTF("with eventfd\n"); |
9940c323 | 471 | watch_vector_notifier(s, n, vector); |
660c97ee | 472 | } else if (msix_enabled(pdev)) { |
97553976 | 473 | IVSHMEM_DPRINTF("with irqfd\n"); |
1309cf44 MA |
474 | ivshmem_add_kvm_msi_virq(s, vector, &err); |
475 | if (err) { | |
476 | error_propagate(errp, err); | |
660c97ee MAL |
477 | return; |
478 | } | |
479 | ||
480 | if (!msix_is_masked(pdev, vector)) { | |
481 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, | |
482 | s->msi_vectors[vector].virq); | |
1309cf44 | 483 | /* TODO handle error */ |
660c97ee MAL |
484 | } |
485 | } else { | |
486 | /* it will be delayed until msix is enabled, in write_config */ | |
97553976 | 487 | IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n"); |
660c97ee MAL |
488 | } |
489 | } | |
490 | ||
1309cf44 | 491 | static void process_msg_shmem(IVShmemState *s, int fd, Error **errp) |
6cbf4c8c | 492 | { |
8381d89b | 493 | Error *local_err = NULL; |
8baeb22b | 494 | struct stat buf; |
5400c02b | 495 | size_t size; |
6cbf4c8c | 496 | |
c2d8019c | 497 | if (s->ivshmem_bar2) { |
1309cf44 | 498 | error_setg(errp, "server sent unexpected shared memory message"); |
ca0b7566 | 499 | close(fd); |
0f14fd71 | 500 | return; |
a2e9011b SH |
501 | } |
502 | ||
8baeb22b MA |
503 | if (fstat(fd, &buf) < 0) { |
504 | error_setg_errno(errp, errno, | |
505 | "can't determine size of shared memory sent by server"); | |
506 | close(fd); | |
507 | return; | |
508 | } | |
509 | ||
5400c02b MA |
510 | size = buf.st_size; |
511 | ||
512 | /* Legacy cruft */ | |
513 | if (s->legacy_size != SIZE_MAX) { | |
514 | if (size < s->legacy_size) { | |
515 | error_setg(errp, "server sent only %zd bytes of shared memory", | |
516 | (size_t)buf.st_size); | |
517 | close(fd); | |
518 | return; | |
519 | } | |
520 | size = s->legacy_size; | |
cd9953f7 MA |
521 | } |
522 | ||
ca0b7566 | 523 | /* mmap the region and map into the BAR2 */ |
8381d89b MAL |
524 | memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s), |
525 | "ivshmem.bar2", size, true, fd, &local_err); | |
526 | if (local_err) { | |
527 | error_propagate(errp, local_err); | |
ca0b7566 | 528 | return; |
6cbf4c8c | 529 | } |
8381d89b | 530 | |
c2d8019c | 531 | s->ivshmem_bar2 = &s->server_bar2; |
ca0b7566 MA |
532 | } |
533 | ||
1309cf44 MA |
534 | static void process_msg_disconnect(IVShmemState *s, uint16_t posn, |
535 | Error **errp) | |
ca0b7566 MA |
536 | { |
537 | IVSHMEM_DPRINTF("posn %d has gone away\n", posn); | |
9db51b4d | 538 | if (posn >= s->nb_peers || posn == s->vm_id) { |
1309cf44 | 539 | error_setg(errp, "invalid peer %d", posn); |
9db51b4d MA |
540 | return; |
541 | } | |
ca0b7566 MA |
542 | close_peer_eventfds(s, posn); |
543 | } | |
6cbf4c8c | 544 | |
1309cf44 MA |
545 | static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd, |
546 | Error **errp) | |
ca0b7566 MA |
547 | { |
548 | Peer *peer = &s->peers[posn]; | |
549 | int vector; | |
9a2f0e64 | 550 | |
ca0b7566 MA |
551 | /* |
552 | * The N-th connect message for this peer comes with the file | |
553 | * descriptor for vector N-1. Count messages to find the vector. | |
554 | */ | |
555 | if (peer->nb_eventfds >= s->vectors) { | |
1309cf44 MA |
556 | error_setg(errp, "Too many eventfd received, device has %d vectors", |
557 | s->vectors); | |
ca0b7566 | 558 | close(fd); |
6f8a16d5 | 559 | return; |
6cbf4c8c | 560 | } |
ca0b7566 | 561 | vector = peer->nb_eventfds++; |
6cbf4c8c | 562 | |
ca0b7566 MA |
563 | IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd); |
564 | event_notifier_init_fd(&peer->eventfds[vector], fd); | |
565 | fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */ | |
945001a1 | 566 | |
ca0b7566 | 567 | if (posn == s->vm_id) { |
1309cf44 MA |
568 | setup_interrupt(s, vector, errp); |
569 | /* TODO do we need to handle the error? */ | |
ca0b7566 | 570 | } |
6cbf4c8c | 571 | |
ca0b7566 MA |
572 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
573 | ivshmem_add_eventfd(s, posn, vector); | |
574 | } | |
575 | } | |
6cbf4c8c | 576 | |
1309cf44 | 577 | static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp) |
ca0b7566 MA |
578 | { |
579 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
6cbf4c8c | 580 | |
ca0b7566 | 581 | if (msg < -1 || msg > IVSHMEM_MAX_PEERS) { |
1309cf44 | 582 | error_setg(errp, "server sent invalid message %" PRId64, msg); |
ca0b7566 | 583 | close(fd); |
6cbf4c8c CM |
584 | return; |
585 | } | |
586 | ||
ca0b7566 | 587 | if (msg == -1) { |
1309cf44 | 588 | process_msg_shmem(s, fd, errp); |
1ee57de4 MAL |
589 | return; |
590 | } | |
591 | ||
ca0b7566 MA |
592 | if (msg >= s->nb_peers) { |
593 | resize_peers(s, msg + 1); | |
594 | } | |
6cbf4c8c | 595 | |
ca0b7566 | 596 | if (fd >= 0) { |
1309cf44 | 597 | process_msg_connect(s, msg, fd, errp); |
ca0b7566 | 598 | } else { |
1309cf44 | 599 | process_msg_disconnect(s, msg, errp); |
6cbf4c8c | 600 | } |
ca0b7566 | 601 | } |
6cbf4c8c | 602 | |
ee276391 MA |
603 | static int ivshmem_can_receive(void *opaque) |
604 | { | |
605 | IVShmemState *s = opaque; | |
606 | ||
607 | assert(s->msg_buffered_bytes < sizeof(s->msg_buf)); | |
608 | return sizeof(s->msg_buf) - s->msg_buffered_bytes; | |
609 | } | |
610 | ||
ca0b7566 MA |
611 | static void ivshmem_read(void *opaque, const uint8_t *buf, int size) |
612 | { | |
613 | IVShmemState *s = opaque; | |
1309cf44 | 614 | Error *err = NULL; |
ca0b7566 MA |
615 | int fd; |
616 | int64_t msg; | |
617 | ||
ee276391 MA |
618 | assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf)); |
619 | memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size); | |
620 | s->msg_buffered_bytes += size; | |
621 | if (s->msg_buffered_bytes < sizeof(s->msg_buf)) { | |
ca0b7566 | 622 | return; |
6cbf4c8c | 623 | } |
ee276391 MA |
624 | msg = le64_to_cpu(s->msg_buf); |
625 | s->msg_buffered_bytes = 0; | |
ca0b7566 | 626 | |
5345fdb4 | 627 | fd = qemu_chr_fe_get_msgfd(&s->server_chr); |
ca0b7566 | 628 | |
1309cf44 MA |
629 | process_msg(s, msg, fd, &err); |
630 | if (err) { | |
631 | error_report_err(err); | |
632 | } | |
6cbf4c8c CM |
633 | } |
634 | ||
1309cf44 | 635 | static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp) |
5105b1d8 | 636 | { |
3a55fc0f MA |
637 | int64_t msg; |
638 | int n, ret; | |
639 | ||
640 | n = 0; | |
641 | do { | |
5345fdb4 MAL |
642 | ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n, |
643 | sizeof(msg) - n); | |
b7b1e9dd PMD |
644 | if (ret < 0) { |
645 | if (ret == -EINTR) { | |
646 | continue; | |
647 | } | |
1309cf44 | 648 | error_setg_errno(errp, -ret, "read from server failed"); |
3a55fc0f MA |
649 | return INT64_MIN; |
650 | } | |
651 | n += ret; | |
652 | } while (n < sizeof(msg)); | |
5105b1d8 | 653 | |
5345fdb4 | 654 | *pfd = qemu_chr_fe_get_msgfd(&s->server_chr); |
51af0ec9 | 655 | return le64_to_cpu(msg); |
3a55fc0f | 656 | } |
5105b1d8 | 657 | |
1309cf44 | 658 | static void ivshmem_recv_setup(IVShmemState *s, Error **errp) |
3a55fc0f | 659 | { |
1309cf44 | 660 | Error *err = NULL; |
3a55fc0f MA |
661 | int64_t msg; |
662 | int fd; | |
663 | ||
1309cf44 MA |
664 | msg = ivshmem_recv_msg(s, &fd, &err); |
665 | if (err) { | |
666 | error_propagate(errp, err); | |
667 | return; | |
668 | } | |
669 | if (msg != IVSHMEM_PROTOCOL_VERSION) { | |
670 | error_setg(errp, "server sent version %" PRId64 ", expecting %d", | |
671 | msg, IVSHMEM_PROTOCOL_VERSION); | |
672 | return; | |
673 | } | |
674 | if (fd != -1) { | |
675 | error_setg(errp, "server sent invalid version message"); | |
5105b1d8 DM |
676 | return; |
677 | } | |
678 | ||
a3feb086 MA |
679 | /* |
680 | * ivshmem-server sends the remaining initial messages in a fixed | |
681 | * order, but the device has always accepted them in any order. | |
682 | * Stay as compatible as practical, just in case people use | |
683 | * servers that behave differently. | |
684 | */ | |
685 | ||
686 | /* | |
687 | * ivshmem_device_spec.txt has always required the ID message | |
688 | * right here, and ivshmem-server has always complied. However, | |
689 | * older versions of the device accepted it out of order, but | |
690 | * broke when an interrupt setup message arrived before it. | |
691 | */ | |
692 | msg = ivshmem_recv_msg(s, &fd, &err); | |
693 | if (err) { | |
694 | error_propagate(errp, err); | |
695 | return; | |
696 | } | |
697 | if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) { | |
698 | error_setg(errp, "server sent invalid ID message"); | |
699 | return; | |
700 | } | |
701 | s->vm_id = msg; | |
702 | ||
3a55fc0f MA |
703 | /* |
704 | * Receive more messages until we got shared memory. | |
705 | */ | |
706 | do { | |
1309cf44 MA |
707 | msg = ivshmem_recv_msg(s, &fd, &err); |
708 | if (err) { | |
709 | error_propagate(errp, err); | |
710 | return; | |
711 | } | |
712 | process_msg(s, msg, fd, &err); | |
713 | if (err) { | |
714 | error_propagate(errp, err); | |
715 | return; | |
716 | } | |
3a55fc0f | 717 | } while (msg != -1); |
1309cf44 MA |
718 | |
719 | /* | |
720 | * This function must either map the shared memory or fail. The | |
721 | * loop above ensures that: it terminates normally only after it | |
722 | * successfully processed the server's shared memory message. | |
723 | * Assert that actually mapped the shared memory: | |
724 | */ | |
c2d8019c | 725 | assert(s->ivshmem_bar2); |
5105b1d8 DM |
726 | } |
727 | ||
4490c711 MT |
728 | /* Select the MSI-X vectors used by device. |
729 | * ivshmem maps events to vectors statically, so | |
730 | * we just enable all vectors on init and after reset. */ | |
082751e8 | 731 | static void ivshmem_msix_vector_use(IVShmemState *s) |
4490c711 | 732 | { |
b7578eaa | 733 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
734 | int i; |
735 | ||
4490c711 | 736 | for (i = 0; i < s->vectors; i++) { |
b7578eaa | 737 | msix_vector_use(d, i); |
4490c711 MT |
738 | } |
739 | } | |
740 | ||
6cbf4c8c CM |
741 | static void ivshmem_reset(DeviceState *d) |
742 | { | |
5400c02b | 743 | IVShmemState *s = IVSHMEM_COMMON(d); |
6cbf4c8c CM |
744 | |
745 | s->intrstatus = 0; | |
972ad215 | 746 | s->intrmask = 0; |
082751e8 MA |
747 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
748 | ivshmem_msix_vector_use(s); | |
749 | } | |
6cbf4c8c CM |
750 | } |
751 | ||
ee640c62 | 752 | static int ivshmem_setup_interrupts(IVShmemState *s, Error **errp) |
4490c711 | 753 | { |
fd47bfe5 MAL |
754 | /* allocate QEMU callback data for receiving interrupts */ |
755 | s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector)); | |
6cbf4c8c | 756 | |
fd47bfe5 | 757 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
ee640c62 | 758 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1, errp)) { |
fd47bfe5 MAL |
759 | return -1; |
760 | } | |
1116b539 | 761 | |
fd47bfe5 | 762 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
082751e8 | 763 | ivshmem_msix_vector_use(s); |
fd47bfe5 | 764 | } |
4490c711 | 765 | |
d58d7e84 | 766 | return 0; |
6cbf4c8c CM |
767 | } |
768 | ||
660c97ee MAL |
769 | static void ivshmem_enable_irqfd(IVShmemState *s) |
770 | { | |
771 | PCIDevice *pdev = PCI_DEVICE(s); | |
772 | int i; | |
773 | ||
774 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
1309cf44 MA |
775 | Error *err = NULL; |
776 | ||
777 | ivshmem_add_kvm_msi_virq(s, i, &err); | |
778 | if (err) { | |
779 | error_report_err(err); | |
780 | /* TODO do we need to handle the error? */ | |
781 | } | |
660c97ee MAL |
782 | } |
783 | ||
784 | if (msix_set_vector_notifiers(pdev, | |
785 | ivshmem_vector_unmask, | |
786 | ivshmem_vector_mask, | |
787 | ivshmem_vector_poll)) { | |
788 | error_report("ivshmem: msix_set_vector_notifiers failed"); | |
789 | } | |
790 | } | |
791 | ||
792 | static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector) | |
793 | { | |
794 | IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector); | |
795 | ||
796 | if (s->msi_vectors[vector].pdev == NULL) { | |
797 | return; | |
798 | } | |
799 | ||
800 | /* it was cleaned when masked in the frontend. */ | |
801 | kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq); | |
802 | ||
803 | s->msi_vectors[vector].pdev = NULL; | |
804 | } | |
805 | ||
806 | static void ivshmem_disable_irqfd(IVShmemState *s) | |
807 | { | |
808 | PCIDevice *pdev = PCI_DEVICE(s); | |
809 | int i; | |
810 | ||
811 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
812 | ivshmem_remove_kvm_msi_virq(s, i); | |
813 | } | |
814 | ||
815 | msix_unset_vector_notifiers(pdev); | |
816 | } | |
817 | ||
818 | static void ivshmem_write_config(PCIDevice *pdev, uint32_t address, | |
d58d7e84 | 819 | uint32_t val, int len) |
4490c711 | 820 | { |
5400c02b | 821 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
660c97ee MAL |
822 | int is_enabled, was_enabled = msix_enabled(pdev); |
823 | ||
824 | pci_default_write_config(pdev, address, val, len); | |
825 | is_enabled = msix_enabled(pdev); | |
826 | ||
1309cf44 | 827 | if (kvm_msi_via_irqfd_enabled()) { |
660c97ee MAL |
828 | if (!was_enabled && is_enabled) { |
829 | ivshmem_enable_irqfd(s); | |
830 | } else if (was_enabled && !is_enabled) { | |
831 | ivshmem_disable_irqfd(s); | |
832 | } | |
833 | } | |
4490c711 MT |
834 | } |
835 | ||
5400c02b | 836 | static void ivshmem_common_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 837 | { |
5400c02b | 838 | IVShmemState *s = IVSHMEM_COMMON(dev); |
d855e275 | 839 | Error *err = NULL; |
6cbf4c8c | 840 | uint8_t *pci_conf; |
9113e3f3 MAL |
841 | uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY | |
842 | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
fe44dc91 | 843 | Error *local_err = NULL; |
6cbf4c8c | 844 | |
6cbf4c8c CM |
845 | /* IRQFD requires MSI */ |
846 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
847 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
d58d7e84 MAL |
848 | error_setg(errp, "ioeventfd/irqfd requires MSI"); |
849 | return; | |
6cbf4c8c CM |
850 | } |
851 | ||
b7578eaa | 852 | pci_conf = dev->config; |
6cbf4c8c | 853 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c | 854 | |
3c161542 | 855 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
856 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
857 | ||
6cbf4c8c | 858 | /* region for registers*/ |
b7578eaa | 859 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 860 | &s->ivshmem_mmio); |
cb06608e | 861 | |
b2b79a69 | 862 | if (s->not_legacy_32bit) { |
9113e3f3 | 863 | attr |= PCI_BASE_ADDRESS_MEM_TYPE_64; |
c08ba66f | 864 | } |
6cbf4c8c | 865 | |
d9453c93 | 866 | if (s->hostmem != NULL) { |
d9453c93 MAL |
867 | IVSHMEM_DPRINTF("using hostmem\n"); |
868 | ||
c2d8019c MA |
869 | s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem, |
870 | &error_abort); | |
5503e285 | 871 | } else { |
0ec7b3e7 | 872 | Chardev *chr = qemu_chr_fe_get_driver(&s->server_chr); |
5345fdb4 | 873 | assert(chr); |
6dc64780 | 874 | |
6cbf4c8c | 875 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", |
5345fdb4 | 876 | chr->filename); |
6cbf4c8c | 877 | |
f456179f | 878 | /* we allocate enough space for 16 peers and grow as needed */ |
1300b273 | 879 | resize_peers(s, 16); |
6cbf4c8c | 880 | |
3a55fc0f MA |
881 | /* |
882 | * Receive setup messages from server synchronously. | |
883 | * Older versions did it asynchronously, but that creates a | |
884 | * number of entertaining race conditions. | |
3a55fc0f | 885 | */ |
1309cf44 MA |
886 | ivshmem_recv_setup(s, &err); |
887 | if (err) { | |
888 | error_propagate(errp, err); | |
889 | return; | |
3a55fc0f MA |
890 | } |
891 | ||
62a830b6 MA |
892 | if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) { |
893 | error_setg(errp, | |
894 | "master must connect to the server before any peers"); | |
895 | return; | |
896 | } | |
897 | ||
5345fdb4 | 898 | qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive, |
81517ba3 | 899 | ivshmem_read, NULL, NULL, s, NULL, true); |
1309cf44 | 900 | |
ee640c62 C |
901 | if (ivshmem_setup_interrupts(s, errp) < 0) { |
902 | error_prepend(errp, "Failed to initialize interrupts: "); | |
3a55fc0f MA |
903 | return; |
904 | } | |
d855e275 MA |
905 | } |
906 | ||
2a845da7 MA |
907 | if (s->master == ON_OFF_AUTO_AUTO) { |
908 | s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | |
909 | } | |
910 | ||
911 | if (!ivshmem_is_master(s)) { | |
d855e275 MA |
912 | error_setg(&s->migration_blocker, |
913 | "Migration is disabled when using feature 'peer mode' in device 'ivshmem'"); | |
fe44dc91 AA |
914 | migrate_add_blocker(s->migration_blocker, &local_err); |
915 | if (local_err) { | |
916 | error_propagate(errp, local_err); | |
917 | error_free(s->migration_blocker); | |
918 | return; | |
919 | } | |
6cbf4c8c | 920 | } |
fe44dc91 AA |
921 | |
922 | vmstate_register_ram(s->ivshmem_bar2, DEVICE(s)); | |
923 | pci_register_bar(PCI_DEVICE(s), 2, attr, s->ivshmem_bar2); | |
6cbf4c8c CM |
924 | } |
925 | ||
5400c02b MA |
926 | static void ivshmem_exit(PCIDevice *dev) |
927 | { | |
928 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
f64a078d MAL |
929 | int i; |
930 | ||
38e0735e AL |
931 | if (s->migration_blocker) { |
932 | migrate_del_blocker(s->migration_blocker); | |
933 | error_free(s->migration_blocker); | |
934 | } | |
935 | ||
c2d8019c | 936 | if (memory_region_is_mapped(s->ivshmem_bar2)) { |
d9453c93 | 937 | if (!s->hostmem) { |
c2d8019c | 938 | void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2); |
56a571d9 | 939 | int fd; |
d9453c93 | 940 | |
5400c02b | 941 | if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) { |
d9453c93 MAL |
942 | error_report("Failed to munmap shared memory %s", |
943 | strerror(errno)); | |
944 | } | |
56a571d9 | 945 | |
4ff87573 | 946 | fd = memory_region_get_fd(s->ivshmem_bar2); |
c2d8019c | 947 | close(fd); |
d9453c93 | 948 | } |
f64a078d | 949 | |
c2d8019c | 950 | vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev)); |
f64a078d MAL |
951 | } |
952 | ||
f64a078d MAL |
953 | if (s->peers) { |
954 | for (i = 0; i < s->nb_peers; i++) { | |
f456179f | 955 | close_peer_eventfds(s, i); |
f64a078d MAL |
956 | } |
957 | g_free(s->peers); | |
958 | } | |
959 | ||
960 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
961 | msix_uninit_exclusive_bar(dev); | |
962 | } | |
963 | ||
0f57350e | 964 | g_free(s->msi_vectors); |
6cbf4c8c CM |
965 | } |
966 | ||
1f8552df MAL |
967 | static int ivshmem_pre_load(void *opaque) |
968 | { | |
969 | IVShmemState *s = opaque; | |
970 | ||
2a845da7 | 971 | if (!ivshmem_is_master(s)) { |
1f8552df MAL |
972 | error_report("'peer' devices are not migratable"); |
973 | return -EINVAL; | |
974 | } | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
979 | static int ivshmem_post_load(void *opaque, int version_id) | |
980 | { | |
981 | IVShmemState *s = opaque; | |
982 | ||
983 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
082751e8 | 984 | ivshmem_msix_vector_use(s); |
1f8552df | 985 | } |
1f8552df MAL |
986 | return 0; |
987 | } | |
988 | ||
5400c02b | 989 | static void ivshmem_common_class_init(ObjectClass *klass, void *data) |
40021f08 | 990 | { |
39bffca2 | 991 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
992 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
993 | ||
5400c02b MA |
994 | k->realize = ivshmem_common_realize; |
995 | k->exit = ivshmem_exit; | |
d58d7e84 | 996 | k->config_write = ivshmem_write_config; |
b8ef62a9 PB |
997 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
998 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 999 | k->class_id = PCI_CLASS_MEMORY_RAM; |
5400c02b | 1000 | k->revision = 1; |
39bffca2 | 1001 | dc->reset = ivshmem_reset; |
125ee0ed | 1002 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
d383537d | 1003 | dc->desc = "Inter-VM shared memory"; |
40021f08 AL |
1004 | } |
1005 | ||
ddc85284 MA |
1006 | static const TypeInfo ivshmem_common_info = { |
1007 | .name = TYPE_IVSHMEM_COMMON, | |
1008 | .parent = TYPE_PCI_DEVICE, | |
1009 | .instance_size = sizeof(IVShmemState), | |
1010 | .abstract = true, | |
1011 | .class_init = ivshmem_common_class_init, | |
fd3b02c8 EH |
1012 | .interfaces = (InterfaceInfo[]) { |
1013 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1014 | { }, | |
1015 | }, | |
ddc85284 | 1016 | }; |
5400c02b | 1017 | |
5400c02b MA |
1018 | static const VMStateDescription ivshmem_plain_vmsd = { |
1019 | .name = TYPE_IVSHMEM_PLAIN, | |
1020 | .version_id = 0, | |
1021 | .minimum_version_id = 0, | |
1022 | .pre_load = ivshmem_pre_load, | |
1023 | .post_load = ivshmem_post_load, | |
1024 | .fields = (VMStateField[]) { | |
1025 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1026 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1027 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1028 | VMSTATE_END_OF_LIST() | |
1029 | }, | |
1030 | }; | |
1031 | ||
1032 | static Property ivshmem_plain_properties[] = { | |
1033 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
e9cb190a FZ |
1034 | DEFINE_PROP_LINK("memdev", IVShmemState, hostmem, TYPE_MEMORY_BACKEND, |
1035 | HostMemoryBackend *), | |
5400c02b MA |
1036 | DEFINE_PROP_END_OF_LIST(), |
1037 | }; | |
1038 | ||
1039 | static void ivshmem_plain_init(Object *obj) | |
1040 | { | |
1041 | IVShmemState *s = IVSHMEM_PLAIN(obj); | |
1042 | ||
b2b79a69 | 1043 | s->not_legacy_32bit = 1; |
5400c02b MA |
1044 | } |
1045 | ||
6dc64780 MAL |
1046 | static void ivshmem_plain_realize(PCIDevice *dev, Error **errp) |
1047 | { | |
1048 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1049 | ||
1050 | if (!s->hostmem) { | |
1051 | error_setg(errp, "You must specify a 'memdev'"); | |
1052 | return; | |
e9cb190a FZ |
1053 | } else if (host_memory_backend_is_mapped(s->hostmem)) { |
1054 | char *path = object_get_canonical_path_component(OBJECT(s->hostmem)); | |
1055 | error_setg(errp, "can't use already busy memdev: %s", path); | |
1056 | g_free(path); | |
1057 | return; | |
6dc64780 MAL |
1058 | } |
1059 | ||
1060 | ivshmem_common_realize(dev, errp); | |
2aece63c XG |
1061 | host_memory_backend_set_mapped(s->hostmem, true); |
1062 | } | |
1063 | ||
1064 | static void ivshmem_plain_exit(PCIDevice *pci_dev) | |
1065 | { | |
1066 | IVShmemState *s = IVSHMEM_COMMON(pci_dev); | |
1067 | ||
1068 | host_memory_backend_set_mapped(s->hostmem, false); | |
6dc64780 MAL |
1069 | } |
1070 | ||
5400c02b MA |
1071 | static void ivshmem_plain_class_init(ObjectClass *klass, void *data) |
1072 | { | |
1073 | DeviceClass *dc = DEVICE_CLASS(klass); | |
6dc64780 | 1074 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
5400c02b | 1075 | |
6dc64780 | 1076 | k->realize = ivshmem_plain_realize; |
2aece63c | 1077 | k->exit = ivshmem_plain_exit; |
5400c02b MA |
1078 | dc->props = ivshmem_plain_properties; |
1079 | dc->vmsd = &ivshmem_plain_vmsd; | |
1080 | } | |
1081 | ||
1082 | static const TypeInfo ivshmem_plain_info = { | |
1083 | .name = TYPE_IVSHMEM_PLAIN, | |
1084 | .parent = TYPE_IVSHMEM_COMMON, | |
1085 | .instance_size = sizeof(IVShmemState), | |
1086 | .instance_init = ivshmem_plain_init, | |
1087 | .class_init = ivshmem_plain_class_init, | |
1088 | }; | |
1089 | ||
1090 | static const VMStateDescription ivshmem_doorbell_vmsd = { | |
1091 | .name = TYPE_IVSHMEM_DOORBELL, | |
1092 | .version_id = 0, | |
1093 | .minimum_version_id = 0, | |
1094 | .pre_load = ivshmem_pre_load, | |
1095 | .post_load = ivshmem_post_load, | |
1096 | .fields = (VMStateField[]) { | |
1097 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1098 | VMSTATE_MSIX(parent_obj, IVShmemState), | |
1099 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1100 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1101 | VMSTATE_END_OF_LIST() | |
1102 | }, | |
1103 | }; | |
1104 | ||
1105 | static Property ivshmem_doorbell_properties[] = { | |
1106 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1107 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1108 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, | |
1109 | true), | |
1110 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
1111 | DEFINE_PROP_END_OF_LIST(), | |
1112 | }; | |
1113 | ||
1114 | static void ivshmem_doorbell_init(Object *obj) | |
1115 | { | |
1116 | IVShmemState *s = IVSHMEM_DOORBELL(obj); | |
1117 | ||
1118 | s->features |= (1 << IVSHMEM_MSI); | |
1119 | s->legacy_size = SIZE_MAX; /* whatever the server sends */ | |
b2b79a69 | 1120 | s->not_legacy_32bit = 1; |
5400c02b MA |
1121 | } |
1122 | ||
6dc64780 MAL |
1123 | static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp) |
1124 | { | |
1125 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1126 | ||
30650701 | 1127 | if (!qemu_chr_fe_backend_connected(&s->server_chr)) { |
6dc64780 MAL |
1128 | error_setg(errp, "You must specify a 'chardev'"); |
1129 | return; | |
1130 | } | |
1131 | ||
1132 | ivshmem_common_realize(dev, errp); | |
1133 | } | |
1134 | ||
5400c02b MA |
1135 | static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data) |
1136 | { | |
1137 | DeviceClass *dc = DEVICE_CLASS(klass); | |
6dc64780 | 1138 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
5400c02b | 1139 | |
6dc64780 | 1140 | k->realize = ivshmem_doorbell_realize; |
5400c02b MA |
1141 | dc->props = ivshmem_doorbell_properties; |
1142 | dc->vmsd = &ivshmem_doorbell_vmsd; | |
1143 | } | |
1144 | ||
1145 | static const TypeInfo ivshmem_doorbell_info = { | |
1146 | .name = TYPE_IVSHMEM_DOORBELL, | |
1147 | .parent = TYPE_IVSHMEM_COMMON, | |
1148 | .instance_size = sizeof(IVShmemState), | |
1149 | .instance_init = ivshmem_doorbell_init, | |
1150 | .class_init = ivshmem_doorbell_class_init, | |
1151 | }; | |
1152 | ||
ddc85284 MA |
1153 | static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id) |
1154 | { | |
1155 | IVShmemState *s = opaque; | |
1156 | PCIDevice *pdev = PCI_DEVICE(s); | |
1157 | int ret; | |
1158 | ||
1159 | IVSHMEM_DPRINTF("ivshmem_load_old\n"); | |
1160 | ||
1161 | if (version_id != 0) { | |
1162 | return -EINVAL; | |
1163 | } | |
1164 | ||
1165 | ret = ivshmem_pre_load(s); | |
1166 | if (ret) { | |
1167 | return ret; | |
1168 | } | |
1169 | ||
1170 | ret = pci_device_load(pdev, f); | |
1171 | if (ret) { | |
1172 | return ret; | |
1173 | } | |
1174 | ||
1175 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
1176 | msix_load(pdev, f); | |
1177 | ivshmem_msix_vector_use(s); | |
1178 | } else { | |
1179 | s->intrstatus = qemu_get_be32(f); | |
1180 | s->intrmask = qemu_get_be32(f); | |
1181 | } | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | static bool test_msix(void *opaque, int version_id) | |
1187 | { | |
1188 | IVShmemState *s = opaque; | |
1189 | ||
1190 | return ivshmem_has_feature(s, IVSHMEM_MSI); | |
1191 | } | |
1192 | ||
1193 | static bool test_no_msix(void *opaque, int version_id) | |
1194 | { | |
1195 | return !test_msix(opaque, version_id); | |
1196 | } | |
1197 | ||
1198 | static const VMStateDescription ivshmem_vmsd = { | |
1199 | .name = "ivshmem", | |
1200 | .version_id = 1, | |
1201 | .minimum_version_id = 1, | |
1202 | .pre_load = ivshmem_pre_load, | |
1203 | .post_load = ivshmem_post_load, | |
1204 | .fields = (VMStateField[]) { | |
1205 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1206 | ||
1207 | VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix), | |
1208 | VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix), | |
1209 | VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix), | |
1210 | ||
1211 | VMSTATE_END_OF_LIST() | |
1212 | }, | |
1213 | .load_state_old = ivshmem_load_old, | |
1214 | .minimum_version_id_old = 0 | |
1215 | }; | |
1216 | ||
1217 | static Property ivshmem_properties[] = { | |
1218 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1219 | DEFINE_PROP_STRING("size", IVShmemState, sizearg), | |
1220 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1221 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, | |
1222 | false), | |
1223 | DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true), | |
1224 | DEFINE_PROP_STRING("shm", IVShmemState, shmobj), | |
1225 | DEFINE_PROP_STRING("role", IVShmemState, role), | |
1226 | DEFINE_PROP_UINT32("use64", IVShmemState, not_legacy_32bit, 1), | |
1227 | DEFINE_PROP_END_OF_LIST(), | |
1228 | }; | |
1229 | ||
1230 | static void desugar_shm(IVShmemState *s) | |
1231 | { | |
1232 | Object *obj; | |
1233 | char *path; | |
1234 | ||
1235 | obj = object_new("memory-backend-file"); | |
1236 | path = g_strdup_printf("/dev/shm/%s", s->shmobj); | |
1237 | object_property_set_str(obj, path, "mem-path", &error_abort); | |
1238 | g_free(path); | |
1239 | object_property_set_int(obj, s->legacy_size, "size", &error_abort); | |
1240 | object_property_set_bool(obj, true, "share", &error_abort); | |
1241 | object_property_add_child(OBJECT(s), "internal-shm-backend", obj, | |
1242 | &error_abort); | |
1243 | user_creatable_complete(obj, &error_abort); | |
1244 | s->hostmem = MEMORY_BACKEND(obj); | |
1245 | } | |
1246 | ||
1247 | static void ivshmem_realize(PCIDevice *dev, Error **errp) | |
1248 | { | |
1249 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1250 | ||
1251 | if (!qtest_enabled()) { | |
1252 | error_report("ivshmem is deprecated, please use ivshmem-plain" | |
1253 | " or ivshmem-doorbell instead"); | |
1254 | } | |
1255 | ||
30650701 | 1256 | if (qemu_chr_fe_backend_connected(&s->server_chr) + !!s->shmobj != 1) { |
13fd2cb6 | 1257 | error_setg(errp, "You must specify either 'shm' or 'chardev'"); |
ddc85284 MA |
1258 | return; |
1259 | } | |
1260 | ||
13fd2cb6 | 1261 | if (s->sizearg == NULL) { |
ddc85284 MA |
1262 | s->legacy_size = 4 << 20; /* 4 MB default */ |
1263 | } else { | |
f17fd4fd | 1264 | int ret; |
f46bfdbf | 1265 | uint64_t size; |
f17fd4fd MA |
1266 | |
1267 | ret = qemu_strtosz_MiB(s->sizearg, NULL, &size); | |
1268 | if (ret < 0 || (size_t)size != size || !is_power_of_2(size)) { | |
ddc85284 MA |
1269 | error_setg(errp, "Invalid size %s", s->sizearg); |
1270 | return; | |
1271 | } | |
1272 | s->legacy_size = size; | |
1273 | } | |
1274 | ||
1275 | /* check that role is reasonable */ | |
1276 | if (s->role) { | |
1277 | if (strncmp(s->role, "peer", 5) == 0) { | |
1278 | s->master = ON_OFF_AUTO_OFF; | |
1279 | } else if (strncmp(s->role, "master", 7) == 0) { | |
1280 | s->master = ON_OFF_AUTO_ON; | |
1281 | } else { | |
1282 | error_setg(errp, "'role' must be 'peer' or 'master'"); | |
1283 | return; | |
1284 | } | |
1285 | } else { | |
1286 | s->master = ON_OFF_AUTO_AUTO; | |
1287 | } | |
1288 | ||
1289 | if (s->shmobj) { | |
1290 | desugar_shm(s); | |
1291 | } | |
1292 | ||
1293 | /* | |
1294 | * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a | |
1295 | * bald-faced lie then. But it's a backwards compatible lie. | |
1296 | */ | |
1297 | pci_config_set_interrupt_pin(dev->config, 1); | |
1298 | ||
1299 | ivshmem_common_realize(dev, errp); | |
1300 | } | |
1301 | ||
ddc85284 MA |
1302 | static void ivshmem_class_init(ObjectClass *klass, void *data) |
1303 | { | |
1304 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1305 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1306 | ||
1307 | k->realize = ivshmem_realize; | |
1308 | k->revision = 0; | |
1309 | dc->desc = "Inter-VM shared memory (legacy)"; | |
1310 | dc->props = ivshmem_properties; | |
1311 | dc->vmsd = &ivshmem_vmsd; | |
1312 | } | |
1313 | ||
1314 | static const TypeInfo ivshmem_info = { | |
1315 | .name = TYPE_IVSHMEM, | |
1316 | .parent = TYPE_IVSHMEM_COMMON, | |
1317 | .instance_size = sizeof(IVShmemState), | |
ddc85284 MA |
1318 | .class_init = ivshmem_class_init, |
1319 | }; | |
1320 | ||
83f7d43a | 1321 | static void ivshmem_register_types(void) |
6cbf4c8c | 1322 | { |
5400c02b MA |
1323 | type_register_static(&ivshmem_common_info); |
1324 | type_register_static(&ivshmem_plain_info); | |
1325 | type_register_static(&ivshmem_doorbell_info); | |
39bffca2 | 1326 | type_register_static(&ivshmem_info); |
6cbf4c8c CM |
1327 | } |
1328 | ||
83f7d43a | 1329 | type_init(ivshmem_register_types) |