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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <cam@cs.ualberta.ca> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
0d1c9782 | 19 | #include "qemu/osdep.h" |
83c9f4ca | 20 | #include "hw/hw.h" |
0d09e41a | 21 | #include "hw/i386/pc.h" |
83c9f4ca | 22 | #include "hw/pci/pci.h" |
660c97ee | 23 | #include "hw/pci/msi.h" |
83c9f4ca | 24 | #include "hw/pci/msix.h" |
9c17d615 | 25 | #include "sysemu/kvm.h" |
caf71f86 | 26 | #include "migration/migration.h" |
d49b6836 | 27 | #include "qemu/error-report.h" |
1de7afc9 | 28 | #include "qemu/event_notifier.h" |
5503e285 | 29 | #include "qom/object_interfaces.h" |
dccfcd0e | 30 | #include "sysemu/char.h" |
d9453c93 MAL |
31 | #include "sysemu/hostmem.h" |
32 | #include "qapi/visitor.h" | |
56a571d9 | 33 | #include "exec/ram_addr.h" |
6cbf4c8c | 34 | |
5105b1d8 DM |
35 | #include "hw/misc/ivshmem.h" |
36 | ||
6cbf4c8c | 37 | #include <sys/mman.h> |
6cbf4c8c | 38 | |
b8ef62a9 PB |
39 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
40 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
41 | ||
cd9953f7 | 42 | #define IVSHMEM_MAX_PEERS UINT16_MAX |
6cbf4c8c CM |
43 | #define IVSHMEM_IOEVENTFD 0 |
44 | #define IVSHMEM_MSI 1 | |
45 | ||
46 | #define IVSHMEM_PEER 0 | |
47 | #define IVSHMEM_MASTER 1 | |
48 | ||
49 | #define IVSHMEM_REG_BAR_SIZE 0x100 | |
50 | ||
a4fa93bf MA |
51 | #define IVSHMEM_DEBUG 0 |
52 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
53 | do { \ | |
54 | if (IVSHMEM_DEBUG) { \ | |
55 | printf("IVSHMEM: " fmt, ## __VA_ARGS__); \ | |
56 | } \ | |
57 | } while (0) | |
6cbf4c8c | 58 | |
eb3fedf3 PC |
59 | #define TYPE_IVSHMEM "ivshmem" |
60 | #define IVSHMEM(obj) \ | |
61 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM) | |
62 | ||
6cbf4c8c CM |
63 | typedef struct Peer { |
64 | int nb_eventfds; | |
563027cc | 65 | EventNotifier *eventfds; |
6cbf4c8c CM |
66 | } Peer; |
67 | ||
0f57350e | 68 | typedef struct MSIVector { |
6cbf4c8c | 69 | PCIDevice *pdev; |
660c97ee | 70 | int virq; |
0f57350e | 71 | } MSIVector; |
6cbf4c8c CM |
72 | |
73 | typedef struct IVShmemState { | |
b7578eaa AF |
74 | /*< private >*/ |
75 | PCIDevice parent_obj; | |
76 | /*< public >*/ | |
77 | ||
d9453c93 | 78 | HostMemoryBackend *hostmem; |
6cbf4c8c CM |
79 | uint32_t intrmask; |
80 | uint32_t intrstatus; | |
6cbf4c8c | 81 | |
6cbf4c8c | 82 | CharDriverState *server_chr; |
cb06608e | 83 | MemoryRegion ivshmem_mmio; |
6cbf4c8c | 84 | |
c2d8019c MA |
85 | MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */ |
86 | MemoryRegion server_bar2; /* used with server_chr */ | |
08183c20 | 87 | size_t ivshmem_size; /* size of shared memory region */ |
c08ba66f | 88 | uint32_t ivshmem_64bit; |
6cbf4c8c CM |
89 | |
90 | Peer *peers; | |
cd9953f7 | 91 | int nb_peers; /* space in @peers[] */ |
6cbf4c8c CM |
92 | |
93 | int vm_id; | |
94 | uint32_t vectors; | |
95 | uint32_t features; | |
0f57350e | 96 | MSIVector *msi_vectors; |
ee276391 MA |
97 | uint64_t msg_buf; /* buffer for receiving server messages */ |
98 | int msg_buffered_bytes; /* #bytes in @msg_buf */ | |
6cbf4c8c | 99 | |
38e0735e AL |
100 | Error *migration_blocker; |
101 | ||
6cbf4c8c CM |
102 | char * shmobj; |
103 | char * sizearg; | |
104 | char * role; | |
105 | int role_val; /* scalar to avoid multiple string comparisons */ | |
106 | } IVShmemState; | |
107 | ||
108 | /* registers for the Inter-VM shared memory device */ | |
109 | enum ivshmem_registers { | |
110 | INTRMASK = 0, | |
111 | INTRSTATUS = 4, | |
112 | IVPOSITION = 8, | |
113 | DOORBELL = 12, | |
114 | }; | |
115 | ||
116 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
117 | unsigned int feature) { | |
118 | return (ivs->features & (1 << feature)); | |
119 | } | |
120 | ||
d8a5da07 | 121 | static void ivshmem_update_irq(IVShmemState *s) |
6cbf4c8c | 122 | { |
b7578eaa | 123 | PCIDevice *d = PCI_DEVICE(s); |
434ad76d | 124 | uint32_t isr = s->intrstatus & s->intrmask; |
6cbf4c8c | 125 | |
2d1d422d MA |
126 | /* No INTx with msi=on, whether the guest enabled MSI-X or not */ |
127 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
128 | return; | |
129 | } | |
130 | ||
6cbf4c8c CM |
131 | /* don't print ISR resets */ |
132 | if (isr) { | |
133 | IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", | |
dbc464d4 | 134 | isr ? 1 : 0, s->intrstatus, s->intrmask); |
6cbf4c8c CM |
135 | } |
136 | ||
434ad76d | 137 | pci_set_irq(d, isr != 0); |
6cbf4c8c CM |
138 | } |
139 | ||
140 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) | |
141 | { | |
142 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
143 | ||
144 | s->intrmask = val; | |
d8a5da07 | 145 | ivshmem_update_irq(s); |
6cbf4c8c CM |
146 | } |
147 | ||
148 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
149 | { | |
150 | uint32_t ret = s->intrmask; | |
151 | ||
152 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
6cbf4c8c CM |
153 | return ret; |
154 | } | |
155 | ||
156 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
157 | { | |
158 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
159 | ||
160 | s->intrstatus = val; | |
d8a5da07 | 161 | ivshmem_update_irq(s); |
6cbf4c8c CM |
162 | } |
163 | ||
164 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
165 | { | |
166 | uint32_t ret = s->intrstatus; | |
167 | ||
168 | /* reading ISR clears all interrupts */ | |
169 | s->intrstatus = 0; | |
d8a5da07 | 170 | ivshmem_update_irq(s); |
6cbf4c8c CM |
171 | return ret; |
172 | } | |
173 | ||
a8170e5e | 174 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 175 | uint64_t val, unsigned size) |
6cbf4c8c CM |
176 | { |
177 | IVShmemState *s = opaque; | |
178 | ||
6cbf4c8c CM |
179 | uint16_t dest = val >> 16; |
180 | uint16_t vector = val & 0xff; | |
181 | ||
182 | addr &= 0xfc; | |
183 | ||
184 | IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); | |
185 | switch (addr) | |
186 | { | |
187 | case INTRMASK: | |
188 | ivshmem_IntrMask_write(s, val); | |
189 | break; | |
190 | ||
191 | case INTRSTATUS: | |
192 | ivshmem_IntrStatus_write(s, val); | |
193 | break; | |
194 | ||
195 | case DOORBELL: | |
196 | /* check that dest VM ID is reasonable */ | |
95c8425c | 197 | if (dest >= s->nb_peers) { |
6cbf4c8c CM |
198 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
199 | break; | |
200 | } | |
201 | ||
202 | /* check doorbell range */ | |
1b27d7a1 | 203 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
204 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
205 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
f59bb378 MAL |
206 | } else { |
207 | IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n", | |
208 | vector, dest); | |
6cbf4c8c CM |
209 | } |
210 | break; | |
211 | default: | |
f59bb378 | 212 | IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); |
6cbf4c8c CM |
213 | } |
214 | } | |
215 | ||
a8170e5e | 216 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 217 | unsigned size) |
6cbf4c8c CM |
218 | { |
219 | ||
220 | IVShmemState *s = opaque; | |
221 | uint32_t ret; | |
222 | ||
223 | switch (addr) | |
224 | { | |
225 | case INTRMASK: | |
226 | ret = ivshmem_IntrMask_read(s); | |
227 | break; | |
228 | ||
229 | case INTRSTATUS: | |
230 | ret = ivshmem_IntrStatus_read(s); | |
231 | break; | |
232 | ||
233 | case IVPOSITION: | |
1309cf44 | 234 | ret = s->vm_id; |
6cbf4c8c CM |
235 | break; |
236 | ||
237 | default: | |
238 | IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); | |
239 | ret = 0; | |
240 | } | |
241 | ||
242 | return ret; | |
243 | } | |
244 | ||
cb06608e AK |
245 | static const MemoryRegionOps ivshmem_mmio_ops = { |
246 | .read = ivshmem_io_read, | |
247 | .write = ivshmem_io_write, | |
248 | .endianness = DEVICE_NATIVE_ENDIAN, | |
249 | .impl = { | |
250 | .min_access_size = 4, | |
251 | .max_access_size = 4, | |
252 | }, | |
6cbf4c8c CM |
253 | }; |
254 | ||
9940c323 MAL |
255 | static void ivshmem_vector_notify(void *opaque) |
256 | { | |
0f57350e | 257 | MSIVector *entry = opaque; |
6cbf4c8c | 258 | PCIDevice *pdev = entry->pdev; |
d160f3f7 | 259 | IVShmemState *s = IVSHMEM(pdev); |
0f57350e | 260 | int vector = entry - s->msi_vectors; |
9940c323 MAL |
261 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
262 | ||
263 | if (!event_notifier_test_and_clear(n)) { | |
264 | return; | |
265 | } | |
6cbf4c8c | 266 | |
d160f3f7 | 267 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector); |
9940c323 | 268 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
082751e8 MA |
269 | if (msix_enabled(pdev)) { |
270 | msix_notify(pdev, vector); | |
271 | } | |
9940c323 MAL |
272 | } else { |
273 | ivshmem_IntrStatus_write(s, 1); | |
274 | } | |
6cbf4c8c CM |
275 | } |
276 | ||
660c97ee MAL |
277 | static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector, |
278 | MSIMessage msg) | |
279 | { | |
280 | IVShmemState *s = IVSHMEM(dev); | |
281 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
282 | MSIVector *v = &s->msi_vectors[vector]; | |
283 | int ret; | |
284 | ||
285 | IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector); | |
286 | ||
287 | ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev); | |
288 | if (ret < 0) { | |
289 | return ret; | |
290 | } | |
291 | ||
292 | return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq); | |
293 | } | |
294 | ||
295 | static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector) | |
296 | { | |
297 | IVShmemState *s = IVSHMEM(dev); | |
298 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
299 | int ret; | |
300 | ||
301 | IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector); | |
302 | ||
303 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, | |
304 | s->msi_vectors[vector].virq); | |
305 | if (ret != 0) { | |
306 | error_report("remove_irqfd_notifier_gsi failed"); | |
307 | } | |
308 | } | |
309 | ||
310 | static void ivshmem_vector_poll(PCIDevice *dev, | |
311 | unsigned int vector_start, | |
312 | unsigned int vector_end) | |
313 | { | |
314 | IVShmemState *s = IVSHMEM(dev); | |
315 | unsigned int vector; | |
316 | ||
317 | IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end); | |
318 | ||
319 | vector_end = MIN(vector_end, s->vectors); | |
320 | ||
321 | for (vector = vector_start; vector < vector_end; vector++) { | |
322 | EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector]; | |
323 | ||
324 | if (!msix_is_masked(dev, vector)) { | |
325 | continue; | |
326 | } | |
327 | ||
328 | if (event_notifier_test_and_clear(notifier)) { | |
329 | msix_set_pending(dev, vector); | |
330 | } | |
331 | } | |
332 | } | |
333 | ||
9940c323 MAL |
334 | static void watch_vector_notifier(IVShmemState *s, EventNotifier *n, |
335 | int vector) | |
6cbf4c8c | 336 | { |
563027cc | 337 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c | 338 | |
3c27969b | 339 | assert(!s->msi_vectors[vector].pdev); |
9940c323 | 340 | s->msi_vectors[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c | 341 | |
9940c323 MAL |
342 | qemu_set_fd_handler(eventfd, ivshmem_vector_notify, |
343 | NULL, &s->msi_vectors[vector]); | |
6cbf4c8c CM |
344 | } |
345 | ||
d58d7e84 MAL |
346 | static int check_shm_size(IVShmemState *s, int fd, Error **errp) |
347 | { | |
6cbf4c8c CM |
348 | /* check that the guest isn't going to try and map more memory than the |
349 | * the object has allocated return -1 to indicate error */ | |
350 | ||
351 | struct stat buf; | |
352 | ||
5edbdbcd | 353 | if (fstat(fd, &buf) < 0) { |
d58d7e84 MAL |
354 | error_setg(errp, "exiting: fstat on fd %d failed: %s", |
355 | fd, strerror(errno)); | |
5edbdbcd HZ |
356 | return -1; |
357 | } | |
6cbf4c8c CM |
358 | |
359 | if (s->ivshmem_size > buf.st_size) { | |
d58d7e84 | 360 | error_setg(errp, "Requested memory size greater" |
08183c20 | 361 | " than shared object size (%zu > %" PRIu64")", |
d58d7e84 | 362 | s->ivshmem_size, (uint64_t)buf.st_size); |
6cbf4c8c CM |
363 | return -1; |
364 | } else { | |
365 | return 0; | |
366 | } | |
367 | } | |
368 | ||
563027cc PB |
369 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
370 | { | |
371 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
372 | DOORBELL, | |
373 | 4, | |
374 | true, | |
375 | (posn << 16) | i, | |
753d5e14 | 376 | &s->peers[posn].eventfds[i]); |
563027cc PB |
377 | } |
378 | ||
379 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
380 | { | |
381 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
382 | DOORBELL, | |
383 | 4, | |
384 | true, | |
385 | (posn << 16) | i, | |
753d5e14 | 386 | &s->peers[posn].eventfds[i]); |
563027cc PB |
387 | } |
388 | ||
f456179f | 389 | static void close_peer_eventfds(IVShmemState *s, int posn) |
6cbf4c8c | 390 | { |
f456179f | 391 | int i, n; |
6cbf4c8c | 392 | |
9db51b4d | 393 | assert(posn >= 0 && posn < s->nb_peers); |
f456179f | 394 | n = s->peers[posn].nb_eventfds; |
6cbf4c8c | 395 | |
9db51b4d MA |
396 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
397 | memory_region_transaction_begin(); | |
398 | for (i = 0; i < n; i++) { | |
399 | ivshmem_del_eventfd(s, posn, i); | |
400 | } | |
401 | memory_region_transaction_commit(); | |
b6a1f3a5 | 402 | } |
9db51b4d | 403 | |
f456179f | 404 | for (i = 0; i < n; i++) { |
563027cc | 405 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
406 | } |
407 | ||
7267c094 | 408 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
409 | s->peers[posn].nb_eventfds = 0; |
410 | } | |
411 | ||
cd9953f7 | 412 | static void resize_peers(IVShmemState *s, int nb_peers) |
34bc07c5 | 413 | { |
cd9953f7 MA |
414 | int old_nb_peers = s->nb_peers; |
415 | int i; | |
6cbf4c8c | 416 | |
cd9953f7 MA |
417 | assert(nb_peers > old_nb_peers); |
418 | IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers); | |
6cbf4c8c | 419 | |
cd9953f7 MA |
420 | s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer)); |
421 | s->nb_peers = nb_peers; | |
1300b273 | 422 | |
cd9953f7 MA |
423 | for (i = old_nb_peers; i < nb_peers; i++) { |
424 | s->peers[i].eventfds = g_new0(EventNotifier, s->vectors); | |
425 | s->peers[i].nb_eventfds = 0; | |
6cbf4c8c CM |
426 | } |
427 | } | |
428 | ||
1309cf44 MA |
429 | static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector, |
430 | Error **errp) | |
660c97ee MAL |
431 | { |
432 | PCIDevice *pdev = PCI_DEVICE(s); | |
433 | MSIMessage msg = msix_get_message(pdev, vector); | |
434 | int ret; | |
435 | ||
436 | IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); | |
3c27969b | 437 | assert(!s->msi_vectors[vector].pdev); |
660c97ee MAL |
438 | |
439 | ret = kvm_irqchip_add_msi_route(kvm_state, msg, pdev); | |
440 | if (ret < 0) { | |
1309cf44 MA |
441 | error_setg(errp, "kvm_irqchip_add_msi_route failed"); |
442 | return; | |
660c97ee MAL |
443 | } |
444 | ||
445 | s->msi_vectors[vector].virq = ret; | |
446 | s->msi_vectors[vector].pdev = pdev; | |
660c97ee MAL |
447 | } |
448 | ||
1309cf44 | 449 | static void setup_interrupt(IVShmemState *s, int vector, Error **errp) |
660c97ee MAL |
450 | { |
451 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
452 | bool with_irqfd = kvm_msi_via_irqfd_enabled() && | |
453 | ivshmem_has_feature(s, IVSHMEM_MSI); | |
454 | PCIDevice *pdev = PCI_DEVICE(s); | |
1309cf44 | 455 | Error *err = NULL; |
660c97ee MAL |
456 | |
457 | IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector); | |
458 | ||
459 | if (!with_irqfd) { | |
97553976 | 460 | IVSHMEM_DPRINTF("with eventfd\n"); |
9940c323 | 461 | watch_vector_notifier(s, n, vector); |
660c97ee | 462 | } else if (msix_enabled(pdev)) { |
97553976 | 463 | IVSHMEM_DPRINTF("with irqfd\n"); |
1309cf44 MA |
464 | ivshmem_add_kvm_msi_virq(s, vector, &err); |
465 | if (err) { | |
466 | error_propagate(errp, err); | |
660c97ee MAL |
467 | return; |
468 | } | |
469 | ||
470 | if (!msix_is_masked(pdev, vector)) { | |
471 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, | |
472 | s->msi_vectors[vector].virq); | |
1309cf44 | 473 | /* TODO handle error */ |
660c97ee MAL |
474 | } |
475 | } else { | |
476 | /* it will be delayed until msix is enabled, in write_config */ | |
97553976 | 477 | IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n"); |
660c97ee MAL |
478 | } |
479 | } | |
480 | ||
1309cf44 | 481 | static void process_msg_shmem(IVShmemState *s, int fd, Error **errp) |
6cbf4c8c | 482 | { |
d58d7e84 | 483 | Error *err = NULL; |
ca0b7566 | 484 | void *ptr; |
6cbf4c8c | 485 | |
c2d8019c | 486 | if (s->ivshmem_bar2) { |
1309cf44 | 487 | error_setg(errp, "server sent unexpected shared memory message"); |
ca0b7566 | 488 | close(fd); |
0f14fd71 | 489 | return; |
a2e9011b SH |
490 | } |
491 | ||
ca0b7566 | 492 | if (check_shm_size(s, fd, &err) == -1) { |
1309cf44 | 493 | error_propagate(errp, err); |
ca0b7566 | 494 | close(fd); |
cd9953f7 MA |
495 | return; |
496 | } | |
497 | ||
ca0b7566 MA |
498 | /* mmap the region and map into the BAR2 */ |
499 | ptr = mmap(0, s->ivshmem_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); | |
500 | if (ptr == MAP_FAILED) { | |
1309cf44 | 501 | error_setg_errno(errp, errno, "Failed to mmap shared memory"); |
ca0b7566 MA |
502 | close(fd); |
503 | return; | |
6cbf4c8c | 504 | } |
c2d8019c | 505 | memory_region_init_ram_ptr(&s->server_bar2, OBJECT(s), |
ca0b7566 | 506 | "ivshmem.bar2", s->ivshmem_size, ptr); |
c2d8019c MA |
507 | qemu_set_ram_fd(memory_region_get_ram_addr(&s->server_bar2), fd); |
508 | s->ivshmem_bar2 = &s->server_bar2; | |
ca0b7566 MA |
509 | } |
510 | ||
1309cf44 MA |
511 | static void process_msg_disconnect(IVShmemState *s, uint16_t posn, |
512 | Error **errp) | |
ca0b7566 MA |
513 | { |
514 | IVSHMEM_DPRINTF("posn %d has gone away\n", posn); | |
9db51b4d | 515 | if (posn >= s->nb_peers || posn == s->vm_id) { |
1309cf44 | 516 | error_setg(errp, "invalid peer %d", posn); |
9db51b4d MA |
517 | return; |
518 | } | |
ca0b7566 MA |
519 | close_peer_eventfds(s, posn); |
520 | } | |
6cbf4c8c | 521 | |
1309cf44 MA |
522 | static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd, |
523 | Error **errp) | |
ca0b7566 MA |
524 | { |
525 | Peer *peer = &s->peers[posn]; | |
526 | int vector; | |
9a2f0e64 | 527 | |
ca0b7566 MA |
528 | /* |
529 | * The N-th connect message for this peer comes with the file | |
530 | * descriptor for vector N-1. Count messages to find the vector. | |
531 | */ | |
532 | if (peer->nb_eventfds >= s->vectors) { | |
1309cf44 MA |
533 | error_setg(errp, "Too many eventfd received, device has %d vectors", |
534 | s->vectors); | |
ca0b7566 | 535 | close(fd); |
6f8a16d5 | 536 | return; |
6cbf4c8c | 537 | } |
ca0b7566 | 538 | vector = peer->nb_eventfds++; |
6cbf4c8c | 539 | |
ca0b7566 MA |
540 | IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd); |
541 | event_notifier_init_fd(&peer->eventfds[vector], fd); | |
542 | fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */ | |
945001a1 | 543 | |
ca0b7566 | 544 | if (posn == s->vm_id) { |
1309cf44 MA |
545 | setup_interrupt(s, vector, errp); |
546 | /* TODO do we need to handle the error? */ | |
ca0b7566 | 547 | } |
6cbf4c8c | 548 | |
ca0b7566 MA |
549 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
550 | ivshmem_add_eventfd(s, posn, vector); | |
551 | } | |
552 | } | |
6cbf4c8c | 553 | |
1309cf44 | 554 | static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp) |
ca0b7566 MA |
555 | { |
556 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
6cbf4c8c | 557 | |
ca0b7566 | 558 | if (msg < -1 || msg > IVSHMEM_MAX_PEERS) { |
1309cf44 | 559 | error_setg(errp, "server sent invalid message %" PRId64, msg); |
ca0b7566 | 560 | close(fd); |
6cbf4c8c CM |
561 | return; |
562 | } | |
563 | ||
ca0b7566 | 564 | if (msg == -1) { |
1309cf44 | 565 | process_msg_shmem(s, fd, errp); |
1ee57de4 MAL |
566 | return; |
567 | } | |
568 | ||
ca0b7566 MA |
569 | if (msg >= s->nb_peers) { |
570 | resize_peers(s, msg + 1); | |
571 | } | |
6cbf4c8c | 572 | |
ca0b7566 | 573 | if (fd >= 0) { |
1309cf44 | 574 | process_msg_connect(s, msg, fd, errp); |
ca0b7566 | 575 | } else { |
1309cf44 | 576 | process_msg_disconnect(s, msg, errp); |
6cbf4c8c | 577 | } |
ca0b7566 | 578 | } |
6cbf4c8c | 579 | |
ee276391 MA |
580 | static int ivshmem_can_receive(void *opaque) |
581 | { | |
582 | IVShmemState *s = opaque; | |
583 | ||
584 | assert(s->msg_buffered_bytes < sizeof(s->msg_buf)); | |
585 | return sizeof(s->msg_buf) - s->msg_buffered_bytes; | |
586 | } | |
587 | ||
ca0b7566 MA |
588 | static void ivshmem_read(void *opaque, const uint8_t *buf, int size) |
589 | { | |
590 | IVShmemState *s = opaque; | |
1309cf44 | 591 | Error *err = NULL; |
ca0b7566 MA |
592 | int fd; |
593 | int64_t msg; | |
594 | ||
ee276391 MA |
595 | assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf)); |
596 | memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size); | |
597 | s->msg_buffered_bytes += size; | |
598 | if (s->msg_buffered_bytes < sizeof(s->msg_buf)) { | |
ca0b7566 | 599 | return; |
6cbf4c8c | 600 | } |
ee276391 MA |
601 | msg = le64_to_cpu(s->msg_buf); |
602 | s->msg_buffered_bytes = 0; | |
ca0b7566 MA |
603 | |
604 | fd = qemu_chr_fe_get_msgfd(s->server_chr); | |
605 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
606 | ||
1309cf44 MA |
607 | process_msg(s, msg, fd, &err); |
608 | if (err) { | |
609 | error_report_err(err); | |
610 | } | |
6cbf4c8c CM |
611 | } |
612 | ||
1309cf44 | 613 | static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp) |
5105b1d8 | 614 | { |
3a55fc0f MA |
615 | int64_t msg; |
616 | int n, ret; | |
617 | ||
618 | n = 0; | |
619 | do { | |
620 | ret = qemu_chr_fe_read_all(s->server_chr, (uint8_t *)&msg + n, | |
621 | sizeof(msg) - n); | |
622 | if (ret < 0 && ret != -EINTR) { | |
1309cf44 | 623 | error_setg_errno(errp, -ret, "read from server failed"); |
3a55fc0f MA |
624 | return INT64_MIN; |
625 | } | |
626 | n += ret; | |
627 | } while (n < sizeof(msg)); | |
5105b1d8 | 628 | |
3a55fc0f MA |
629 | *pfd = qemu_chr_fe_get_msgfd(s->server_chr); |
630 | return msg; | |
631 | } | |
5105b1d8 | 632 | |
1309cf44 | 633 | static void ivshmem_recv_setup(IVShmemState *s, Error **errp) |
3a55fc0f | 634 | { |
1309cf44 | 635 | Error *err = NULL; |
3a55fc0f MA |
636 | int64_t msg; |
637 | int fd; | |
638 | ||
1309cf44 MA |
639 | msg = ivshmem_recv_msg(s, &fd, &err); |
640 | if (err) { | |
641 | error_propagate(errp, err); | |
642 | return; | |
643 | } | |
644 | if (msg != IVSHMEM_PROTOCOL_VERSION) { | |
645 | error_setg(errp, "server sent version %" PRId64 ", expecting %d", | |
646 | msg, IVSHMEM_PROTOCOL_VERSION); | |
647 | return; | |
648 | } | |
649 | if (fd != -1) { | |
650 | error_setg(errp, "server sent invalid version message"); | |
5105b1d8 DM |
651 | return; |
652 | } | |
653 | ||
a3feb086 MA |
654 | /* |
655 | * ivshmem-server sends the remaining initial messages in a fixed | |
656 | * order, but the device has always accepted them in any order. | |
657 | * Stay as compatible as practical, just in case people use | |
658 | * servers that behave differently. | |
659 | */ | |
660 | ||
661 | /* | |
662 | * ivshmem_device_spec.txt has always required the ID message | |
663 | * right here, and ivshmem-server has always complied. However, | |
664 | * older versions of the device accepted it out of order, but | |
665 | * broke when an interrupt setup message arrived before it. | |
666 | */ | |
667 | msg = ivshmem_recv_msg(s, &fd, &err); | |
668 | if (err) { | |
669 | error_propagate(errp, err); | |
670 | return; | |
671 | } | |
672 | if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) { | |
673 | error_setg(errp, "server sent invalid ID message"); | |
674 | return; | |
675 | } | |
676 | s->vm_id = msg; | |
677 | ||
3a55fc0f MA |
678 | /* |
679 | * Receive more messages until we got shared memory. | |
680 | */ | |
681 | do { | |
1309cf44 MA |
682 | msg = ivshmem_recv_msg(s, &fd, &err); |
683 | if (err) { | |
684 | error_propagate(errp, err); | |
685 | return; | |
686 | } | |
687 | process_msg(s, msg, fd, &err); | |
688 | if (err) { | |
689 | error_propagate(errp, err); | |
690 | return; | |
691 | } | |
3a55fc0f | 692 | } while (msg != -1); |
1309cf44 MA |
693 | |
694 | /* | |
695 | * This function must either map the shared memory or fail. The | |
696 | * loop above ensures that: it terminates normally only after it | |
697 | * successfully processed the server's shared memory message. | |
698 | * Assert that actually mapped the shared memory: | |
699 | */ | |
c2d8019c | 700 | assert(s->ivshmem_bar2); |
5105b1d8 DM |
701 | } |
702 | ||
4490c711 MT |
703 | /* Select the MSI-X vectors used by device. |
704 | * ivshmem maps events to vectors statically, so | |
705 | * we just enable all vectors on init and after reset. */ | |
082751e8 | 706 | static void ivshmem_msix_vector_use(IVShmemState *s) |
4490c711 | 707 | { |
b7578eaa | 708 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
709 | int i; |
710 | ||
4490c711 | 711 | for (i = 0; i < s->vectors; i++) { |
b7578eaa | 712 | msix_vector_use(d, i); |
4490c711 MT |
713 | } |
714 | } | |
715 | ||
6cbf4c8c CM |
716 | static void ivshmem_reset(DeviceState *d) |
717 | { | |
eb3fedf3 | 718 | IVShmemState *s = IVSHMEM(d); |
6cbf4c8c CM |
719 | |
720 | s->intrstatus = 0; | |
972ad215 | 721 | s->intrmask = 0; |
082751e8 MA |
722 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
723 | ivshmem_msix_vector_use(s); | |
724 | } | |
6cbf4c8c CM |
725 | } |
726 | ||
fd47bfe5 | 727 | static int ivshmem_setup_interrupts(IVShmemState *s) |
4490c711 | 728 | { |
fd47bfe5 MAL |
729 | /* allocate QEMU callback data for receiving interrupts */ |
730 | s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector)); | |
6cbf4c8c | 731 | |
fd47bfe5 MAL |
732 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
733 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) { | |
734 | return -1; | |
735 | } | |
1116b539 | 736 | |
fd47bfe5 | 737 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
082751e8 | 738 | ivshmem_msix_vector_use(s); |
fd47bfe5 | 739 | } |
4490c711 | 740 | |
d58d7e84 | 741 | return 0; |
6cbf4c8c CM |
742 | } |
743 | ||
660c97ee MAL |
744 | static void ivshmem_enable_irqfd(IVShmemState *s) |
745 | { | |
746 | PCIDevice *pdev = PCI_DEVICE(s); | |
747 | int i; | |
748 | ||
749 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
1309cf44 MA |
750 | Error *err = NULL; |
751 | ||
752 | ivshmem_add_kvm_msi_virq(s, i, &err); | |
753 | if (err) { | |
754 | error_report_err(err); | |
755 | /* TODO do we need to handle the error? */ | |
756 | } | |
660c97ee MAL |
757 | } |
758 | ||
759 | if (msix_set_vector_notifiers(pdev, | |
760 | ivshmem_vector_unmask, | |
761 | ivshmem_vector_mask, | |
762 | ivshmem_vector_poll)) { | |
763 | error_report("ivshmem: msix_set_vector_notifiers failed"); | |
764 | } | |
765 | } | |
766 | ||
767 | static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector) | |
768 | { | |
769 | IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector); | |
770 | ||
771 | if (s->msi_vectors[vector].pdev == NULL) { | |
772 | return; | |
773 | } | |
774 | ||
775 | /* it was cleaned when masked in the frontend. */ | |
776 | kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq); | |
777 | ||
778 | s->msi_vectors[vector].pdev = NULL; | |
779 | } | |
780 | ||
781 | static void ivshmem_disable_irqfd(IVShmemState *s) | |
782 | { | |
783 | PCIDevice *pdev = PCI_DEVICE(s); | |
784 | int i; | |
785 | ||
786 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
787 | ivshmem_remove_kvm_msi_virq(s, i); | |
788 | } | |
789 | ||
790 | msix_unset_vector_notifiers(pdev); | |
791 | } | |
792 | ||
793 | static void ivshmem_write_config(PCIDevice *pdev, uint32_t address, | |
d58d7e84 | 794 | uint32_t val, int len) |
4490c711 | 795 | { |
660c97ee MAL |
796 | IVShmemState *s = IVSHMEM(pdev); |
797 | int is_enabled, was_enabled = msix_enabled(pdev); | |
798 | ||
799 | pci_default_write_config(pdev, address, val, len); | |
800 | is_enabled = msix_enabled(pdev); | |
801 | ||
1309cf44 | 802 | if (kvm_msi_via_irqfd_enabled()) { |
660c97ee MAL |
803 | if (!was_enabled && is_enabled) { |
804 | ivshmem_enable_irqfd(s); | |
805 | } else if (was_enabled && !is_enabled) { | |
806 | ivshmem_disable_irqfd(s); | |
807 | } | |
808 | } | |
4490c711 MT |
809 | } |
810 | ||
5503e285 MA |
811 | static void desugar_shm(IVShmemState *s) |
812 | { | |
813 | Object *obj; | |
814 | char *path; | |
815 | ||
816 | obj = object_new("memory-backend-file"); | |
817 | path = g_strdup_printf("/dev/shm/%s", s->shmobj); | |
818 | object_property_set_str(obj, path, "mem-path", &error_abort); | |
819 | g_free(path); | |
820 | object_property_set_int(obj, s->ivshmem_size, "size", &error_abort); | |
821 | object_property_set_bool(obj, true, "share", &error_abort); | |
822 | object_property_add_child(OBJECT(s), "internal-shm-backend", obj, | |
823 | &error_abort); | |
824 | user_creatable_complete(obj, &error_abort); | |
825 | s->hostmem = MEMORY_BACKEND(obj); | |
826 | } | |
827 | ||
d58d7e84 | 828 | static void pci_ivshmem_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 829 | { |
eb3fedf3 | 830 | IVShmemState *s = IVSHMEM(dev); |
d855e275 | 831 | Error *err = NULL; |
6cbf4c8c | 832 | uint8_t *pci_conf; |
9113e3f3 MAL |
833 | uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY | |
834 | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
6cbf4c8c | 835 | |
d9453c93 | 836 | if (!!s->server_chr + !!s->shmobj + !!s->hostmem != 1) { |
1d649244 MA |
837 | error_setg(errp, |
838 | "You must specify either 'shm', 'chardev' or 'x-memdev'"); | |
d9453c93 MAL |
839 | return; |
840 | } | |
841 | ||
842 | if (s->hostmem) { | |
843 | MemoryRegion *mr; | |
844 | ||
845 | if (s->sizearg) { | |
846 | g_warning("size argument ignored with hostmem"); | |
847 | } | |
848 | ||
9cf70c52 | 849 | mr = host_memory_backend_get_memory(s->hostmem, &error_abort); |
d9453c93 MAL |
850 | s->ivshmem_size = memory_region_size(mr); |
851 | } else if (s->sizearg == NULL) { | |
6cbf4c8c | 852 | s->ivshmem_size = 4 << 20; /* 4 MB default */ |
d58d7e84 | 853 | } else { |
2c04752c MAL |
854 | char *end; |
855 | int64_t size = qemu_strtosz(s->sizearg, &end); | |
08183c20 MA |
856 | if (size < 0 || (size_t)size != size || *end != '\0' |
857 | || !is_power_of_2(size)) { | |
2c04752c | 858 | error_setg(errp, "Invalid size %s", s->sizearg); |
d58d7e84 MAL |
859 | return; |
860 | } | |
2c04752c | 861 | s->ivshmem_size = size; |
6cbf4c8c CM |
862 | } |
863 | ||
6cbf4c8c CM |
864 | /* IRQFD requires MSI */ |
865 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
866 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
d58d7e84 MAL |
867 | error_setg(errp, "ioeventfd/irqfd requires MSI"); |
868 | return; | |
6cbf4c8c CM |
869 | } |
870 | ||
871 | /* check that role is reasonable */ | |
872 | if (s->role) { | |
873 | if (strncmp(s->role, "peer", 5) == 0) { | |
874 | s->role_val = IVSHMEM_PEER; | |
875 | } else if (strncmp(s->role, "master", 7) == 0) { | |
876 | s->role_val = IVSHMEM_MASTER; | |
877 | } else { | |
d58d7e84 MAL |
878 | error_setg(errp, "'role' must be 'peer' or 'master'"); |
879 | return; | |
6cbf4c8c CM |
880 | } |
881 | } else { | |
882 | s->role_val = IVSHMEM_MASTER; /* default */ | |
883 | } | |
884 | ||
b7578eaa | 885 | pci_conf = dev->config; |
6cbf4c8c | 886 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c | 887 | |
2d1d422d MA |
888 | /* |
889 | * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a | |
890 | * bald-faced lie then. But it's a backwards compatible lie. | |
891 | */ | |
6cbf4c8c CM |
892 | pci_config_set_interrupt_pin(pci_conf, 1); |
893 | ||
3c161542 | 894 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
895 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
896 | ||
6cbf4c8c | 897 | /* region for registers*/ |
b7578eaa | 898 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 899 | &s->ivshmem_mmio); |
cb06608e | 900 | |
c08ba66f | 901 | if (s->ivshmem_64bit) { |
9113e3f3 | 902 | attr |= PCI_BASE_ADDRESS_MEM_TYPE_64; |
c08ba66f | 903 | } |
6cbf4c8c | 904 | |
5503e285 MA |
905 | if (s->shmobj) { |
906 | desugar_shm(s); | |
907 | } | |
908 | ||
d9453c93 | 909 | if (s->hostmem != NULL) { |
d9453c93 MAL |
910 | IVSHMEM_DPRINTF("using hostmem\n"); |
911 | ||
c2d8019c MA |
912 | s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem, |
913 | &error_abort); | |
5503e285 | 914 | } else { |
6cbf4c8c | 915 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", |
dbc464d4 | 916 | s->server_chr->filename); |
6cbf4c8c | 917 | |
f456179f | 918 | /* we allocate enough space for 16 peers and grow as needed */ |
1300b273 | 919 | resize_peers(s, 16); |
6cbf4c8c | 920 | |
3a55fc0f MA |
921 | /* |
922 | * Receive setup messages from server synchronously. | |
923 | * Older versions did it asynchronously, but that creates a | |
924 | * number of entertaining race conditions. | |
3a55fc0f | 925 | */ |
1309cf44 MA |
926 | ivshmem_recv_setup(s, &err); |
927 | if (err) { | |
928 | error_propagate(errp, err); | |
929 | return; | |
3a55fc0f MA |
930 | } |
931 | ||
1309cf44 MA |
932 | qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive, |
933 | ivshmem_read, NULL, s); | |
934 | ||
3a55fc0f MA |
935 | if (ivshmem_setup_interrupts(s) < 0) { |
936 | error_setg(errp, "failed to initialize interrupts"); | |
937 | return; | |
938 | } | |
d855e275 MA |
939 | } |
940 | ||
c2d8019c MA |
941 | vmstate_register_ram(s->ivshmem_bar2, DEVICE(s)); |
942 | pci_register_bar(PCI_DEVICE(s), 2, attr, s->ivshmem_bar2); | |
943 | ||
d855e275 MA |
944 | if (s->role_val == IVSHMEM_PEER) { |
945 | error_setg(&s->migration_blocker, | |
946 | "Migration is disabled when using feature 'peer mode' in device 'ivshmem'"); | |
947 | migrate_add_blocker(s->migration_blocker); | |
6cbf4c8c | 948 | } |
6cbf4c8c CM |
949 | } |
950 | ||
d58d7e84 | 951 | static void pci_ivshmem_exit(PCIDevice *dev) |
6cbf4c8c | 952 | { |
eb3fedf3 | 953 | IVShmemState *s = IVSHMEM(dev); |
f64a078d MAL |
954 | int i; |
955 | ||
38e0735e AL |
956 | if (s->migration_blocker) { |
957 | migrate_del_blocker(s->migration_blocker); | |
958 | error_free(s->migration_blocker); | |
959 | } | |
960 | ||
c2d8019c | 961 | if (memory_region_is_mapped(s->ivshmem_bar2)) { |
d9453c93 | 962 | if (!s->hostmem) { |
c2d8019c | 963 | void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2); |
56a571d9 | 964 | int fd; |
d9453c93 MAL |
965 | |
966 | if (munmap(addr, s->ivshmem_size) == -1) { | |
967 | error_report("Failed to munmap shared memory %s", | |
968 | strerror(errno)); | |
969 | } | |
56a571d9 | 970 | |
c2d8019c MA |
971 | fd = qemu_get_ram_fd(memory_region_get_ram_addr(s->ivshmem_bar2)); |
972 | close(fd); | |
d9453c93 | 973 | } |
f64a078d | 974 | |
c2d8019c | 975 | vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev)); |
f64a078d MAL |
976 | } |
977 | ||
f64a078d MAL |
978 | if (s->peers) { |
979 | for (i = 0; i < s->nb_peers; i++) { | |
f456179f | 980 | close_peer_eventfds(s, i); |
f64a078d MAL |
981 | } |
982 | g_free(s->peers); | |
983 | } | |
984 | ||
985 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
986 | msix_uninit_exclusive_bar(dev); | |
987 | } | |
988 | ||
0f57350e | 989 | g_free(s->msi_vectors); |
6cbf4c8c CM |
990 | } |
991 | ||
1f8552df MAL |
992 | static bool test_msix(void *opaque, int version_id) |
993 | { | |
994 | IVShmemState *s = opaque; | |
995 | ||
996 | return ivshmem_has_feature(s, IVSHMEM_MSI); | |
997 | } | |
998 | ||
999 | static bool test_no_msix(void *opaque, int version_id) | |
1000 | { | |
1001 | return !test_msix(opaque, version_id); | |
1002 | } | |
1003 | ||
1004 | static int ivshmem_pre_load(void *opaque) | |
1005 | { | |
1006 | IVShmemState *s = opaque; | |
1007 | ||
1008 | if (s->role_val == IVSHMEM_PEER) { | |
1009 | error_report("'peer' devices are not migratable"); | |
1010 | return -EINVAL; | |
1011 | } | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | static int ivshmem_post_load(void *opaque, int version_id) | |
1017 | { | |
1018 | IVShmemState *s = opaque; | |
1019 | ||
1020 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
082751e8 | 1021 | ivshmem_msix_vector_use(s); |
1f8552df | 1022 | } |
1f8552df MAL |
1023 | return 0; |
1024 | } | |
1025 | ||
1026 | static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id) | |
1027 | { | |
1028 | IVShmemState *s = opaque; | |
1029 | PCIDevice *pdev = PCI_DEVICE(s); | |
1030 | int ret; | |
1031 | ||
1032 | IVSHMEM_DPRINTF("ivshmem_load_old\n"); | |
1033 | ||
1034 | if (version_id != 0) { | |
1035 | return -EINVAL; | |
1036 | } | |
1037 | ||
1038 | if (s->role_val == IVSHMEM_PEER) { | |
1039 | error_report("'peer' devices are not migratable"); | |
1040 | return -EINVAL; | |
1041 | } | |
1042 | ||
1043 | ret = pci_device_load(pdev, f); | |
1044 | if (ret) { | |
1045 | return ret; | |
1046 | } | |
1047 | ||
1048 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
1049 | msix_load(pdev, f); | |
082751e8 | 1050 | ivshmem_msix_vector_use(s); |
1f8552df MAL |
1051 | } else { |
1052 | s->intrstatus = qemu_get_be32(f); | |
1053 | s->intrmask = qemu_get_be32(f); | |
1054 | } | |
1055 | ||
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | static const VMStateDescription ivshmem_vmsd = { | |
1060 | .name = "ivshmem", | |
1061 | .version_id = 1, | |
1062 | .minimum_version_id = 1, | |
1063 | .pre_load = ivshmem_pre_load, | |
1064 | .post_load = ivshmem_post_load, | |
1065 | .fields = (VMStateField[]) { | |
1066 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1067 | ||
1068 | VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix), | |
1069 | VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix), | |
1070 | VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix), | |
1071 | ||
1072 | VMSTATE_END_OF_LIST() | |
1073 | }, | |
1074 | .load_state_old = ivshmem_load_old, | |
1075 | .minimum_version_id_old = 0 | |
1076 | }; | |
1077 | ||
40021f08 AL |
1078 | static Property ivshmem_properties[] = { |
1079 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1080 | DEFINE_PROP_STRING("size", IVShmemState, sizearg), | |
1081 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1082 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, false), | |
1083 | DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true), | |
1084 | DEFINE_PROP_STRING("shm", IVShmemState, shmobj), | |
1085 | DEFINE_PROP_STRING("role", IVShmemState, role), | |
c08ba66f | 1086 | DEFINE_PROP_UINT32("use64", IVShmemState, ivshmem_64bit, 1), |
40021f08 AL |
1087 | DEFINE_PROP_END_OF_LIST(), |
1088 | }; | |
1089 | ||
1090 | static void ivshmem_class_init(ObjectClass *klass, void *data) | |
1091 | { | |
39bffca2 | 1092 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1093 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1094 | ||
d58d7e84 MAL |
1095 | k->realize = pci_ivshmem_realize; |
1096 | k->exit = pci_ivshmem_exit; | |
1097 | k->config_write = ivshmem_write_config; | |
b8ef62a9 PB |
1098 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
1099 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 1100 | k->class_id = PCI_CLASS_MEMORY_RAM; |
39bffca2 AL |
1101 | dc->reset = ivshmem_reset; |
1102 | dc->props = ivshmem_properties; | |
1f8552df | 1103 | dc->vmsd = &ivshmem_vmsd; |
125ee0ed | 1104 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
d383537d | 1105 | dc->desc = "Inter-VM shared memory"; |
40021f08 AL |
1106 | } |
1107 | ||
d9453c93 MAL |
1108 | static void ivshmem_check_memdev_is_busy(Object *obj, const char *name, |
1109 | Object *val, Error **errp) | |
1110 | { | |
1111 | MemoryRegion *mr; | |
1112 | ||
9cf70c52 | 1113 | mr = host_memory_backend_get_memory(MEMORY_BACKEND(val), &error_abort); |
d9453c93 MAL |
1114 | if (memory_region_is_mapped(mr)) { |
1115 | char *path = object_get_canonical_path_component(val); | |
1116 | error_setg(errp, "can't use already busy memdev: %s", path); | |
1117 | g_free(path); | |
1118 | } else { | |
1119 | qdev_prop_allow_set_link_before_realize(obj, name, val, errp); | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | static void ivshmem_init(Object *obj) | |
1124 | { | |
1125 | IVShmemState *s = IVSHMEM(obj); | |
1126 | ||
1d649244 | 1127 | object_property_add_link(obj, "x-memdev", TYPE_MEMORY_BACKEND, |
d9453c93 MAL |
1128 | (Object **)&s->hostmem, |
1129 | ivshmem_check_memdev_is_busy, | |
1130 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
1131 | &error_abort); | |
1132 | } | |
1133 | ||
8c43a6f0 | 1134 | static const TypeInfo ivshmem_info = { |
eb3fedf3 | 1135 | .name = TYPE_IVSHMEM, |
39bffca2 AL |
1136 | .parent = TYPE_PCI_DEVICE, |
1137 | .instance_size = sizeof(IVShmemState), | |
d9453c93 | 1138 | .instance_init = ivshmem_init, |
39bffca2 | 1139 | .class_init = ivshmem_class_init, |
6cbf4c8c CM |
1140 | }; |
1141 | ||
83f7d43a | 1142 | static void ivshmem_register_types(void) |
6cbf4c8c | 1143 | { |
39bffca2 | 1144 | type_register_static(&ivshmem_info); |
6cbf4c8c CM |
1145 | } |
1146 | ||
83f7d43a | 1147 | type_init(ivshmem_register_types) |