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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <cam@cs.ualberta.ca> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
0d1c9782 | 19 | #include "qemu/osdep.h" |
83c9f4ca | 20 | #include "hw/hw.h" |
0d09e41a | 21 | #include "hw/i386/pc.h" |
83c9f4ca | 22 | #include "hw/pci/pci.h" |
660c97ee | 23 | #include "hw/pci/msi.h" |
83c9f4ca | 24 | #include "hw/pci/msix.h" |
9c17d615 | 25 | #include "sysemu/kvm.h" |
caf71f86 | 26 | #include "migration/migration.h" |
d49b6836 | 27 | #include "qemu/error-report.h" |
1de7afc9 | 28 | #include "qemu/event_notifier.h" |
a2e9011b | 29 | #include "qemu/fifo8.h" |
dccfcd0e | 30 | #include "sysemu/char.h" |
d9453c93 MAL |
31 | #include "sysemu/hostmem.h" |
32 | #include "qapi/visitor.h" | |
56a571d9 | 33 | #include "exec/ram_addr.h" |
6cbf4c8c | 34 | |
5105b1d8 DM |
35 | #include "hw/misc/ivshmem.h" |
36 | ||
6cbf4c8c | 37 | #include <sys/mman.h> |
6cbf4c8c | 38 | |
b8ef62a9 PB |
39 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
40 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
41 | ||
cd9953f7 | 42 | #define IVSHMEM_MAX_PEERS UINT16_MAX |
6cbf4c8c CM |
43 | #define IVSHMEM_IOEVENTFD 0 |
44 | #define IVSHMEM_MSI 1 | |
45 | ||
46 | #define IVSHMEM_PEER 0 | |
47 | #define IVSHMEM_MASTER 1 | |
48 | ||
49 | #define IVSHMEM_REG_BAR_SIZE 0x100 | |
50 | ||
a4fa93bf MA |
51 | #define IVSHMEM_DEBUG 0 |
52 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
53 | do { \ | |
54 | if (IVSHMEM_DEBUG) { \ | |
55 | printf("IVSHMEM: " fmt, ## __VA_ARGS__); \ | |
56 | } \ | |
57 | } while (0) | |
6cbf4c8c | 58 | |
eb3fedf3 PC |
59 | #define TYPE_IVSHMEM "ivshmem" |
60 | #define IVSHMEM(obj) \ | |
61 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM) | |
62 | ||
6cbf4c8c CM |
63 | typedef struct Peer { |
64 | int nb_eventfds; | |
563027cc | 65 | EventNotifier *eventfds; |
6cbf4c8c CM |
66 | } Peer; |
67 | ||
0f57350e | 68 | typedef struct MSIVector { |
6cbf4c8c | 69 | PCIDevice *pdev; |
660c97ee | 70 | int virq; |
0f57350e | 71 | } MSIVector; |
6cbf4c8c CM |
72 | |
73 | typedef struct IVShmemState { | |
b7578eaa AF |
74 | /*< private >*/ |
75 | PCIDevice parent_obj; | |
76 | /*< public >*/ | |
77 | ||
d9453c93 | 78 | HostMemoryBackend *hostmem; |
6cbf4c8c CM |
79 | uint32_t intrmask; |
80 | uint32_t intrstatus; | |
6cbf4c8c | 81 | |
6cbf4c8c | 82 | CharDriverState *server_chr; |
a2e9011b | 83 | Fifo8 incoming_fifo; |
cb06608e | 84 | MemoryRegion ivshmem_mmio; |
6cbf4c8c | 85 | |
cb06608e AK |
86 | /* We might need to register the BAR before we actually have the memory. |
87 | * So prepare a container MemoryRegion for the BAR immediately and | |
88 | * add a subregion when we have the memory. | |
89 | */ | |
90 | MemoryRegion bar; | |
91 | MemoryRegion ivshmem; | |
6cbf4c8c | 92 | uint64_t ivshmem_size; /* size of shared memory region */ |
c08ba66f | 93 | uint32_t ivshmem_64bit; |
6cbf4c8c CM |
94 | |
95 | Peer *peers; | |
cd9953f7 | 96 | int nb_peers; /* space in @peers[] */ |
6cbf4c8c CM |
97 | |
98 | int vm_id; | |
99 | uint32_t vectors; | |
100 | uint32_t features; | |
0f57350e | 101 | MSIVector *msi_vectors; |
6cbf4c8c | 102 | |
38e0735e AL |
103 | Error *migration_blocker; |
104 | ||
6cbf4c8c CM |
105 | char * shmobj; |
106 | char * sizearg; | |
107 | char * role; | |
108 | int role_val; /* scalar to avoid multiple string comparisons */ | |
109 | } IVShmemState; | |
110 | ||
111 | /* registers for the Inter-VM shared memory device */ | |
112 | enum ivshmem_registers { | |
113 | INTRMASK = 0, | |
114 | INTRSTATUS = 4, | |
115 | IVPOSITION = 8, | |
116 | DOORBELL = 12, | |
117 | }; | |
118 | ||
119 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
120 | unsigned int feature) { | |
121 | return (ivs->features & (1 << feature)); | |
122 | } | |
123 | ||
d8a5da07 | 124 | static void ivshmem_update_irq(IVShmemState *s) |
6cbf4c8c | 125 | { |
b7578eaa | 126 | PCIDevice *d = PCI_DEVICE(s); |
434ad76d | 127 | uint32_t isr = s->intrstatus & s->intrmask; |
6cbf4c8c | 128 | |
2d1d422d MA |
129 | /* No INTx with msi=on, whether the guest enabled MSI-X or not */ |
130 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
131 | return; | |
132 | } | |
133 | ||
6cbf4c8c CM |
134 | /* don't print ISR resets */ |
135 | if (isr) { | |
136 | IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", | |
dbc464d4 | 137 | isr ? 1 : 0, s->intrstatus, s->intrmask); |
6cbf4c8c CM |
138 | } |
139 | ||
434ad76d | 140 | pci_set_irq(d, isr != 0); |
6cbf4c8c CM |
141 | } |
142 | ||
143 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) | |
144 | { | |
145 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
146 | ||
147 | s->intrmask = val; | |
d8a5da07 | 148 | ivshmem_update_irq(s); |
6cbf4c8c CM |
149 | } |
150 | ||
151 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
152 | { | |
153 | uint32_t ret = s->intrmask; | |
154 | ||
155 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
6cbf4c8c CM |
156 | return ret; |
157 | } | |
158 | ||
159 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
160 | { | |
161 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
162 | ||
163 | s->intrstatus = val; | |
d8a5da07 | 164 | ivshmem_update_irq(s); |
6cbf4c8c CM |
165 | } |
166 | ||
167 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
168 | { | |
169 | uint32_t ret = s->intrstatus; | |
170 | ||
171 | /* reading ISR clears all interrupts */ | |
172 | s->intrstatus = 0; | |
d8a5da07 | 173 | ivshmem_update_irq(s); |
6cbf4c8c CM |
174 | return ret; |
175 | } | |
176 | ||
a8170e5e | 177 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 178 | uint64_t val, unsigned size) |
6cbf4c8c CM |
179 | { |
180 | IVShmemState *s = opaque; | |
181 | ||
6cbf4c8c CM |
182 | uint16_t dest = val >> 16; |
183 | uint16_t vector = val & 0xff; | |
184 | ||
185 | addr &= 0xfc; | |
186 | ||
187 | IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); | |
188 | switch (addr) | |
189 | { | |
190 | case INTRMASK: | |
191 | ivshmem_IntrMask_write(s, val); | |
192 | break; | |
193 | ||
194 | case INTRSTATUS: | |
195 | ivshmem_IntrStatus_write(s, val); | |
196 | break; | |
197 | ||
198 | case DOORBELL: | |
199 | /* check that dest VM ID is reasonable */ | |
95c8425c | 200 | if (dest >= s->nb_peers) { |
6cbf4c8c CM |
201 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
202 | break; | |
203 | } | |
204 | ||
205 | /* check doorbell range */ | |
1b27d7a1 | 206 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
207 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
208 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
f59bb378 MAL |
209 | } else { |
210 | IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n", | |
211 | vector, dest); | |
6cbf4c8c CM |
212 | } |
213 | break; | |
214 | default: | |
f59bb378 | 215 | IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); |
6cbf4c8c CM |
216 | } |
217 | } | |
218 | ||
a8170e5e | 219 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 220 | unsigned size) |
6cbf4c8c CM |
221 | { |
222 | ||
223 | IVShmemState *s = opaque; | |
224 | uint32_t ret; | |
225 | ||
226 | switch (addr) | |
227 | { | |
228 | case INTRMASK: | |
229 | ret = ivshmem_IntrMask_read(s); | |
230 | break; | |
231 | ||
232 | case INTRSTATUS: | |
233 | ret = ivshmem_IntrStatus_read(s); | |
234 | break; | |
235 | ||
236 | case IVPOSITION: | |
237 | /* return my VM ID if the memory is mapped */ | |
f689d281 | 238 | if (memory_region_is_mapped(&s->ivshmem)) { |
6cbf4c8c CM |
239 | ret = s->vm_id; |
240 | } else { | |
241 | ret = -1; | |
242 | } | |
243 | break; | |
244 | ||
245 | default: | |
246 | IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); | |
247 | ret = 0; | |
248 | } | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
cb06608e AK |
253 | static const MemoryRegionOps ivshmem_mmio_ops = { |
254 | .read = ivshmem_io_read, | |
255 | .write = ivshmem_io_write, | |
256 | .endianness = DEVICE_NATIVE_ENDIAN, | |
257 | .impl = { | |
258 | .min_access_size = 4, | |
259 | .max_access_size = 4, | |
260 | }, | |
6cbf4c8c CM |
261 | }; |
262 | ||
6cbf4c8c CM |
263 | static int ivshmem_can_receive(void * opaque) |
264 | { | |
f7a199b2 | 265 | return sizeof(int64_t); |
6cbf4c8c CM |
266 | } |
267 | ||
9940c323 MAL |
268 | static void ivshmem_vector_notify(void *opaque) |
269 | { | |
0f57350e | 270 | MSIVector *entry = opaque; |
6cbf4c8c | 271 | PCIDevice *pdev = entry->pdev; |
d160f3f7 | 272 | IVShmemState *s = IVSHMEM(pdev); |
0f57350e | 273 | int vector = entry - s->msi_vectors; |
9940c323 MAL |
274 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
275 | ||
276 | if (!event_notifier_test_and_clear(n)) { | |
277 | return; | |
278 | } | |
6cbf4c8c | 279 | |
d160f3f7 | 280 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector); |
9940c323 | 281 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
082751e8 MA |
282 | if (msix_enabled(pdev)) { |
283 | msix_notify(pdev, vector); | |
284 | } | |
9940c323 MAL |
285 | } else { |
286 | ivshmem_IntrStatus_write(s, 1); | |
287 | } | |
6cbf4c8c CM |
288 | } |
289 | ||
660c97ee MAL |
290 | static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector, |
291 | MSIMessage msg) | |
292 | { | |
293 | IVShmemState *s = IVSHMEM(dev); | |
294 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
295 | MSIVector *v = &s->msi_vectors[vector]; | |
296 | int ret; | |
297 | ||
298 | IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector); | |
299 | ||
300 | ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev); | |
301 | if (ret < 0) { | |
302 | return ret; | |
303 | } | |
304 | ||
305 | return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq); | |
306 | } | |
307 | ||
308 | static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector) | |
309 | { | |
310 | IVShmemState *s = IVSHMEM(dev); | |
311 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
312 | int ret; | |
313 | ||
314 | IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector); | |
315 | ||
316 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, | |
317 | s->msi_vectors[vector].virq); | |
318 | if (ret != 0) { | |
319 | error_report("remove_irqfd_notifier_gsi failed"); | |
320 | } | |
321 | } | |
322 | ||
323 | static void ivshmem_vector_poll(PCIDevice *dev, | |
324 | unsigned int vector_start, | |
325 | unsigned int vector_end) | |
326 | { | |
327 | IVShmemState *s = IVSHMEM(dev); | |
328 | unsigned int vector; | |
329 | ||
330 | IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end); | |
331 | ||
332 | vector_end = MIN(vector_end, s->vectors); | |
333 | ||
334 | for (vector = vector_start; vector < vector_end; vector++) { | |
335 | EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector]; | |
336 | ||
337 | if (!msix_is_masked(dev, vector)) { | |
338 | continue; | |
339 | } | |
340 | ||
341 | if (event_notifier_test_and_clear(notifier)) { | |
342 | msix_set_pending(dev, vector); | |
343 | } | |
344 | } | |
345 | } | |
346 | ||
9940c323 MAL |
347 | static void watch_vector_notifier(IVShmemState *s, EventNotifier *n, |
348 | int vector) | |
6cbf4c8c | 349 | { |
563027cc | 350 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c | 351 | |
3c27969b | 352 | assert(!s->msi_vectors[vector].pdev); |
9940c323 | 353 | s->msi_vectors[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c | 354 | |
9940c323 MAL |
355 | qemu_set_fd_handler(eventfd, ivshmem_vector_notify, |
356 | NULL, &s->msi_vectors[vector]); | |
6cbf4c8c CM |
357 | } |
358 | ||
d58d7e84 MAL |
359 | static int check_shm_size(IVShmemState *s, int fd, Error **errp) |
360 | { | |
6cbf4c8c CM |
361 | /* check that the guest isn't going to try and map more memory than the |
362 | * the object has allocated return -1 to indicate error */ | |
363 | ||
364 | struct stat buf; | |
365 | ||
5edbdbcd | 366 | if (fstat(fd, &buf) < 0) { |
d58d7e84 MAL |
367 | error_setg(errp, "exiting: fstat on fd %d failed: %s", |
368 | fd, strerror(errno)); | |
5edbdbcd HZ |
369 | return -1; |
370 | } | |
6cbf4c8c CM |
371 | |
372 | if (s->ivshmem_size > buf.st_size) { | |
d58d7e84 MAL |
373 | error_setg(errp, "Requested memory size greater" |
374 | " than shared object size (%" PRIu64 " > %" PRIu64")", | |
375 | s->ivshmem_size, (uint64_t)buf.st_size); | |
6cbf4c8c CM |
376 | return -1; |
377 | } else { | |
378 | return 0; | |
379 | } | |
380 | } | |
381 | ||
382 | /* create the shared memory BAR when we are not using the server, so we can | |
383 | * create the BAR and map the memory immediately */ | |
d58d7e84 MAL |
384 | static int create_shared_memory_BAR(IVShmemState *s, int fd, uint8_t attr, |
385 | Error **errp) | |
386 | { | |
6cbf4c8c CM |
387 | void * ptr; |
388 | ||
6cbf4c8c | 389 | ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
d58d7e84 MAL |
390 | if (ptr == MAP_FAILED) { |
391 | error_setg_errno(errp, errno, "Failed to mmap shared memory"); | |
392 | return -1; | |
393 | } | |
394 | ||
3c161542 | 395 | memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2", |
cb06608e | 396 | s->ivshmem_size, ptr); |
8e41fb63 | 397 | qemu_set_ram_fd(memory_region_get_ram_addr(&s->ivshmem), fd); |
eb3fedf3 | 398 | vmstate_register_ram(&s->ivshmem, DEVICE(s)); |
cb06608e | 399 | memory_region_add_subregion(&s->bar, 0, &s->ivshmem); |
6cbf4c8c CM |
400 | |
401 | /* region for shared memory */ | |
9113e3f3 | 402 | pci_register_bar(PCI_DEVICE(s), 2, attr, &s->bar); |
d58d7e84 MAL |
403 | |
404 | return 0; | |
6cbf4c8c CM |
405 | } |
406 | ||
563027cc PB |
407 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
408 | { | |
409 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
410 | DOORBELL, | |
411 | 4, | |
412 | true, | |
413 | (posn << 16) | i, | |
753d5e14 | 414 | &s->peers[posn].eventfds[i]); |
563027cc PB |
415 | } |
416 | ||
417 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
418 | { | |
419 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
420 | DOORBELL, | |
421 | 4, | |
422 | true, | |
423 | (posn << 16) | i, | |
753d5e14 | 424 | &s->peers[posn].eventfds[i]); |
563027cc PB |
425 | } |
426 | ||
f456179f | 427 | static void close_peer_eventfds(IVShmemState *s, int posn) |
6cbf4c8c | 428 | { |
f456179f | 429 | int i, n; |
6cbf4c8c | 430 | |
98609cd8 PB |
431 | if (!ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
432 | return; | |
433 | } | |
363ba1c7 | 434 | if (posn < 0 || posn >= s->nb_peers) { |
ffa99afd | 435 | error_report("invalid peer %d", posn); |
363ba1c7 SH |
436 | return; |
437 | } | |
98609cd8 | 438 | |
f456179f | 439 | n = s->peers[posn].nb_eventfds; |
6cbf4c8c | 440 | |
b6a1f3a5 | 441 | memory_region_transaction_begin(); |
f456179f | 442 | for (i = 0; i < n; i++) { |
563027cc | 443 | ivshmem_del_eventfd(s, posn, i); |
b6a1f3a5 PB |
444 | } |
445 | memory_region_transaction_commit(); | |
f456179f | 446 | for (i = 0; i < n; i++) { |
563027cc | 447 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
448 | } |
449 | ||
7267c094 | 450 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
451 | s->peers[posn].nb_eventfds = 0; |
452 | } | |
453 | ||
cd9953f7 | 454 | static void resize_peers(IVShmemState *s, int nb_peers) |
34bc07c5 | 455 | { |
cd9953f7 MA |
456 | int old_nb_peers = s->nb_peers; |
457 | int i; | |
6cbf4c8c | 458 | |
cd9953f7 MA |
459 | assert(nb_peers > old_nb_peers); |
460 | IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers); | |
6cbf4c8c | 461 | |
cd9953f7 MA |
462 | s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer)); |
463 | s->nb_peers = nb_peers; | |
1300b273 | 464 | |
cd9953f7 MA |
465 | for (i = old_nb_peers; i < nb_peers; i++) { |
466 | s->peers[i].eventfds = g_new0(EventNotifier, s->vectors); | |
467 | s->peers[i].nb_eventfds = 0; | |
6cbf4c8c CM |
468 | } |
469 | } | |
470 | ||
0f14fd71 MAL |
471 | static bool fifo_update_and_get(IVShmemState *s, const uint8_t *buf, int size, |
472 | void *data, size_t len) | |
473 | { | |
474 | const uint8_t *p; | |
475 | uint32_t num; | |
476 | ||
f7a199b2 | 477 | assert(len <= sizeof(int64_t)); /* limitation of the fifo */ |
0f14fd71 MAL |
478 | if (fifo8_is_empty(&s->incoming_fifo) && size == len) { |
479 | memcpy(data, buf, size); | |
480 | return true; | |
481 | } | |
482 | ||
483 | IVSHMEM_DPRINTF("short read of %d bytes\n", size); | |
484 | ||
f7a199b2 | 485 | num = MIN(size, sizeof(int64_t) - fifo8_num_used(&s->incoming_fifo)); |
0f14fd71 MAL |
486 | fifo8_push_all(&s->incoming_fifo, buf, num); |
487 | ||
488 | if (fifo8_num_used(&s->incoming_fifo) < len) { | |
489 | assert(num == 0); | |
490 | return false; | |
491 | } | |
492 | ||
493 | size -= num; | |
494 | buf += num; | |
495 | p = fifo8_pop_buf(&s->incoming_fifo, len, &num); | |
496 | assert(num == len); | |
497 | ||
498 | memcpy(data, p, len); | |
499 | ||
500 | if (size > 0) { | |
501 | fifo8_push_all(&s->incoming_fifo, buf, size); | |
502 | } | |
503 | ||
504 | return true; | |
505 | } | |
506 | ||
f7a199b2 MAL |
507 | static bool fifo_update_and_get_i64(IVShmemState *s, |
508 | const uint8_t *buf, int size, int64_t *i64) | |
509 | { | |
510 | if (fifo_update_and_get(s, buf, size, i64, sizeof(*i64))) { | |
511 | *i64 = GINT64_FROM_LE(*i64); | |
512 | return true; | |
513 | } | |
514 | ||
515 | return false; | |
516 | } | |
517 | ||
660c97ee MAL |
518 | static int ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector) |
519 | { | |
520 | PCIDevice *pdev = PCI_DEVICE(s); | |
521 | MSIMessage msg = msix_get_message(pdev, vector); | |
522 | int ret; | |
523 | ||
524 | IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); | |
3c27969b | 525 | assert(!s->msi_vectors[vector].pdev); |
660c97ee MAL |
526 | |
527 | ret = kvm_irqchip_add_msi_route(kvm_state, msg, pdev); | |
528 | if (ret < 0) { | |
529 | error_report("ivshmem: kvm_irqchip_add_msi_route failed"); | |
530 | return -1; | |
531 | } | |
532 | ||
533 | s->msi_vectors[vector].virq = ret; | |
534 | s->msi_vectors[vector].pdev = pdev; | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | static void setup_interrupt(IVShmemState *s, int vector) | |
540 | { | |
541 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
542 | bool with_irqfd = kvm_msi_via_irqfd_enabled() && | |
543 | ivshmem_has_feature(s, IVSHMEM_MSI); | |
544 | PCIDevice *pdev = PCI_DEVICE(s); | |
545 | ||
546 | IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector); | |
547 | ||
548 | if (!with_irqfd) { | |
97553976 | 549 | IVSHMEM_DPRINTF("with eventfd\n"); |
9940c323 | 550 | watch_vector_notifier(s, n, vector); |
660c97ee | 551 | } else if (msix_enabled(pdev)) { |
97553976 | 552 | IVSHMEM_DPRINTF("with irqfd\n"); |
660c97ee MAL |
553 | if (ivshmem_add_kvm_msi_virq(s, vector) < 0) { |
554 | return; | |
555 | } | |
556 | ||
557 | if (!msix_is_masked(pdev, vector)) { | |
558 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, | |
559 | s->msi_vectors[vector].virq); | |
560 | } | |
561 | } else { | |
562 | /* it will be delayed until msix is enabled, in write_config */ | |
97553976 | 563 | IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n"); |
660c97ee MAL |
564 | } |
565 | } | |
566 | ||
ca0b7566 | 567 | static void process_msg_shmem(IVShmemState *s, int fd) |
6cbf4c8c | 568 | { |
d58d7e84 | 569 | Error *err = NULL; |
ca0b7566 | 570 | void *ptr; |
6cbf4c8c | 571 | |
ca0b7566 MA |
572 | if (memory_region_is_mapped(&s->ivshmem)) { |
573 | error_report("shm already initialized"); | |
574 | close(fd); | |
0f14fd71 | 575 | return; |
a2e9011b SH |
576 | } |
577 | ||
ca0b7566 MA |
578 | if (check_shm_size(s, fd, &err) == -1) { |
579 | error_report_err(err); | |
580 | close(fd); | |
cd9953f7 MA |
581 | return; |
582 | } | |
583 | ||
ca0b7566 MA |
584 | /* mmap the region and map into the BAR2 */ |
585 | ptr = mmap(0, s->ivshmem_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); | |
586 | if (ptr == MAP_FAILED) { | |
587 | error_report("Failed to mmap shared memory %s", strerror(errno)); | |
588 | close(fd); | |
589 | return; | |
6cbf4c8c | 590 | } |
ca0b7566 MA |
591 | memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), |
592 | "ivshmem.bar2", s->ivshmem_size, ptr); | |
593 | qemu_set_ram_fd(memory_region_get_ram_addr(&s->ivshmem), fd); | |
594 | vmstate_register_ram(&s->ivshmem, DEVICE(s)); | |
595 | memory_region_add_subregion(&s->bar, 0, &s->ivshmem); | |
596 | } | |
597 | ||
598 | static void process_msg_disconnect(IVShmemState *s, uint16_t posn) | |
599 | { | |
600 | IVSHMEM_DPRINTF("posn %d has gone away\n", posn); | |
601 | close_peer_eventfds(s, posn); | |
602 | } | |
6cbf4c8c | 603 | |
ca0b7566 MA |
604 | static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd) |
605 | { | |
606 | Peer *peer = &s->peers[posn]; | |
607 | int vector; | |
9a2f0e64 | 608 | |
ca0b7566 MA |
609 | /* |
610 | * The N-th connect message for this peer comes with the file | |
611 | * descriptor for vector N-1. Count messages to find the vector. | |
612 | */ | |
613 | if (peer->nb_eventfds >= s->vectors) { | |
614 | error_report("Too many eventfd received, device has %d vectors", | |
615 | s->vectors); | |
616 | close(fd); | |
6f8a16d5 | 617 | return; |
6cbf4c8c | 618 | } |
ca0b7566 | 619 | vector = peer->nb_eventfds++; |
6cbf4c8c | 620 | |
ca0b7566 MA |
621 | IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd); |
622 | event_notifier_init_fd(&peer->eventfds[vector], fd); | |
623 | fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */ | |
945001a1 | 624 | |
ca0b7566 MA |
625 | if (posn == s->vm_id) { |
626 | setup_interrupt(s, vector); | |
627 | } | |
6cbf4c8c | 628 | |
ca0b7566 MA |
629 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
630 | ivshmem_add_eventfd(s, posn, vector); | |
631 | } | |
632 | } | |
6cbf4c8c | 633 | |
ca0b7566 MA |
634 | static void process_msg(IVShmemState *s, int64_t msg, int fd) |
635 | { | |
636 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
6cbf4c8c | 637 | |
ca0b7566 MA |
638 | if (msg < -1 || msg > IVSHMEM_MAX_PEERS) { |
639 | error_report("server sent invalid message %" PRId64, msg); | |
640 | close(fd); | |
6cbf4c8c CM |
641 | return; |
642 | } | |
643 | ||
ca0b7566 MA |
644 | if (msg == -1) { |
645 | process_msg_shmem(s, fd); | |
1ee57de4 MAL |
646 | return; |
647 | } | |
648 | ||
ca0b7566 MA |
649 | if (msg >= s->nb_peers) { |
650 | resize_peers(s, msg + 1); | |
651 | } | |
6cbf4c8c | 652 | |
ca0b7566 MA |
653 | if (fd >= 0) { |
654 | process_msg_connect(s, msg, fd); | |
655 | } else if (s->vm_id == -1) { | |
656 | s->vm_id = msg; | |
657 | } else { | |
658 | process_msg_disconnect(s, msg); | |
6cbf4c8c | 659 | } |
ca0b7566 | 660 | } |
6cbf4c8c | 661 | |
ca0b7566 MA |
662 | static void ivshmem_read(void *opaque, const uint8_t *buf, int size) |
663 | { | |
664 | IVShmemState *s = opaque; | |
665 | int fd; | |
666 | int64_t msg; | |
667 | ||
668 | if (!fifo_update_and_get_i64(s, buf, size, &msg)) { | |
669 | return; | |
6cbf4c8c | 670 | } |
ca0b7566 MA |
671 | |
672 | fd = qemu_chr_fe_get_msgfd(s->server_chr); | |
673 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
674 | ||
675 | process_msg(s, msg, fd); | |
6cbf4c8c CM |
676 | } |
677 | ||
5105b1d8 DM |
678 | static void ivshmem_check_version(void *opaque, const uint8_t * buf, int size) |
679 | { | |
680 | IVShmemState *s = opaque; | |
681 | int tmp; | |
f7a199b2 | 682 | int64_t version; |
5105b1d8 | 683 | |
f7a199b2 | 684 | if (!fifo_update_and_get_i64(s, buf, size, &version)) { |
5105b1d8 DM |
685 | return; |
686 | } | |
687 | ||
688 | tmp = qemu_chr_fe_get_msgfd(s->server_chr); | |
689 | if (tmp != -1 || version != IVSHMEM_PROTOCOL_VERSION) { | |
690 | fprintf(stderr, "incompatible version, you are connecting to a ivshmem-" | |
691 | "server using a different protocol please check your setup\n"); | |
71c26581 | 692 | qemu_chr_add_handlers(s->server_chr, NULL, NULL, NULL, s); |
5105b1d8 DM |
693 | return; |
694 | } | |
695 | ||
696 | IVSHMEM_DPRINTF("version check ok, switch to real chardev handler\n"); | |
697 | qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive, ivshmem_read, | |
c20fc0c3 | 698 | NULL, s); |
5105b1d8 DM |
699 | } |
700 | ||
4490c711 MT |
701 | /* Select the MSI-X vectors used by device. |
702 | * ivshmem maps events to vectors statically, so | |
703 | * we just enable all vectors on init and after reset. */ | |
082751e8 | 704 | static void ivshmem_msix_vector_use(IVShmemState *s) |
4490c711 | 705 | { |
b7578eaa | 706 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
707 | int i; |
708 | ||
4490c711 | 709 | for (i = 0; i < s->vectors; i++) { |
b7578eaa | 710 | msix_vector_use(d, i); |
4490c711 MT |
711 | } |
712 | } | |
713 | ||
6cbf4c8c CM |
714 | static void ivshmem_reset(DeviceState *d) |
715 | { | |
eb3fedf3 | 716 | IVShmemState *s = IVSHMEM(d); |
6cbf4c8c CM |
717 | |
718 | s->intrstatus = 0; | |
972ad215 | 719 | s->intrmask = 0; |
082751e8 MA |
720 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
721 | ivshmem_msix_vector_use(s); | |
722 | } | |
6cbf4c8c CM |
723 | } |
724 | ||
fd47bfe5 | 725 | static int ivshmem_setup_interrupts(IVShmemState *s) |
4490c711 | 726 | { |
fd47bfe5 MAL |
727 | /* allocate QEMU callback data for receiving interrupts */ |
728 | s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector)); | |
6cbf4c8c | 729 | |
fd47bfe5 MAL |
730 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
731 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) { | |
732 | return -1; | |
733 | } | |
1116b539 | 734 | |
fd47bfe5 | 735 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
082751e8 | 736 | ivshmem_msix_vector_use(s); |
fd47bfe5 | 737 | } |
4490c711 | 738 | |
d58d7e84 | 739 | return 0; |
6cbf4c8c CM |
740 | } |
741 | ||
660c97ee MAL |
742 | static void ivshmem_enable_irqfd(IVShmemState *s) |
743 | { | |
744 | PCIDevice *pdev = PCI_DEVICE(s); | |
745 | int i; | |
746 | ||
747 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
748 | ivshmem_add_kvm_msi_virq(s, i); | |
749 | } | |
750 | ||
751 | if (msix_set_vector_notifiers(pdev, | |
752 | ivshmem_vector_unmask, | |
753 | ivshmem_vector_mask, | |
754 | ivshmem_vector_poll)) { | |
755 | error_report("ivshmem: msix_set_vector_notifiers failed"); | |
756 | } | |
757 | } | |
758 | ||
759 | static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector) | |
760 | { | |
761 | IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector); | |
762 | ||
763 | if (s->msi_vectors[vector].pdev == NULL) { | |
764 | return; | |
765 | } | |
766 | ||
767 | /* it was cleaned when masked in the frontend. */ | |
768 | kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq); | |
769 | ||
770 | s->msi_vectors[vector].pdev = NULL; | |
771 | } | |
772 | ||
773 | static void ivshmem_disable_irqfd(IVShmemState *s) | |
774 | { | |
775 | PCIDevice *pdev = PCI_DEVICE(s); | |
776 | int i; | |
777 | ||
778 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
779 | ivshmem_remove_kvm_msi_virq(s, i); | |
780 | } | |
781 | ||
782 | msix_unset_vector_notifiers(pdev); | |
783 | } | |
784 | ||
785 | static void ivshmem_write_config(PCIDevice *pdev, uint32_t address, | |
d58d7e84 | 786 | uint32_t val, int len) |
4490c711 | 787 | { |
660c97ee MAL |
788 | IVShmemState *s = IVSHMEM(pdev); |
789 | int is_enabled, was_enabled = msix_enabled(pdev); | |
790 | ||
791 | pci_default_write_config(pdev, address, val, len); | |
792 | is_enabled = msix_enabled(pdev); | |
793 | ||
794 | if (kvm_msi_via_irqfd_enabled() && s->vm_id != -1) { | |
795 | if (!was_enabled && is_enabled) { | |
796 | ivshmem_enable_irqfd(s); | |
797 | } else if (was_enabled && !is_enabled) { | |
798 | ivshmem_disable_irqfd(s); | |
799 | } | |
800 | } | |
4490c711 MT |
801 | } |
802 | ||
d58d7e84 | 803 | static void pci_ivshmem_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 804 | { |
eb3fedf3 | 805 | IVShmemState *s = IVSHMEM(dev); |
d855e275 | 806 | Error *err = NULL; |
6cbf4c8c | 807 | uint8_t *pci_conf; |
9113e3f3 MAL |
808 | uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY | |
809 | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
6cbf4c8c | 810 | |
d9453c93 | 811 | if (!!s->server_chr + !!s->shmobj + !!s->hostmem != 1) { |
1d649244 MA |
812 | error_setg(errp, |
813 | "You must specify either 'shm', 'chardev' or 'x-memdev'"); | |
d9453c93 MAL |
814 | return; |
815 | } | |
816 | ||
817 | if (s->hostmem) { | |
818 | MemoryRegion *mr; | |
819 | ||
820 | if (s->sizearg) { | |
821 | g_warning("size argument ignored with hostmem"); | |
822 | } | |
823 | ||
9cf70c52 | 824 | mr = host_memory_backend_get_memory(s->hostmem, &error_abort); |
d9453c93 MAL |
825 | s->ivshmem_size = memory_region_size(mr); |
826 | } else if (s->sizearg == NULL) { | |
6cbf4c8c | 827 | s->ivshmem_size = 4 << 20; /* 4 MB default */ |
d58d7e84 | 828 | } else { |
2c04752c MAL |
829 | char *end; |
830 | int64_t size = qemu_strtosz(s->sizearg, &end); | |
831 | if (size < 0 || *end != '\0' || !is_power_of_2(size)) { | |
832 | error_setg(errp, "Invalid size %s", s->sizearg); | |
d58d7e84 MAL |
833 | return; |
834 | } | |
2c04752c | 835 | s->ivshmem_size = size; |
6cbf4c8c CM |
836 | } |
837 | ||
6cbf4c8c CM |
838 | /* IRQFD requires MSI */ |
839 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
840 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
d58d7e84 MAL |
841 | error_setg(errp, "ioeventfd/irqfd requires MSI"); |
842 | return; | |
6cbf4c8c CM |
843 | } |
844 | ||
845 | /* check that role is reasonable */ | |
846 | if (s->role) { | |
847 | if (strncmp(s->role, "peer", 5) == 0) { | |
848 | s->role_val = IVSHMEM_PEER; | |
849 | } else if (strncmp(s->role, "master", 7) == 0) { | |
850 | s->role_val = IVSHMEM_MASTER; | |
851 | } else { | |
d58d7e84 MAL |
852 | error_setg(errp, "'role' must be 'peer' or 'master'"); |
853 | return; | |
6cbf4c8c CM |
854 | } |
855 | } else { | |
856 | s->role_val = IVSHMEM_MASTER; /* default */ | |
857 | } | |
858 | ||
b7578eaa | 859 | pci_conf = dev->config; |
6cbf4c8c | 860 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c | 861 | |
2d1d422d MA |
862 | /* |
863 | * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a | |
864 | * bald-faced lie then. But it's a backwards compatible lie. | |
865 | */ | |
6cbf4c8c CM |
866 | pci_config_set_interrupt_pin(pci_conf, 1); |
867 | ||
3c161542 | 868 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
869 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
870 | ||
6cbf4c8c | 871 | /* region for registers*/ |
b7578eaa | 872 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 873 | &s->ivshmem_mmio); |
cb06608e | 874 | |
3c161542 | 875 | memory_region_init(&s->bar, OBJECT(s), "ivshmem-bar2-container", s->ivshmem_size); |
c08ba66f | 876 | if (s->ivshmem_64bit) { |
9113e3f3 | 877 | attr |= PCI_BASE_ADDRESS_MEM_TYPE_64; |
c08ba66f | 878 | } |
6cbf4c8c | 879 | |
d9453c93 MAL |
880 | if (s->hostmem != NULL) { |
881 | MemoryRegion *mr; | |
882 | ||
883 | IVSHMEM_DPRINTF("using hostmem\n"); | |
884 | ||
9cf70c52 MA |
885 | mr = host_memory_backend_get_memory(MEMORY_BACKEND(s->hostmem), |
886 | &error_abort); | |
d9453c93 MAL |
887 | vmstate_register_ram(mr, DEVICE(s)); |
888 | memory_region_add_subregion(&s->bar, 0, mr); | |
889 | pci_register_bar(PCI_DEVICE(s), 2, attr, &s->bar); | |
890 | } else if (s->server_chr != NULL) { | |
2825717c | 891 | /* FIXME do not rely on what chr drivers put into filename */ |
36617792 MAL |
892 | if (strncmp(s->server_chr->filename, "unix:", 5)) { |
893 | error_setg(errp, "chardev is not a unix client socket"); | |
894 | return; | |
895 | } | |
896 | ||
6cbf4c8c CM |
897 | /* if we get a UNIX socket as the parameter we will talk |
898 | * to the ivshmem server to receive the memory region */ | |
899 | ||
6cbf4c8c | 900 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", |
dbc464d4 | 901 | s->server_chr->filename); |
6cbf4c8c | 902 | |
fd47bfe5 MAL |
903 | if (ivshmem_setup_interrupts(s) < 0) { |
904 | error_setg(errp, "failed to initialize interrupts"); | |
d58d7e84 | 905 | return; |
6cbf4c8c CM |
906 | } |
907 | ||
f456179f | 908 | /* we allocate enough space for 16 peers and grow as needed */ |
1300b273 | 909 | resize_peers(s, 16); |
6cbf4c8c CM |
910 | s->vm_id = -1; |
911 | ||
9113e3f3 | 912 | pci_register_bar(dev, 2, attr, &s->bar); |
6cbf4c8c | 913 | |
5105b1d8 | 914 | qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive, |
c20fc0c3 | 915 | ivshmem_check_version, NULL, s); |
6cbf4c8c CM |
916 | } else { |
917 | /* just map the file immediately, we're not using a server */ | |
918 | int fd; | |
919 | ||
6cbf4c8c CM |
920 | IVSHMEM_DPRINTF("using shm_open (shm object = %s)\n", s->shmobj); |
921 | ||
922 | /* try opening with O_EXCL and if it succeeds zero the memory | |
923 | * by truncating to 0 */ | |
924 | if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR|O_EXCL, | |
925 | S_IRWXU|S_IRWXG|S_IRWXO)) > 0) { | |
926 | /* truncate file to length PCI device's memory */ | |
927 | if (ftruncate(fd, s->ivshmem_size) != 0) { | |
dbc464d4 | 928 | error_report("could not truncate shared file"); |
6cbf4c8c CM |
929 | } |
930 | ||
931 | } else if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR, | |
932 | S_IRWXU|S_IRWXG|S_IRWXO)) < 0) { | |
d58d7e84 MAL |
933 | error_setg(errp, "could not open shared file"); |
934 | return; | |
6cbf4c8c CM |
935 | } |
936 | ||
d58d7e84 MAL |
937 | if (check_shm_size(s, fd, errp) == -1) { |
938 | return; | |
6cbf4c8c CM |
939 | } |
940 | ||
d855e275 MA |
941 | create_shared_memory_BAR(s, fd, attr, &err); |
942 | if (err) { | |
943 | error_propagate(errp, err); | |
944 | return; | |
945 | } | |
946 | } | |
947 | ||
948 | fifo8_create(&s->incoming_fifo, sizeof(int64_t)); | |
949 | ||
950 | if (s->role_val == IVSHMEM_PEER) { | |
951 | error_setg(&s->migration_blocker, | |
952 | "Migration is disabled when using feature 'peer mode' in device 'ivshmem'"); | |
953 | migrate_add_blocker(s->migration_blocker); | |
6cbf4c8c | 954 | } |
6cbf4c8c CM |
955 | } |
956 | ||
d58d7e84 | 957 | static void pci_ivshmem_exit(PCIDevice *dev) |
6cbf4c8c | 958 | { |
eb3fedf3 | 959 | IVShmemState *s = IVSHMEM(dev); |
f64a078d MAL |
960 | int i; |
961 | ||
962 | fifo8_destroy(&s->incoming_fifo); | |
6cbf4c8c | 963 | |
38e0735e AL |
964 | if (s->migration_blocker) { |
965 | migrate_del_blocker(s->migration_blocker); | |
966 | error_free(s->migration_blocker); | |
967 | } | |
968 | ||
f689d281 | 969 | if (memory_region_is_mapped(&s->ivshmem)) { |
d9453c93 MAL |
970 | if (!s->hostmem) { |
971 | void *addr = memory_region_get_ram_ptr(&s->ivshmem); | |
56a571d9 | 972 | int fd; |
d9453c93 MAL |
973 | |
974 | if (munmap(addr, s->ivshmem_size) == -1) { | |
975 | error_report("Failed to munmap shared memory %s", | |
976 | strerror(errno)); | |
977 | } | |
56a571d9 | 978 | |
8e41fb63 FZ |
979 | fd = qemu_get_ram_fd(memory_region_get_ram_addr(&s->ivshmem)); |
980 | if (fd != -1) { | |
56a571d9 | 981 | close(fd); |
8e41fb63 | 982 | } |
d9453c93 | 983 | } |
f64a078d MAL |
984 | |
985 | vmstate_unregister_ram(&s->ivshmem, DEVICE(dev)); | |
986 | memory_region_del_subregion(&s->bar, &s->ivshmem); | |
f64a078d MAL |
987 | } |
988 | ||
f64a078d MAL |
989 | if (s->peers) { |
990 | for (i = 0; i < s->nb_peers; i++) { | |
f456179f | 991 | close_peer_eventfds(s, i); |
f64a078d MAL |
992 | } |
993 | g_free(s->peers); | |
994 | } | |
995 | ||
996 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
997 | msix_uninit_exclusive_bar(dev); | |
998 | } | |
999 | ||
0f57350e | 1000 | g_free(s->msi_vectors); |
6cbf4c8c CM |
1001 | } |
1002 | ||
1f8552df MAL |
1003 | static bool test_msix(void *opaque, int version_id) |
1004 | { | |
1005 | IVShmemState *s = opaque; | |
1006 | ||
1007 | return ivshmem_has_feature(s, IVSHMEM_MSI); | |
1008 | } | |
1009 | ||
1010 | static bool test_no_msix(void *opaque, int version_id) | |
1011 | { | |
1012 | return !test_msix(opaque, version_id); | |
1013 | } | |
1014 | ||
1015 | static int ivshmem_pre_load(void *opaque) | |
1016 | { | |
1017 | IVShmemState *s = opaque; | |
1018 | ||
1019 | if (s->role_val == IVSHMEM_PEER) { | |
1020 | error_report("'peer' devices are not migratable"); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | static int ivshmem_post_load(void *opaque, int version_id) | |
1028 | { | |
1029 | IVShmemState *s = opaque; | |
1030 | ||
1031 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
082751e8 | 1032 | ivshmem_msix_vector_use(s); |
1f8552df | 1033 | } |
1f8552df MAL |
1034 | return 0; |
1035 | } | |
1036 | ||
1037 | static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id) | |
1038 | { | |
1039 | IVShmemState *s = opaque; | |
1040 | PCIDevice *pdev = PCI_DEVICE(s); | |
1041 | int ret; | |
1042 | ||
1043 | IVSHMEM_DPRINTF("ivshmem_load_old\n"); | |
1044 | ||
1045 | if (version_id != 0) { | |
1046 | return -EINVAL; | |
1047 | } | |
1048 | ||
1049 | if (s->role_val == IVSHMEM_PEER) { | |
1050 | error_report("'peer' devices are not migratable"); | |
1051 | return -EINVAL; | |
1052 | } | |
1053 | ||
1054 | ret = pci_device_load(pdev, f); | |
1055 | if (ret) { | |
1056 | return ret; | |
1057 | } | |
1058 | ||
1059 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
1060 | msix_load(pdev, f); | |
082751e8 | 1061 | ivshmem_msix_vector_use(s); |
1f8552df MAL |
1062 | } else { |
1063 | s->intrstatus = qemu_get_be32(f); | |
1064 | s->intrmask = qemu_get_be32(f); | |
1065 | } | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static const VMStateDescription ivshmem_vmsd = { | |
1071 | .name = "ivshmem", | |
1072 | .version_id = 1, | |
1073 | .minimum_version_id = 1, | |
1074 | .pre_load = ivshmem_pre_load, | |
1075 | .post_load = ivshmem_post_load, | |
1076 | .fields = (VMStateField[]) { | |
1077 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1078 | ||
1079 | VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix), | |
1080 | VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix), | |
1081 | VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix), | |
1082 | ||
1083 | VMSTATE_END_OF_LIST() | |
1084 | }, | |
1085 | .load_state_old = ivshmem_load_old, | |
1086 | .minimum_version_id_old = 0 | |
1087 | }; | |
1088 | ||
40021f08 AL |
1089 | static Property ivshmem_properties[] = { |
1090 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1091 | DEFINE_PROP_STRING("size", IVShmemState, sizearg), | |
1092 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1093 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, false), | |
1094 | DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true), | |
1095 | DEFINE_PROP_STRING("shm", IVShmemState, shmobj), | |
1096 | DEFINE_PROP_STRING("role", IVShmemState, role), | |
c08ba66f | 1097 | DEFINE_PROP_UINT32("use64", IVShmemState, ivshmem_64bit, 1), |
40021f08 AL |
1098 | DEFINE_PROP_END_OF_LIST(), |
1099 | }; | |
1100 | ||
1101 | static void ivshmem_class_init(ObjectClass *klass, void *data) | |
1102 | { | |
39bffca2 | 1103 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1104 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1105 | ||
d58d7e84 MAL |
1106 | k->realize = pci_ivshmem_realize; |
1107 | k->exit = pci_ivshmem_exit; | |
1108 | k->config_write = ivshmem_write_config; | |
b8ef62a9 PB |
1109 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
1110 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 1111 | k->class_id = PCI_CLASS_MEMORY_RAM; |
39bffca2 AL |
1112 | dc->reset = ivshmem_reset; |
1113 | dc->props = ivshmem_properties; | |
1f8552df | 1114 | dc->vmsd = &ivshmem_vmsd; |
125ee0ed | 1115 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
d383537d | 1116 | dc->desc = "Inter-VM shared memory"; |
40021f08 AL |
1117 | } |
1118 | ||
d9453c93 MAL |
1119 | static void ivshmem_check_memdev_is_busy(Object *obj, const char *name, |
1120 | Object *val, Error **errp) | |
1121 | { | |
1122 | MemoryRegion *mr; | |
1123 | ||
9cf70c52 | 1124 | mr = host_memory_backend_get_memory(MEMORY_BACKEND(val), &error_abort); |
d9453c93 MAL |
1125 | if (memory_region_is_mapped(mr)) { |
1126 | char *path = object_get_canonical_path_component(val); | |
1127 | error_setg(errp, "can't use already busy memdev: %s", path); | |
1128 | g_free(path); | |
1129 | } else { | |
1130 | qdev_prop_allow_set_link_before_realize(obj, name, val, errp); | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | static void ivshmem_init(Object *obj) | |
1135 | { | |
1136 | IVShmemState *s = IVSHMEM(obj); | |
1137 | ||
1d649244 | 1138 | object_property_add_link(obj, "x-memdev", TYPE_MEMORY_BACKEND, |
d9453c93 MAL |
1139 | (Object **)&s->hostmem, |
1140 | ivshmem_check_memdev_is_busy, | |
1141 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
1142 | &error_abort); | |
1143 | } | |
1144 | ||
8c43a6f0 | 1145 | static const TypeInfo ivshmem_info = { |
eb3fedf3 | 1146 | .name = TYPE_IVSHMEM, |
39bffca2 AL |
1147 | .parent = TYPE_PCI_DEVICE, |
1148 | .instance_size = sizeof(IVShmemState), | |
d9453c93 | 1149 | .instance_init = ivshmem_init, |
39bffca2 | 1150 | .class_init = ivshmem_class_init, |
6cbf4c8c CM |
1151 | }; |
1152 | ||
83f7d43a | 1153 | static void ivshmem_register_types(void) |
6cbf4c8c | 1154 | { |
39bffca2 | 1155 | type_register_static(&ivshmem_info); |
6cbf4c8c CM |
1156 | } |
1157 | ||
83f7d43a | 1158 | type_init(ivshmem_register_types) |