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Commit | Line | Data |
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267002cd | 1 | /* |
3cbee15b | 2 | * QEMU PowerMac CUDA device support |
5fafdf24 | 3 | * |
3cbee15b JM |
4 | * Copyright (c) 2004-2007 Fabrice Bellard |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
5fafdf24 | 6 | * |
267002cd FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0d75590d | 25 | #include "qemu/osdep.h" |
83c9f4ca PB |
26 | #include "hw/hw.h" |
27 | #include "hw/ppc/mac.h" | |
0d09e41a | 28 | #include "hw/input/adb.h" |
1de7afc9 | 29 | #include "qemu/timer.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
f348b6d1 | 31 | #include "qemu/cutils.h" |
03dd024f | 32 | #include "qemu/log.h" |
267002cd | 33 | |
61271e5c FB |
34 | /* XXX: implement all timer modes */ |
35 | ||
ea026b2f | 36 | /* debug CUDA */ |
819e712b | 37 | //#define DEBUG_CUDA |
ea026b2f BS |
38 | |
39 | /* debug CUDA packets */ | |
819e712b FB |
40 | //#define DEBUG_CUDA_PACKET |
41 | ||
ea026b2f | 42 | #ifdef DEBUG_CUDA |
001faf32 BS |
43 | #define CUDA_DPRINTF(fmt, ...) \ |
44 | do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0) | |
ea026b2f | 45 | #else |
001faf32 | 46 | #define CUDA_DPRINTF(fmt, ...) |
ea026b2f BS |
47 | #endif |
48 | ||
267002cd FB |
49 | /* Bits in B data register: all active low */ |
50 | #define TREQ 0x08 /* Transfer request (input) */ | |
51 | #define TACK 0x10 /* Transfer acknowledge (output) */ | |
52 | #define TIP 0x20 /* Transfer in progress (output) */ | |
53 | ||
54 | /* Bits in ACR */ | |
55 | #define SR_CTRL 0x1c /* Shift register control bits */ | |
56 | #define SR_EXT 0x0c /* Shift on external clock */ | |
57 | #define SR_OUT 0x10 /* Shift out if 1 */ | |
58 | ||
59 | /* Bits in IFR and IER */ | |
60 | #define IER_SET 0x80 /* set bits in IER */ | |
61 | #define IER_CLR 0 /* clear bits in IER */ | |
62 | #define SR_INT 0x04 /* Shift register full/empty */ | |
d271ae36 MCA |
63 | #define SR_DATA_INT 0x08 |
64 | #define SR_CLOCK_INT 0x10 | |
267002cd | 65 | #define T1_INT 0x40 /* Timer 1 interrupt */ |
61271e5c | 66 | #define T2_INT 0x20 /* Timer 2 interrupt */ |
267002cd FB |
67 | |
68 | /* Bits in ACR */ | |
69 | #define T1MODE 0xc0 /* Timer 1 mode */ | |
70 | #define T1MODE_CONT 0x40 /* continuous interrupts */ | |
71 | ||
72 | /* commands (1st byte) */ | |
73 | #define ADB_PACKET 0 | |
74 | #define CUDA_PACKET 1 | |
75 | #define ERROR_PACKET 2 | |
76 | #define TIMER_PACKET 3 | |
77 | #define POWER_PACKET 4 | |
78 | #define MACIIC_PACKET 5 | |
79 | #define PMU_PACKET 6 | |
80 | ||
81 | ||
82 | /* CUDA commands (2nd byte) */ | |
83 | #define CUDA_WARM_START 0x0 | |
84 | #define CUDA_AUTOPOLL 0x1 | |
85 | #define CUDA_GET_6805_ADDR 0x2 | |
86 | #define CUDA_GET_TIME 0x3 | |
87 | #define CUDA_GET_PRAM 0x7 | |
88 | #define CUDA_SET_6805_ADDR 0x8 | |
89 | #define CUDA_SET_TIME 0x9 | |
90 | #define CUDA_POWERDOWN 0xa | |
91 | #define CUDA_POWERUP_TIME 0xb | |
92 | #define CUDA_SET_PRAM 0xc | |
93 | #define CUDA_MS_RESET 0xd | |
94 | #define CUDA_SEND_DFAC 0xe | |
95 | #define CUDA_BATTERY_SWAP_SENSE 0x10 | |
96 | #define CUDA_RESET_SYSTEM 0x11 | |
97 | #define CUDA_SET_IPL 0x12 | |
98 | #define CUDA_FILE_SERVER_FLAG 0x13 | |
99 | #define CUDA_SET_AUTO_RATE 0x14 | |
100 | #define CUDA_GET_AUTO_RATE 0x16 | |
101 | #define CUDA_SET_DEVICE_LIST 0x19 | |
102 | #define CUDA_GET_DEVICE_LIST 0x1a | |
103 | #define CUDA_SET_ONE_SECOND_MODE 0x1b | |
104 | #define CUDA_SET_POWER_MESSAGES 0x21 | |
105 | #define CUDA_GET_SET_IIC 0x22 | |
106 | #define CUDA_WAKEUP 0x23 | |
107 | #define CUDA_TIMER_TICKLE 0x24 | |
108 | #define CUDA_COMBINED_FORMAT_IIC 0x25 | |
109 | ||
110 | #define CUDA_TIMER_FREQ (4700000 / 6) | |
111 | ||
d7ce296f FB |
112 | /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ |
113 | #define RTC_OFFSET 2082844800 | |
114 | ||
b5ac0410 MCA |
115 | /* CUDA registers */ |
116 | #define CUDA_REG_B 0x00 | |
117 | #define CUDA_REG_A 0x01 | |
118 | #define CUDA_REG_DIRB 0x02 | |
119 | #define CUDA_REG_DIRA 0x03 | |
120 | #define CUDA_REG_T1CL 0x04 | |
121 | #define CUDA_REG_T1CH 0x05 | |
122 | #define CUDA_REG_T1LL 0x06 | |
123 | #define CUDA_REG_T1LH 0x07 | |
124 | #define CUDA_REG_T2CL 0x08 | |
125 | #define CUDA_REG_T2CH 0x09 | |
126 | #define CUDA_REG_SR 0x0a | |
127 | #define CUDA_REG_ACR 0x0b | |
128 | #define CUDA_REG_PCR 0x0c | |
129 | #define CUDA_REG_IFR 0x0d | |
130 | #define CUDA_REG_IER 0x0e | |
131 | #define CUDA_REG_ANH 0x0f | |
132 | ||
267002cd | 133 | static void cuda_update(CUDAState *s); |
5fafdf24 | 134 | static void cuda_receive_packet_from_host(CUDAState *s, |
267002cd | 135 | const uint8_t *data, int len); |
5fafdf24 | 136 | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
819e712b | 137 | int64_t current_time); |
267002cd FB |
138 | |
139 | static void cuda_update_irq(CUDAState *s) | |
140 | { | |
a53cfdcc | 141 | if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) { |
d537cf6c | 142 | qemu_irq_raise(s->irq); |
267002cd | 143 | } else { |
d537cf6c | 144 | qemu_irq_lower(s->irq); |
267002cd FB |
145 | } |
146 | } | |
147 | ||
eda14abb | 148 | static uint64_t get_tb(uint64_t time, uint64_t freq) |
b981289c | 149 | { |
73bcb24d | 150 | return muldiv64(time, freq, NANOSECONDS_PER_SECOND); |
b981289c AG |
151 | } |
152 | ||
0174adb6 | 153 | static unsigned int get_counter(CUDATimer *ti) |
267002cd FB |
154 | { |
155 | int64_t d; | |
156 | unsigned int counter; | |
b981289c | 157 | uint64_t tb_diff; |
eda14abb | 158 | uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
b981289c AG |
159 | |
160 | /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */ | |
0174adb6 MCA |
161 | tb_diff = get_tb(current_time, ti->frequency) - ti->load_time; |
162 | d = (tb_diff * 0xBF401675E5DULL) / (ti->frequency << 24); | |
267002cd | 163 | |
0174adb6 | 164 | if (ti->index == 0) { |
61271e5c | 165 | /* the timer goes down from latch to -1 (period of latch + 2) */ |
0174adb6 MCA |
166 | if (d <= (ti->counter_value + 1)) { |
167 | counter = (ti->counter_value - d) & 0xffff; | |
61271e5c | 168 | } else { |
0174adb6 MCA |
169 | counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); |
170 | counter = (ti->latch - counter) & 0xffff; | |
61271e5c | 171 | } |
267002cd | 172 | } else { |
0174adb6 | 173 | counter = (ti->counter_value - d) & 0xffff; |
267002cd FB |
174 | } |
175 | return counter; | |
176 | } | |
177 | ||
819e712b | 178 | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
267002cd | 179 | { |
a53cfdcc | 180 | CUDA_DPRINTF("T%d.counter=%d\n", 1 + ti->index, val); |
eda14abb MCA |
181 | ti->load_time = get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
182 | s->frequency); | |
819e712b FB |
183 | ti->counter_value = val; |
184 | cuda_timer_update(s, ti, ti->load_time); | |
267002cd FB |
185 | } |
186 | ||
187 | static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) | |
188 | { | |
61271e5c FB |
189 | int64_t d, next_time; |
190 | unsigned int counter; | |
191 | ||
267002cd | 192 | /* current counter value */ |
5fafdf24 | 193 | d = muldiv64(current_time - s->load_time, |
73bcb24d | 194 | CUDA_TIMER_FREQ, NANOSECONDS_PER_SECOND); |
61271e5c FB |
195 | /* the timer goes down from latch to -1 (period of latch + 2) */ |
196 | if (d <= (s->counter_value + 1)) { | |
197 | counter = (s->counter_value - d) & 0xffff; | |
198 | } else { | |
199 | counter = (d - (s->counter_value + 1)) % (s->latch + 2); | |
5fafdf24 | 200 | counter = (s->latch - counter) & 0xffff; |
61271e5c | 201 | } |
3b46e624 | 202 | |
61271e5c FB |
203 | /* Note: we consider the irq is raised on 0 */ |
204 | if (counter == 0xffff) { | |
205 | next_time = d + s->latch + 1; | |
206 | } else if (counter == 0) { | |
207 | next_time = d + s->latch + 2; | |
208 | } else { | |
209 | next_time = d + counter; | |
267002cd | 210 | } |
ea026b2f BS |
211 | CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", |
212 | s->latch, d, next_time - d); | |
73bcb24d | 213 | next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, CUDA_TIMER_FREQ) + |
267002cd FB |
214 | s->load_time; |
215 | if (next_time <= current_time) | |
216 | next_time = current_time + 1; | |
217 | return next_time; | |
218 | } | |
219 | ||
5fafdf24 | 220 | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
819e712b FB |
221 | int64_t current_time) |
222 | { | |
223 | if (!ti->timer) | |
224 | return; | |
a53cfdcc | 225 | if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) { |
bc72ad67 | 226 | timer_del(ti->timer); |
819e712b FB |
227 | } else { |
228 | ti->next_irq_time = get_next_irq_time(ti, current_time); | |
bc72ad67 | 229 | timer_mod(ti->timer, ti->next_irq_time); |
819e712b FB |
230 | } |
231 | } | |
232 | ||
267002cd FB |
233 | static void cuda_timer1(void *opaque) |
234 | { | |
235 | CUDAState *s = opaque; | |
236 | CUDATimer *ti = &s->timers[0]; | |
237 | ||
819e712b | 238 | cuda_timer_update(s, ti, ti->next_irq_time); |
267002cd FB |
239 | s->ifr |= T1_INT; |
240 | cuda_update_irq(s); | |
241 | } | |
242 | ||
a53cfdcc MCA |
243 | static void cuda_timer2(void *opaque) |
244 | { | |
245 | CUDAState *s = opaque; | |
246 | CUDATimer *ti = &s->timers[1]; | |
247 | ||
248 | cuda_timer_update(s, ti, ti->next_irq_time); | |
249 | s->ifr |= T2_INT; | |
250 | cuda_update_irq(s); | |
251 | } | |
252 | ||
cffc331a MCA |
253 | static void cuda_set_sr_int(void *opaque) |
254 | { | |
255 | CUDAState *s = opaque; | |
256 | ||
257 | CUDA_DPRINTF("CUDA: %s:%d\n", __func__, __LINE__); | |
258 | s->ifr |= SR_INT; | |
259 | cuda_update_irq(s); | |
260 | } | |
261 | ||
262 | static void cuda_delay_set_sr_int(CUDAState *s) | |
263 | { | |
264 | int64_t expire; | |
265 | ||
266 | if (s->dirb == 0xff) { | |
267 | /* Not in Mac OS, fire the IRQ directly */ | |
268 | cuda_set_sr_int(s); | |
269 | return; | |
270 | } | |
271 | ||
272 | CUDA_DPRINTF("CUDA: %s:%d\n", __func__, __LINE__); | |
273 | ||
274 | expire = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 300 * SCALE_US; | |
275 | timer_mod(s->sr_delay_timer, expire); | |
276 | } | |
277 | ||
a8170e5e | 278 | static uint32_t cuda_readb(void *opaque, hwaddr addr) |
267002cd FB |
279 | { |
280 | CUDAState *s = opaque; | |
281 | uint32_t val; | |
282 | ||
283 | addr = (addr >> 9) & 0xf; | |
284 | switch(addr) { | |
b5ac0410 | 285 | case CUDA_REG_B: |
267002cd FB |
286 | val = s->b; |
287 | break; | |
b5ac0410 | 288 | case CUDA_REG_A: |
267002cd FB |
289 | val = s->a; |
290 | break; | |
b5ac0410 | 291 | case CUDA_REG_DIRB: |
267002cd FB |
292 | val = s->dirb; |
293 | break; | |
b5ac0410 | 294 | case CUDA_REG_DIRA: |
267002cd FB |
295 | val = s->dira; |
296 | break; | |
b5ac0410 | 297 | case CUDA_REG_T1CL: |
267002cd FB |
298 | val = get_counter(&s->timers[0]) & 0xff; |
299 | s->ifr &= ~T1_INT; | |
300 | cuda_update_irq(s); | |
301 | break; | |
b5ac0410 | 302 | case CUDA_REG_T1CH: |
267002cd | 303 | val = get_counter(&s->timers[0]) >> 8; |
267002cd FB |
304 | cuda_update_irq(s); |
305 | break; | |
b5ac0410 | 306 | case CUDA_REG_T1LL: |
267002cd FB |
307 | val = s->timers[0].latch & 0xff; |
308 | break; | |
b5ac0410 | 309 | case CUDA_REG_T1LH: |
61271e5c | 310 | /* XXX: check this */ |
267002cd FB |
311 | val = (s->timers[0].latch >> 8) & 0xff; |
312 | break; | |
b5ac0410 | 313 | case CUDA_REG_T2CL: |
267002cd | 314 | val = get_counter(&s->timers[1]) & 0xff; |
61271e5c | 315 | s->ifr &= ~T2_INT; |
a53cfdcc | 316 | cuda_update_irq(s); |
267002cd | 317 | break; |
b5ac0410 | 318 | case CUDA_REG_T2CH: |
267002cd FB |
319 | val = get_counter(&s->timers[1]) >> 8; |
320 | break; | |
b5ac0410 | 321 | case CUDA_REG_SR: |
819e712b | 322 | val = s->sr; |
d271ae36 | 323 | s->ifr &= ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT); |
819e712b | 324 | cuda_update_irq(s); |
267002cd | 325 | break; |
b5ac0410 | 326 | case CUDA_REG_ACR: |
267002cd FB |
327 | val = s->acr; |
328 | break; | |
b5ac0410 | 329 | case CUDA_REG_PCR: |
267002cd FB |
330 | val = s->pcr; |
331 | break; | |
b5ac0410 | 332 | case CUDA_REG_IFR: |
267002cd | 333 | val = s->ifr; |
b5ac0410 | 334 | if (s->ifr & s->ier) { |
b7c7b181 | 335 | val |= 0x80; |
b5ac0410 | 336 | } |
267002cd | 337 | break; |
b5ac0410 | 338 | case CUDA_REG_IER: |
b7c7b181 | 339 | val = s->ier | 0x80; |
267002cd FB |
340 | break; |
341 | default: | |
b5ac0410 | 342 | case CUDA_REG_ANH: |
267002cd FB |
343 | val = s->anh; |
344 | break; | |
345 | } | |
b5ac0410 | 346 | if (addr != CUDA_REG_IFR || val != 0) { |
ea026b2f | 347 | CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val); |
3c83eb4f BS |
348 | } |
349 | ||
267002cd FB |
350 | return val; |
351 | } | |
352 | ||
a8170e5e | 353 | static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val) |
267002cd FB |
354 | { |
355 | CUDAState *s = opaque; | |
3b46e624 | 356 | |
267002cd | 357 | addr = (addr >> 9) & 0xf; |
ea026b2f | 358 | CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val); |
267002cd FB |
359 | |
360 | switch(addr) { | |
b5ac0410 | 361 | case CUDA_REG_B: |
267002cd FB |
362 | s->b = val; |
363 | cuda_update(s); | |
364 | break; | |
b5ac0410 | 365 | case CUDA_REG_A: |
267002cd FB |
366 | s->a = val; |
367 | break; | |
b5ac0410 | 368 | case CUDA_REG_DIRB: |
267002cd FB |
369 | s->dirb = val; |
370 | break; | |
b5ac0410 | 371 | case CUDA_REG_DIRA: |
267002cd FB |
372 | s->dira = val; |
373 | break; | |
b5ac0410 | 374 | case CUDA_REG_T1CL: |
61271e5c | 375 | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
bc72ad67 | 376 | cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
267002cd | 377 | break; |
b5ac0410 | 378 | case CUDA_REG_T1CH: |
61271e5c FB |
379 | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
380 | s->ifr &= ~T1_INT; | |
381 | set_counter(s, &s->timers[0], s->timers[0].latch); | |
267002cd | 382 | break; |
b5ac0410 | 383 | case CUDA_REG_T1LL: |
267002cd | 384 | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
bc72ad67 | 385 | cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
267002cd | 386 | break; |
b5ac0410 | 387 | case CUDA_REG_T1LH: |
267002cd | 388 | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
61271e5c | 389 | s->ifr &= ~T1_INT; |
bc72ad67 | 390 | cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
267002cd | 391 | break; |
b5ac0410 | 392 | case CUDA_REG_T2CL: |
a53cfdcc | 393 | s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; |
267002cd | 394 | break; |
b5ac0410 | 395 | case CUDA_REG_T2CH: |
a53cfdcc MCA |
396 | /* To ensure T2 generates an interrupt on zero crossing with the |
397 | common timer code, write the value directly from the latch to | |
398 | the counter */ | |
399 | s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); | |
400 | s->ifr &= ~T2_INT; | |
401 | set_counter(s, &s->timers[1], s->timers[1].latch); | |
267002cd | 402 | break; |
b5ac0410 | 403 | case CUDA_REG_SR: |
267002cd FB |
404 | s->sr = val; |
405 | break; | |
b5ac0410 | 406 | case CUDA_REG_ACR: |
267002cd | 407 | s->acr = val; |
bc72ad67 | 408 | cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
267002cd FB |
409 | cuda_update(s); |
410 | break; | |
b5ac0410 | 411 | case CUDA_REG_PCR: |
267002cd FB |
412 | s->pcr = val; |
413 | break; | |
b5ac0410 | 414 | case CUDA_REG_IFR: |
267002cd FB |
415 | /* reset bits */ |
416 | s->ifr &= ~val; | |
417 | cuda_update_irq(s); | |
418 | break; | |
b5ac0410 | 419 | case CUDA_REG_IER: |
267002cd FB |
420 | if (val & IER_SET) { |
421 | /* set bits */ | |
422 | s->ier |= val & 0x7f; | |
423 | } else { | |
424 | /* reset bits */ | |
425 | s->ier &= ~val; | |
426 | } | |
427 | cuda_update_irq(s); | |
428 | break; | |
429 | default: | |
b5ac0410 | 430 | case CUDA_REG_ANH: |
267002cd FB |
431 | s->anh = val; |
432 | break; | |
433 | } | |
434 | } | |
435 | ||
436 | /* NOTE: TIP and TREQ are negated */ | |
437 | static void cuda_update(CUDAState *s) | |
438 | { | |
819e712b FB |
439 | int packet_received, len; |
440 | ||
441 | packet_received = 0; | |
442 | if (!(s->b & TIP)) { | |
443 | /* transfer requested from host */ | |
267002cd | 444 | |
819e712b FB |
445 | if (s->acr & SR_OUT) { |
446 | /* data output */ | |
447 | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { | |
448 | if (s->data_out_index < sizeof(s->data_out)) { | |
ea026b2f | 449 | CUDA_DPRINTF("send: %02x\n", s->sr); |
819e712b | 450 | s->data_out[s->data_out_index++] = s->sr; |
cffc331a | 451 | cuda_delay_set_sr_int(s); |
819e712b FB |
452 | } |
453 | } | |
454 | } else { | |
455 | if (s->data_in_index < s->data_in_size) { | |
456 | /* data input */ | |
457 | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { | |
458 | s->sr = s->data_in[s->data_in_index++]; | |
ea026b2f | 459 | CUDA_DPRINTF("recv: %02x\n", s->sr); |
819e712b FB |
460 | /* indicate end of transfer */ |
461 | if (s->data_in_index >= s->data_in_size) { | |
462 | s->b = (s->b | TREQ); | |
463 | } | |
cffc331a | 464 | cuda_delay_set_sr_int(s); |
819e712b | 465 | } |
267002cd | 466 | } |
819e712b FB |
467 | } |
468 | } else { | |
469 | /* no transfer requested: handle sync case */ | |
470 | if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) { | |
471 | /* update TREQ state each time TACK change state */ | |
472 | if (s->b & TACK) | |
473 | s->b = (s->b | TREQ); | |
474 | else | |
475 | s->b = (s->b & ~TREQ); | |
cffc331a | 476 | cuda_delay_set_sr_int(s); |
819e712b FB |
477 | } else { |
478 | if (!(s->last_b & TIP)) { | |
e91c8a77 | 479 | /* handle end of host to cuda transfer */ |
819e712b | 480 | packet_received = (s->data_out_index > 0); |
e91c8a77 | 481 | /* always an IRQ at the end of transfer */ |
cffc331a | 482 | cuda_delay_set_sr_int(s); |
819e712b FB |
483 | } |
484 | /* signal if there is data to read */ | |
485 | if (s->data_in_index < s->data_in_size) { | |
486 | s->b = (s->b & ~TREQ); | |
487 | } | |
267002cd FB |
488 | } |
489 | } | |
490 | ||
267002cd FB |
491 | s->last_acr = s->acr; |
492 | s->last_b = s->b; | |
819e712b FB |
493 | |
494 | /* NOTE: cuda_receive_packet_from_host() can call cuda_update() | |
495 | recursively */ | |
496 | if (packet_received) { | |
497 | len = s->data_out_index; | |
498 | s->data_out_index = 0; | |
499 | cuda_receive_packet_from_host(s, s->data_out, len); | |
500 | } | |
267002cd FB |
501 | } |
502 | ||
5fafdf24 | 503 | static void cuda_send_packet_to_host(CUDAState *s, |
267002cd FB |
504 | const uint8_t *data, int len) |
505 | { | |
819e712b FB |
506 | #ifdef DEBUG_CUDA_PACKET |
507 | { | |
508 | int i; | |
509 | printf("cuda_send_packet_to_host:\n"); | |
510 | for(i = 0; i < len; i++) | |
511 | printf(" %02x", data[i]); | |
512 | printf("\n"); | |
513 | } | |
514 | #endif | |
267002cd FB |
515 | memcpy(s->data_in, data, len); |
516 | s->data_in_size = len; | |
517 | s->data_in_index = 0; | |
518 | cuda_update(s); | |
cffc331a | 519 | cuda_delay_set_sr_int(s); |
267002cd FB |
520 | } |
521 | ||
7db4eea6 | 522 | static void cuda_adb_poll(void *opaque) |
e2733d20 FB |
523 | { |
524 | CUDAState *s = opaque; | |
525 | uint8_t obuf[ADB_MAX_OUT_LEN + 2]; | |
526 | int olen; | |
527 | ||
216c906e | 528 | olen = adb_poll(&s->adb_bus, obuf + 2, s->adb_poll_mask); |
e2733d20 FB |
529 | if (olen > 0) { |
530 | obuf[0] = ADB_PACKET; | |
531 | obuf[1] = 0x40; /* polled data */ | |
532 | cuda_send_packet_to_host(s, obuf, olen + 2); | |
533 | } | |
bc72ad67 AB |
534 | timer_mod(s->adb_poll_timer, |
535 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
73bcb24d | 536 | (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); |
e2733d20 FB |
537 | } |
538 | ||
d20efaeb HP |
539 | /* description of commands */ |
540 | typedef struct CudaCommand { | |
541 | uint8_t command; | |
542 | const char *name; | |
543 | bool (*handler)(CUDAState *s, | |
544 | const uint8_t *in_args, int in_len, | |
545 | uint8_t *out_args, int *out_len); | |
546 | } CudaCommand; | |
547 | ||
1cdab104 HP |
548 | static bool cuda_cmd_autopoll(CUDAState *s, |
549 | const uint8_t *in_data, int in_len, | |
550 | uint8_t *out_data, int *out_len) | |
551 | { | |
552 | int autopoll; | |
553 | ||
554 | if (in_len != 1) { | |
555 | return false; | |
556 | } | |
557 | ||
558 | autopoll = (in_data[0] != 0); | |
559 | if (autopoll != s->autopoll) { | |
560 | s->autopoll = autopoll; | |
561 | if (autopoll) { | |
562 | timer_mod(s->adb_poll_timer, | |
563 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
73bcb24d | 564 | (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); |
1cdab104 HP |
565 | } else { |
566 | timer_del(s->adb_poll_timer); | |
567 | } | |
568 | } | |
569 | return true; | |
570 | } | |
571 | ||
374312e7 HP |
572 | static bool cuda_cmd_set_autorate(CUDAState *s, |
573 | const uint8_t *in_data, int in_len, | |
574 | uint8_t *out_data, int *out_len) | |
575 | { | |
576 | if (in_len != 1) { | |
577 | return false; | |
578 | } | |
579 | ||
580 | /* we don't want a period of 0 ms */ | |
581 | /* FIXME: check what real hardware does */ | |
582 | if (in_data[0] == 0) { | |
583 | return false; | |
584 | } | |
585 | ||
586 | s->autopoll_rate_ms = in_data[0]; | |
587 | if (s->autopoll) { | |
588 | timer_mod(s->adb_poll_timer, | |
589 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
73bcb24d | 590 | (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); |
374312e7 HP |
591 | } |
592 | return true; | |
593 | } | |
594 | ||
216c906e HP |
595 | static bool cuda_cmd_set_device_list(CUDAState *s, |
596 | const uint8_t *in_data, int in_len, | |
597 | uint8_t *out_data, int *out_len) | |
598 | { | |
599 | if (in_len != 2) { | |
600 | return false; | |
601 | } | |
602 | ||
603 | s->adb_poll_mask = (((uint16_t)in_data[0]) << 8) | in_data[1]; | |
604 | return true; | |
605 | } | |
606 | ||
017da0b5 HP |
607 | static bool cuda_cmd_powerdown(CUDAState *s, |
608 | const uint8_t *in_data, int in_len, | |
609 | uint8_t *out_data, int *out_len) | |
610 | { | |
611 | if (in_len != 0) { | |
612 | return false; | |
613 | } | |
614 | ||
cf83f140 | 615 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
017da0b5 HP |
616 | return true; |
617 | } | |
618 | ||
54e89444 HP |
619 | static bool cuda_cmd_reset_system(CUDAState *s, |
620 | const uint8_t *in_data, int in_len, | |
621 | uint8_t *out_data, int *out_len) | |
622 | { | |
623 | if (in_len != 0) { | |
624 | return false; | |
625 | } | |
626 | ||
cf83f140 | 627 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
54e89444 HP |
628 | return true; |
629 | } | |
630 | ||
f5b94112 HP |
631 | static bool cuda_cmd_set_file_server_flag(CUDAState *s, |
632 | const uint8_t *in_data, int in_len, | |
633 | uint8_t *out_data, int *out_len) | |
634 | { | |
635 | if (in_len != 1) { | |
636 | return false; | |
637 | } | |
638 | ||
639 | qemu_log_mask(LOG_UNIMP, | |
640 | "CUDA: unimplemented command FILE_SERVER_FLAG %d\n", | |
641 | in_data[0]); | |
642 | return true; | |
643 | } | |
644 | ||
15b7b09b HP |
645 | static bool cuda_cmd_set_power_message(CUDAState *s, |
646 | const uint8_t *in_data, int in_len, | |
647 | uint8_t *out_data, int *out_len) | |
648 | { | |
649 | if (in_len != 1) { | |
650 | return false; | |
651 | } | |
652 | ||
653 | qemu_log_mask(LOG_UNIMP, | |
654 | "CUDA: unimplemented command SET_POWER_MESSAGE %d\n", | |
655 | in_data[0]); | |
656 | return true; | |
657 | } | |
658 | ||
547a4d19 HP |
659 | static bool cuda_cmd_get_time(CUDAState *s, |
660 | const uint8_t *in_data, int in_len, | |
661 | uint8_t *out_data, int *out_len) | |
662 | { | |
663 | uint32_t ti; | |
664 | ||
665 | if (in_len != 0) { | |
666 | return false; | |
667 | } | |
668 | ||
669 | ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) | |
73bcb24d | 670 | / NANOSECONDS_PER_SECOND); |
547a4d19 HP |
671 | out_data[0] = ti >> 24; |
672 | out_data[1] = ti >> 16; | |
673 | out_data[2] = ti >> 8; | |
674 | out_data[3] = ti; | |
675 | *out_len = 4; | |
676 | return true; | |
677 | } | |
678 | ||
e6473178 HP |
679 | static bool cuda_cmd_set_time(CUDAState *s, |
680 | const uint8_t *in_data, int in_len, | |
681 | uint8_t *out_data, int *out_len) | |
682 | { | |
683 | uint32_t ti; | |
684 | ||
685 | if (in_len != 4) { | |
686 | return false; | |
687 | } | |
688 | ||
ed3d807b AJ |
689 | ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16) |
690 | + (((uint32_t)in_data[2]) << 8) + in_data[3]; | |
e6473178 | 691 | s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) |
73bcb24d | 692 | / NANOSECONDS_PER_SECOND); |
e6473178 HP |
693 | return true; |
694 | } | |
695 | ||
d20efaeb | 696 | static const CudaCommand handlers[] = { |
1cdab104 | 697 | { CUDA_AUTOPOLL, "AUTOPOLL", cuda_cmd_autopoll }, |
374312e7 | 698 | { CUDA_SET_AUTO_RATE, "SET_AUTO_RATE", cuda_cmd_set_autorate }, |
216c906e | 699 | { CUDA_SET_DEVICE_LIST, "SET_DEVICE_LIST", cuda_cmd_set_device_list }, |
017da0b5 | 700 | { CUDA_POWERDOWN, "POWERDOWN", cuda_cmd_powerdown }, |
54e89444 | 701 | { CUDA_RESET_SYSTEM, "RESET_SYSTEM", cuda_cmd_reset_system }, |
f5b94112 HP |
702 | { CUDA_FILE_SERVER_FLAG, "FILE_SERVER_FLAG", |
703 | cuda_cmd_set_file_server_flag }, | |
15b7b09b HP |
704 | { CUDA_SET_POWER_MESSAGES, "SET_POWER_MESSAGES", |
705 | cuda_cmd_set_power_message }, | |
547a4d19 | 706 | { CUDA_GET_TIME, "GET_TIME", cuda_cmd_get_time }, |
e6473178 | 707 | { CUDA_SET_TIME, "SET_TIME", cuda_cmd_set_time }, |
d20efaeb HP |
708 | }; |
709 | ||
5fafdf24 | 710 | static void cuda_receive_packet(CUDAState *s, |
267002cd FB |
711 | const uint8_t *data, int len) |
712 | { | |
4202e63c | 713 | uint8_t obuf[16] = { CUDA_PACKET, 0, data[0] }; |
d20efaeb | 714 | int i, out_len = 0; |
267002cd | 715 | |
d20efaeb HP |
716 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { |
717 | const CudaCommand *desc = &handlers[i]; | |
718 | if (desc->command == data[0]) { | |
719 | CUDA_DPRINTF("handling command %s\n", desc->name); | |
720 | out_len = 0; | |
721 | if (desc->handler(s, data + 1, len - 1, obuf + 3, &out_len)) { | |
722 | cuda_send_packet_to_host(s, obuf, 3 + out_len); | |
723 | } else { | |
724 | qemu_log_mask(LOG_GUEST_ERROR, | |
725 | "CUDA: %s: wrong parameters %d\n", | |
726 | desc->name, len); | |
727 | obuf[0] = ERROR_PACKET; | |
728 | obuf[1] = 0x5; /* bad parameters */ | |
729 | obuf[2] = CUDA_PACKET; | |
730 | obuf[3] = data[0]; | |
731 | cuda_send_packet_to_host(s, obuf, 4); | |
732 | } | |
733 | return; | |
734 | } | |
735 | } | |
736 | ||
0e8176e8 HP |
737 | qemu_log_mask(LOG_GUEST_ERROR, "CUDA: unknown command 0x%02x\n", data[0]); |
738 | obuf[0] = ERROR_PACKET; | |
739 | obuf[1] = 0x2; /* unknown command */ | |
740 | obuf[2] = CUDA_PACKET; | |
741 | obuf[3] = data[0]; | |
742 | cuda_send_packet_to_host(s, obuf, 4); | |
267002cd FB |
743 | } |
744 | ||
5fafdf24 | 745 | static void cuda_receive_packet_from_host(CUDAState *s, |
267002cd FB |
746 | const uint8_t *data, int len) |
747 | { | |
819e712b FB |
748 | #ifdef DEBUG_CUDA_PACKET |
749 | { | |
750 | int i; | |
cadae95f | 751 | printf("cuda_receive_packet_from_host:\n"); |
819e712b FB |
752 | for(i = 0; i < len; i++) |
753 | printf(" %02x", data[i]); | |
754 | printf("\n"); | |
755 | } | |
756 | #endif | |
267002cd FB |
757 | switch(data[0]) { |
758 | case ADB_PACKET: | |
e2733d20 | 759 | { |
6729aa40 | 760 | uint8_t obuf[ADB_MAX_OUT_LEN + 3]; |
e2733d20 | 761 | int olen; |
293c867d | 762 | olen = adb_request(&s->adb_bus, obuf + 2, data + 1, len - 1); |
38f0b147 | 763 | if (olen > 0) { |
e2733d20 FB |
764 | obuf[0] = ADB_PACKET; |
765 | obuf[1] = 0x00; | |
6729aa40 | 766 | cuda_send_packet_to_host(s, obuf, olen + 2); |
e2733d20 | 767 | } else { |
38f0b147 | 768 | /* error */ |
e2733d20 | 769 | obuf[0] = ADB_PACKET; |
38f0b147 | 770 | obuf[1] = -olen; |
6729aa40 | 771 | obuf[2] = data[1]; |
38f0b147 | 772 | olen = 0; |
6729aa40 | 773 | cuda_send_packet_to_host(s, obuf, olen + 3); |
e2733d20 | 774 | } |
e2733d20 | 775 | } |
267002cd FB |
776 | break; |
777 | case CUDA_PACKET: | |
778 | cuda_receive_packet(s, data + 1, len - 1); | |
779 | break; | |
780 | } | |
781 | } | |
782 | ||
a8170e5e | 783 | static void cuda_writew (void *opaque, hwaddr addr, uint32_t value) |
267002cd FB |
784 | { |
785 | } | |
786 | ||
a8170e5e | 787 | static void cuda_writel (void *opaque, hwaddr addr, uint32_t value) |
267002cd FB |
788 | { |
789 | } | |
790 | ||
a8170e5e | 791 | static uint32_t cuda_readw (void *opaque, hwaddr addr) |
267002cd FB |
792 | { |
793 | return 0; | |
794 | } | |
795 | ||
a8170e5e | 796 | static uint32_t cuda_readl (void *opaque, hwaddr addr) |
267002cd FB |
797 | { |
798 | return 0; | |
799 | } | |
800 | ||
a348f108 | 801 | static const MemoryRegionOps cuda_ops = { |
ea0a7eb4 AG |
802 | .old_mmio = { |
803 | .write = { | |
804 | cuda_writeb, | |
805 | cuda_writew, | |
806 | cuda_writel, | |
807 | }, | |
808 | .read = { | |
809 | cuda_readb, | |
810 | cuda_readw, | |
811 | cuda_readl, | |
812 | }, | |
813 | }, | |
814 | .endianness = DEVICE_NATIVE_ENDIAN, | |
267002cd FB |
815 | }; |
816 | ||
c0a93a9e | 817 | static bool cuda_timer_exist(void *opaque, int version_id) |
9b64997f | 818 | { |
c0a93a9e | 819 | CUDATimer *s = opaque; |
9b64997f | 820 | |
c0a93a9e | 821 | return s->timer != NULL; |
9b64997f BS |
822 | } |
823 | ||
c0a93a9e JQ |
824 | static const VMStateDescription vmstate_cuda_timer = { |
825 | .name = "cuda_timer", | |
826 | .version_id = 0, | |
827 | .minimum_version_id = 0, | |
35d08458 | 828 | .fields = (VMStateField[]) { |
c0a93a9e JQ |
829 | VMSTATE_UINT16(latch, CUDATimer), |
830 | VMSTATE_UINT16(counter_value, CUDATimer), | |
831 | VMSTATE_INT64(load_time, CUDATimer), | |
832 | VMSTATE_INT64(next_irq_time, CUDATimer), | |
e720677e | 833 | VMSTATE_TIMER_PTR_TEST(timer, CUDATimer, cuda_timer_exist), |
c0a93a9e JQ |
834 | VMSTATE_END_OF_LIST() |
835 | } | |
836 | }; | |
9b64997f | 837 | |
c0a93a9e JQ |
838 | static const VMStateDescription vmstate_cuda = { |
839 | .name = "cuda", | |
374312e7 HP |
840 | .version_id = 4, |
841 | .minimum_version_id = 4, | |
35d08458 | 842 | .fields = (VMStateField[]) { |
c0a93a9e JQ |
843 | VMSTATE_UINT8(a, CUDAState), |
844 | VMSTATE_UINT8(b, CUDAState), | |
ff57eae5 | 845 | VMSTATE_UINT8(last_b, CUDAState), |
c0a93a9e JQ |
846 | VMSTATE_UINT8(dira, CUDAState), |
847 | VMSTATE_UINT8(dirb, CUDAState), | |
848 | VMSTATE_UINT8(sr, CUDAState), | |
849 | VMSTATE_UINT8(acr, CUDAState), | |
ff57eae5 | 850 | VMSTATE_UINT8(last_acr, CUDAState), |
c0a93a9e JQ |
851 | VMSTATE_UINT8(pcr, CUDAState), |
852 | VMSTATE_UINT8(ifr, CUDAState), | |
853 | VMSTATE_UINT8(ier, CUDAState), | |
854 | VMSTATE_UINT8(anh, CUDAState), | |
855 | VMSTATE_INT32(data_in_size, CUDAState), | |
856 | VMSTATE_INT32(data_in_index, CUDAState), | |
857 | VMSTATE_INT32(data_out_index, CUDAState), | |
858 | VMSTATE_UINT8(autopoll, CUDAState), | |
374312e7 | 859 | VMSTATE_UINT8(autopoll_rate_ms, CUDAState), |
216c906e | 860 | VMSTATE_UINT16(adb_poll_mask, CUDAState), |
c0a93a9e JQ |
861 | VMSTATE_BUFFER(data_in, CUDAState), |
862 | VMSTATE_BUFFER(data_out, CUDAState), | |
863 | VMSTATE_UINT32(tick_offset, CUDAState), | |
864 | VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1, | |
865 | vmstate_cuda_timer, CUDATimer), | |
6cb577dd | 866 | VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState), |
ff57eae5 | 867 | VMSTATE_TIMER_PTR(sr_delay_timer, CUDAState), |
c0a93a9e JQ |
868 | VMSTATE_END_OF_LIST() |
869 | } | |
870 | }; | |
9b64997f | 871 | |
45fa67fb | 872 | static void cuda_reset(DeviceState *dev) |
6e6b7363 | 873 | { |
45fa67fb | 874 | CUDAState *s = CUDA(dev); |
6e6b7363 BS |
875 | |
876 | s->b = 0; | |
877 | s->a = 0; | |
cffc331a | 878 | s->dirb = 0xff; |
6e6b7363 BS |
879 | s->dira = 0; |
880 | s->sr = 0; | |
881 | s->acr = 0; | |
882 | s->pcr = 0; | |
883 | s->ifr = 0; | |
884 | s->ier = 0; | |
885 | // s->ier = T1_INT | SR_INT; | |
886 | s->anh = 0; | |
887 | s->data_in_size = 0; | |
888 | s->data_in_index = 0; | |
889 | s->data_out_index = 0; | |
890 | s->autopoll = 0; | |
891 | ||
892 | s->timers[0].latch = 0xffff; | |
893 | set_counter(s, &s->timers[0], 0xffff); | |
894 | ||
a53cfdcc | 895 | s->timers[1].latch = 0xffff; |
cffc331a MCA |
896 | |
897 | s->sr_delay_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_set_sr_int, s); | |
6e6b7363 BS |
898 | } |
899 | ||
45fa67fb | 900 | static void cuda_realizefn(DeviceState *dev, Error **errp) |
267002cd | 901 | { |
45fa67fb | 902 | CUDAState *s = CUDA(dev); |
5703c174 | 903 | struct tm tm; |
819e712b | 904 | |
bc72ad67 | 905 | s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s); |
b981289c | 906 | s->timers[0].frequency = s->frequency; |
a53cfdcc MCA |
907 | s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2, s); |
908 | s->timers[1].frequency = (SCALE_US * 6000) / 4700; | |
61271e5c | 909 | |
9c554c1c AJ |
910 | qemu_get_timedate(&tm, 0); |
911 | s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; | |
5703c174 | 912 | |
bc72ad67 | 913 | s->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, s); |
374312e7 | 914 | s->autopoll_rate_ms = 20; |
216c906e | 915 | s->adb_poll_mask = 0xffff; |
45fa67fb AF |
916 | } |
917 | ||
918 | static void cuda_initfn(Object *obj) | |
919 | { | |
920 | SysBusDevice *d = SYS_BUS_DEVICE(obj); | |
921 | CUDAState *s = CUDA(obj); | |
922 | int i; | |
923 | ||
81e0ab48 | 924 | memory_region_init_io(&s->mem, obj, &cuda_ops, s, "cuda", 0x2000); |
45fa67fb AF |
925 | sysbus_init_mmio(d, &s->mem); |
926 | sysbus_init_irq(d, &s->irq); | |
927 | ||
928 | for (i = 0; i < ARRAY_SIZE(s->timers); i++) { | |
929 | s->timers[i].index = i; | |
930 | } | |
84ede329 | 931 | |
fb17dfe0 AF |
932 | qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, |
933 | DEVICE(obj), "adb.0"); | |
45fa67fb AF |
934 | } |
935 | ||
b981289c AG |
936 | static Property cuda_properties[] = { |
937 | DEFINE_PROP_UINT64("frequency", CUDAState, frequency, 0), | |
938 | DEFINE_PROP_END_OF_LIST() | |
939 | }; | |
940 | ||
45fa67fb AF |
941 | static void cuda_class_init(ObjectClass *oc, void *data) |
942 | { | |
943 | DeviceClass *dc = DEVICE_CLASS(oc); | |
ea0a7eb4 | 944 | |
45fa67fb AF |
945 | dc->realize = cuda_realizefn; |
946 | dc->reset = cuda_reset; | |
947 | dc->vmsd = &vmstate_cuda; | |
b981289c | 948 | dc->props = cuda_properties; |
599d7326 | 949 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
267002cd | 950 | } |
45fa67fb AF |
951 | |
952 | static const TypeInfo cuda_type_info = { | |
953 | .name = TYPE_CUDA, | |
954 | .parent = TYPE_SYS_BUS_DEVICE, | |
955 | .instance_size = sizeof(CUDAState), | |
956 | .instance_init = cuda_initfn, | |
957 | .class_init = cuda_class_init, | |
958 | }; | |
959 | ||
960 | static void cuda_register_types(void) | |
961 | { | |
962 | type_register_static(&cuda_type_info); | |
963 | } | |
964 | ||
965 | type_init(cuda_register_types) |