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3cbee15b
JM
1/*
2 * PowerMac MacIO device emulation
3 *
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
0d75590d 25#include "qemu/osdep.h"
da34e65c 26#include "qapi/error.h"
83c9f4ca
PB
27#include "hw/hw.h"
28#include "hw/ppc/mac.h"
29#include "hw/pci/pci.h"
0d09e41a
PB
30#include "hw/ppc/mac_dbdma.h"
31#include "hw/char/escc.h"
3cbee15b 32
fcf1bbab
AF
33#define TYPE_MACIO "macio"
34#define MACIO(obj) OBJECT_CHECK(MacIOState, (obj), TYPE_MACIO)
35
d8c51b05
AL
36typedef struct MacIOState
37{
fcf1bbab 38 /*< private >*/
d8c51b05 39 PCIDevice parent;
fcf1bbab
AF
40 /*< public >*/
41
23c5e4ca 42 MemoryRegion bar;
45fa67fb 43 CUDAState cuda;
ecba28db 44 DBDMAState *dbdma;
23c5e4ca 45 MemoryRegion *pic_mem;
23c5e4ca 46 MemoryRegion *escc_mem;
b981289c 47 uint64_t frequency;
d8c51b05 48} MacIOState;
3cbee15b 49
95ed3b7c
AF
50#define OLDWORLD_MACIO(obj) \
51 OBJECT_CHECK(OldWorldMacIOState, (obj), TYPE_OLDWORLD_MACIO)
52
53typedef struct OldWorldMacIOState {
54 /*< private >*/
55 MacIOState parent_obj;
56 /*< public >*/
57
14eefd0e 58 qemu_irq irqs[5];
07a7484e 59
95ed3b7c 60 MacIONVRAMState nvram;
14eefd0e 61 MACIOIDEState ide[2];
95ed3b7c
AF
62} OldWorldMacIOState;
63
07a7484e
AF
64#define NEWWORLD_MACIO(obj) \
65 OBJECT_CHECK(NewWorldMacIOState, (obj), TYPE_NEWWORLD_MACIO)
66
67typedef struct NewWorldMacIOState {
68 /*< private >*/
69 MacIOState parent_obj;
70 /*< public >*/
45fa67fb 71 qemu_irq irqs[5];
07a7484e
AF
72 MACIOIDEState ide[2];
73} NewWorldMacIOState;
74
0d54a502
AG
75/*
76 * The mac-io has two interfaces to the ESCC. One is called "escc-legacy",
77 * while the other one is the normal, current ESCC interface.
78 *
79 * The magic below creates memory aliases to spawn the escc-legacy device
80 * purely by rerouting the respective registers to our escc region. This
81 * works because the only difference between the two memory regions is the
82 * register layout, not their semantics.
83 *
84 * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
85 */
86static void macio_escc_legacy_setup(MacIOState *macio_state)
87{
88 MemoryRegion *escc_legacy = g_new(MemoryRegion, 1);
89 MemoryRegion *bar = &macio_state->bar;
90 int i;
91 static const int maps[] = {
dd2fa4f7
BH
92 0x00, 0x00, /* Command B */
93 0x02, 0x20, /* Command A */
94 0x04, 0x10, /* Data B */
95 0x06, 0x30, /* Data A */
96 0x08, 0x40, /* Enhancement B */
97 0x0A, 0x50, /* Enhancement A */
98 0x80, 0x80, /* Recovery count */
99 0x90, 0x90, /* Start A */
100 0xa0, 0xa0, /* Start B */
101 0xb0, 0xb0, /* Detect AB */
0d54a502
AG
102 };
103
81e0ab48 104 memory_region_init(escc_legacy, OBJECT(macio_state), "escc-legacy", 256);
0d54a502
AG
105 for (i = 0; i < ARRAY_SIZE(maps); i += 2) {
106 MemoryRegion *port = g_new(MemoryRegion, 1);
81e0ab48 107 memory_region_init_alias(port, OBJECT(macio_state), "escc-legacy-port",
2c9b15ca 108 macio_state->escc_mem, maps[i+1], 0x2);
0d54a502
AG
109 memory_region_add_subregion(escc_legacy, maps[i], port);
110 }
111
112 memory_region_add_subregion(bar, 0x12000, escc_legacy);
113}
114
d8c51b05 115static void macio_bar_setup(MacIOState *macio_state)
3cbee15b 116{
23c5e4ca 117 MemoryRegion *bar = &macio_state->bar;
3cbee15b 118
23c5e4ca
AK
119 if (macio_state->escc_mem) {
120 memory_region_add_subregion(bar, 0x13000, macio_state->escc_mem);
0d54a502 121 macio_escc_legacy_setup(macio_state);
7fa9ae1a 122 }
3cbee15b
JM
123}
124
62e9cd77 125static void macio_common_realize(PCIDevice *d, Error **errp)
d8c51b05 126{
7b925079 127 MacIOState *s = MACIO(d);
45fa67fb 128 SysBusDevice *sysbus_dev;
62e9cd77 129 Error *err = NULL;
c7104402 130
ecba28db
MCA
131 object_property_set_bool(OBJECT(s->dbdma), true, "realized", &err);
132 if (err) {
133 error_propagate(errp, err);
134 return;
135 }
136 sysbus_dev = SYS_BUS_DEVICE(s->dbdma);
137 memory_region_add_subregion(&s->bar, 0x08000,
138 sysbus_mmio_get_region(sysbus_dev, 0));
7b925079 139
62e9cd77
MA
140 object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
141 if (err) {
142 error_propagate(errp, err);
143 return;
45fa67fb
AF
144 }
145 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
146 memory_region_add_subregion(&s->bar, 0x16000,
147 sysbus_mmio_get_region(sysbus_dev, 0));
148
7b925079
AF
149 macio_bar_setup(s);
150 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
d8c51b05
AL
151}
152
62e9cd77
MA
153static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide,
154 qemu_irq irq0, qemu_irq irq1, int dmaid,
155 Error **errp)
14eefd0e
AG
156{
157 SysBusDevice *sysbus_dev;
158
159 sysbus_dev = SYS_BUS_DEVICE(ide);
160 sysbus_connect_irq(sysbus_dev, 0, irq0);
161 sysbus_connect_irq(sysbus_dev, 1, irq1);
0fc84331 162 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid);
e451b85f
MCA
163 object_property_set_link(OBJECT(ide), OBJECT(s->dbdma), "dbdma", errp);
164 macio_ide_register_dma(ide);
0fc84331 165
62e9cd77 166 object_property_set_bool(OBJECT(ide), true, "realized", errp);
14eefd0e
AG
167}
168
62e9cd77 169static void macio_oldworld_realize(PCIDevice *d, Error **errp)
d037834a
AF
170{
171 MacIOState *s = MACIO(d);
95ed3b7c 172 OldWorldMacIOState *os = OLDWORLD_MACIO(d);
62e9cd77 173 Error *err = NULL;
95ed3b7c 174 SysBusDevice *sysbus_dev;
14eefd0e
AG
175 int i;
176 int cur_irq = 0;
62e9cd77
MA
177
178 macio_common_realize(d, &err);
179 if (err) {
180 error_propagate(errp, err);
181 return;
d037834a
AF
182 }
183
45fa67fb 184 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
14eefd0e 185 sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);
45fa67fb 186
62e9cd77
MA
187 object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err);
188 if (err) {
189 error_propagate(errp, err);
190 return;
95ed3b7c
AF
191 }
192 sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
193 memory_region_add_subregion(&s->bar, 0x60000,
194 sysbus_mmio_get_region(sysbus_dev, 0));
195 pmac_format_nvram_partition(&os->nvram, os->nvram.size);
196
d037834a
AF
197 if (s->pic_mem) {
198 /* Heathrow PIC */
199 memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem);
200 }
201
14eefd0e
AG
202 /* IDE buses */
203 for (i = 0; i < ARRAY_SIZE(os->ide); i++) {
204 qemu_irq irq0 = os->irqs[cur_irq++];
205 qemu_irq irq1 = os->irqs[cur_irq++];
206
62e9cd77
MA
207 macio_realize_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4), &err);
208 if (err) {
209 error_propagate(errp, err);
210 return;
14eefd0e 211 }
07a7484e 212 }
d037834a
AF
213}
214
213f0c4f
AF
215static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, size_t ide_size,
216 int index)
14eefd0e
AG
217{
218 gchar *name;
219
213f0c4f 220 object_initialize(ide, ide_size, TYPE_MACIO_IDE);
14eefd0e
AG
221 qdev_set_parent_bus(DEVICE(ide), sysbus_get_default());
222 memory_region_add_subregion(&s->bar, 0x1f000 + ((index + 1) * 0x1000),
223 &ide->mem);
224 name = g_strdup_printf("ide[%i]", index);
225 object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL);
226 g_free(name);
227}
228
95ed3b7c
AF
229static void macio_oldworld_init(Object *obj)
230{
07a7484e 231 MacIOState *s = MACIO(obj);
95ed3b7c
AF
232 OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
233 DeviceState *dev;
14eefd0e 234 int i;
95ed3b7c 235
07a7484e
AF
236 qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs));
237
213f0c4f 238 object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM);
95ed3b7c
AF
239 dev = DEVICE(&os->nvram);
240 qdev_prop_set_uint32(dev, "size", 0x2000);
241 qdev_prop_set_uint32(dev, "it_shift", 4);
07a7484e 242
14eefd0e 243 for (i = 0; i < 2; i++) {
213f0c4f 244 macio_init_ide(s, &os->ide[i], sizeof(os->ide[i]), i);
14eefd0e 245 }
95ed3b7c
AF
246}
247
a0f9fdfd
AG
248static void timer_write(void *opaque, hwaddr addr, uint64_t value,
249 unsigned size)
250{
251}
252
253static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
254{
255 uint32_t value = 0;
d696760b
AG
256 uint64_t systime = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
257 uint64_t kltime;
258
73bcb24d 259 kltime = muldiv64(systime, 4194300, NANOSECONDS_PER_SECOND * 4);
d696760b 260 kltime = muldiv64(kltime, 18432000, 1048575);
a0f9fdfd
AG
261
262 switch (addr) {
263 case 0x38:
d696760b 264 value = kltime;
a0f9fdfd
AG
265 break;
266 case 0x3c:
d696760b 267 value = kltime >> 32;
a0f9fdfd
AG
268 break;
269 }
270
271 return value;
272}
273
274static const MemoryRegionOps timer_ops = {
275 .read = timer_read,
276 .write = timer_write,
9397a7c8 277 .endianness = DEVICE_LITTLE_ENDIAN,
a0f9fdfd
AG
278};
279
62e9cd77 280static void macio_newworld_realize(PCIDevice *d, Error **errp)
d037834a
AF
281{
282 MacIOState *s = MACIO(d);
07a7484e 283 NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
62e9cd77 284 Error *err = NULL;
07a7484e 285 SysBusDevice *sysbus_dev;
6c5819c4 286 MemoryRegion *timer_memory = NULL;
14eefd0e
AG
287 int i;
288 int cur_irq = 0;
62e9cd77
MA
289
290 macio_common_realize(d, &err);
291 if (err) {
292 error_propagate(errp, err);
293 return;
d037834a
AF
294 }
295
45fa67fb 296 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
14eefd0e 297 sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]);
45fa67fb 298
d037834a
AF
299 if (s->pic_mem) {
300 /* OpenPIC */
301 memory_region_add_subregion(&s->bar, 0x40000, s->pic_mem);
302 }
303
14eefd0e
AG
304 /* IDE buses */
305 for (i = 0; i < ARRAY_SIZE(ns->ide); i++) {
306 qemu_irq irq0 = ns->irqs[cur_irq++];
307 qemu_irq irq1 = ns->irqs[cur_irq++];
07a7484e 308
62e9cd77
MA
309 macio_realize_ide(s, &ns->ide[i], irq0, irq1, 0x16 + (i * 4), &err);
310 if (err) {
311 error_propagate(errp, err);
312 return;
14eefd0e 313 }
07a7484e
AF
314 }
315
a0f9fdfd 316 /* Timer */
6c5819c4 317 timer_memory = g_new(MemoryRegion, 1);
a0f9fdfd
AG
318 memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",
319 0x1000);
320 memory_region_add_subregion(&s->bar, 0x15000, timer_memory);
d037834a
AF
321}
322
07a7484e
AF
323static void macio_newworld_init(Object *obj)
324{
325 MacIOState *s = MACIO(obj);
326 NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
327 int i;
07a7484e
AF
328
329 qdev_init_gpio_out(DEVICE(obj), ns->irqs, ARRAY_SIZE(ns->irqs));
330
331 for (i = 0; i < 2; i++) {
213f0c4f 332 macio_init_ide(s, &ns->ide[i], sizeof(ns->ide[i]), i);
07a7484e
AF
333 }
334}
335
fcf1bbab
AF
336static void macio_instance_init(Object *obj)
337{
338 MacIOState *s = MACIO(obj);
339
81e0ab48 340 memory_region_init(&s->bar, obj, "macio", 0x80000);
07a7484e 341
213f0c4f 342 object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA);
45fa67fb
AF
343 qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default());
344 object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL);
ecba28db
MCA
345
346 s->dbdma = MAC_DBDMA(object_new(TYPE_MAC_DBDMA));
347 object_property_add_child(obj, "dbdma", OBJECT(s->dbdma), NULL);
fcf1bbab
AF
348}
349
02635923
MCA
350static const VMStateDescription vmstate_macio_oldworld = {
351 .name = "macio-oldworld",
352 .version_id = 0,
353 .minimum_version_id = 0,
354 .fields = (VMStateField[]) {
355 VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState),
356 VMSTATE_END_OF_LIST()
357 }
358};
359
d037834a
AF
360static void macio_oldworld_class_init(ObjectClass *oc, void *data)
361{
362 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
02635923 363 DeviceClass *dc = DEVICE_CLASS(oc);
d037834a 364
62e9cd77 365 pdc->realize = macio_oldworld_realize;
d037834a 366 pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201;
02635923 367 dc->vmsd = &vmstate_macio_oldworld;
d037834a
AF
368}
369
02635923
MCA
370static const VMStateDescription vmstate_macio_newworld = {
371 .name = "macio-newworld",
372 .version_id = 0,
373 .minimum_version_id = 0,
374 .fields = (VMStateField[]) {
375 VMSTATE_PCI_DEVICE(parent_obj.parent, NewWorldMacIOState),
376 VMSTATE_END_OF_LIST()
377 }
378};
379
d037834a
AF
380static void macio_newworld_class_init(ObjectClass *oc, void *data)
381{
382 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
02635923 383 DeviceClass *dc = DEVICE_CLASS(oc);
d037834a 384
62e9cd77 385 pdc->realize = macio_newworld_realize;
d037834a 386 pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL;
02635923 387 dc->vmsd = &vmstate_macio_newworld;
d037834a
AF
388}
389
b981289c
AG
390static Property macio_properties[] = {
391 DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0),
392 DEFINE_PROP_END_OF_LIST()
393};
394
40021f08
AL
395static void macio_class_init(ObjectClass *klass, void *data)
396{
397 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
b981289c 398 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 399
40021f08
AL
400 k->vendor_id = PCI_VENDOR_ID_APPLE;
401 k->class_id = PCI_CLASS_OTHERS << 8;
b981289c 402 dc->props = macio_properties;
f9f2a9f2 403 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
40021f08
AL
404}
405
d037834a
AF
406static const TypeInfo macio_oldworld_type_info = {
407 .name = TYPE_OLDWORLD_MACIO,
408 .parent = TYPE_MACIO,
95ed3b7c
AF
409 .instance_size = sizeof(OldWorldMacIOState),
410 .instance_init = macio_oldworld_init,
d037834a
AF
411 .class_init = macio_oldworld_class_init,
412};
413
414static const TypeInfo macio_newworld_type_info = {
415 .name = TYPE_NEWWORLD_MACIO,
416 .parent = TYPE_MACIO,
07a7484e
AF
417 .instance_size = sizeof(NewWorldMacIOState),
418 .instance_init = macio_newworld_init,
d037834a
AF
419 .class_init = macio_newworld_class_init,
420};
421
fcf1bbab
AF
422static const TypeInfo macio_type_info = {
423 .name = TYPE_MACIO,
39bffca2
AL
424 .parent = TYPE_PCI_DEVICE,
425 .instance_size = sizeof(MacIOState),
fcf1bbab 426 .instance_init = macio_instance_init,
d037834a 427 .abstract = true,
39bffca2 428 .class_init = macio_class_init,
fd3b02c8
EH
429 .interfaces = (InterfaceInfo[]) {
430 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
431 { },
432 },
d8c51b05
AL
433};
434
83f7d43a 435static void macio_register_types(void)
d8c51b05 436{
fcf1bbab 437 type_register_static(&macio_type_info);
d037834a
AF
438 type_register_static(&macio_oldworld_type_info);
439 type_register_static(&macio_newworld_type_info);
d8c51b05
AL
440}
441
83f7d43a 442type_init(macio_register_types)
d8c51b05 443
d037834a 444void macio_init(PCIDevice *d,
07a7484e 445 MemoryRegion *pic_mem,
d037834a 446 MemoryRegion *escc_mem)
3cbee15b 447{
d037834a 448 MacIOState *macio_state = MACIO(d);
3cbee15b 449
23c5e4ca 450 macio_state->pic_mem = pic_mem;
23c5e4ca 451 macio_state->escc_mem = escc_mem;
3cbee15b
JM
452 /* Note: this code is strongly inspirated from the corresponding code
453 in PearPC */
27c5cee1 454 qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "timebase-frequency",
b981289c 455 macio_state->frequency);
deb54399 456
7b925079 457 qdev_init_nofail(DEVICE(d));
3cbee15b 458}