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3cbee15b
JM
1/*
2 * PowerMac MacIO device emulation
3 *
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
0d75590d 25#include "qemu/osdep.h"
da34e65c 26#include "qapi/error.h"
83c9f4ca
PB
27#include "hw/hw.h"
28#include "hw/ppc/mac.h"
7092e84d 29#include "hw/misc/macio/cuda.h"
83c9f4ca 30#include "hw/pci/pci.h"
0d09e41a
PB
31#include "hw/ppc/mac_dbdma.h"
32#include "hw/char/escc.h"
3cbee15b 33
fcf1bbab
AF
34#define TYPE_MACIO "macio"
35#define MACIO(obj) OBJECT_CHECK(MacIOState, (obj), TYPE_MACIO)
36
d8c51b05
AL
37typedef struct MacIOState
38{
fcf1bbab 39 /*< private >*/
d8c51b05 40 PCIDevice parent;
fcf1bbab
AF
41 /*< public >*/
42
23c5e4ca 43 MemoryRegion bar;
45fa67fb 44 CUDAState cuda;
ecba28db 45 DBDMAState *dbdma;
23c5e4ca 46 MemoryRegion *pic_mem;
23c5e4ca 47 MemoryRegion *escc_mem;
b981289c 48 uint64_t frequency;
d8c51b05 49} MacIOState;
3cbee15b 50
95ed3b7c
AF
51#define OLDWORLD_MACIO(obj) \
52 OBJECT_CHECK(OldWorldMacIOState, (obj), TYPE_OLDWORLD_MACIO)
53
54typedef struct OldWorldMacIOState {
55 /*< private >*/
56 MacIOState parent_obj;
57 /*< public >*/
58
14eefd0e 59 qemu_irq irqs[5];
07a7484e 60
95ed3b7c 61 MacIONVRAMState nvram;
14eefd0e 62 MACIOIDEState ide[2];
95ed3b7c
AF
63} OldWorldMacIOState;
64
07a7484e
AF
65#define NEWWORLD_MACIO(obj) \
66 OBJECT_CHECK(NewWorldMacIOState, (obj), TYPE_NEWWORLD_MACIO)
67
68typedef struct NewWorldMacIOState {
69 /*< private >*/
70 MacIOState parent_obj;
71 /*< public >*/
45fa67fb 72 qemu_irq irqs[5];
07a7484e
AF
73 MACIOIDEState ide[2];
74} NewWorldMacIOState;
75
0d54a502
AG
76/*
77 * The mac-io has two interfaces to the ESCC. One is called "escc-legacy",
78 * while the other one is the normal, current ESCC interface.
79 *
80 * The magic below creates memory aliases to spawn the escc-legacy device
81 * purely by rerouting the respective registers to our escc region. This
82 * works because the only difference between the two memory regions is the
83 * register layout, not their semantics.
84 *
85 * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
86 */
87static void macio_escc_legacy_setup(MacIOState *macio_state)
88{
89 MemoryRegion *escc_legacy = g_new(MemoryRegion, 1);
90 MemoryRegion *bar = &macio_state->bar;
91 int i;
92 static const int maps[] = {
dd2fa4f7
BH
93 0x00, 0x00, /* Command B */
94 0x02, 0x20, /* Command A */
95 0x04, 0x10, /* Data B */
96 0x06, 0x30, /* Data A */
97 0x08, 0x40, /* Enhancement B */
98 0x0A, 0x50, /* Enhancement A */
99 0x80, 0x80, /* Recovery count */
100 0x90, 0x90, /* Start A */
101 0xa0, 0xa0, /* Start B */
102 0xb0, 0xb0, /* Detect AB */
0d54a502
AG
103 };
104
81e0ab48 105 memory_region_init(escc_legacy, OBJECT(macio_state), "escc-legacy", 256);
0d54a502
AG
106 for (i = 0; i < ARRAY_SIZE(maps); i += 2) {
107 MemoryRegion *port = g_new(MemoryRegion, 1);
81e0ab48 108 memory_region_init_alias(port, OBJECT(macio_state), "escc-legacy-port",
2c9b15ca 109 macio_state->escc_mem, maps[i+1], 0x2);
0d54a502
AG
110 memory_region_add_subregion(escc_legacy, maps[i], port);
111 }
112
113 memory_region_add_subregion(bar, 0x12000, escc_legacy);
114}
115
d8c51b05 116static void macio_bar_setup(MacIOState *macio_state)
3cbee15b 117{
23c5e4ca 118 MemoryRegion *bar = &macio_state->bar;
3cbee15b 119
23c5e4ca
AK
120 if (macio_state->escc_mem) {
121 memory_region_add_subregion(bar, 0x13000, macio_state->escc_mem);
0d54a502 122 macio_escc_legacy_setup(macio_state);
7fa9ae1a 123 }
3cbee15b
JM
124}
125
62e9cd77 126static void macio_common_realize(PCIDevice *d, Error **errp)
d8c51b05 127{
7b925079 128 MacIOState *s = MACIO(d);
45fa67fb 129 SysBusDevice *sysbus_dev;
62e9cd77 130 Error *err = NULL;
c7104402 131
ecba28db
MCA
132 object_property_set_bool(OBJECT(s->dbdma), true, "realized", &err);
133 if (err) {
134 error_propagate(errp, err);
135 return;
136 }
137 sysbus_dev = SYS_BUS_DEVICE(s->dbdma);
138 memory_region_add_subregion(&s->bar, 0x08000,
139 sysbus_mmio_get_region(sysbus_dev, 0));
7b925079 140
62e9cd77
MA
141 object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
142 if (err) {
143 error_propagate(errp, err);
144 return;
45fa67fb
AF
145 }
146 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
147 memory_region_add_subregion(&s->bar, 0x16000,
148 sysbus_mmio_get_region(sysbus_dev, 0));
149
7b925079
AF
150 macio_bar_setup(s);
151 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
d8c51b05
AL
152}
153
62e9cd77
MA
154static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide,
155 qemu_irq irq0, qemu_irq irq1, int dmaid,
156 Error **errp)
14eefd0e
AG
157{
158 SysBusDevice *sysbus_dev;
159
160 sysbus_dev = SYS_BUS_DEVICE(ide);
161 sysbus_connect_irq(sysbus_dev, 0, irq0);
162 sysbus_connect_irq(sysbus_dev, 1, irq1);
0fc84331 163 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid);
e451b85f
MCA
164 object_property_set_link(OBJECT(ide), OBJECT(s->dbdma), "dbdma", errp);
165 macio_ide_register_dma(ide);
0fc84331 166
62e9cd77 167 object_property_set_bool(OBJECT(ide), true, "realized", errp);
14eefd0e
AG
168}
169
62e9cd77 170static void macio_oldworld_realize(PCIDevice *d, Error **errp)
d037834a
AF
171{
172 MacIOState *s = MACIO(d);
95ed3b7c 173 OldWorldMacIOState *os = OLDWORLD_MACIO(d);
62e9cd77 174 Error *err = NULL;
95ed3b7c 175 SysBusDevice *sysbus_dev;
14eefd0e
AG
176 int i;
177 int cur_irq = 0;
62e9cd77
MA
178
179 macio_common_realize(d, &err);
180 if (err) {
181 error_propagate(errp, err);
182 return;
d037834a
AF
183 }
184
45fa67fb 185 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
14eefd0e 186 sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);
45fa67fb 187
62e9cd77
MA
188 object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err);
189 if (err) {
190 error_propagate(errp, err);
191 return;
95ed3b7c
AF
192 }
193 sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
194 memory_region_add_subregion(&s->bar, 0x60000,
195 sysbus_mmio_get_region(sysbus_dev, 0));
196 pmac_format_nvram_partition(&os->nvram, os->nvram.size);
197
d037834a
AF
198 if (s->pic_mem) {
199 /* Heathrow PIC */
200 memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem);
201 }
202
14eefd0e
AG
203 /* IDE buses */
204 for (i = 0; i < ARRAY_SIZE(os->ide); i++) {
205 qemu_irq irq0 = os->irqs[cur_irq++];
206 qemu_irq irq1 = os->irqs[cur_irq++];
207
62e9cd77
MA
208 macio_realize_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4), &err);
209 if (err) {
210 error_propagate(errp, err);
211 return;
14eefd0e 212 }
07a7484e 213 }
d037834a
AF
214}
215
213f0c4f
AF
216static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, size_t ide_size,
217 int index)
14eefd0e
AG
218{
219 gchar *name;
220
213f0c4f 221 object_initialize(ide, ide_size, TYPE_MACIO_IDE);
14eefd0e
AG
222 qdev_set_parent_bus(DEVICE(ide), sysbus_get_default());
223 memory_region_add_subregion(&s->bar, 0x1f000 + ((index + 1) * 0x1000),
224 &ide->mem);
225 name = g_strdup_printf("ide[%i]", index);
226 object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL);
227 g_free(name);
228}
229
95ed3b7c
AF
230static void macio_oldworld_init(Object *obj)
231{
07a7484e 232 MacIOState *s = MACIO(obj);
95ed3b7c
AF
233 OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
234 DeviceState *dev;
14eefd0e 235 int i;
95ed3b7c 236
07a7484e
AF
237 qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs));
238
213f0c4f 239 object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM);
95ed3b7c
AF
240 dev = DEVICE(&os->nvram);
241 qdev_prop_set_uint32(dev, "size", 0x2000);
242 qdev_prop_set_uint32(dev, "it_shift", 4);
07a7484e 243
14eefd0e 244 for (i = 0; i < 2; i++) {
213f0c4f 245 macio_init_ide(s, &os->ide[i], sizeof(os->ide[i]), i);
14eefd0e 246 }
95ed3b7c
AF
247}
248
a0f9fdfd
AG
249static void timer_write(void *opaque, hwaddr addr, uint64_t value,
250 unsigned size)
251{
252}
253
254static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
255{
256 uint32_t value = 0;
d696760b
AG
257 uint64_t systime = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
258 uint64_t kltime;
259
73bcb24d 260 kltime = muldiv64(systime, 4194300, NANOSECONDS_PER_SECOND * 4);
d696760b 261 kltime = muldiv64(kltime, 18432000, 1048575);
a0f9fdfd
AG
262
263 switch (addr) {
264 case 0x38:
d696760b 265 value = kltime;
a0f9fdfd
AG
266 break;
267 case 0x3c:
d696760b 268 value = kltime >> 32;
a0f9fdfd
AG
269 break;
270 }
271
272 return value;
273}
274
275static const MemoryRegionOps timer_ops = {
276 .read = timer_read,
277 .write = timer_write,
9397a7c8 278 .endianness = DEVICE_LITTLE_ENDIAN,
a0f9fdfd
AG
279};
280
62e9cd77 281static void macio_newworld_realize(PCIDevice *d, Error **errp)
d037834a
AF
282{
283 MacIOState *s = MACIO(d);
07a7484e 284 NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
62e9cd77 285 Error *err = NULL;
07a7484e 286 SysBusDevice *sysbus_dev;
6c5819c4 287 MemoryRegion *timer_memory = NULL;
14eefd0e
AG
288 int i;
289 int cur_irq = 0;
62e9cd77
MA
290
291 macio_common_realize(d, &err);
292 if (err) {
293 error_propagate(errp, err);
294 return;
d037834a
AF
295 }
296
45fa67fb 297 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
14eefd0e 298 sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]);
45fa67fb 299
d037834a
AF
300 if (s->pic_mem) {
301 /* OpenPIC */
302 memory_region_add_subregion(&s->bar, 0x40000, s->pic_mem);
303 }
304
14eefd0e
AG
305 /* IDE buses */
306 for (i = 0; i < ARRAY_SIZE(ns->ide); i++) {
307 qemu_irq irq0 = ns->irqs[cur_irq++];
308 qemu_irq irq1 = ns->irqs[cur_irq++];
07a7484e 309
62e9cd77
MA
310 macio_realize_ide(s, &ns->ide[i], irq0, irq1, 0x16 + (i * 4), &err);
311 if (err) {
312 error_propagate(errp, err);
313 return;
14eefd0e 314 }
07a7484e
AF
315 }
316
a0f9fdfd 317 /* Timer */
6c5819c4 318 timer_memory = g_new(MemoryRegion, 1);
a0f9fdfd
AG
319 memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",
320 0x1000);
321 memory_region_add_subregion(&s->bar, 0x15000, timer_memory);
d037834a
AF
322}
323
07a7484e
AF
324static void macio_newworld_init(Object *obj)
325{
326 MacIOState *s = MACIO(obj);
327 NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
328 int i;
07a7484e
AF
329
330 qdev_init_gpio_out(DEVICE(obj), ns->irqs, ARRAY_SIZE(ns->irqs));
331
332 for (i = 0; i < 2; i++) {
213f0c4f 333 macio_init_ide(s, &ns->ide[i], sizeof(ns->ide[i]), i);
07a7484e
AF
334 }
335}
336
fcf1bbab
AF
337static void macio_instance_init(Object *obj)
338{
339 MacIOState *s = MACIO(obj);
340
81e0ab48 341 memory_region_init(&s->bar, obj, "macio", 0x80000);
07a7484e 342
213f0c4f 343 object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA);
45fa67fb
AF
344 qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default());
345 object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL);
ecba28db
MCA
346
347 s->dbdma = MAC_DBDMA(object_new(TYPE_MAC_DBDMA));
348 object_property_add_child(obj, "dbdma", OBJECT(s->dbdma), NULL);
fcf1bbab
AF
349}
350
02635923
MCA
351static const VMStateDescription vmstate_macio_oldworld = {
352 .name = "macio-oldworld",
353 .version_id = 0,
354 .minimum_version_id = 0,
355 .fields = (VMStateField[]) {
356 VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState),
357 VMSTATE_END_OF_LIST()
358 }
359};
360
d037834a
AF
361static void macio_oldworld_class_init(ObjectClass *oc, void *data)
362{
363 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
02635923 364 DeviceClass *dc = DEVICE_CLASS(oc);
d037834a 365
62e9cd77 366 pdc->realize = macio_oldworld_realize;
d037834a 367 pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201;
02635923 368 dc->vmsd = &vmstate_macio_oldworld;
d037834a
AF
369}
370
02635923
MCA
371static const VMStateDescription vmstate_macio_newworld = {
372 .name = "macio-newworld",
373 .version_id = 0,
374 .minimum_version_id = 0,
375 .fields = (VMStateField[]) {
376 VMSTATE_PCI_DEVICE(parent_obj.parent, NewWorldMacIOState),
377 VMSTATE_END_OF_LIST()
378 }
379};
380
d037834a
AF
381static void macio_newworld_class_init(ObjectClass *oc, void *data)
382{
383 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
02635923 384 DeviceClass *dc = DEVICE_CLASS(oc);
d037834a 385
62e9cd77 386 pdc->realize = macio_newworld_realize;
d037834a 387 pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL;
02635923 388 dc->vmsd = &vmstate_macio_newworld;
d037834a
AF
389}
390
b981289c
AG
391static Property macio_properties[] = {
392 DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0),
393 DEFINE_PROP_END_OF_LIST()
394};
395
40021f08
AL
396static void macio_class_init(ObjectClass *klass, void *data)
397{
398 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
b981289c 399 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 400
40021f08
AL
401 k->vendor_id = PCI_VENDOR_ID_APPLE;
402 k->class_id = PCI_CLASS_OTHERS << 8;
b981289c 403 dc->props = macio_properties;
f9f2a9f2 404 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
40021f08
AL
405}
406
d037834a
AF
407static const TypeInfo macio_oldworld_type_info = {
408 .name = TYPE_OLDWORLD_MACIO,
409 .parent = TYPE_MACIO,
95ed3b7c
AF
410 .instance_size = sizeof(OldWorldMacIOState),
411 .instance_init = macio_oldworld_init,
d037834a
AF
412 .class_init = macio_oldworld_class_init,
413};
414
415static const TypeInfo macio_newworld_type_info = {
416 .name = TYPE_NEWWORLD_MACIO,
417 .parent = TYPE_MACIO,
07a7484e
AF
418 .instance_size = sizeof(NewWorldMacIOState),
419 .instance_init = macio_newworld_init,
d037834a
AF
420 .class_init = macio_newworld_class_init,
421};
422
fcf1bbab
AF
423static const TypeInfo macio_type_info = {
424 .name = TYPE_MACIO,
39bffca2
AL
425 .parent = TYPE_PCI_DEVICE,
426 .instance_size = sizeof(MacIOState),
fcf1bbab 427 .instance_init = macio_instance_init,
d037834a 428 .abstract = true,
39bffca2 429 .class_init = macio_class_init,
fd3b02c8
EH
430 .interfaces = (InterfaceInfo[]) {
431 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
432 { },
433 },
d8c51b05
AL
434};
435
83f7d43a 436static void macio_register_types(void)
d8c51b05 437{
fcf1bbab 438 type_register_static(&macio_type_info);
d037834a
AF
439 type_register_static(&macio_oldworld_type_info);
440 type_register_static(&macio_newworld_type_info);
d8c51b05
AL
441}
442
83f7d43a 443type_init(macio_register_types)
d8c51b05 444
d037834a 445void macio_init(PCIDevice *d,
07a7484e 446 MemoryRegion *pic_mem,
d037834a 447 MemoryRegion *escc_mem)
3cbee15b 448{
d037834a 449 MacIOState *macio_state = MACIO(d);
3cbee15b 450
23c5e4ca 451 macio_state->pic_mem = pic_mem;
23c5e4ca 452 macio_state->escc_mem = escc_mem;
3cbee15b
JM
453 /* Note: this code is strongly inspirated from the corresponding code
454 in PearPC */
27c5cee1 455 qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "timebase-frequency",
b981289c 456 macio_state->frequency);
deb54399 457
7b925079 458 qdev_init_nofail(DEVICE(d));
3cbee15b 459}