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1 | /* |
2 | * Inter-Thread Communication Unit emulation. | |
3 | * | |
4 | * Copyright (c) 2016 Imagination Technologies | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qapi/error.h" | |
22 | #include "hw/hw.h" | |
23 | #include "hw/sysbus.h" | |
24 | #include "sysemu/sysemu.h" | |
25 | #include "hw/misc/mips_itu.h" | |
26 | ||
27 | #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8) | |
28 | /* Initialize as 4kB area to fit all 32 cells with default 128B grain. | |
29 | Storage may be resized by the software. */ | |
30 | #define ITC_STORAGE_ADDRSPACE_SZ 0x1000 | |
31 | ||
32 | #define ITC_FIFO_NUM_MAX 16 | |
33 | #define ITC_SEMAPH_NUM_MAX 16 | |
34 | #define ITC_AM1_NUMENTRIES_OFS 20 | |
35 | ||
36 | #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL | |
37 | #define ITC_AM0_EN_MASK 0x1 | |
38 | ||
39 | #define ITC_AM1_ADDR_MASK_MASK 0x1FC00 | |
40 | #define ITC_AM1_ENTRY_GRAIN_MASK 0x7 | |
41 | ||
42 | MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) | |
43 | { | |
44 | return &itu->tag_io; | |
45 | } | |
46 | ||
47 | static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) | |
48 | { | |
49 | MIPSITUState *tag = (MIPSITUState *)opaque; | |
50 | uint64_t index = addr >> 3; | |
51 | uint64_t ret = 0; | |
52 | ||
53 | switch (index) { | |
54 | case 0 ... ITC_ADDRESSMAP_NUM: | |
55 | ret = tag->ITCAddressMap[index]; | |
56 | break; | |
57 | default: | |
58 | qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr); | |
59 | break; | |
60 | } | |
61 | ||
62 | return ret; | |
63 | } | |
64 | ||
65 | static void itc_reconfigure(MIPSITUState *tag) | |
66 | { | |
67 | uint64_t *am = &tag->ITCAddressMap[0]; | |
68 | MemoryRegion *mr = &tag->storage_io; | |
69 | hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; | |
70 | uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK); | |
71 | bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; | |
72 | ||
73 | memory_region_transaction_begin(); | |
74 | if (!(size & (size - 1))) { | |
75 | memory_region_set_size(mr, size); | |
76 | } | |
77 | memory_region_set_address(mr, address); | |
78 | memory_region_set_enabled(mr, is_enabled); | |
79 | memory_region_transaction_commit(); | |
80 | } | |
81 | ||
82 | static void itc_tag_write(void *opaque, hwaddr addr, | |
83 | uint64_t data, unsigned size) | |
84 | { | |
85 | MIPSITUState *tag = (MIPSITUState *)opaque; | |
86 | uint64_t *am = &tag->ITCAddressMap[0]; | |
87 | uint64_t am_old, mask; | |
88 | uint64_t index = addr >> 3; | |
89 | ||
90 | switch (index) { | |
91 | case 0: | |
92 | mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK; | |
93 | break; | |
94 | case 1: | |
95 | mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK; | |
96 | break; | |
97 | default: | |
98 | qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr); | |
99 | return; | |
100 | } | |
101 | ||
102 | am_old = am[index]; | |
103 | am[index] = (data & mask) | (am_old & ~mask); | |
104 | if (am_old != am[index]) { | |
105 | itc_reconfigure(tag); | |
106 | } | |
107 | } | |
108 | ||
109 | static const MemoryRegionOps itc_tag_ops = { | |
110 | .read = itc_tag_read, | |
111 | .write = itc_tag_write, | |
112 | .impl = { | |
113 | .max_access_size = 8, | |
114 | }, | |
115 | .endianness = DEVICE_NATIVE_ENDIAN, | |
116 | }; | |
117 | ||
118 | static inline uint32_t get_num_cells(MIPSITUState *s) | |
119 | { | |
120 | return s->num_fifo + s->num_semaphores; | |
121 | } | |
122 | ||
123 | static const MemoryRegionOps itc_storage_ops = { | |
124 | .endianness = DEVICE_NATIVE_ENDIAN, | |
125 | }; | |
126 | ||
127 | static void itc_reset_cells(MIPSITUState *s) | |
128 | { | |
129 | int i; | |
130 | ||
131 | memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0])); | |
132 | ||
133 | for (i = 0; i < s->num_fifo; i++) { | |
134 | s->cell[i].tag.E = 1; | |
135 | s->cell[i].tag.FIFO = 1; | |
136 | s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT; | |
137 | } | |
138 | } | |
139 | ||
140 | static void mips_itu_init(Object *obj) | |
141 | { | |
142 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
143 | MIPSITUState *s = MIPS_ITU(obj); | |
144 | ||
145 | memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s, | |
146 | "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ); | |
147 | sysbus_init_mmio(sbd, &s->storage_io); | |
148 | ||
149 | memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s, | |
150 | "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ); | |
151 | } | |
152 | ||
153 | static void mips_itu_realize(DeviceState *dev, Error **errp) | |
154 | { | |
155 | MIPSITUState *s = MIPS_ITU(dev); | |
156 | ||
157 | if (s->num_fifo > ITC_FIFO_NUM_MAX) { | |
158 | error_setg(errp, "Exceed maximum number of FIFO cells: %d", | |
159 | s->num_fifo); | |
160 | return; | |
161 | } | |
162 | if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) { | |
163 | error_setg(errp, "Exceed maximum number of Semaphore cells: %d", | |
164 | s->num_semaphores); | |
165 | return; | |
166 | } | |
167 | ||
168 | s->cell = g_new(ITCStorageCell, get_num_cells(s)); | |
169 | } | |
170 | ||
171 | static void mips_itu_reset(DeviceState *dev) | |
172 | { | |
173 | MIPSITUState *s = MIPS_ITU(dev); | |
174 | ||
175 | s->ITCAddressMap[0] = 0; | |
176 | s->ITCAddressMap[1] = | |
177 | ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | | |
178 | (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); | |
179 | itc_reconfigure(s); | |
180 | ||
181 | itc_reset_cells(s); | |
182 | } | |
183 | ||
184 | static Property mips_itu_properties[] = { | |
185 | DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, | |
186 | ITC_FIFO_NUM_MAX), | |
187 | DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores, | |
188 | ITC_SEMAPH_NUM_MAX), | |
189 | DEFINE_PROP_END_OF_LIST(), | |
190 | }; | |
191 | ||
192 | static void mips_itu_class_init(ObjectClass *klass, void *data) | |
193 | { | |
194 | DeviceClass *dc = DEVICE_CLASS(klass); | |
195 | ||
196 | dc->props = mips_itu_properties; | |
197 | dc->realize = mips_itu_realize; | |
198 | dc->reset = mips_itu_reset; | |
199 | } | |
200 | ||
201 | static const TypeInfo mips_itu_info = { | |
202 | .name = TYPE_MIPS_ITU, | |
203 | .parent = TYPE_SYS_BUS_DEVICE, | |
204 | .instance_size = sizeof(MIPSITUState), | |
205 | .instance_init = mips_itu_init, | |
206 | .class_init = mips_itu_class_init, | |
207 | }; | |
208 | ||
209 | static void mips_itu_register_types(void) | |
210 | { | |
211 | type_register_static(&mips_itu_info); | |
212 | } | |
213 | ||
214 | type_init(mips_itu_register_types) |