[mirror_qemu.git] / hw / misc / puv3_pm.c

/*
 * Power Management device simulation in PKUnity SoC
 *
 * Copyright (C) 2010-2012 Guan Xuetao
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation, or any later version.
 * See the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qom/object.h"

#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
#include "qemu/log.h"

#define TYPE_PUV3_PM "puv3_pm"
typedef struct PUV3PMState PUV3PMState;
DECLARE_INSTANCE_CHECKER(PUV3PMState, PUV3_PM,
                         TYPE_PUV3_PM)

struct PUV3PMState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    uint32_t reg_PMCR;
    uint32_t reg_PCGR;
    uint32_t reg_PLL_SYS_CFG;
    uint32_t reg_PLL_DDR_CFG;
    uint32_t reg_PLL_VGA_CFG;
    uint32_t reg_DIVCFG;
};

static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
        unsigned size)
{
    PUV3PMState *s = opaque;
    uint32_t ret = 0;

    switch (offset) {
    case 0x14:
        ret = s->reg_PCGR;
        break;
    case 0x18:
        ret = s->reg_PLL_SYS_CFG;
        break;
    case 0x1c:
        ret = s->reg_PLL_DDR_CFG;
        break;
    case 0x20:
        ret = s->reg_PLL_VGA_CFG;
        break;
    case 0x24:
        ret = s->reg_DIVCFG;
        break;
    case 0x28: /* PLL SYS STATUS */
        ret = 0x00002401;
        break;
    case 0x2c: /* PLL DDR STATUS */
        ret = 0x00100c00;
        break;
    case 0x30: /* PLL VGA STATUS */
        ret = 0x00003801;
        break;
    case 0x34: /* DIV STATUS */
        ret = 0x22f52015;
        break;
    case 0x38: /* SW RESET */
        ret = 0x0;
        break;
    case 0x44: /* PLL DFC DONE */
        ret = 0x7;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
                      __func__, offset);
    }
    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);

    return ret;
}

static void puv3_pm_write(void *opaque, hwaddr offset,
        uint64_t value, unsigned size)
{
    PUV3PMState *s = opaque;

    switch (offset) {
    case 0x0:
        s->reg_PMCR = value;
        break;
    case 0x14:
        s->reg_PCGR = value;
        break;
    case 0x18:
        s->reg_PLL_SYS_CFG = value;
        break;
    case 0x1c:
        s->reg_PLL_DDR_CFG = value;
        break;
    case 0x20:
        s->reg_PLL_VGA_CFG = value;
        break;
    case 0x24:
    case 0x38:
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
                      __func__, offset);
    }
    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}

static const MemoryRegionOps puv3_pm_ops = {
    .read = puv3_pm_read,
    .write = puv3_pm_write,
    .impl = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void puv3_pm_realize(DeviceState *dev, Error **errp)
{
    PUV3PMState *s = PUV3_PM(dev);

    s->reg_PCGR = 0x0;

    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
            PUV3_REGS_OFFSET);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
}

static void puv3_pm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = puv3_pm_realize;
}

static const TypeInfo puv3_pm_info = {
    .name = TYPE_PUV3_PM,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PUV3PMState),
    .class_init = puv3_pm_class_init,
};

static void puv3_pm_register_type(void)
{
    type_register_static(&puv3_pm_info);
}

type_init(puv3_pm_register_type)
Commit	Line	Data
f716c197 GX	1	/*
	2	* Power Management device simulation in PKUnity SoC
	3	*
	4	* Copyright (C) 2010-2012 Guan Xuetao
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation, or any later version.
	9	* See the COPYING file in the top-level directory.
	10	*/
0b8fa32f	11
5af98cc5	12	#include "qemu/osdep.h"
83c9f4ca	13	#include "hw/sysbus.h"
db1015e9	14	#include "qom/object.h"
f716c197 GX	15
f716c197 GX	16	#undef DEBUG_PUV3
0d09e41a	17	#include "hw/unicore32/puv3.h"
0b8fa32f	18	#include "qemu/module.h"
3b34ee67	19	#include "qemu/log.h"
f716c197	20
af89a444	21	#define TYPE_PUV3_PM "puv3_pm"
db1015e9	22	typedef struct PUV3PMState PUV3PMState;
8110fa1d EH	23	DECLARE_INSTANCE_CHECKER(PUV3PMState, PUV3_PM,
8110fa1d EH	24	TYPE_PUV3_PM)
af89a444	25
db1015e9	26	struct PUV3PMState {
af89a444 AF	27	SysBusDevice parent_obj;
af89a444 AF	28
f716c197 GX	29	MemoryRegion iomem;
	30
	31	uint32_t reg_PMCR;
	32	uint32_t reg_PCGR;
	33	uint32_t reg_PLL_SYS_CFG;
	34	uint32_t reg_PLL_DDR_CFG;
	35	uint32_t reg_PLL_VGA_CFG;
	36	uint32_t reg_DIVCFG;
db1015e9	37	};
f716c197	38
a8170e5e	39	static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
f716c197 GX	40	unsigned size)
	41	{
	42	PUV3PMState *s = opaque;
	43	uint32_t ret = 0;
	44
	45	switch (offset) {
	46	case 0x14:
	47	ret = s->reg_PCGR;
	48	break;
	49	case 0x18:
	50	ret = s->reg_PLL_SYS_CFG;
	51	break;
	52	case 0x1c:
	53	ret = s->reg_PLL_DDR_CFG;
	54	break;
	55	case 0x20:
	56	ret = s->reg_PLL_VGA_CFG;
	57	break;
	58	case 0x24:
	59	ret = s->reg_DIVCFG;
	60	break;
	61	case 0x28: /* PLL SYS STATUS */
	62	ret = 0x00002401;
	63	break;
	64	case 0x2c: /* PLL DDR STATUS */
	65	ret = 0x00100c00;
	66	break;
	67	case 0x30: /* PLL VGA STATUS */
	68	ret = 0x00003801;
	69	break;
	70	case 0x34: /* DIV STATUS */
	71	ret = 0x22f52015;
	72	break;
	73	case 0x38: /* SW RESET */
	74	ret = 0x0;
	75	break;
	76	case 0x44: /* PLL DFC DONE */
	77	ret = 0x7;
	78	break;
	79	default:
3b34ee67 PMD	80	qemu_log_mask(LOG_GUEST_ERROR,
	81	"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
	82	__func__, offset);
f716c197 GX	83	}
	84	DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
	85
	86	return ret;
	87	}
	88
a8170e5e	89	static void puv3_pm_write(void *opaque, hwaddr offset,
f716c197 GX	90	uint64_t value, unsigned size)
	91	{
	92	PUV3PMState *s = opaque;
	93
	94	switch (offset) {
	95	case 0x0:
	96	s->reg_PMCR = value;
	97	break;
	98	case 0x14:
	99	s->reg_PCGR = value;
	100	break;
	101	case 0x18:
	102	s->reg_PLL_SYS_CFG = value;
	103	break;
	104	case 0x1c:
	105	s->reg_PLL_DDR_CFG = value;
	106	break;
	107	case 0x20:
	108	s->reg_PLL_VGA_CFG = value;
	109	break;
	110	case 0x24:
	111	case 0x38:
	112	break;
	113	default:
3b34ee67 PMD	114	qemu_log_mask(LOG_GUEST_ERROR,
	115	"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
	116	__func__, offset);
f716c197 GX	117	}
	118	DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
	119	}
	120
	121	static const MemoryRegionOps puv3_pm_ops = {
	122	.read = puv3_pm_read,
	123	.write = puv3_pm_write,
	124	.impl = {
	125	.min_access_size = 4,
	126	.max_access_size = 4,
	127	},
	128	.endianness = DEVICE_NATIVE_ENDIAN,
	129	};
	130
96cd4594	131	static void puv3_pm_realize(DeviceState dev, Error *errp)
f716c197	132	{
af89a444	133	PUV3PMState *s = PUV3_PM(dev);
f716c197 GX	134
	135	s->reg_PCGR = 0x0;
	136
3c161542	137	memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
f716c197	138	PUV3_REGS_OFFSET);
96cd4594	139	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
f716c197 GX	140	}
	141
	142	static void puv3_pm_class_init(ObjectClass klass, void data)
	143	{
96cd4594	144	DeviceClass *dc = DEVICE_CLASS(klass);
f716c197	145
96cd4594	146	dc->realize = puv3_pm_realize;
f716c197 GX	147	}
	148
	149	static const TypeInfo puv3_pm_info = {
af89a444	150	.name = TYPE_PUV3_PM,
f716c197 GX	151	.parent = TYPE_SYS_BUS_DEVICE,
	152	.instance_size = sizeof(PUV3PMState),
	153	.class_init = puv3_pm_class_init,
	154	};
	155
	156	static void puv3_pm_register_type(void)
	157	{
	158	type_register_static(&puv3_pm_info);
	159	}
	160
	161	type_init(puv3_pm_register_type)