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Commit | Line | Data |
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3475187d FB |
1 | /* |
2 | * QEMU Sparc SLAVIO aux io port emulation | |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
2582cfa0 | 24 | |
0d1c9782 | 25 | #include "qemu/osdep.h" |
9c17d615 | 26 | #include "sysemu/sysemu.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
0b8fa32f | 28 | #include "qemu/module.h" |
97bf4851 | 29 | #include "trace.h" |
3475187d FB |
30 | |
31 | /* | |
32 | * This is the auxio port, chip control and system control part of | |
33 | * chip STP2001 (Slave I/O), also produced as NCR89C105. See | |
34 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt | |
35 | * | |
36 | * This also includes the PMC CPU idle controller. | |
37 | */ | |
38 | ||
95eb2084 AF |
39 | #define TYPE_SLAVIO_MISC "slavio_misc" |
40 | #define SLAVIO_MISC(obj) OBJECT_CHECK(MiscState, (obj), TYPE_SLAVIO_MISC) | |
41 | ||
3475187d | 42 | typedef struct MiscState { |
95eb2084 AF |
43 | SysBusDevice parent_obj; |
44 | ||
dd703aae | 45 | MemoryRegion cfg_iomem; |
96891e59 | 46 | MemoryRegion diag_iomem; |
2e66ac3d | 47 | MemoryRegion mdm_iomem; |
aca23c71 | 48 | MemoryRegion led_iomem; |
cd64a524 | 49 | MemoryRegion sysctrl_iomem; |
cccd43c5 | 50 | MemoryRegion aux1_iomem; |
40ce02fc | 51 | MemoryRegion aux2_iomem; |
d537cf6c | 52 | qemu_irq irq; |
97bbb109 | 53 | qemu_irq fdc_tc; |
d37adb09 | 54 | uint32_t dummy; |
3475187d FB |
55 | uint8_t config; |
56 | uint8_t aux1, aux2; | |
bfa30a38 | 57 | uint8_t diag, mctrl; |
d37adb09 | 58 | uint8_t sysctrl; |
6a3b9cc9 | 59 | uint16_t leds; |
3475187d FB |
60 | } MiscState; |
61 | ||
f1a0a79f AF |
62 | #define TYPE_APC "apc" |
63 | #define APC(obj) OBJECT_CHECK(APCState, (obj), TYPE_APC) | |
64 | ||
2582cfa0 | 65 | typedef struct APCState { |
f1a0a79f AF |
66 | SysBusDevice parent_obj; |
67 | ||
9c48dee6 | 68 | MemoryRegion iomem; |
2582cfa0 BS |
69 | qemu_irq cpu_halt; |
70 | } APCState; | |
71 | ||
5aca8c3b | 72 | #define MISC_SIZE 1 |
0e1cd657 | 73 | #define LED_SIZE 2 |
a8f48dcc | 74 | #define SYSCTRL_SIZE 4 |
3475187d | 75 | |
2be17ebd BS |
76 | #define AUX1_TC 0x02 |
77 | ||
7debeb82 BS |
78 | #define AUX2_PWROFF 0x01 |
79 | #define AUX2_PWRINTCLR 0x02 | |
80 | #define AUX2_PWRFAIL 0x20 | |
81 | ||
82 | #define CFG_PWRINTEN 0x08 | |
83 | ||
84 | #define SYS_RESET 0x01 | |
85 | #define SYS_RESETSTAT 0x02 | |
86 | ||
3475187d FB |
87 | static void slavio_misc_update_irq(void *opaque) |
88 | { | |
89 | MiscState *s = opaque; | |
90 | ||
7debeb82 | 91 | if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) { |
97bf4851 | 92 | trace_slavio_misc_update_irq_raise(); |
d537cf6c | 93 | qemu_irq_raise(s->irq); |
3475187d | 94 | } else { |
97bf4851 | 95 | trace_slavio_misc_update_irq_lower(); |
d537cf6c | 96 | qemu_irq_lower(s->irq); |
3475187d FB |
97 | } |
98 | } | |
99 | ||
1795057a | 100 | static void slavio_misc_reset(DeviceState *d) |
3475187d | 101 | { |
95eb2084 | 102 | MiscState *s = SLAVIO_MISC(d); |
3475187d | 103 | |
4e3b1ea1 | 104 | // Diagnostic and system control registers not cleared in reset |
3475187d FB |
105 | s->config = s->aux1 = s->aux2 = s->mctrl = 0; |
106 | } | |
107 | ||
b2b6f6ec | 108 | static void slavio_set_power_fail(void *opaque, int irq, int power_failing) |
3475187d FB |
109 | { |
110 | MiscState *s = opaque; | |
111 | ||
97bf4851 | 112 | trace_slavio_set_power_fail(power_failing, s->config); |
7debeb82 BS |
113 | if (power_failing && (s->config & CFG_PWRINTEN)) { |
114 | s->aux2 |= AUX2_PWRFAIL; | |
3475187d | 115 | } else { |
7debeb82 | 116 | s->aux2 &= ~AUX2_PWRFAIL; |
3475187d FB |
117 | } |
118 | slavio_misc_update_irq(s); | |
119 | } | |
120 | ||
a8170e5e | 121 | static void slavio_cfg_mem_writeb(void *opaque, hwaddr addr, |
dd703aae | 122 | uint64_t val, unsigned size) |
a8f48dcc BS |
123 | { |
124 | MiscState *s = opaque; | |
125 | ||
97bf4851 | 126 | trace_slavio_cfg_mem_writeb(val & 0xff); |
a8f48dcc BS |
127 | s->config = val & 0xff; |
128 | slavio_misc_update_irq(s); | |
129 | } | |
130 | ||
a8170e5e | 131 | static uint64_t slavio_cfg_mem_readb(void *opaque, hwaddr addr, |
dd703aae | 132 | unsigned size) |
a8f48dcc BS |
133 | { |
134 | MiscState *s = opaque; | |
135 | uint32_t ret = 0; | |
136 | ||
137 | ret = s->config; | |
97bf4851 | 138 | trace_slavio_cfg_mem_readb(ret); |
a8f48dcc BS |
139 | return ret; |
140 | } | |
141 | ||
dd703aae BC |
142 | static const MemoryRegionOps slavio_cfg_mem_ops = { |
143 | .read = slavio_cfg_mem_readb, | |
144 | .write = slavio_cfg_mem_writeb, | |
145 | .endianness = DEVICE_NATIVE_ENDIAN, | |
146 | .valid = { | |
147 | .min_access_size = 1, | |
148 | .max_access_size = 1, | |
149 | }, | |
a8f48dcc BS |
150 | }; |
151 | ||
a8170e5e | 152 | static void slavio_diag_mem_writeb(void *opaque, hwaddr addr, |
96891e59 | 153 | uint64_t val, unsigned size) |
3475187d FB |
154 | { |
155 | MiscState *s = opaque; | |
156 | ||
97bf4851 | 157 | trace_slavio_diag_mem_writeb(val & 0xff); |
a8f48dcc | 158 | s->diag = val & 0xff; |
3475187d FB |
159 | } |
160 | ||
a8170e5e | 161 | static uint64_t slavio_diag_mem_readb(void *opaque, hwaddr addr, |
96891e59 | 162 | unsigned size) |
3475187d FB |
163 | { |
164 | MiscState *s = opaque; | |
165 | uint32_t ret = 0; | |
166 | ||
a8f48dcc | 167 | ret = s->diag; |
97bf4851 | 168 | trace_slavio_diag_mem_readb(ret); |
a8f48dcc BS |
169 | return ret; |
170 | } | |
171 | ||
96891e59 BC |
172 | static const MemoryRegionOps slavio_diag_mem_ops = { |
173 | .read = slavio_diag_mem_readb, | |
174 | .write = slavio_diag_mem_writeb, | |
175 | .endianness = DEVICE_NATIVE_ENDIAN, | |
176 | .valid = { | |
177 | .min_access_size = 1, | |
178 | .max_access_size = 1, | |
179 | }, | |
a8f48dcc BS |
180 | }; |
181 | ||
a8170e5e | 182 | static void slavio_mdm_mem_writeb(void *opaque, hwaddr addr, |
2e66ac3d | 183 | uint64_t val, unsigned size) |
a8f48dcc BS |
184 | { |
185 | MiscState *s = opaque; | |
186 | ||
97bf4851 | 187 | trace_slavio_mdm_mem_writeb(val & 0xff); |
a8f48dcc BS |
188 | s->mctrl = val & 0xff; |
189 | } | |
190 | ||
a8170e5e | 191 | static uint64_t slavio_mdm_mem_readb(void *opaque, hwaddr addr, |
2e66ac3d | 192 | unsigned size) |
a8f48dcc BS |
193 | { |
194 | MiscState *s = opaque; | |
195 | uint32_t ret = 0; | |
196 | ||
197 | ret = s->mctrl; | |
97bf4851 | 198 | trace_slavio_mdm_mem_readb(ret); |
3475187d FB |
199 | return ret; |
200 | } | |
201 | ||
2e66ac3d BC |
202 | static const MemoryRegionOps slavio_mdm_mem_ops = { |
203 | .read = slavio_mdm_mem_readb, | |
204 | .write = slavio_mdm_mem_writeb, | |
205 | .endianness = DEVICE_NATIVE_ENDIAN, | |
206 | .valid = { | |
207 | .min_access_size = 1, | |
208 | .max_access_size = 1, | |
209 | }, | |
3475187d FB |
210 | }; |
211 | ||
a8170e5e | 212 | static void slavio_aux1_mem_writeb(void *opaque, hwaddr addr, |
cccd43c5 | 213 | uint64_t val, unsigned size) |
0019ad53 BS |
214 | { |
215 | MiscState *s = opaque; | |
216 | ||
97bf4851 | 217 | trace_slavio_aux1_mem_writeb(val & 0xff); |
2be17ebd BS |
218 | if (val & AUX1_TC) { |
219 | // Send a pulse to floppy terminal count line | |
220 | if (s->fdc_tc) { | |
221 | qemu_irq_raise(s->fdc_tc); | |
222 | qemu_irq_lower(s->fdc_tc); | |
223 | } | |
224 | val &= ~AUX1_TC; | |
225 | } | |
0019ad53 BS |
226 | s->aux1 = val & 0xff; |
227 | } | |
228 | ||
a8170e5e | 229 | static uint64_t slavio_aux1_mem_readb(void *opaque, hwaddr addr, |
cccd43c5 | 230 | unsigned size) |
0019ad53 BS |
231 | { |
232 | MiscState *s = opaque; | |
233 | uint32_t ret = 0; | |
234 | ||
235 | ret = s->aux1; | |
97bf4851 | 236 | trace_slavio_aux1_mem_readb(ret); |
0019ad53 BS |
237 | return ret; |
238 | } | |
239 | ||
cccd43c5 BC |
240 | static const MemoryRegionOps slavio_aux1_mem_ops = { |
241 | .read = slavio_aux1_mem_readb, | |
242 | .write = slavio_aux1_mem_writeb, | |
243 | .endianness = DEVICE_NATIVE_ENDIAN, | |
244 | .valid = { | |
245 | .min_access_size = 1, | |
246 | .max_access_size = 1, | |
247 | }, | |
0019ad53 BS |
248 | }; |
249 | ||
a8170e5e | 250 | static void slavio_aux2_mem_writeb(void *opaque, hwaddr addr, |
40ce02fc | 251 | uint64_t val, unsigned size) |
0019ad53 BS |
252 | { |
253 | MiscState *s = opaque; | |
254 | ||
255 | val &= AUX2_PWRINTCLR | AUX2_PWROFF; | |
97bf4851 | 256 | trace_slavio_aux2_mem_writeb(val & 0xff); |
0019ad53 BS |
257 | val |= s->aux2 & AUX2_PWRFAIL; |
258 | if (val & AUX2_PWRINTCLR) // Clear Power Fail int | |
259 | val &= AUX2_PWROFF; | |
260 | s->aux2 = val; | |
261 | if (val & AUX2_PWROFF) | |
cf83f140 | 262 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
0019ad53 BS |
263 | slavio_misc_update_irq(s); |
264 | } | |
265 | ||
a8170e5e | 266 | static uint64_t slavio_aux2_mem_readb(void *opaque, hwaddr addr, |
40ce02fc | 267 | unsigned size) |
0019ad53 BS |
268 | { |
269 | MiscState *s = opaque; | |
270 | uint32_t ret = 0; | |
271 | ||
272 | ret = s->aux2; | |
97bf4851 | 273 | trace_slavio_aux2_mem_readb(ret); |
0019ad53 BS |
274 | return ret; |
275 | } | |
276 | ||
40ce02fc BC |
277 | static const MemoryRegionOps slavio_aux2_mem_ops = { |
278 | .read = slavio_aux2_mem_readb, | |
279 | .write = slavio_aux2_mem_writeb, | |
280 | .endianness = DEVICE_NATIVE_ENDIAN, | |
281 | .valid = { | |
282 | .min_access_size = 1, | |
283 | .max_access_size = 1, | |
284 | }, | |
0019ad53 BS |
285 | }; |
286 | ||
a8170e5e | 287 | static void apc_mem_writeb(void *opaque, hwaddr addr, |
9c48dee6 | 288 | uint64_t val, unsigned size) |
0019ad53 | 289 | { |
2582cfa0 | 290 | APCState *s = opaque; |
0019ad53 | 291 | |
97bf4851 | 292 | trace_apc_mem_writeb(val & 0xff); |
6d0c293d | 293 | qemu_irq_raise(s->cpu_halt); |
0019ad53 BS |
294 | } |
295 | ||
a8170e5e | 296 | static uint64_t apc_mem_readb(void *opaque, hwaddr addr, |
9c48dee6 | 297 | unsigned size) |
0019ad53 BS |
298 | { |
299 | uint32_t ret = 0; | |
300 | ||
97bf4851 | 301 | trace_apc_mem_readb(ret); |
0019ad53 BS |
302 | return ret; |
303 | } | |
304 | ||
9c48dee6 BC |
305 | static const MemoryRegionOps apc_mem_ops = { |
306 | .read = apc_mem_readb, | |
307 | .write = apc_mem_writeb, | |
308 | .endianness = DEVICE_NATIVE_ENDIAN, | |
309 | .valid = { | |
310 | .min_access_size = 1, | |
311 | .max_access_size = 1, | |
312 | } | |
0019ad53 BS |
313 | }; |
314 | ||
a8170e5e | 315 | static uint64_t slavio_sysctrl_mem_readl(void *opaque, hwaddr addr, |
cd64a524 | 316 | unsigned size) |
bfa30a38 BS |
317 | { |
318 | MiscState *s = opaque; | |
a8f48dcc | 319 | uint32_t ret = 0; |
bfa30a38 | 320 | |
a8f48dcc | 321 | switch (addr) { |
bfa30a38 BS |
322 | case 0: |
323 | ret = s->sysctrl; | |
324 | break; | |
325 | default: | |
326 | break; | |
327 | } | |
97bf4851 | 328 | trace_slavio_sysctrl_mem_readl(ret); |
bfa30a38 BS |
329 | return ret; |
330 | } | |
331 | ||
a8170e5e | 332 | static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr, |
cd64a524 | 333 | uint64_t val, unsigned size) |
bfa30a38 BS |
334 | { |
335 | MiscState *s = opaque; | |
bfa30a38 | 336 | |
97bf4851 | 337 | trace_slavio_sysctrl_mem_writel(val); |
a8f48dcc | 338 | switch (addr) { |
bfa30a38 | 339 | case 0: |
7debeb82 BS |
340 | if (val & SYS_RESET) { |
341 | s->sysctrl = SYS_RESETSTAT; | |
cf83f140 | 342 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
bfa30a38 BS |
343 | } |
344 | break; | |
345 | default: | |
346 | break; | |
347 | } | |
348 | } | |
349 | ||
cd64a524 BC |
350 | static const MemoryRegionOps slavio_sysctrl_mem_ops = { |
351 | .read = slavio_sysctrl_mem_readl, | |
352 | .write = slavio_sysctrl_mem_writel, | |
353 | .endianness = DEVICE_NATIVE_ENDIAN, | |
354 | .valid = { | |
355 | .min_access_size = 4, | |
356 | .max_access_size = 4, | |
357 | }, | |
bfa30a38 BS |
358 | }; |
359 | ||
a8170e5e | 360 | static uint64_t slavio_led_mem_readw(void *opaque, hwaddr addr, |
aca23c71 | 361 | unsigned size) |
6a3b9cc9 BS |
362 | { |
363 | MiscState *s = opaque; | |
a8f48dcc | 364 | uint32_t ret = 0; |
6a3b9cc9 | 365 | |
a8f48dcc | 366 | switch (addr) { |
6a3b9cc9 BS |
367 | case 0: |
368 | ret = s->leds; | |
369 | break; | |
370 | default: | |
371 | break; | |
372 | } | |
97bf4851 | 373 | trace_slavio_led_mem_readw(ret); |
6a3b9cc9 BS |
374 | return ret; |
375 | } | |
376 | ||
a8170e5e | 377 | static void slavio_led_mem_writew(void *opaque, hwaddr addr, |
aca23c71 | 378 | uint64_t val, unsigned size) |
6a3b9cc9 BS |
379 | { |
380 | MiscState *s = opaque; | |
6a3b9cc9 | 381 | |
f3a64b8c | 382 | trace_slavio_led_mem_writew(val & 0xffff); |
a8f48dcc | 383 | switch (addr) { |
6a3b9cc9 | 384 | case 0: |
d5296cb5 | 385 | s->leds = val; |
6a3b9cc9 BS |
386 | break; |
387 | default: | |
388 | break; | |
389 | } | |
390 | } | |
391 | ||
aca23c71 BC |
392 | static const MemoryRegionOps slavio_led_mem_ops = { |
393 | .read = slavio_led_mem_readw, | |
394 | .write = slavio_led_mem_writew, | |
395 | .endianness = DEVICE_NATIVE_ENDIAN, | |
396 | .valid = { | |
397 | .min_access_size = 2, | |
398 | .max_access_size = 2, | |
399 | }, | |
6a3b9cc9 BS |
400 | }; |
401 | ||
d37adb09 BS |
402 | static const VMStateDescription vmstate_misc = { |
403 | .name ="slavio_misc", | |
404 | .version_id = 1, | |
405 | .minimum_version_id = 1, | |
35d08458 | 406 | .fields = (VMStateField[]) { |
d37adb09 BS |
407 | VMSTATE_UINT32(dummy, MiscState), |
408 | VMSTATE_UINT8(config, MiscState), | |
409 | VMSTATE_UINT8(aux1, MiscState), | |
410 | VMSTATE_UINT8(aux2, MiscState), | |
411 | VMSTATE_UINT8(diag, MiscState), | |
412 | VMSTATE_UINT8(mctrl, MiscState), | |
413 | VMSTATE_UINT8(sysctrl, MiscState), | |
414 | VMSTATE_END_OF_LIST() | |
415 | } | |
416 | }; | |
3475187d | 417 | |
46eedc0e | 418 | static void apc_init(Object *obj) |
2582cfa0 | 419 | { |
46eedc0e XZ |
420 | APCState *s = APC(obj); |
421 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
3475187d | 422 | |
2582cfa0 BS |
423 | sysbus_init_irq(dev, &s->cpu_halt); |
424 | ||
425 | /* Power management (APC) XXX: not a Slavio device */ | |
46eedc0e | 426 | memory_region_init_io(&s->iomem, obj, &apc_mem_ops, s, |
9c48dee6 | 427 | "apc", MISC_SIZE); |
750ecd44 | 428 | sysbus_init_mmio(dev, &s->iomem); |
2582cfa0 BS |
429 | } |
430 | ||
46eedc0e | 431 | static void slavio_misc_init(Object *obj) |
2582cfa0 | 432 | { |
46eedc0e XZ |
433 | DeviceState *dev = DEVICE(obj); |
434 | MiscState *s = SLAVIO_MISC(obj); | |
435 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
2582cfa0 | 436 | |
95eb2084 AF |
437 | sysbus_init_irq(sbd, &s->irq); |
438 | sysbus_init_irq(sbd, &s->fdc_tc); | |
2582cfa0 BS |
439 | |
440 | /* 8 bit registers */ | |
441 | /* Slavio control */ | |
46eedc0e | 442 | memory_region_init_io(&s->cfg_iomem, obj, &slavio_cfg_mem_ops, s, |
dd703aae | 443 | "configuration", MISC_SIZE); |
95eb2084 | 444 | sysbus_init_mmio(sbd, &s->cfg_iomem); |
2582cfa0 BS |
445 | |
446 | /* Diagnostics */ | |
46eedc0e | 447 | memory_region_init_io(&s->diag_iomem, obj, &slavio_diag_mem_ops, s, |
96891e59 | 448 | "diagnostic", MISC_SIZE); |
95eb2084 | 449 | sysbus_init_mmio(sbd, &s->diag_iomem); |
2582cfa0 BS |
450 | |
451 | /* Modem control */ | |
46eedc0e | 452 | memory_region_init_io(&s->mdm_iomem, obj, &slavio_mdm_mem_ops, s, |
2e66ac3d | 453 | "modem", MISC_SIZE); |
95eb2084 | 454 | sysbus_init_mmio(sbd, &s->mdm_iomem); |
2582cfa0 BS |
455 | |
456 | /* 16 bit registers */ | |
457 | /* ss600mp diag LEDs */ | |
46eedc0e | 458 | memory_region_init_io(&s->led_iomem, obj, &slavio_led_mem_ops, s, |
0e1cd657 | 459 | "leds", LED_SIZE); |
95eb2084 | 460 | sysbus_init_mmio(sbd, &s->led_iomem); |
2582cfa0 BS |
461 | |
462 | /* 32 bit registers */ | |
463 | /* System control */ | |
46eedc0e | 464 | memory_region_init_io(&s->sysctrl_iomem, obj, &slavio_sysctrl_mem_ops, s, |
0e1cd657 | 465 | "system-control", SYSCTRL_SIZE); |
95eb2084 | 466 | sysbus_init_mmio(sbd, &s->sysctrl_iomem); |
2582cfa0 BS |
467 | |
468 | /* AUX 1 (Misc System Functions) */ | |
46eedc0e | 469 | memory_region_init_io(&s->aux1_iomem, obj, &slavio_aux1_mem_ops, s, |
cccd43c5 | 470 | "misc-system-functions", MISC_SIZE); |
95eb2084 | 471 | sysbus_init_mmio(sbd, &s->aux1_iomem); |
2582cfa0 BS |
472 | |
473 | /* AUX 2 (Software Powerdown Control) */ | |
46eedc0e | 474 | memory_region_init_io(&s->aux2_iomem, obj, &slavio_aux2_mem_ops, s, |
40ce02fc | 475 | "software-powerdown-control", MISC_SIZE); |
95eb2084 | 476 | sysbus_init_mmio(sbd, &s->aux2_iomem); |
2582cfa0 | 477 | |
95eb2084 | 478 | qdev_init_gpio_in(dev, slavio_set_power_fail, 1); |
2582cfa0 | 479 | } |
0019ad53 | 480 | |
999e12bb AL |
481 | static void slavio_misc_class_init(ObjectClass *klass, void *data) |
482 | { | |
39bffca2 | 483 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 484 | |
39bffca2 AL |
485 | dc->reset = slavio_misc_reset; |
486 | dc->vmsd = &vmstate_misc; | |
999e12bb AL |
487 | } |
488 | ||
8c43a6f0 | 489 | static const TypeInfo slavio_misc_info = { |
95eb2084 | 490 | .name = TYPE_SLAVIO_MISC, |
39bffca2 AL |
491 | .parent = TYPE_SYS_BUS_DEVICE, |
492 | .instance_size = sizeof(MiscState), | |
46eedc0e | 493 | .instance_init = slavio_misc_init, |
39bffca2 | 494 | .class_init = slavio_misc_class_init, |
2582cfa0 BS |
495 | }; |
496 | ||
8c43a6f0 | 497 | static const TypeInfo apc_info = { |
f1a0a79f | 498 | .name = TYPE_APC, |
39bffca2 AL |
499 | .parent = TYPE_SYS_BUS_DEVICE, |
500 | .instance_size = sizeof(MiscState), | |
46eedc0e | 501 | .instance_init = apc_init, |
2582cfa0 BS |
502 | }; |
503 | ||
83f7d43a | 504 | static void slavio_misc_register_types(void) |
2582cfa0 | 505 | { |
39bffca2 AL |
506 | type_register_static(&slavio_misc_info); |
507 | type_register_static(&apc_info); | |
3475187d | 508 | } |
2582cfa0 | 509 | |
83f7d43a | 510 | type_init(slavio_misc_register_types) |