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Commit | Line | Data |
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d0fb9657 | 1 | # See docs/devel/tracing.rst for syntax documentation. |
6b5bacf6 | 2 | |
d26af5de | 3 | # allwinner-cpucfg.c |
2539eade | 4 | allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32 |
d26af5de NL |
5 | allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
6 | allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
6556617c | 7 | |
b71d0385 NL |
8 | # allwinner-h3-dramc.c |
9 | allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror" | |
10 | allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64 | |
11 | allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
12 | allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
13 | allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
14 | allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
15 | allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
16 | allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
17 | ||
4a52ef61 Z |
18 | # allwinner-r40-dramc.c |
19 | allwinner_r40_dramc_detect_cells_disable(void) "Disable detect cells" | |
20 | allwinner_r40_dramc_detect_cells_enable(void) "Enable detect cells" | |
21 | allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) "DRAM layout: row_bits %d, bank_bits %d, col_bits %d" | |
22 | allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d bank %d col %d" | |
23 | allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 "" | |
24 | allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 "" | |
25 | allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
26 | allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
27 | allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
28 | allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
29 | allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
30 | allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
31 | ||
6556617c NL |
32 | # allwinner-sid.c |
33 | allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
34 | allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | |
d26af5de | 35 | |
05def917 Z |
36 | # allwinner-sramc.c |
37 | allwinner_sramc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 | |
38 | allwinner_sramc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 | |
39 | ||
dc288de0 MR |
40 | # avr_power.c |
41 | avr_power_read(uint8_t value) "power_reduc read value:%u" | |
42 | avr_power_write(uint8_t value) "power_reduc write value:%u" | |
43 | ||
a9545430 Z |
44 | # axp2xx |
45 | axp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8 | |
46 | axp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8 | |
47 | axp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8 | |
632dfea3 | 48 | |
500016e5 | 49 | # eccmemctl.c |
8908eb1a VSO |
50 | ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" |
51 | ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" | |
52 | ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status 0x%08x" | |
53 | ecc_mem_writel_vcr(uint32_t val) "Write slot configuration 0x%08x" | |
54 | ecc_mem_writel_dr(uint32_t val) "Write diagnostic 0x%08x" | |
55 | ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 0x%08x" | |
56 | ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 0x%08x" | |
57 | ecc_mem_readl_mer(uint32_t ret) "Read memory enable 0x%08x" | |
58 | ecc_mem_readl_mdr(uint32_t ret) "Read memory delay 0x%08x" | |
59 | ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status 0x%08x" | |
60 | ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration 0x%08x" | |
61 | ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 0x%08x" | |
62 | ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 0x%08x" | |
63 | ecc_mem_readl_dr(uint32_t ret) "Read diagnostic 0x%08x" | |
64 | ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 0x%08x" | |
65 | ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 0x%08x" | |
66 | ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = 0x%02x" | |
67 | ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= 0x%02x" | |
6b5bacf6 | 68 | |
6007523a | 69 | # empty_slot.c |
6007523a PMD |
70 | empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]" |
71 | ||
500016e5 | 72 | # slavio_misc.c |
6b5bacf6 DB |
73 | slavio_misc_update_irq_raise(void) "Raise IRQ" |
74 | slavio_misc_update_irq_lower(void) "Lower IRQ" | |
75 | slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" | |
8908eb1a VSO |
76 | slavio_cfg_mem_writeb(uint32_t val) "Write config 0x%02x" |
77 | slavio_cfg_mem_readb(uint32_t ret) "Read config 0x%02x" | |
78 | slavio_diag_mem_writeb(uint32_t val) "Write diag 0x%02x" | |
79 | slavio_diag_mem_readb(uint32_t ret) "Read diag 0x%02x" | |
80 | slavio_mdm_mem_writeb(uint32_t val) "Write modem control 0x%02x" | |
81 | slavio_mdm_mem_readb(uint32_t ret) "Read modem control 0x%02x" | |
82 | slavio_aux1_mem_writeb(uint32_t val) "Write aux1 0x%02x" | |
83 | slavio_aux1_mem_readb(uint32_t ret) "Read aux1 0x%02x" | |
84 | slavio_aux2_mem_writeb(uint32_t val) "Write aux2 0x%02x" | |
85 | slavio_aux2_mem_readb(uint32_t ret) "Read aux2 0x%02x" | |
86 | apc_mem_writeb(uint32_t val) "Write power management 0x%02x" | |
87 | apc_mem_readb(uint32_t ret) "Read power management 0x%02x" | |
88 | slavio_sysctrl_mem_writel(uint32_t val) "Write system control 0x%08x" | |
89 | slavio_sysctrl_mem_readl(uint32_t ret) "Read system control 0x%08x" | |
90 | slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x" | |
91 | slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x" | |
6b5bacf6 | 92 | |
500016e5 | 93 | # aspeed_scu.c |
1c8a2388 | 94 | aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
673a6d16 | 95 | aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
dd73185b | 96 | |
dec97760 | 97 | # mps2-scc.c |
dd73185b PM |
98 | mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
99 | mps2_scc_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | |
100 | mps2_scc_reset(void) "MPS2 SCC: reset" | |
dd73185b PM |
101 | mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 |
102 | mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 | |
0ee1e1f4 | 103 | |
dec97760 | 104 | # mps2-fpgaio.c |
9a52d999 PM |
105 | mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
106 | mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | |
107 | mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" | |
9a52d999 | 108 | |
500016e5 | 109 | # msf2-sysreg.c |
787bbc30 DB |
110 | msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 |
111 | msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 | |
0ee1e1f4 | 112 | msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register" |
30b2f870 | 113 | |
500016e5 | 114 | # imx7_gpr.c |
787bbc30 DB |
115 | imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 |
116 | imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64 | |
51f233ec | 117 | |
500016e5 | 118 | # mos6522.c |
51f233ec | 119 | mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" |
2539eade | 120 | mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 |
51f233ec | 121 | mos6522_set_sr_int(void) "set sr_int" |
6c726698 MCA |
122 | mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 |
123 | mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x" | |
9eb8040c | 124 | |
e331f79e HS |
125 | # npcm7xx_clk.c |
126 | npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | |
127 | npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | |
128 | ||
e5a7ba87 HS |
129 | # npcm7xx_gcr.c |
130 | npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | |
131 | npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | |
132 | ||
380a37e4 HW |
133 | # npcm7xx_mft.c |
134 | npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 | |
135 | npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 | |
136 | npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32 | |
137 | npcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d" | |
138 | npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64 | |
139 | npcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d" | |
140 | ||
326ccfe2 HS |
141 | # npcm7xx_rng.c |
142 | npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" | |
143 | npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" | |
144 | ||
1e943c58 HW |
145 | # npcm7xx_pwm.c |
146 | npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | |
147 | npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | |
148 | npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" | |
149 | npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" | |
150 | ||
b15e402f | 151 | # stm32f4xx_syscfg.c |
cba42d61 | 152 | stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d" |
870c034d AF |
153 | stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" |
154 | stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " | |
155 | stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" | |
156 | ||
b15e402f | 157 | # stm32f4xx_exti.c |
9b4b4e51 | 158 | stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d" |
e64d8c83 AF |
159 | stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " |
160 | stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" | |
161 | ||
500016e5 | 162 | # tz-mpc.c |
344f4b15 PM |
163 | tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" |
164 | tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" | |
165 | tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d" | |
166 | tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" | |
167 | tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s" | |
dd29d068 | 168 | tz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64 |
344f4b15 | 169 | |
500016e5 | 170 | # tz-msc.c |
211e701d PM |
171 | tz_msc_reset(void) "TZ MSC: reset" |
172 | tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d" | |
173 | tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d" | |
211e701d PM |
174 | tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d" |
175 | tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d" | |
176 | tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked" | |
177 | ||
500016e5 | 178 | # tz-ppc.c |
9eb8040c PM |
179 | tz_ppc_reset(void) "TZ PPC: reset" |
180 | tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" | |
181 | tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" | |
182 | tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" | |
183 | tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" | |
184 | tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | |
185 | tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | |
f32408f3 DB |
186 | tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked" |
187 | tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked" | |
de343bb6 | 188 | |
500016e5 | 189 | # iotkit-secctl.c |
de343bb6 PM |
190 | iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" |
191 | iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" | |
192 | iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" | |
193 | iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" | |
781182e1 | 194 | |
500016e5 | 195 | # imx6ul_ccm.c |
794dcb54 PMD |
196 | ccm_entry(void) "" |
197 | ccm_freq(uint32_t freq) "freq = %d" | |
198 | ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" | |
199 | ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | |
200 | ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | |
75750e4d | 201 | |
12517bc9 JCD |
202 | # imx7_src.c |
203 | imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | |
204 | imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | |
205 | ||
dec97760 | 206 | # iotkit-sysinfo.c |
75750e4d PM |
207 | iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
208 | iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | |
dec97760 MA |
209 | |
210 | # iotkit-sysctl.c | |
75750e4d PM |
211 | iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
212 | iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | |
213 | iotkit_sysctl_reset(void) "IoTKit SysCtl: reset" | |
5aeb3689 | 214 | |
4239b311 PM |
215 | # armsse-cpu-pwrctrl.c |
216 | armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | |
217 | armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | |
218 | ||
500016e5 | 219 | # armsse-cpuid.c |
5aeb3689 PM |
220 | armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
221 | armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | |
cdf63440 | 222 | |
500016e5 | 223 | # armsse-mhu.c |
cdf63440 PM |
224 | armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
225 | armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | |
118c82e7 EJ |
226 | |
227 | # aspeed_xdma.c | |
228 | aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 | |
19845504 | 229 | |
119df56b TL |
230 | # aspeed_i3c.c |
231 | aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 | |
232 | aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 | |
233 | aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 | |
234 | aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 | |
235 | ||
3671342a CLG |
236 | # aspeed_sdmc.c |
237 | aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 | |
238 | aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 | |
239 | ||
55c57023 PD |
240 | # aspeed_peci.c |
241 | aspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 | |
242 | aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 | |
243 | aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32 | |
244 | ||
b15e402f MA |
245 | # bcm2835_property.c |
246 | bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" | |
247 | ||
19845504 PMD |
248 | # bcm2835_mbox.c |
249 | bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 | |
250 | bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 | |
251 | bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u" | |
b2619c15 LV |
252 | |
253 | # mac_via.c | |
254 | via1_rtc_update_data_out(int count, int value) "count=%d value=0x%02x" | |
255 | via1_rtc_update_data_in(int count, int value) "count=%d value=0x%02x" | |
256 | via1_rtc_internal_status(int cmd, int alt, int value) "cmd=0x%02x alt=0x%02x value=0x%02x" | |
257 | via1_rtc_internal_cmd(int cmd) "cmd=0x%02x" | |
258 | via1_rtc_cmd_invalid(int value) "value=0x%02x" | |
259 | via1_rtc_internal_time(uint32_t time) "time=0x%08x" | |
260 | via1_rtc_internal_set_cmd(int cmd) "cmd=0x%02x" | |
261 | via1_rtc_internal_ignore_cmd(int cmd) "cmd=0x%02x" | |
262 | via1_rtc_internal_set_alt(int alt, int sector, int offset) "alt=0x%02x sector=%u offset=%u" | |
263 | via1_rtc_cmd_seconds_read(int reg, int value) "reg=%d value=0x%02x" | |
264 | via1_rtc_cmd_seconds_write(int reg, int value) "reg=%d value=0x%02x" | |
265 | via1_rtc_cmd_test_write(int value) "value=0x%02x" | |
266 | via1_rtc_cmd_wprotect_write(int value) "value=0x%02x" | |
267 | via1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x" | |
268 | via1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x" | |
935cac9c MCA |
269 | via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" |
270 | via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" | |
975fcedd MCA |
271 | via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s" |
272 | via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" | |
273 | via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" | |
20069049 | 274 | via1_adb_netbsd_enum_hack(void) "using NetBSD enum hack" |
291bc180 | 275 | via1_auxmode(int mode) "setting auxmode to %d" |
366d2779 | 276 | via1_timer_hack_state(int state) "setting timer_hack_state to %d" |
d15188dd PMD |
277 | |
278 | # grlib_ahb_apb_pnp.c | |
09d12c81 PM |
279 | grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" |
280 | grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" | |
b989b89f | 281 | |
c1b29826 PMD |
282 | # led.c |
283 | led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%" | |
4aef4399 | 284 | led_change_intensity(const char *color, const char *desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) "LED desc:'%s' color:%s intensity %u%% -> %u%%" |
c1b29826 | 285 | |
b989b89f PMD |
286 | # pca9552.c |
287 | pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]" | |
d82ab293 | 288 | pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u" |
fc14176b LM |
289 | |
290 | # bcm2835_cprman.c | |
291 | bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 | |
292 | bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 | |
293 | bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 | |
0791bc02 LV |
294 | |
295 | # virt_ctrl.c | |
296 | virt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 | |
297 | virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 | |
298 | virt_ctrl_reset(void *dev) "ctrl: %p" | |
299 | virt_ctrl_realize(void *dev) "ctrl: %p" | |
300 | virt_ctrl_instance_init(void *dev) "ctrl: %p" | |
45f569a1 MCA |
301 | |
302 | # lasi.c | |
303 | lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" | |
304 | lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" | |
305 | lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" | |
e2fd695e MCA |
306 | |
307 | # djmemc.c | |
308 | djmemc_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" | |
309 | djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" | |
bdc2c77d MCA |
310 | |
311 | # iosb.c | |
312 | iosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" | |
313 | iosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" |