[mirror_qemu.git] / hw / msix.c

/*
 * MSI-X device support
 *
 * This module includes support for MSI-X in pci devices.
 *
 * Author: Michael S. Tsirkin <mst@redhat.com>
 *
 *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */

#include "hw.h"
#include "msix.h"
#include "pci.h"

/* MSI-X capability structure */
#define MSIX_TABLE_OFFSET 4
#define MSIX_PBA_OFFSET 8
#define MSIX_CAP_LENGTH 12

/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)

/* MSI-X table format */
#define MSIX_MSG_ADDR 0
#define MSIX_MSG_UPPER_ADDR 4
#define MSIX_MSG_DATA 8
#define MSIX_VECTOR_CTRL 12
#define MSIX_ENTRY_SIZE 16
#define MSIX_VECTOR_MASK 0x1

/* How much space does an MSIX table need. */
/* The spec requires giving the table structure
 * a 4K aligned region all by itself. */
#define MSIX_PAGE_SIZE 0x1000
/* Reserve second half of the page for pending bits */
#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
#define MSIX_MAX_ENTRIES 32


#ifdef MSIX_DEBUG
#define DEBUG(fmt, ...)                                       \
    do {                                                      \
      fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__);    \
    } while (0)
#else
#define DEBUG(fmt, ...) do { } while(0)
#endif

/* Flag for interrupt controller to declare MSI-X support */
int msix_supported;

/* Add MSI-X capability to the config space for the device. */
/* Given a bar and its size, add MSI-X table on top of it
 * and fill MSI-X capability in the config space.
 * Original bar size must be a power of 2 or 0.
 * New bar size is returned. */
static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
                           unsigned bar_nr, unsigned bar_size)
{
    int config_offset;
    uint8_t *config;
    uint32_t new_size;

    if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
        return -EINVAL;
    if (bar_size > 0x80000000)
        return -ENOSPC;

    /* Add space for MSI-X structures */
    if (!bar_size) {
        new_size = MSIX_PAGE_SIZE;
    } else if (bar_size < MSIX_PAGE_SIZE) {
        bar_size = MSIX_PAGE_SIZE;
        new_size = MSIX_PAGE_SIZE * 2;
    } else {
        new_size = bar_size * 2;
    }

    pdev->msix_bar_size = new_size;
    config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    if (config_offset < 0)
        return config_offset;
    config = pdev->config + config_offset;

    pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
    /* Table on top of BAR */
    pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
    /* Pending bits on top of that */
    pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
                 bar_nr);
    pdev->msix_cap = config_offset;
    /* Make flags bit writeable. */
    pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
	    MSIX_MASKALL_MASK;
    return 0;
}

static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    void *page = dev->msix_table_page;

    return pci_get_long(page + offset);
}

static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
{
    fprintf(stderr, "MSI-X: only dword read is allowed!\n");
    return 0;
}

static uint8_t msix_pending_mask(int vector)
{
    return 1 << (vector % 8);
}

static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
{
    return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
}

static int msix_is_pending(PCIDevice *dev, int vector)
{
    return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
}

static void msix_set_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
}

static void msix_clr_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
}

static int msix_function_masked(PCIDevice *dev)
{
    return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
}

static int msix_is_masked(PCIDevice *dev, int vector)
{
    unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
    return msix_function_masked(dev) ||
	   dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
}

static void msix_handle_mask_update(PCIDevice *dev, int vector)
{
    if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
        msix_clr_pending(dev, vector);
        msix_notify(dev, vector);
    }
}

/* Handle MSI-X capability config write. */
void msix_write_config(PCIDevice *dev, uint32_t addr,
                       uint32_t val, int len)
{
    unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
    int vector;

    if (!range_covers_byte(addr, len, enable_pos)) {
        return;
    }

    if (!msix_enabled(dev)) {
        return;
    }

    qemu_set_irq(dev->irq[0], 0);

    if (msix_function_masked(dev)) {
        return;
    }

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        msix_handle_mask_update(dev, vector);
    }
}

static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int vector = offset / MSIX_ENTRY_SIZE;
    pci_set_long(dev->msix_table_page + offset, val);
    msix_handle_mask_update(dev, vector);
}

static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    fprintf(stderr, "MSI-X: only dword write is allowed!\n");
}

static CPUWriteMemoryFunc * const msix_mmio_write[] = {
    msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
};

static CPUReadMemoryFunc * const msix_mmio_read[] = {
    msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
};

/* Should be called from device's map method. */
void msix_mmio_map(PCIDevice *d, int region_num,
                   pcibus_t addr, pcibus_t size, int type)
{
    uint8_t *config = d->config + d->msix_cap;
    uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
    uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
    /* TODO: for assigned devices, we'll want to make it possible to map
     * pending bits separately in case they are in a separate bar. */
    int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;

    if (table_bir != region_num)
        return;
    if (size <= offset)
        return;
    cpu_register_physical_memory(addr + offset, size - offset,
                                 d->msix_mmio_index);
}

static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
{
    int vector;
    for (vector = 0; vector < nentries; ++vector) {
        unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
        dev->msix_table_page[offset] |= MSIX_VECTOR_MASK;
    }
}

/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 * modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
              unsigned bar_nr, unsigned bar_size)
{
    int ret;
    /* Nothing to do if MSI is not supported by interrupt controller */
    if (!msix_supported)
        return -ENOTSUP;

    if (nentries > MSIX_MAX_ENTRIES)
        return -EINVAL;

    dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
                                        sizeof *dev->msix_entry_used);

    dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
    msix_mask_all(dev, nentries);

    dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
                                                  msix_mmio_write, dev);
    if (dev->msix_mmio_index == -1) {
        ret = -EBUSY;
        goto err_index;
    }

    dev->msix_entries_nr = nentries;
    ret = msix_add_config(dev, nentries, bar_nr, bar_size);
    if (ret)
        goto err_config;

    dev->cap_present |= QEMU_PCI_CAP_MSIX;
    return 0;

err_config:
    dev->msix_entries_nr = 0;
    cpu_unregister_io_memory(dev->msix_mmio_index);
err_index:
    qemu_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    qemu_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    return ret;
}

static void msix_free_irq_entries(PCIDevice *dev)
{
    int vector;

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        dev->msix_entry_used[vector] = 0;
        msix_clr_pending(dev, vector);
    }
}

/* Clean up resources for the device. */
int msix_uninit(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return 0;
    pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    dev->msix_cap = 0;
    msix_free_irq_entries(dev);
    dev->msix_entries_nr = 0;
    cpu_unregister_io_memory(dev->msix_mmio_index);
    qemu_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    qemu_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
    return 0;
}

void msix_save(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
    qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Should be called after restoring the config space. */
void msix_load(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    msix_free_irq_entries(dev);
    qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
    qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Does device support MSI-X? */
int msix_present(PCIDevice *dev)
{
    return dev->cap_present & QEMU_PCI_CAP_MSIX;
}

/* Is MSI-X enabled? */
int msix_enabled(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
         MSIX_ENABLE_MASK);
}

/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
uint32_t msix_bar_size(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
        dev->msix_bar_size : 0;
}

/* Send an MSI-X message */
void msix_notify(PCIDevice *dev, unsigned vector)
{
    uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
    uint64_t address;
    uint32_t data;

    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
        return;
    if (msix_is_masked(dev, vector)) {
        msix_set_pending(dev, vector);
        return;
    }

    address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
    address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
    data = pci_get_long(table_entry + MSIX_MSG_DATA);
    stl_phys(address, data);
}

void msix_reset(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
    dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
	    ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
    memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
    msix_mask_all(dev, dev->msix_entries_nr);
}

/* PCI spec suggests that devices make it possible for software to configure
 * less vectors than supported by the device, but does not specify a standard
 * mechanism for devices to do so.
 *
 * We support this by asking devices to declare vectors software is going to
 * actually use, and checking this on the notification path. Devices that
 * don't want to follow the spec suggestion can declare all vectors as used. */

/* Mark vector as used. */
int msix_vector_use(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr)
        return -EINVAL;
    dev->msix_entry_used[vector]++;
    return 0;
}

/* Mark vector as unused. */
void msix_vector_unuse(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
        return;
    }
    if (--dev->msix_entry_used[vector]) {
        return;
    }
    msix_clr_pending(dev, vector);
}

void msix_unuse_all_vectors(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
}
Commit	Line	Data
02eb84d0 MT	1	/*
	2	* MSI-X device support
	3	*
	4	* This module includes support for MSI-X in pci devices.
	5	*
	6	* Author: Michael S. Tsirkin <mst@redhat.com>
	7	*
	8	* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2. See
	11	* the COPYING file in the top-level directory.
	12	*/
	13
	14	#include "hw.h"
	15	#include "msix.h"
	16	#include "pci.h"
	17
02eb84d0 MT	18	/* MSI-X capability structure */
	19	#define MSIX_TABLE_OFFSET 4
	20	#define MSIX_PBA_OFFSET 8
	21	#define MSIX_CAP_LENGTH 12
	22
2760952b MT	23	/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
2760952b MT	24	#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
02eb84d0	25	#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
5b5cb086	26	#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
02eb84d0 MT	27
	28	/* MSI-X table format */
	29	#define MSIX_MSG_ADDR 0
	30	#define MSIX_MSG_UPPER_ADDR 4
	31	#define MSIX_MSG_DATA 8
	32	#define MSIX_VECTOR_CTRL 12
	33	#define MSIX_ENTRY_SIZE 16
	34	#define MSIX_VECTOR_MASK 0x1
5a1fc5e8 MT	35
	36	/* How much space does an MSIX table need. */
	37	/* The spec requires giving the table structure
	38	* a 4K aligned region all by itself. */
	39	#define MSIX_PAGE_SIZE 0x1000
	40	/* Reserve second half of the page for pending bits */
	41	#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
02eb84d0 MT	42	#define MSIX_MAX_ENTRIES 32
	43
	44
	45	#ifdef MSIX_DEBUG
	46	#define DEBUG(fmt, ...) \
	47	do { \
	48	fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
	49	} while (0)
	50	#else
	51	#define DEBUG(fmt, ...) do { } while(0)
	52	#endif
	53
	54	/* Flag for interrupt controller to declare MSI-X support */
	55	int msix_supported;
	56
	57	/* Add MSI-X capability to the config space for the device. */
	58	/* Given a bar and its size, add MSI-X table on top of it
	59	* and fill MSI-X capability in the config space.
	60	* Original bar size must be a power of 2 or 0.
	61	* New bar size is returned. */
	62	static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
	63	unsigned bar_nr, unsigned bar_size)
	64	{
	65	int config_offset;
	66	uint8_t *config;
	67	uint32_t new_size;
	68
	69	if (nentries < 1 \|\| nentries > PCI_MSIX_FLAGS_QSIZE + 1)
	70	return -EINVAL;
	71	if (bar_size > 0x80000000)
	72	return -ENOSPC;
	73
	74	/* Add space for MSI-X structures */
5e520a7d	75	if (!bar_size) {
5a1fc5e8 MT	76	new_size = MSIX_PAGE_SIZE;
	77	} else if (bar_size < MSIX_PAGE_SIZE) {
	78	bar_size = MSIX_PAGE_SIZE;
	79	new_size = MSIX_PAGE_SIZE * 2;
	80	} else {
02eb84d0	81	new_size = bar_size * 2;
5a1fc5e8	82	}
02eb84d0 MT	83
	84	pdev->msix_bar_size = new_size;
	85	config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	86	if (config_offset < 0)
	87	return config_offset;
	88	config = pdev->config + config_offset;
	89
	90	pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
	91	/* Table on top of BAR */
	92	pci_set_long(config + MSIX_TABLE_OFFSET, bar_size \| bar_nr);
	93	/* Pending bits on top of that */
5a1fc5e8 MT	94	pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) \|
5a1fc5e8 MT	95	bar_nr);
02eb84d0 MT	96	pdev->msix_cap = config_offset;
02eb84d0 MT	97	/* Make flags bit writeable. */
5b5cb086 MT	98	pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] \|= MSIX_ENABLE_MASK \|
5b5cb086 MT	99	MSIX_MASKALL_MASK;
02eb84d0 MT	100	return 0;
	101	}
	102
c227f099	103	static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
02eb84d0 MT	104	{
02eb84d0 MT	105	PCIDevice *dev = opaque;
76f5159d	106	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	107	void *page = dev->msix_table_page;
02eb84d0	108
76f5159d	109	return pci_get_long(page + offset);
02eb84d0 MT	110	}
02eb84d0 MT	111
c227f099	112	static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
02eb84d0 MT	113	{
	114	fprintf(stderr, "MSI-X: only dword read is allowed!\n");
	115	return 0;
	116	}
	117
	118	static uint8_t msix_pending_mask(int vector)
	119	{
	120	return 1 << (vector % 8);
	121	}
	122
	123	static uint8_t msix_pending_byte(PCIDevice dev, int vector)
	124	{
5a1fc5e8	125	return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
02eb84d0 MT	126	}
	127
	128	static int msix_is_pending(PCIDevice *dev, int vector)
	129	{
	130	return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
	131	}
	132
	133	static void msix_set_pending(PCIDevice *dev, int vector)
	134	{
	135	*msix_pending_byte(dev, vector) \|= msix_pending_mask(vector);
	136	}
	137
	138	static void msix_clr_pending(PCIDevice *dev, int vector)
	139	{
	140	*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
	141	}
	142
5b5cb086 MT	143	static int msix_function_masked(PCIDevice *dev)
	144	{
	145	return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
	146	}
	147
02eb84d0 MT	148	static int msix_is_masked(PCIDevice *dev, int vector)
	149	{
	150	unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
5b5cb086 MT	151	return msix_function_masked(dev) \|\|
	152	dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
	153	}
	154
	155	static void msix_handle_mask_update(PCIDevice *dev, int vector)
	156	{
	157	if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
	158	msix_clr_pending(dev, vector);
	159	msix_notify(dev, vector);
	160	}
	161	}
	162
	163	/* Handle MSI-X capability config write. */
	164	void msix_write_config(PCIDevice *dev, uint32_t addr,
	165	uint32_t val, int len)
	166	{
	167	unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
	168	int vector;
	169
98a3cb02	170	if (!range_covers_byte(addr, len, enable_pos)) {
5b5cb086 MT	171	return;
	172	}
	173
	174	if (!msix_enabled(dev)) {
	175	return;
	176	}
	177
	178	qemu_set_irq(dev->irq[0], 0);
	179
	180	if (msix_function_masked(dev)) {
	181	return;
	182	}
	183
	184	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
	185	msix_handle_mask_update(dev, vector);
	186	}
02eb84d0 MT	187	}
02eb84d0 MT	188
c227f099	189	static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
02eb84d0 MT	190	uint32_t val)
	191	{
	192	PCIDevice *dev = opaque;
76f5159d	193	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	194	int vector = offset / MSIX_ENTRY_SIZE;
76f5159d	195	pci_set_long(dev->msix_table_page + offset, val);
5b5cb086	196	msix_handle_mask_update(dev, vector);
02eb84d0 MT	197	}
02eb84d0 MT	198
c227f099	199	static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
02eb84d0 MT	200	uint32_t val)
	201	{
	202	fprintf(stderr, "MSI-X: only dword write is allowed!\n");
	203	}
	204
d60efc6b	205	static CPUWriteMemoryFunc * const msix_mmio_write[] = {
02eb84d0 MT	206	msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
	207	};
	208
d60efc6b	209	static CPUReadMemoryFunc * const msix_mmio_read[] = {
02eb84d0 MT	210	msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
	211	};
	212
	213	/* Should be called from device's map method. */
	214	void msix_mmio_map(PCIDevice *d, int region_num,
6e355d90	215	pcibus_t addr, pcibus_t size, int type)
02eb84d0 MT	216	{
	217	uint8_t *config = d->config + d->msix_cap;
	218	uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
5a1fc5e8	219	uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
02eb84d0 MT	220	/* TODO: for assigned devices, we'll want to make it possible to map
	221	* pending bits separately in case they are in a separate bar. */
	222	int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
	223
	224	if (table_bir != region_num)
	225	return;
	226	if (size <= offset)
	227	return;
	228	cpu_register_physical_memory(addr + offset, size - offset,
	229	d->msix_mmio_index);
	230	}
	231
ae1be0bb MT	232	static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
	233	{
	234	int vector;
	235	for (vector = 0; vector < nentries; ++vector) {
	236	unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
	237	dev->msix_table_page[offset] \|= MSIX_VECTOR_MASK;
	238	}
	239	}
	240
02eb84d0 MT	241	/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
	242	* modified, it should be retrieved with msix_bar_size. */
	243	int msix_init(struct PCIDevice *dev, unsigned short nentries,
5a1fc5e8	244	unsigned bar_nr, unsigned bar_size)
02eb84d0 MT	245	{
	246	int ret;
	247	/* Nothing to do if MSI is not supported by interrupt controller */
	248	if (!msix_supported)
	249	return -ENOTSUP;
	250
	251	if (nentries > MSIX_MAX_ENTRIES)
	252	return -EINVAL;
	253
	254	dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
	255	sizeof *dev->msix_entry_used);
	256
5a1fc5e8	257	dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
ae1be0bb	258	msix_mask_all(dev, nentries);
02eb84d0 MT	259
	260	dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
	261	msix_mmio_write, dev);
	262	if (dev->msix_mmio_index == -1) {
	263	ret = -EBUSY;
	264	goto err_index;
	265	}
	266
	267	dev->msix_entries_nr = nentries;
	268	ret = msix_add_config(dev, nentries, bar_nr, bar_size);
	269	if (ret)
	270	goto err_config;
	271
	272	dev->cap_present \|= QEMU_PCI_CAP_MSIX;
	273	return 0;
	274
	275	err_config:
3174ecd1	276	dev->msix_entries_nr = 0;
02eb84d0 MT	277	cpu_unregister_io_memory(dev->msix_mmio_index);
	278	err_index:
	279	qemu_free(dev->msix_table_page);
	280	dev->msix_table_page = NULL;
	281	qemu_free(dev->msix_entry_used);
	282	dev->msix_entry_used = NULL;
	283	return ret;
	284	}
	285
98304c84 MT	286	static void msix_free_irq_entries(PCIDevice *dev)
	287	{
	288	int vector;
	289
	290	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
	291	dev->msix_entry_used[vector] = 0;
	292	msix_clr_pending(dev, vector);
	293	}
	294	}
	295
02eb84d0 MT	296	/* Clean up resources for the device. */
	297	int msix_uninit(PCIDevice *dev)
	298	{
	299	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	300	return 0;
	301	pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	302	dev->msix_cap = 0;
	303	msix_free_irq_entries(dev);
	304	dev->msix_entries_nr = 0;
	305	cpu_unregister_io_memory(dev->msix_mmio_index);
	306	qemu_free(dev->msix_table_page);
	307	dev->msix_table_page = NULL;
	308	qemu_free(dev->msix_entry_used);
	309	dev->msix_entry_used = NULL;
	310	dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
	311	return 0;
	312	}
	313
	314	void msix_save(PCIDevice dev, QEMUFile f)
	315	{
9a3e12c8 MT	316	unsigned n = dev->msix_entries_nr;
9a3e12c8 MT	317
72755a70	318	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
9a3e12c8	319	return;
72755a70	320	}
9a3e12c8 MT	321
9a3e12c8 MT	322	qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
5a1fc5e8	323	qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	324	}
	325
	326	/* Should be called after restoring the config space. */
	327	void msix_load(PCIDevice dev, QEMUFile f)
	328	{
	329	unsigned n = dev->msix_entries_nr;
	330
98846d73	331	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
02eb84d0	332	return;
98846d73	333	}
02eb84d0	334
4bfd1712	335	msix_free_irq_entries(dev);
02eb84d0	336	qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
5a1fc5e8	337	qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	338	}
	339
	340	/* Does device support MSI-X? */
	341	int msix_present(PCIDevice *dev)
	342	{
	343	return dev->cap_present & QEMU_PCI_CAP_MSIX;
	344	}
	345
	346	/* Is MSI-X enabled? */
	347	int msix_enabled(PCIDevice *dev)
	348	{
	349	return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
2760952b	350	(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
02eb84d0 MT	351	MSIX_ENABLE_MASK);
	352	}
	353
	354	/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
	355	uint32_t msix_bar_size(PCIDevice *dev)
	356	{
	357	return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
	358	dev->msix_bar_size : 0;
	359	}
	360
	361	/* Send an MSI-X message */
	362	void msix_notify(PCIDevice *dev, unsigned vector)
	363	{
	364	uint8_t table_entry = dev->msix_table_page + vector MSIX_ENTRY_SIZE;
	365	uint64_t address;
	366	uint32_t data;
	367
	368	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector])
	369	return;
	370	if (msix_is_masked(dev, vector)) {
	371	msix_set_pending(dev, vector);
	372	return;
	373	}
	374
	375	address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
	376	address = (address << 32) \| pci_get_long(table_entry + MSIX_MSG_ADDR);
	377	data = pci_get_long(table_entry + MSIX_MSG_DATA);
	378	stl_phys(address, data);
	379	}
	380
	381	void msix_reset(PCIDevice *dev)
	382	{
	383	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	384	return;
	385	msix_free_irq_entries(dev);
2760952b MT	386	dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
2760952b MT	387	~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
5a1fc5e8	388	memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
ae1be0bb	389	msix_mask_all(dev, dev->msix_entries_nr);
02eb84d0 MT	390	}
	391
	392	/* PCI spec suggests that devices make it possible for software to configure
	393	* less vectors than supported by the device, but does not specify a standard
	394	* mechanism for devices to do so.
	395	*
	396	* We support this by asking devices to declare vectors software is going to
	397	* actually use, and checking this on the notification path. Devices that
	398	* don't want to follow the spec suggestion can declare all vectors as used. */
	399
	400	/* Mark vector as used. */
	401	int msix_vector_use(PCIDevice *dev, unsigned vector)
	402	{
	403	if (vector >= dev->msix_entries_nr)
	404	return -EINVAL;
	405	dev->msix_entry_used[vector]++;
	406	return 0;
	407	}
	408
	409	/* Mark vector as unused. */
	410	void msix_vector_unuse(PCIDevice *dev, unsigned vector)
	411	{
98304c84 MT	412	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector]) {
	413	return;
	414	}
	415	if (--dev->msix_entry_used[vector]) {
	416	return;
	417	}
	418	msix_clr_pending(dev, vector);
02eb84d0	419	}
b5f28bca MT	420
	421	void msix_unuse_all_vectors(PCIDevice *dev)
	422	{
	423	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	424	return;
	425	msix_free_irq_entries(dev);
	426	}