[mirror_qemu.git] / hw / msix.c

/*
 * MSI-X device support
 *
 * This module includes support for MSI-X in pci devices.
 *
 * Author: Michael S. Tsirkin <mst@redhat.com>
 *
 *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */

#include "hw.h"
#include "msix.h"
#include "pci.h"
#include "range.h"

#define MSIX_CAP_LENGTH 12

/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)

/* How much space does an MSIX table need. */
/* The spec requires giving the table structure
 * a 4K aligned region all by itself. */
#define MSIX_PAGE_SIZE 0x1000
/* Reserve second half of the page for pending bits */
#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
#define MSIX_MAX_ENTRIES 32


/* Flag for interrupt controller to declare MSI-X support */
int msix_supported;

/* Add MSI-X capability to the config space for the device. */
/* Given a bar and its size, add MSI-X table on top of it
 * and fill MSI-X capability in the config space.
 * Original bar size must be a power of 2 or 0.
 * New bar size is returned. */
static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
                           unsigned bar_nr, unsigned bar_size)
{
    int config_offset;
    uint8_t *config;
    uint32_t new_size;

    if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
        return -EINVAL;
    if (bar_size > 0x80000000)
        return -ENOSPC;

    /* Add space for MSI-X structures */
    if (!bar_size) {
        new_size = MSIX_PAGE_SIZE;
    } else if (bar_size < MSIX_PAGE_SIZE) {
        bar_size = MSIX_PAGE_SIZE;
        new_size = MSIX_PAGE_SIZE * 2;
    } else {
        new_size = bar_size * 2;
    }

    pdev->msix_bar_size = new_size;
    config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
                                       0, MSIX_CAP_LENGTH);
    if (config_offset < 0)
        return config_offset;
    config = pdev->config + config_offset;

    pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
    /* Table on top of BAR */
    pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
    /* Pending bits on top of that */
    pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
                 bar_nr);
    pdev->msix_cap = config_offset;
    /* Make flags bit writable. */
    pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
	    MSIX_MASKALL_MASK;
    pdev->msix_function_masked = true;
    return 0;
}

static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
                               unsigned size)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    void *page = dev->msix_table_page;

    return pci_get_long(page + offset);
}

static uint8_t msix_pending_mask(int vector)
{
    return 1 << (vector % 8);
}

static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
{
    return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
}

static int msix_is_pending(PCIDevice *dev, int vector)
{
    return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
}

static void msix_set_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
}

static void msix_clr_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
}

static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
{
    unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
    return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
}

static bool msix_is_masked(PCIDevice *dev, int vector)
{
    return msix_vector_masked(dev, vector, dev->msix_function_masked);
}

static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
{
    bool is_masked = msix_is_masked(dev, vector);
    if (is_masked == was_masked) {
        return;
    }

    if (!is_masked && msix_is_pending(dev, vector)) {
        msix_clr_pending(dev, vector);
        msix_notify(dev, vector);
    }
}

static void msix_update_function_masked(PCIDevice *dev)
{
    dev->msix_function_masked = !msix_enabled(dev) ||
        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
}

/* Handle MSI-X capability config write. */
void msix_write_config(PCIDevice *dev, uint32_t addr,
                       uint32_t val, int len)
{
    unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
    int vector;
    bool was_masked;

    if (!range_covers_byte(addr, len, enable_pos)) {
        return;
    }

    was_masked = dev->msix_function_masked;
    msix_update_function_masked(dev);

    if (!msix_enabled(dev)) {
        return;
    }

    pci_device_deassert_intx(dev);

    if (dev->msix_function_masked == was_masked) {
        return;
    }

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        msix_handle_mask_update(dev, vector,
                                msix_vector_masked(dev, vector, was_masked));
    }
}

static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned size)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int vector = offset / PCI_MSIX_ENTRY_SIZE;
    bool was_masked;

    /* MSI-X page includes a read-only PBA and a writeable Vector Control. */
    if (vector >= dev->msix_entries_nr) {
        return;
    }

    was_masked = msix_is_masked(dev, vector);
    pci_set_long(dev->msix_table_page + offset, val);
    msix_handle_mask_update(dev, vector, was_masked);
}

static const MemoryRegionOps msix_mmio_ops = {
    .read = msix_mmio_read,
    .write = msix_mmio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
{
    uint8_t *config = d->config + d->msix_cap;
    uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
    uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
    /* TODO: for assigned devices, we'll want to make it possible to map
     * pending bits separately in case they are in a separate bar. */

    memory_region_add_subregion(bar, offset, &d->msix_mmio);
}

static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
{
    int vector;
    for (vector = 0; vector < nentries; ++vector) {
        unsigned offset =
            vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
        dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
    }
}

/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 * modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
              MemoryRegion *bar,
              unsigned bar_nr, unsigned bar_size)
{
    int ret;
    /* Nothing to do if MSI is not supported by interrupt controller */
    if (!msix_supported)
        return -ENOTSUP;

    if (nentries > MSIX_MAX_ENTRIES)
        return -EINVAL;

    dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
                                        sizeof *dev->msix_entry_used);

    dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
    msix_mask_all(dev, nentries);

    memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
                          "msix", MSIX_PAGE_SIZE);

    dev->msix_entries_nr = nentries;
    ret = msix_add_config(dev, nentries, bar_nr, bar_size);
    if (ret)
        goto err_config;

    dev->cap_present |= QEMU_PCI_CAP_MSIX;
    msix_mmio_setup(dev, bar);
    return 0;

err_config:
    dev->msix_entries_nr = 0;
    memory_region_destroy(&dev->msix_mmio);
    g_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    g_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    return ret;
}

static void msix_free_irq_entries(PCIDevice *dev)
{
    int vector;

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        dev->msix_entry_used[vector] = 0;
        msix_clr_pending(dev, vector);
    }
}

/* Clean up resources for the device. */
int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return 0;
    pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    dev->msix_cap = 0;
    msix_free_irq_entries(dev);
    dev->msix_entries_nr = 0;
    memory_region_del_subregion(bar, &dev->msix_mmio);
    memory_region_destroy(&dev->msix_mmio);
    g_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    g_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
    return 0;
}

void msix_save(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
    qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Should be called after restoring the config space. */
void msix_load(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    msix_free_irq_entries(dev);
    qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
    qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
    msix_update_function_masked(dev);
}

/* Does device support MSI-X? */
int msix_present(PCIDevice *dev)
{
    return dev->cap_present & QEMU_PCI_CAP_MSIX;
}

/* Is MSI-X enabled? */
int msix_enabled(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
         MSIX_ENABLE_MASK);
}

/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
uint32_t msix_bar_size(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
        dev->msix_bar_size : 0;
}

/* Send an MSI-X message */
void msix_notify(PCIDevice *dev, unsigned vector)
{
    uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
    uint64_t address;
    uint32_t data;

    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
        return;
    if (msix_is_masked(dev, vector)) {
        msix_set_pending(dev, vector);
        return;
    }

    address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
    data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
    stl_le_phys(address, data);
}

void msix_reset(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
    dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
	    ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
    memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
    msix_mask_all(dev, dev->msix_entries_nr);
}

/* PCI spec suggests that devices make it possible for software to configure
 * less vectors than supported by the device, but does not specify a standard
 * mechanism for devices to do so.
 *
 * We support this by asking devices to declare vectors software is going to
 * actually use, and checking this on the notification path. Devices that
 * don't want to follow the spec suggestion can declare all vectors as used. */

/* Mark vector as used. */
int msix_vector_use(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr)
        return -EINVAL;
    dev->msix_entry_used[vector]++;
    return 0;
}

/* Mark vector as unused. */
void msix_vector_unuse(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
        return;
    }
    if (--dev->msix_entry_used[vector]) {
        return;
    }
    msix_clr_pending(dev, vector);
}

void msix_unuse_all_vectors(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
}
Commit	Line	Data
02eb84d0 MT	1	/*
	2	* MSI-X device support
	3	*
	4	* This module includes support for MSI-X in pci devices.
	5	*
	6	* Author: Michael S. Tsirkin <mst@redhat.com>
	7	*
	8	* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2. See
	11	* the COPYING file in the top-level directory.
	12	*/
	13
	14	#include "hw.h"
	15	#include "msix.h"
	16	#include "pci.h"
bf1b0071	17	#include "range.h"
02eb84d0	18
02eb84d0 MT	19	#define MSIX_CAP_LENGTH 12
02eb84d0 MT	20
2760952b MT	21	/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
2760952b MT	22	#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
02eb84d0	23	#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
5b5cb086	24	#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
02eb84d0	25
5a1fc5e8 MT	26	/* How much space does an MSIX table need. */
	27	/* The spec requires giving the table structure
	28	* a 4K aligned region all by itself. */
	29	#define MSIX_PAGE_SIZE 0x1000
	30	/* Reserve second half of the page for pending bits */
	31	#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
02eb84d0 MT	32	#define MSIX_MAX_ENTRIES 32
	33
	34
02eb84d0 MT	35	/* Flag for interrupt controller to declare MSI-X support */
	36	int msix_supported;
	37
	38	/* Add MSI-X capability to the config space for the device. */
	39	/* Given a bar and its size, add MSI-X table on top of it
	40	* and fill MSI-X capability in the config space.
	41	* Original bar size must be a power of 2 or 0.
	42	* New bar size is returned. */
	43	static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
	44	unsigned bar_nr, unsigned bar_size)
	45	{
	46	int config_offset;
	47	uint8_t *config;
	48	uint32_t new_size;
	49
	50	if (nentries < 1 \|\| nentries > PCI_MSIX_FLAGS_QSIZE + 1)
	51	return -EINVAL;
	52	if (bar_size > 0x80000000)
	53	return -ENOSPC;
	54
	55	/* Add space for MSI-X structures */
5e520a7d	56	if (!bar_size) {
5a1fc5e8 MT	57	new_size = MSIX_PAGE_SIZE;
	58	} else if (bar_size < MSIX_PAGE_SIZE) {
	59	bar_size = MSIX_PAGE_SIZE;
	60	new_size = MSIX_PAGE_SIZE * 2;
	61	} else {
02eb84d0	62	new_size = bar_size * 2;
5a1fc5e8	63	}
02eb84d0 MT	64
02eb84d0 MT	65	pdev->msix_bar_size = new_size;
ca77089d IY	66	config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
ca77089d IY	67	0, MSIX_CAP_LENGTH);
02eb84d0 MT	68	if (config_offset < 0)
	69	return config_offset;
	70	config = pdev->config + config_offset;
	71
	72	pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
	73	/* Table on top of BAR */
01731cfb	74	pci_set_long(config + PCI_MSIX_TABLE, bar_size \| bar_nr);
02eb84d0	75	/* Pending bits on top of that */
01731cfb	76	pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) \|
5a1fc5e8	77	bar_nr);
02eb84d0	78	pdev->msix_cap = config_offset;
ebabb67a	79	/* Make flags bit writable. */
5b5cb086 MT	80	pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] \|= MSIX_ENABLE_MASK \|
5b5cb086 MT	81	MSIX_MASKALL_MASK;
50322249	82	pdev->msix_function_masked = true;
02eb84d0 MT	83	return 0;
	84	}
	85
95524ae8 AK	86	static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
95524ae8 AK	87	unsigned size)
02eb84d0 MT	88	{
02eb84d0 MT	89	PCIDevice *dev = opaque;
76f5159d	90	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	91	void *page = dev->msix_table_page;
02eb84d0	92
76f5159d	93	return pci_get_long(page + offset);
02eb84d0 MT	94	}
02eb84d0 MT	95
02eb84d0 MT	96	static uint8_t msix_pending_mask(int vector)
	97	{
	98	return 1 << (vector % 8);
	99	}
	100
	101	static uint8_t msix_pending_byte(PCIDevice dev, int vector)
	102	{
5a1fc5e8	103	return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
02eb84d0 MT	104	}
	105
	106	static int msix_is_pending(PCIDevice *dev, int vector)
	107	{
	108	return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
	109	}
	110
	111	static void msix_set_pending(PCIDevice *dev, int vector)
	112	{
	113	*msix_pending_byte(dev, vector) \|= msix_pending_mask(vector);
	114	}
	115
	116	static void msix_clr_pending(PCIDevice *dev, int vector)
	117	{
	118	*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
	119	}
	120
ae392c41	121	static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
02eb84d0	122	{
ae392c41 MT	123	unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
ae392c41 MT	124	return fmask \|\| dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
5b5cb086 MT	125	}
5b5cb086 MT	126
ae392c41	127	static bool msix_is_masked(PCIDevice *dev, int vector)
5b5cb086	128	{
ae392c41 MT	129	return msix_vector_masked(dev, vector, dev->msix_function_masked);
	130	}
	131
	132	static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
	133	{
	134	bool is_masked = msix_is_masked(dev, vector);
	135	if (is_masked == was_masked) {
	136	return;
	137	}
	138
	139	if (!is_masked && msix_is_pending(dev, vector)) {
5b5cb086 MT	140	msix_clr_pending(dev, vector);
	141	msix_notify(dev, vector);
	142	}
	143	}
	144
50322249 MT	145	static void msix_update_function_masked(PCIDevice *dev)
	146	{
	147	dev->msix_function_masked = !msix_enabled(dev) \|\|
	148	(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
	149	}
	150
5b5cb086 MT	151	/* Handle MSI-X capability config write. */
	152	void msix_write_config(PCIDevice *dev, uint32_t addr,
	153	uint32_t val, int len)
	154	{
	155	unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
	156	int vector;
50322249	157	bool was_masked;
5b5cb086	158
98a3cb02	159	if (!range_covers_byte(addr, len, enable_pos)) {
5b5cb086 MT	160	return;
	161	}
	162
50322249 MT	163	was_masked = dev->msix_function_masked;
	164	msix_update_function_masked(dev);
	165
5b5cb086 MT	166	if (!msix_enabled(dev)) {
	167	return;
	168	}
	169
e407bf13	170	pci_device_deassert_intx(dev);
5b5cb086	171
50322249	172	if (dev->msix_function_masked == was_masked) {
5b5cb086 MT	173	return;
	174	}
	175
	176	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
ae392c41 MT	177	msix_handle_mask_update(dev, vector,
ae392c41 MT	178	msix_vector_masked(dev, vector, was_masked));
5b5cb086	179	}
02eb84d0 MT	180	}
02eb84d0 MT	181
95524ae8 AK	182	static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
95524ae8 AK	183	uint64_t val, unsigned size)
02eb84d0 MT	184	{
02eb84d0 MT	185	PCIDevice *dev = opaque;
76f5159d	186	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
01731cfb	187	int vector = offset / PCI_MSIX_ENTRY_SIZE;
ae392c41	188	bool was_masked;
9a93b617 MT	189
	190	/* MSI-X page includes a read-only PBA and a writeable Vector Control. */
	191	if (vector >= dev->msix_entries_nr) {
	192	return;
	193	}
	194
ae392c41	195	was_masked = msix_is_masked(dev, vector);
76f5159d	196	pci_set_long(dev->msix_table_page + offset, val);
ae392c41	197	msix_handle_mask_update(dev, vector, was_masked);
02eb84d0 MT	198	}
02eb84d0 MT	199
95524ae8 AK	200	static const MemoryRegionOps msix_mmio_ops = {
	201	.read = msix_mmio_read,
	202	.write = msix_mmio_write,
	203	.endianness = DEVICE_NATIVE_ENDIAN,
	204	.valid = {
	205	.min_access_size = 4,
	206	.max_access_size = 4,
	207	},
02eb84d0 MT	208	};
02eb84d0 MT	209
95524ae8	210	static void msix_mmio_setup(PCIDevice d, MemoryRegion bar)
02eb84d0 MT	211	{
02eb84d0 MT	212	uint8_t *config = d->config + d->msix_cap;
01731cfb	213	uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
5a1fc5e8	214	uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
02eb84d0 MT	215	/* TODO: for assigned devices, we'll want to make it possible to map
02eb84d0 MT	216	* pending bits separately in case they are in a separate bar. */
02eb84d0	217
95524ae8	218	memory_region_add_subregion(bar, offset, &d->msix_mmio);
02eb84d0 MT	219	}
02eb84d0 MT	220
ae1be0bb MT	221	static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
	222	{
	223	int vector;
	224	for (vector = 0; vector < nentries; ++vector) {
01731cfb JK	225	unsigned offset =
	226	vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
	227	dev->msix_table_page[offset] \|= PCI_MSIX_ENTRY_CTRL_MASKBIT;
ae1be0bb MT	228	}
	229	}
	230
02eb84d0 MT	231	/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
	232	* modified, it should be retrieved with msix_bar_size. */
	233	int msix_init(struct PCIDevice *dev, unsigned short nentries,
95524ae8	234	MemoryRegion *bar,
5a1fc5e8	235	unsigned bar_nr, unsigned bar_size)
02eb84d0 MT	236	{
	237	int ret;
	238	/* Nothing to do if MSI is not supported by interrupt controller */
	239	if (!msix_supported)
	240	return -ENOTSUP;
	241
	242	if (nentries > MSIX_MAX_ENTRIES)
	243	return -EINVAL;
	244
7267c094	245	dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
02eb84d0 MT	246	sizeof *dev->msix_entry_used);
02eb84d0 MT	247
7267c094	248	dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
ae1be0bb	249	msix_mask_all(dev, nentries);
02eb84d0	250
95524ae8 AK	251	memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
95524ae8 AK	252	"msix", MSIX_PAGE_SIZE);
02eb84d0 MT	253
	254	dev->msix_entries_nr = nentries;
	255	ret = msix_add_config(dev, nentries, bar_nr, bar_size);
	256	if (ret)
	257	goto err_config;
	258
	259	dev->cap_present \|= QEMU_PCI_CAP_MSIX;
95524ae8	260	msix_mmio_setup(dev, bar);
02eb84d0 MT	261	return 0;
	262
	263	err_config:
3174ecd1	264	dev->msix_entries_nr = 0;
95524ae8	265	memory_region_destroy(&dev->msix_mmio);
7267c094	266	g_free(dev->msix_table_page);
02eb84d0	267	dev->msix_table_page = NULL;
7267c094	268	g_free(dev->msix_entry_used);
02eb84d0 MT	269	dev->msix_entry_used = NULL;
	270	return ret;
	271	}
	272
98304c84 MT	273	static void msix_free_irq_entries(PCIDevice *dev)
	274	{
	275	int vector;
	276
	277	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
	278	dev->msix_entry_used[vector] = 0;
	279	msix_clr_pending(dev, vector);
	280	}
	281	}
	282
02eb84d0	283	/* Clean up resources for the device. */
95524ae8	284	int msix_uninit(PCIDevice dev, MemoryRegion bar)
02eb84d0 MT	285	{
	286	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	287	return 0;
	288	pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	289	dev->msix_cap = 0;
	290	msix_free_irq_entries(dev);
	291	dev->msix_entries_nr = 0;
95524ae8 AK	292	memory_region_del_subregion(bar, &dev->msix_mmio);
95524ae8 AK	293	memory_region_destroy(&dev->msix_mmio);
7267c094	294	g_free(dev->msix_table_page);
02eb84d0	295	dev->msix_table_page = NULL;
7267c094	296	g_free(dev->msix_entry_used);
02eb84d0 MT	297	dev->msix_entry_used = NULL;
	298	dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
	299	return 0;
	300	}
	301
	302	void msix_save(PCIDevice dev, QEMUFile f)
	303	{
9a3e12c8 MT	304	unsigned n = dev->msix_entries_nr;
9a3e12c8 MT	305
72755a70	306	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
9a3e12c8	307	return;
72755a70	308	}
9a3e12c8	309
01731cfb	310	qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
5a1fc5e8	311	qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	312	}
	313
	314	/* Should be called after restoring the config space. */
	315	void msix_load(PCIDevice dev, QEMUFile f)
	316	{
	317	unsigned n = dev->msix_entries_nr;
	318
98846d73	319	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
02eb84d0	320	return;
98846d73	321	}
02eb84d0	322
4bfd1712	323	msix_free_irq_entries(dev);
01731cfb	324	qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
5a1fc5e8	325	qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
50322249	326	msix_update_function_masked(dev);
02eb84d0 MT	327	}
	328
	329	/* Does device support MSI-X? */
	330	int msix_present(PCIDevice *dev)
	331	{
	332	return dev->cap_present & QEMU_PCI_CAP_MSIX;
	333	}
	334
	335	/* Is MSI-X enabled? */
	336	int msix_enabled(PCIDevice *dev)
	337	{
	338	return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
2760952b	339	(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
02eb84d0 MT	340	MSIX_ENABLE_MASK);
	341	}
	342
	343	/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
	344	uint32_t msix_bar_size(PCIDevice *dev)
	345	{
	346	return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
	347	dev->msix_bar_size : 0;
	348	}
	349
	350	/* Send an MSI-X message */
	351	void msix_notify(PCIDevice *dev, unsigned vector)
	352	{
01731cfb	353	uint8_t table_entry = dev->msix_table_page + vector PCI_MSIX_ENTRY_SIZE;
02eb84d0 MT	354	uint64_t address;
	355	uint32_t data;
	356
	357	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector])
	358	return;
	359	if (msix_is_masked(dev, vector)) {
	360	msix_set_pending(dev, vector);
	361	return;
	362	}
	363
01731cfb JK	364	address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
01731cfb JK	365	data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
ae5d3eb4	366	stl_le_phys(address, data);
02eb84d0 MT	367	}
	368
	369	void msix_reset(PCIDevice *dev)
	370	{
	371	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	372	return;
	373	msix_free_irq_entries(dev);
2760952b MT	374	dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
2760952b MT	375	~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
5a1fc5e8	376	memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
ae1be0bb	377	msix_mask_all(dev, dev->msix_entries_nr);
02eb84d0 MT	378	}
	379
	380	/* PCI spec suggests that devices make it possible for software to configure
	381	* less vectors than supported by the device, but does not specify a standard
	382	* mechanism for devices to do so.
	383	*
	384	* We support this by asking devices to declare vectors software is going to
	385	* actually use, and checking this on the notification path. Devices that
	386	* don't want to follow the spec suggestion can declare all vectors as used. */
	387
	388	/* Mark vector as used. */
	389	int msix_vector_use(PCIDevice *dev, unsigned vector)
	390	{
	391	if (vector >= dev->msix_entries_nr)
	392	return -EINVAL;
	393	dev->msix_entry_used[vector]++;
	394	return 0;
	395	}
	396
	397	/* Mark vector as unused. */
	398	void msix_vector_unuse(PCIDevice *dev, unsigned vector)
	399	{
98304c84 MT	400	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector]) {
	401	return;
	402	}
	403	if (--dev->msix_entry_used[vector]) {
	404	return;
	405	}
	406	msix_clr_pending(dev, vector);
02eb84d0	407	}
b5f28bca MT	408
	409	void msix_unuse_all_vectors(PCIDevice *dev)
	410	{
	411	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	412	return;
	413	msix_free_irq_entries(dev);
	414	}