[mirror_qemu.git] / hw / mst_fpga.c

/*
 * PXA270-based Intel Mainstone platforms.
 * FPGA driver
 *
 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
 *                                    <akuster@mvista.com>
 *
 * This code is licensed under the GNU GPL v2.
 */
#include "hw.h"
#include "sysbus.h"

/* Mainstone FPGA for extern irqs */
#define FPGA_GPIO_PIN	0
#define MST_NUM_IRQS	16
#define MST_LEDDAT1		0x10
#define MST_LEDDAT2		0x14
#define MST_LEDCTRL		0x40
#define MST_GPSWR		0x60
#define MST_MSCWR1		0x80
#define MST_MSCWR2		0x84
#define MST_MSCWR3		0x88
#define MST_MSCRD		0x90
#define MST_INTMSKENA	0xc0
#define MST_INTSETCLR	0xd0
#define MST_PCMCIA0		0xe0
#define MST_PCMCIA1		0xe4

#define MST_PCMCIAx_READY	(1 << 10)
#define MST_PCMCIAx_nCD		(1 << 5)

#define MST_PCMCIA_CD0_IRQ	9
#define MST_PCMCIA_CD1_IRQ	13

typedef struct mst_irq_state{
	SysBusDevice busdev;
	MemoryRegion iomem;

	qemu_irq parent;

	uint32_t prev_level;
	uint32_t leddat1;
	uint32_t leddat2;
	uint32_t ledctrl;
	uint32_t gpswr;
	uint32_t mscwr1;
	uint32_t mscwr2;
	uint32_t mscwr3;
	uint32_t mscrd;
	uint32_t intmskena;
	uint32_t intsetclr;
	uint32_t pcmcia0;
	uint32_t pcmcia1;
}mst_irq_state;

static void
mst_fpga_set_irq(void *opaque, int irq, int level)
{
	mst_irq_state *s = (mst_irq_state *)opaque;
	uint32_t oldint = s->intsetclr & s->intmskena;

	if (level)
		s->prev_level |= 1u << irq;
	else
		s->prev_level &= ~(1u << irq);

	switch(irq) {
	case MST_PCMCIA_CD0_IRQ:
		if (level)
			s->pcmcia0 &= ~MST_PCMCIAx_nCD;
		else
			s->pcmcia0 |=  MST_PCMCIAx_nCD;
		break;
	case MST_PCMCIA_CD1_IRQ:
		if (level)
			s->pcmcia1 &= ~MST_PCMCIAx_nCD;
		else
			s->pcmcia1 |=  MST_PCMCIAx_nCD;
		break;
	}

	if ((s->intmskena & (1u << irq)) && level)
		s->intsetclr |= 1u << irq;

	if (oldint != (s->intsetclr & s->intmskena))
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
}


static uint64_t
mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
{
	mst_irq_state *s = (mst_irq_state *) opaque;

	switch (addr) {
	case MST_LEDDAT1:
		return s->leddat1;
	case MST_LEDDAT2:
		return s->leddat2;
	case MST_LEDCTRL:
		return s->ledctrl;
	case MST_GPSWR:
		return s->gpswr;
	case MST_MSCWR1:
		return s->mscwr1;
	case MST_MSCWR2:
		return s->mscwr2;
	case MST_MSCWR3:
		return s->mscwr3;
	case MST_MSCRD:
		return s->mscrd;
	case MST_INTMSKENA:
		return s->intmskena;
	case MST_INTSETCLR:
		return s->intsetclr;
	case MST_PCMCIA0:
		return s->pcmcia0;
	case MST_PCMCIA1:
		return s->pcmcia1;
	default:
		printf("Mainstone - mst_fpga_readb: Bad register offset "
			"0x" TARGET_FMT_plx "\n", addr);
	}
	return 0;
}

static void
mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
		unsigned size)
{
	mst_irq_state *s = (mst_irq_state *) opaque;
	value &= 0xffffffff;

	switch (addr) {
	case MST_LEDDAT1:
		s->leddat1 = value;
		break;
	case MST_LEDDAT2:
		s->leddat2 = value;
		break;
	case MST_LEDCTRL:
		s->ledctrl = value;
		break;
	case MST_GPSWR:
		s->gpswr = value;
		break;
	case MST_MSCWR1:
		s->mscwr1 = value;
		break;
	case MST_MSCWR2:
		s->mscwr2 = value;
		break;
	case MST_MSCWR3:
		s->mscwr3 = value;
		break;
	case MST_MSCRD:
		s->mscrd =  value;
		break;
	case MST_INTMSKENA:	/* Mask interrupt */
		s->intmskena = (value & 0xFEEFF);
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
		break;
	case MST_INTSETCLR:	/* clear or set interrupt */
		s->intsetclr = (value & 0xFEEFF);
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
		break;
		/* For PCMCIAx allow the to change only power and reset */
	case MST_PCMCIA0:
		s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
		break;
	case MST_PCMCIA1:
		s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
		break;
	default:
		printf("Mainstone - mst_fpga_writeb: Bad register offset "
			"0x" TARGET_FMT_plx "\n", addr);
	}
}

static const MemoryRegionOps mst_fpga_ops = {
	.read = mst_fpga_readb,
	.write = mst_fpga_writeb,
	.endianness = DEVICE_NATIVE_ENDIAN,
};

static int mst_fpga_post_load(void *opaque, int version_id)
{
	mst_irq_state *s = (mst_irq_state *) opaque;

	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
	return 0;
}

static int mst_fpga_init(SysBusDevice *dev)
{
	mst_irq_state *s;

	s = FROM_SYSBUS(mst_irq_state, dev);

	s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
	s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;

	sysbus_init_irq(dev, &s->parent);

	/* alloc the external 16 irqs */
	qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);

	memory_region_init_io(&s->iomem, &mst_fpga_ops, s,
			    "fpga", 0x00100000);
	sysbus_init_mmio(dev, &s->iomem);
	return 0;
}

static VMStateDescription vmstate_mst_fpga_regs = {
	.name = "mainstone_fpga",
	.version_id = 0,
	.minimum_version_id = 0,
	.minimum_version_id_old = 0,
	.post_load = mst_fpga_post_load,
	.fields = (VMStateField []) {
		VMSTATE_UINT32(prev_level, mst_irq_state),
		VMSTATE_UINT32(leddat1, mst_irq_state),
		VMSTATE_UINT32(leddat2, mst_irq_state),
		VMSTATE_UINT32(ledctrl, mst_irq_state),
		VMSTATE_UINT32(gpswr, mst_irq_state),
		VMSTATE_UINT32(mscwr1, mst_irq_state),
		VMSTATE_UINT32(mscwr2, mst_irq_state),
		VMSTATE_UINT32(mscwr3, mst_irq_state),
		VMSTATE_UINT32(mscrd, mst_irq_state),
		VMSTATE_UINT32(intmskena, mst_irq_state),
		VMSTATE_UINT32(intsetclr, mst_irq_state),
		VMSTATE_UINT32(pcmcia0, mst_irq_state),
		VMSTATE_UINT32(pcmcia1, mst_irq_state),
		VMSTATE_END_OF_LIST(),
	},
};

static SysBusDeviceInfo mst_fpga_info = {
	.init = mst_fpga_init,
	.qdev.name = "mainstone-fpga",
	.qdev.desc = "Mainstone II FPGA",
	.qdev.size = sizeof(mst_irq_state),
	.qdev.vmsd = &vmstate_mst_fpga_regs,
};

static void mst_fpga_register(void)
{
	sysbus_register_withprop(&mst_fpga_info);
}
device_init(mst_fpga_register);
Commit	Line	Data
7233b355 TS	1	/*
	2	* PXA270-based Intel Mainstone platforms.
	3	* FPGA driver
	4	*
	5	* Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
	6	* <akuster@mvista.com>
	7	*
	8	* This code is licensed under the GNU GPL v2.
	9	*/
	10	#include "hw.h"
cb380f61	11	#include "sysbus.h"
7233b355 TS	12
	13	/* Mainstone FPGA for extern irqs */
	14	#define FPGA_GPIO_PIN 0
	15	#define MST_NUM_IRQS 16
7233b355 TS	16	#define MST_LEDDAT1 0x10
	17	#define MST_LEDDAT2 0x14
	18	#define MST_LEDCTRL 0x40
	19	#define MST_GPSWR 0x60
	20	#define MST_MSCWR1 0x80
	21	#define MST_MSCWR2 0x84
	22	#define MST_MSCWR3 0x88
	23	#define MST_MSCRD 0x90
	24	#define MST_INTMSKENA 0xc0
	25	#define MST_INTSETCLR 0xd0
	26	#define MST_PCMCIA0 0xe0
	27	#define MST_PCMCIA1 0xe4
	28
b651fc6f DES	29	#define MST_PCMCIAx_READY (1 << 10)
	30	#define MST_PCMCIAx_nCD (1 << 5)
	31
	32	#define MST_PCMCIA_CD0_IRQ 9
	33	#define MST_PCMCIA_CD1_IRQ 13
	34
7233b355	35	typedef struct mst_irq_state{
cb380f61	36	SysBusDevice busdev;
b9441ebb	37	MemoryRegion iomem;
cb380f61	38
bb70651e	39	qemu_irq parent;
7233b355 TS	40
	41	uint32_t prev_level;
	42	uint32_t leddat1;
	43	uint32_t leddat2;
	44	uint32_t ledctrl;
	45	uint32_t gpswr;
	46	uint32_t mscwr1;
	47	uint32_t mscwr2;
	48	uint32_t mscwr3;
	49	uint32_t mscrd;
	50	uint32_t intmskena;
	51	uint32_t intsetclr;
	52	uint32_t pcmcia0;
	53	uint32_t pcmcia1;
	54	}mst_irq_state;
	55
7233b355 TS	56	static void
	57	mst_fpga_set_irq(void *opaque, int irq, int level)
	58	{
	59	mst_irq_state s = (mst_irq_state )opaque;
3e1dbc3b	60	uint32_t oldint = s->intsetclr & s->intmskena;
7233b355 TS	61
	62	if (level)
	63	s->prev_level \|= 1u << irq;
	64	else
	65	s->prev_level &= ~(1u << irq);
	66
b651fc6f DES	67	switch(irq) {
	68	case MST_PCMCIA_CD0_IRQ:
	69	if (level)
	70	s->pcmcia0 &= ~MST_PCMCIAx_nCD;
	71	else
	72	s->pcmcia0 \|= MST_PCMCIAx_nCD;
	73	break;
	74	case MST_PCMCIA_CD1_IRQ:
	75	if (level)
	76	s->pcmcia1 &= ~MST_PCMCIAx_nCD;
	77	else
	78	s->pcmcia1 \|= MST_PCMCIAx_nCD;
	79	break;
	80	}
	81
43d91709 DES	82	if ((s->intmskena & (1u << irq)) && level)
	83	s->intsetclr \|= 1u << irq;
	84
	85	if (oldint != (s->intsetclr & s->intmskena))
	86	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	87	}
	88
	89
b9441ebb BC	90	static uint64_t
b9441ebb BC	91	mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
7233b355 TS	92	{
7233b355 TS	93	mst_irq_state s = (mst_irq_state ) opaque;
7233b355 TS	94
	95	switch (addr) {
	96	case MST_LEDDAT1:
	97	return s->leddat1;
	98	case MST_LEDDAT2:
	99	return s->leddat2;
	100	case MST_LEDCTRL:
	101	return s->ledctrl;
	102	case MST_GPSWR:
	103	return s->gpswr;
	104	case MST_MSCWR1:
	105	return s->mscwr1;
	106	case MST_MSCWR2:
	107	return s->mscwr2;
	108	case MST_MSCWR3:
	109	return s->mscwr3;
	110	case MST_MSCRD:
	111	return s->mscrd;
	112	case MST_INTMSKENA:
	113	return s->intmskena;
	114	case MST_INTSETCLR:
	115	return s->intsetclr;
	116	case MST_PCMCIA0:
	117	return s->pcmcia0;
	118	case MST_PCMCIA1:
	119	return s->pcmcia1;
	120	default:
	121	printf("Mainstone - mst_fpga_readb: Bad register offset "
b2bedb21	122	"0x" TARGET_FMT_plx "\n", addr);
7233b355 TS	123	}
	124	return 0;
	125	}
	126
	127	static void
b9441ebb BC	128	mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
b9441ebb BC	129	unsigned size)
7233b355 TS	130	{
7233b355 TS	131	mst_irq_state s = (mst_irq_state ) opaque;
7233b355 TS	132	value &= 0xffffffff;
	133
	134	switch (addr) {
	135	case MST_LEDDAT1:
	136	s->leddat1 = value;
	137	break;
	138	case MST_LEDDAT2:
	139	s->leddat2 = value;
	140	break;
	141	case MST_LEDCTRL:
	142	s->ledctrl = value;
	143	break;
	144	case MST_GPSWR:
	145	s->gpswr = value;
	146	break;
	147	case MST_MSCWR1:
	148	s->mscwr1 = value;
	149	break;
	150	case MST_MSCWR2:
	151	s->mscwr2 = value;
	152	break;
	153	case MST_MSCWR3:
	154	s->mscwr3 = value;
	155	break;
	156	case MST_MSCRD:
	157	s->mscrd = value;
	158	break;
ff2712ba	159	case MST_INTMSKENA: /* Mask interrupt */
7233b355	160	s->intmskena = (value & 0xFEEFF);
43d91709	161	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	162	break;
	163	case MST_INTSETCLR: /* clear or set interrupt */
	164	s->intsetclr = (value & 0xFEEFF);
3e1dbc3b	165	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355	166	break;
b651fc6f	167	/* For PCMCIAx allow the to change only power and reset */
7233b355	168	case MST_PCMCIA0:
b651fc6f	169	s->pcmcia0 = (value & 0x1f) \| (s->pcmcia0 & ~0x1f);
7233b355 TS	170	break;
7233b355 TS	171	case MST_PCMCIA1:
b651fc6f	172	s->pcmcia1 = (value & 0x1f) \| (s->pcmcia1 & ~0x1f);
7233b355 TS	173	break;
	174	default:
	175	printf("Mainstone - mst_fpga_writeb: Bad register offset "
b2bedb21	176	"0x" TARGET_FMT_plx "\n", addr);
7233b355 TS	177	}
	178	}
	179
b9441ebb BC	180	static const MemoryRegionOps mst_fpga_ops = {
	181	.read = mst_fpga_readb,
	182	.write = mst_fpga_writeb,
	183	.endianness = DEVICE_NATIVE_ENDIAN,
7233b355	184	};
7233b355	185
cb380f61	186	static int mst_fpga_post_load(void *opaque, int version_id)
7233b355 TS	187	{
	188	mst_irq_state s = (mst_irq_state ) opaque;
	189
43d91709	190	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	191	return 0;
	192	}
	193
cb380f61	194	static int mst_fpga_init(SysBusDevice *dev)
7233b355 TS	195	{
7233b355 TS	196	mst_irq_state *s;
7233b355	197
cb380f61	198	s = FROM_SYSBUS(mst_irq_state, dev);
7233b355	199
b651fc6f DES	200	s->pcmcia0 = MST_PCMCIAx_READY \| MST_PCMCIAx_nCD;
	201	s->pcmcia1 = MST_PCMCIAx_READY \| MST_PCMCIAx_nCD;
	202
cb380f61	203	sysbus_init_irq(dev, &s->parent);
7233b355 TS	204
7233b355 TS	205	/* alloc the external 16 irqs */
cb380f61	206	qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
7233b355	207
b9441ebb BC	208	memory_region_init_io(&s->iomem, &mst_fpga_ops, s,
b9441ebb BC	209	"fpga", 0x00100000);
750ecd44	210	sysbus_init_mmio(dev, &s->iomem);
cb380f61 DES	211	return 0;
	212	}
	213
	214	static VMStateDescription vmstate_mst_fpga_regs = {
	215	.name = "mainstone_fpga",
	216	.version_id = 0,
	217	.minimum_version_id = 0,
	218	.minimum_version_id_old = 0,
	219	.post_load = mst_fpga_post_load,
	220	.fields = (VMStateField []) {
	221	VMSTATE_UINT32(prev_level, mst_irq_state),
	222	VMSTATE_UINT32(leddat1, mst_irq_state),
	223	VMSTATE_UINT32(leddat2, mst_irq_state),
	224	VMSTATE_UINT32(ledctrl, mst_irq_state),
	225	VMSTATE_UINT32(gpswr, mst_irq_state),
	226	VMSTATE_UINT32(mscwr1, mst_irq_state),
	227	VMSTATE_UINT32(mscwr2, mst_irq_state),
	228	VMSTATE_UINT32(mscwr3, mst_irq_state),
	229	VMSTATE_UINT32(mscrd, mst_irq_state),
	230	VMSTATE_UINT32(intmskena, mst_irq_state),
	231	VMSTATE_UINT32(intsetclr, mst_irq_state),
	232	VMSTATE_UINT32(pcmcia0, mst_irq_state),
	233	VMSTATE_UINT32(pcmcia1, mst_irq_state),
	234	VMSTATE_END_OF_LIST(),
	235	},
	236	};
	237
	238	static SysBusDeviceInfo mst_fpga_info = {
	239	.init = mst_fpga_init,
	240	.qdev.name = "mainstone-fpga",
	241	.qdev.desc = "Mainstone II FPGA",
	242	.qdev.size = sizeof(mst_irq_state),
	243	.qdev.vmsd = &vmstate_mst_fpga_regs,
	244	};
	245
	246	static void mst_fpga_register(void)
	247	{
	248	sysbus_register_withprop(&mst_fpga_info);
7233b355	249	}
cb380f61	250	device_init(mst_fpga_register);