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Use NICInfo::model for eepro100 savevm ID string (Mark McLoughlin)
[mirror_qemu.git] / hw / musicpal.c
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24859b68
AZ		 1/*
2 * Marvell MV88W8618 / Freecom MusicPal emulation.
3 *
4 * Copyright (c) 2008 Jan Kiszka
5 *
6 * This code is licenced under the GNU GPL v2.
7 */
8
9#include "hw.h"
10#include "arm-misc.h"
11#include "devices.h"
12#include "net.h"
13#include "sysemu.h"
14#include "boards.h"
15#include "pc.h"
16#include "qemu-timer.h"
17#include "block.h"
18#include "flash.h"
19#include "console.h"
20#include "audio/audio.h"
21#include "i2c.h"
22
718ec0be 23#define MP_MISC_BASE 0x80002000
24#define MP_MISC_SIZE 0x00001000
25
24859b68
AZ		 26#define MP_ETH_BASE 0x80008000
27#define MP_ETH_SIZE 0x00001000
28
718ec0be 29#define MP_WLAN_BASE 0x8000C000
30#define MP_WLAN_SIZE 0x00000800
31
24859b68
AZ		 32#define MP_UART1_BASE 0x8000C840
33#define MP_UART2_BASE 0x8000C940
34
718ec0be 35#define MP_GPIO_BASE 0x8000D000
36#define MP_GPIO_SIZE 0x00001000
37
24859b68
AZ		 38#define MP_FLASHCFG_BASE 0x90006000
39#define MP_FLASHCFG_SIZE 0x00001000
40
41#define MP_AUDIO_BASE 0x90007000
42#define MP_AUDIO_SIZE 0x00001000
43
44#define MP_PIC_BASE 0x90008000
45#define MP_PIC_SIZE 0x00001000
46
47#define MP_PIT_BASE 0x90009000
48#define MP_PIT_SIZE 0x00001000
49
50#define MP_LCD_BASE 0x9000c000
51#define MP_LCD_SIZE 0x00001000
52
53#define MP_SRAM_BASE 0xC0000000
54#define MP_SRAM_SIZE 0x00020000
55
56#define MP_RAM_DEFAULT_SIZE 32*1024*1024
57#define MP_FLASH_SIZE_MAX 32*1024*1024
58
59#define MP_TIMER1_IRQ 4
60/* ... */
61#define MP_TIMER4_IRQ 7
62#define MP_EHCI_IRQ 8
63#define MP_ETH_IRQ 9
64#define MP_UART1_IRQ 11
65#define MP_UART2_IRQ 11
66#define MP_GPIO_IRQ 12
67#define MP_RTC_IRQ 28
68#define MP_AUDIO_IRQ 30
69
70static uint32_t gpio_in_state = 0xffffffff;
7c6ce4ba 71static uint32_t gpio_isr;
24859b68
AZ		 72static uint32_t gpio_out_state;
73static ram_addr_t sram_off;
74
24859b68
AZ		 75typedef enum i2c_state {
76 STOPPED = 0,
77 INITIALIZING,
78 SENDING_BIT7,
79 SENDING_BIT6,
80 SENDING_BIT5,
81 SENDING_BIT4,
82 SENDING_BIT3,
83 SENDING_BIT2,
84 SENDING_BIT1,
85 SENDING_BIT0,
86 WAITING_FOR_ACK,
87 RECEIVING_BIT7,
88 RECEIVING_BIT6,
89 RECEIVING_BIT5,
90 RECEIVING_BIT4,
91 RECEIVING_BIT3,
92 RECEIVING_BIT2,
93 RECEIVING_BIT1,
94 RECEIVING_BIT0,
95 SENDING_ACK
96} i2c_state;
97
98typedef struct i2c_interface {
99 i2c_bus *bus;
100 i2c_state state;
101 int last_data;
102 int last_clock;
103 uint8_t buffer;
104 int current_addr;
105} i2c_interface;
106
107static void i2c_enter_stop(i2c_interface *i2c)
108{
109 if (i2c->current_addr >= 0)
110 i2c_end_transfer(i2c->bus);
111 i2c->current_addr = -1;
112 i2c->state = STOPPED;
113}
114
115static void i2c_state_update(i2c_interface *i2c, int data, int clock)
116{
117 if (!i2c)
118 return;
119
120 switch (i2c->state) {
121 case STOPPED:
122 if (data == 0 && i2c->last_data == 1 && clock == 1)
123 i2c->state = INITIALIZING;
124 break;
125
126 case INITIALIZING:
127 if (clock == 0 && i2c->last_clock == 1 && data == 0)
128 i2c->state = SENDING_BIT7;
129 else
130 i2c_enter_stop(i2c);
131 break;
132
133 case SENDING_BIT7 ... SENDING_BIT0:
134 if (clock == 0 && i2c->last_clock == 1) {
135 i2c->buffer = (i2c->buffer << 1) | data;
136 i2c->state++; /* will end up in WAITING_FOR_ACK */
137 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
138 i2c_enter_stop(i2c);
139 break;
140
141 case WAITING_FOR_ACK:
142 if (clock == 0 && i2c->last_clock == 1) {
143 if (i2c->current_addr < 0) {
144 i2c->current_addr = i2c->buffer;
145 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
146 i2c->buffer & 1);
147 } else
148 i2c_send(i2c->bus, i2c->buffer);
149 if (i2c->current_addr & 1) {
150 i2c->state = RECEIVING_BIT7;
151 i2c->buffer = i2c_recv(i2c->bus);
152 } else
153 i2c->state = SENDING_BIT7;
154 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
155 i2c_enter_stop(i2c);
156 break;
157
158 case RECEIVING_BIT7 ... RECEIVING_BIT0:
159 if (clock == 0 && i2c->last_clock == 1) {
160 i2c->state++; /* will end up in SENDING_ACK */
161 i2c->buffer <<= 1;
162 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
163 i2c_enter_stop(i2c);
164 break;
165
166 case SENDING_ACK:
167 if (clock == 0 && i2c->last_clock == 1) {
168 i2c->state = RECEIVING_BIT7;
169 if (data == 0)
170 i2c->buffer = i2c_recv(i2c->bus);
171 else
172 i2c_nack(i2c->bus);
173 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
174 i2c_enter_stop(i2c);
175 break;
176 }
177
178 i2c->last_data = data;
179 i2c->last_clock = clock;
180}
181
182static int i2c_get_data(i2c_interface *i2c)
183{
184 if (!i2c)
185 return 0;
186
187 switch (i2c->state) {
188 case RECEIVING_BIT7 ... RECEIVING_BIT0:
189 return (i2c->buffer >> 7);
190
191 case WAITING_FOR_ACK:
192 default:
193 return 0;
194 }
195}
196
197static i2c_interface *mixer_i2c;
198
199#ifdef HAS_AUDIO
200
201/* Audio register offsets */
202#define MP_AUDIO_PLAYBACK_MODE 0x00
203#define MP_AUDIO_CLOCK_DIV 0x18
204#define MP_AUDIO_IRQ_STATUS 0x20
205#define MP_AUDIO_IRQ_ENABLE 0x24
206#define MP_AUDIO_TX_START_LO 0x28
207#define MP_AUDIO_TX_THRESHOLD 0x2C
208#define MP_AUDIO_TX_STATUS 0x38
209#define MP_AUDIO_TX_START_HI 0x40
210
211/* Status register and IRQ enable bits */
212#define MP_AUDIO_TX_HALF (1 << 6)
213#define MP_AUDIO_TX_FULL (1 << 7)
214
215/* Playback mode bits */
216#define MP_AUDIO_16BIT_SAMPLE (1 << 0)
217#define MP_AUDIO_PLAYBACK_EN (1 << 7)
218#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
4001a81e 219#define MP_AUDIO_MONO (1 << 14)
24859b68
AZ		 220
221/* Wolfson 8750 I2C address */
222#define MP_WM_ADDR 0x34
223
b1d8e52e 224static const char audio_name[] = "mv88w8618";
24859b68
AZ		 225
226typedef struct musicpal_audio_state {
24859b68
AZ		 227 qemu_irq irq;
228 uint32_t playback_mode;
229 uint32_t status;
230 uint32_t irq_enable;
231 unsigned long phys_buf;
930c8682 232 uint32_t target_buffer;
24859b68
AZ		 233 unsigned int threshold;
234 unsigned int play_pos;
235 unsigned int last_free;
236 uint32_t clock_div;
237 i2c_slave *wm;
238} musicpal_audio_state;
239
240static void audio_callback(void *opaque, int free_out, int free_in)
241{
242 musicpal_audio_state *s = opaque;
4f3cb3be 243 int16_t *codec_buffer;
930c8682 244 int8_t buf[4096];
a350e694 245 int8_t *mem_buffer;
24859b68
AZ		 246 int pos, block_size;
247
248 if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
249 return;
250
251 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
4001a81e
AZ		 252 free_out <<= 1;
253
254 if (!(s->playback_mode & MP_AUDIO_MONO))
24859b68
AZ		 255 free_out <<= 1;
256
257 block_size = s->threshold/2;
258 if (free_out - s->last_free < block_size)
259 return;
260
930c8682
PB		 261 if (block_size > 4096)
262 return;
263
264 cpu_physical_memory_read(s->target_buffer + s->play_pos, (void *)buf,
265 block_size);
266 mem_buffer = buf;
4001a81e
AZ		 267 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
268 if (s->playback_mode & MP_AUDIO_MONO) {
269 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
270 for (pos = 0; pos < block_size; pos += 2) {
a350e694
AZ		 271 *codec_buffer++ = *(int16_t *)mem_buffer;
272 *codec_buffer++ = *(int16_t *)mem_buffer;
4f3cb3be 273 mem_buffer += 2;
4001a81e
AZ		 274 }
275 } else
276 memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
277 (uint32_t *)mem_buffer, block_size);
278 } else {
279 if (s->playback_mode & MP_AUDIO_MONO) {
280 codec_buffer = wm8750_dac_buffer(s->wm, block_size);
281 for (pos = 0; pos < block_size; pos++) {
a350e694
AZ		 282 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
283 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
4001a81e
AZ		 284 }
285 } else {
286 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
287 for (pos = 0; pos < block_size; pos += 2) {
a350e694
AZ		 288 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
289 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
4001a81e 290 }
24859b68 291 }
662caa6f
AZ		 292 }
293 wm8750_dac_commit(s->wm);
24859b68
AZ		 294
295 s->last_free = free_out - block_size;
296
297 if (s->play_pos == 0) {
298 s->status |= MP_AUDIO_TX_HALF;
299 s->play_pos = block_size;
300 } else {
301 s->status |= MP_AUDIO_TX_FULL;
302 s->play_pos = 0;
303 }
304
305 if (s->status & s->irq_enable)
306 qemu_irq_raise(s->irq);
307}
308
af83e09e
AZ		 309static void musicpal_audio_clock_update(musicpal_audio_state *s)
310{
311 int rate;
312
313 if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
314 rate = 24576000 / 64; /* 24.576MHz */
315 else
316 rate = 11289600 / 64; /* 11.2896MHz */
317
318 rate /= ((s->clock_div >> 8) & 0xff) + 1;
319
91834991 320 wm8750_set_bclk_in(s->wm, rate);
af83e09e
AZ		 321}
322
24859b68
AZ		 323static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
324{
325 musicpal_audio_state *s = opaque;
326
24859b68
AZ		 327 switch (offset) {
328 case MP_AUDIO_PLAYBACK_MODE:
329 return s->playback_mode;
330
331 case MP_AUDIO_CLOCK_DIV:
332 return s->clock_div;
333
334 case MP_AUDIO_IRQ_STATUS:
335 return s->status;
336
337 case MP_AUDIO_IRQ_ENABLE:
338 return s->irq_enable;
339
340 case MP_AUDIO_TX_STATUS:
341 return s->play_pos >> 2;
342
343 default:
344 return 0;
345 }
346}
347
348static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
349 uint32_t value)
350{
351 musicpal_audio_state *s = opaque;
352
24859b68
AZ		 353 switch (offset) {
354 case MP_AUDIO_PLAYBACK_MODE:
355 if (value & MP_AUDIO_PLAYBACK_EN &&
356 !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
357 s->status = 0;
358 s->last_free = 0;
359 s->play_pos = 0;
360 }
361 s->playback_mode = value;
af83e09e 362 musicpal_audio_clock_update(s);
24859b68
AZ		 363 break;
364
365 case MP_AUDIO_CLOCK_DIV:
366 s->clock_div = value;
367 s->last_free = 0;
368 s->play_pos = 0;
af83e09e 369 musicpal_audio_clock_update(s);
24859b68
AZ		 370 break;
371
372 case MP_AUDIO_IRQ_STATUS:
373 s->status &= ~value;
374 break;
375
376 case MP_AUDIO_IRQ_ENABLE:
377 s->irq_enable = value;
378 if (s->status & s->irq_enable)
379 qemu_irq_raise(s->irq);
380 break;
381
382 case MP_AUDIO_TX_START_LO:
383 s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
930c8682 384 s->target_buffer = s->phys_buf;
24859b68
AZ		 385 s->play_pos = 0;
386 s->last_free = 0;
387 break;
388
389 case MP_AUDIO_TX_THRESHOLD:
390 s->threshold = (value + 1) * 4;
391 break;
392
393 case MP_AUDIO_TX_START_HI:
394 s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
930c8682 395 s->target_buffer = s->phys_buf;
24859b68
AZ		 396 s->play_pos = 0;
397 s->last_free = 0;
398 break;
399 }
400}
401
402static void musicpal_audio_reset(void *opaque)
403{
404 musicpal_audio_state *s = opaque;
405
406 s->playback_mode = 0;
407 s->status = 0;
408 s->irq_enable = 0;
409}
410
411static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
412 musicpal_audio_read,
413 musicpal_audio_read,
414 musicpal_audio_read
415};
416
417static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
418 musicpal_audio_write,
419 musicpal_audio_write,
420 musicpal_audio_write
421};
422
718ec0be 423static i2c_interface *musicpal_audio_init(qemu_irq irq)
24859b68
AZ		 424{
425 AudioState *audio;
426 musicpal_audio_state *s;
427 i2c_interface *i2c;
428 int iomemtype;
429
430 audio = AUD_init();
431 if (!audio) {
432 AUD_log(audio_name, "No audio state\n");
433 return NULL;
434 }
435
436 s = qemu_mallocz(sizeof(musicpal_audio_state));
24859b68
AZ		 437 s->irq = irq;
438
439 i2c = qemu_mallocz(sizeof(i2c_interface));
24859b68
AZ		 440 i2c->bus = i2c_init_bus();
441 i2c->current_addr = -1;
442
443 s->wm = wm8750_init(i2c->bus, audio);
444 if (!s->wm)
445 return NULL;
446 i2c_set_slave_address(s->wm, MP_WM_ADDR);
447 wm8750_data_req_set(s->wm, audio_callback, s);
448
449 iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
450 musicpal_audio_writefn, s);
718ec0be 451 cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
24859b68
AZ		 452
453 qemu_register_reset(musicpal_audio_reset, s);
454
455 return i2c;
456}
457#else /* !HAS_AUDIO */
718ec0be 458static i2c_interface *musicpal_audio_init(qemu_irq irq)
24859b68
AZ		 459{
460 return NULL;
461}
462#endif /* !HAS_AUDIO */
463
464/* Ethernet register offsets */
465#define MP_ETH_SMIR 0x010
466#define MP_ETH_PCXR 0x408
467#define MP_ETH_SDCMR 0x448
468#define MP_ETH_ICR 0x450
469#define MP_ETH_IMR 0x458
470#define MP_ETH_FRDP0 0x480
471#define MP_ETH_FRDP1 0x484
472#define MP_ETH_FRDP2 0x488
473#define MP_ETH_FRDP3 0x48C
474#define MP_ETH_CRDP0 0x4A0
475#define MP_ETH_CRDP1 0x4A4
476#define MP_ETH_CRDP2 0x4A8
477#define MP_ETH_CRDP3 0x4AC
478#define MP_ETH_CTDP0 0x4E0
479#define MP_ETH_CTDP1 0x4E4
480#define MP_ETH_CTDP2 0x4E8
481#define MP_ETH_CTDP3 0x4EC
482
483/* MII PHY access */
484#define MP_ETH_SMIR_DATA 0x0000FFFF
485#define MP_ETH_SMIR_ADDR 0x03FF0000
486#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
487#define MP_ETH_SMIR_RDVALID (1 << 27)
488
489/* PHY registers */
490#define MP_ETH_PHY1_BMSR 0x00210000
491#define MP_ETH_PHY1_PHYSID1 0x00410000
492#define MP_ETH_PHY1_PHYSID2 0x00610000
493
494#define MP_PHY_BMSR_LINK 0x0004
495#define MP_PHY_BMSR_AUTONEG 0x0008
496
497#define MP_PHY_88E3015 0x01410E20
498
499/* TX descriptor status */
500#define MP_ETH_TX_OWN (1 << 31)
501
502/* RX descriptor status */
503#define MP_ETH_RX_OWN (1 << 31)
504
505/* Interrupt cause/mask bits */
506#define MP_ETH_IRQ_RX_BIT 0
507#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
508#define MP_ETH_IRQ_TXHI_BIT 2
509#define MP_ETH_IRQ_TXLO_BIT 3
510
511/* Port config bits */
512#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
513
514/* SDMA command bits */
515#define MP_ETH_CMD_TXHI (1 << 23)
516#define MP_ETH_CMD_TXLO (1 << 22)
517
518typedef struct mv88w8618_tx_desc {
519 uint32_t cmdstat;
520 uint16_t res;
521 uint16_t bytes;
522 uint32_t buffer;
523 uint32_t next;
524} mv88w8618_tx_desc;
525
526typedef struct mv88w8618_rx_desc {
527 uint32_t cmdstat;
528 uint16_t bytes;
529 uint16_t buffer_size;
530 uint32_t buffer;
531 uint32_t next;
532} mv88w8618_rx_desc;
533
534typedef struct mv88w8618_eth_state {
24859b68
AZ		 535 qemu_irq irq;
536 uint32_t smir;
537 uint32_t icr;
538 uint32_t imr;
539 int vlan_header;
930c8682
PB		 540 uint32_t tx_queue[2];
541 uint32_t rx_queue[4];
542 uint32_t frx_queue[4];
543 uint32_t cur_rx[4];
24859b68
AZ		 544 VLANClientState *vc;
545} mv88w8618_eth_state;
546
930c8682
PB		 547static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
548{
549 cpu_to_le32s(&desc->cmdstat);
550 cpu_to_le16s(&desc->bytes);
551 cpu_to_le16s(&desc->buffer_size);
552 cpu_to_le32s(&desc->buffer);
553 cpu_to_le32s(&desc->next);
554 cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
555}
556
557static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
558{
559 cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
560 le32_to_cpus(&desc->cmdstat);
561 le16_to_cpus(&desc->bytes);
562 le16_to_cpus(&desc->buffer_size);
563 le32_to_cpus(&desc->buffer);
564 le32_to_cpus(&desc->next);
565}
566
24859b68
AZ		 567static int eth_can_receive(void *opaque)
568{
569 return 1;
570}
571
572static void eth_receive(void *opaque, const uint8_t *buf, int size)
573{
574 mv88w8618_eth_state *s = opaque;
930c8682
PB		 575 uint32_t desc_addr;
576 mv88w8618_rx_desc desc;
24859b68
AZ		 577 int i;
578
579 for (i = 0; i < 4; i++) {
930c8682
PB		 580 desc_addr = s->cur_rx[i];
581 if (!desc_addr)
24859b68
AZ		 582 continue;
583 do {
930c8682
PB		 584 eth_rx_desc_get(desc_addr, &desc);
585 if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
586 cpu_physical_memory_write(desc.buffer + s->vlan_header,
587 buf, size);
588 desc.bytes = size + s->vlan_header;
589 desc.cmdstat &= ~MP_ETH_RX_OWN;
590 s->cur_rx[i] = desc.next;
24859b68
AZ		 591
592 s->icr |= MP_ETH_IRQ_RX;
593 if (s->icr & s->imr)
594 qemu_irq_raise(s->irq);
930c8682 595 eth_rx_desc_put(desc_addr, &desc);
24859b68
AZ		 596 return;
597 }
930c8682
PB		 598 desc_addr = desc.next;
599 } while (desc_addr != s->rx_queue[i]);
24859b68
AZ		 600 }
601}
602
930c8682
PB		 603static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
604{
605 cpu_to_le32s(&desc->cmdstat);
606 cpu_to_le16s(&desc->res);
607 cpu_to_le16s(&desc->bytes);
608 cpu_to_le32s(&desc->buffer);
609 cpu_to_le32s(&desc->next);
610 cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
611}
612
613static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
614{
615 cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
616 le32_to_cpus(&desc->cmdstat);
617 le16_to_cpus(&desc->res);
618 le16_to_cpus(&desc->bytes);
619 le32_to_cpus(&desc->buffer);
620 le32_to_cpus(&desc->next);
621}
622
24859b68
AZ		 623static void eth_send(mv88w8618_eth_state *s, int queue_index)
624{
930c8682
PB		 625 uint32_t desc_addr = s->tx_queue[queue_index];
626 mv88w8618_tx_desc desc;
627 uint8_t buf[2048];
628 int len;
629
24859b68
AZ		 630
631 do {
930c8682
PB		 632 eth_tx_desc_get(desc_addr, &desc);
633 if (desc.cmdstat & MP_ETH_TX_OWN) {
634 len = desc.bytes;
635 if (len < 2048) {
636 cpu_physical_memory_read(desc.buffer, buf, len);
637 qemu_send_packet(s->vc, buf, len);
638 }
639 desc.cmdstat &= ~MP_ETH_TX_OWN;
24859b68 640 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
930c8682 641 eth_tx_desc_put(desc_addr, &desc);
24859b68 642 }
930c8682
PB		 643 desc_addr = desc.next;
644 } while (desc_addr != s->tx_queue[queue_index]);
24859b68
AZ		 645}
646
647static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
648{
649 mv88w8618_eth_state *s = opaque;
650
24859b68
AZ		 651 switch (offset) {
652 case MP_ETH_SMIR:
653 if (s->smir & MP_ETH_SMIR_OPCODE) {
654 switch (s->smir & MP_ETH_SMIR_ADDR) {
655 case MP_ETH_PHY1_BMSR:
656 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
657 MP_ETH_SMIR_RDVALID;
658 case MP_ETH_PHY1_PHYSID1:
659 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
660 case MP_ETH_PHY1_PHYSID2:
661 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
662 default:
663 return MP_ETH_SMIR_RDVALID;
664 }
665 }
666 return 0;
667
668 case MP_ETH_ICR:
669 return s->icr;
670
671 case MP_ETH_IMR:
672 return s->imr;
673
674 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
930c8682 675 return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
24859b68
AZ		 676
677 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
930c8682 678 return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
24859b68
AZ		 679
680 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
930c8682 681 return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
24859b68
AZ		 682
683 default:
684 return 0;
685 }
686}
687
688static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
689 uint32_t value)
690{
691 mv88w8618_eth_state *s = opaque;
692
24859b68
AZ		 693 switch (offset) {
694 case MP_ETH_SMIR:
695 s->smir = value;
696 break;
697
698 case MP_ETH_PCXR:
699 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
700 break;
701
702 case MP_ETH_SDCMR:
703 if (value & MP_ETH_CMD_TXHI)
704 eth_send(s, 1);
705 if (value & MP_ETH_CMD_TXLO)
706 eth_send(s, 0);
707 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
708 qemu_irq_raise(s->irq);
709 break;
710
711 case MP_ETH_ICR:
712 s->icr &= value;
713 break;
714
715 case MP_ETH_IMR:
716 s->imr = value;
717 if (s->icr & s->imr)
718 qemu_irq_raise(s->irq);
719 break;
720
721 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
930c8682 722 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
24859b68
AZ		 723 break;
724
725 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
726 s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
930c8682 727 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
24859b68
AZ		 728 break;
729
730 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
930c8682 731 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
24859b68
AZ		 732 break;
733 }
734}
735
736static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
737 mv88w8618_eth_read,
738 mv88w8618_eth_read,
739 mv88w8618_eth_read
740};
741
742static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
743 mv88w8618_eth_write,
744 mv88w8618_eth_write,
745 mv88w8618_eth_write
746};
747
748static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
749{
750 mv88w8618_eth_state *s;
751 int iomemtype;
752
0ae18cee
AL		 753 qemu_check_nic_model(nd, "mv88w8618");
754
24859b68 755 s = qemu_mallocz(sizeof(mv88w8618_eth_state));
24859b68 756 s->irq = irq;
7a9f6e4a 757 s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
bf38c1a0 758 eth_receive, eth_can_receive, s);
24859b68
AZ		 759 iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
760 mv88w8618_eth_writefn, s);
761 cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype);
762}
763
764/* LCD register offsets */
765#define MP_LCD_IRQCTRL 0x180
766#define MP_LCD_IRQSTAT 0x184
767#define MP_LCD_SPICTRL 0x1ac
768#define MP_LCD_INST 0x1bc
769#define MP_LCD_DATA 0x1c0
770
771/* Mode magics */
772#define MP_LCD_SPI_DATA 0x00100011
773#define MP_LCD_SPI_CMD 0x00104011
774#define MP_LCD_SPI_INVALID 0x00000000
775
776/* Commmands */
777#define MP_LCD_INST_SETPAGE0 0xB0
778/* ... */
779#define MP_LCD_INST_SETPAGE7 0xB7
780
781#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
782
783typedef struct musicpal_lcd_state {
24859b68
AZ		 784 uint32_t mode;
785 uint32_t irqctrl;
786 int page;
787 int page_off;
788 DisplayState *ds;
789 uint8_t video_ram[128*64/8];
790} musicpal_lcd_state;
791
792static uint32_t lcd_brightness;
793
794static uint8_t scale_lcd_color(uint8_t col)
795{
796 int tmp = col;
797
798 switch (lcd_brightness) {
799 case 0x00000007: /* 0 */
800 return 0;
801
802 case 0x00020000: /* 1 */
803 return (tmp * 1) / 7;
804
805 case 0x00020001: /* 2 */
806 return (tmp * 2) / 7;
807
808 case 0x00040000: /* 3 */
809 return (tmp * 3) / 7;
810
811 case 0x00010006: /* 4 */
812 return (tmp * 4) / 7;
813
814 case 0x00020005: /* 5 */
815 return (tmp * 5) / 7;
816
817 case 0x00040003: /* 6 */
818 return (tmp * 6) / 7;
819
820 case 0x00030004: /* 7 */
821 default:
822 return col;
823 }
824}
825
0266f2c7
AZ		 826#define SET_LCD_PIXEL(depth, type) \
827static inline void glue(set_lcd_pixel, depth) \
828 (musicpal_lcd_state *s, int x, int y, type col) \
829{ \
830 int dx, dy; \
0e1f5a0c 831 type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
0266f2c7
AZ		 832\
833 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
834 for (dx = 0; dx < 3; dx++, pixel++) \
835 *pixel = col; \
24859b68 836}
0266f2c7
AZ		 837SET_LCD_PIXEL(8, uint8_t)
838SET_LCD_PIXEL(16, uint16_t)
839SET_LCD_PIXEL(32, uint32_t)
840
841#include "pixel_ops.h"
24859b68
AZ		 842
843static void lcd_refresh(void *opaque)
844{
845 musicpal_lcd_state *s = opaque;
0266f2c7 846 int x, y, col;
24859b68 847
0e1f5a0c 848 switch (ds_get_bits_per_pixel(s->ds)) {
0266f2c7
AZ		 849 case 0:
850 return;
851#define LCD_REFRESH(depth, func) \
852 case depth: \
853 col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
854 scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
855 scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
856 for (x = 0; x < 128; x++) \
857 for (y = 0; y < 64; y++) \
858 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
859 glue(set_lcd_pixel, depth)(s, x, y, col); \
860 else \
861 glue(set_lcd_pixel, depth)(s, x, y, 0); \
862 break;
863 LCD_REFRESH(8, rgb_to_pixel8)
864 LCD_REFRESH(16, rgb_to_pixel16)
bf9b48af
AL		 865 LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
866 rgb_to_pixel32bgr : rgb_to_pixel32))
0266f2c7
AZ		 867 default:
868 cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
0e1f5a0c 869 ds_get_bits_per_pixel(s->ds));
0266f2c7 870 }
24859b68
AZ		 871
872 dpy_update(s->ds, 0, 0, 128*3, 64*3);
873}
874
167bc3d2
AZ		 875static void lcd_invalidate(void *opaque)
876{
167bc3d2
AZ		 877}
878
24859b68
AZ		 879static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
880{
881 musicpal_lcd_state *s = opaque;
882
24859b68
AZ		 883 switch (offset) {
884 case MP_LCD_IRQCTRL:
885 return s->irqctrl;
886
887 default:
888 return 0;
889 }
890}
891
892static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
893 uint32_t value)
894{
895 musicpal_lcd_state *s = opaque;
896
24859b68
AZ		 897 switch (offset) {
898 case MP_LCD_IRQCTRL:
899 s->irqctrl = value;
900 break;
901
902 case MP_LCD_SPICTRL:
903 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
904 s->mode = value;
905 else
906 s->mode = MP_LCD_SPI_INVALID;
907 break;
908
909 case MP_LCD_INST:
910 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
911 s->page = value - MP_LCD_INST_SETPAGE0;
912 s->page_off = 0;
913 }
914 break;
915
916 case MP_LCD_DATA:
917 if (s->mode == MP_LCD_SPI_CMD) {
918 if (value >= MP_LCD_INST_SETPAGE0 &&
919 value <= MP_LCD_INST_SETPAGE7) {
920 s->page = value - MP_LCD_INST_SETPAGE0;
921 s->page_off = 0;
922 }
923 } else if (s->mode == MP_LCD_SPI_DATA) {
924 s->video_ram[s->page*128 + s->page_off] = value;
925 s->page_off = (s->page_off + 1) & 127;
926 }
927 break;
928 }
929}
930
931static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
932 musicpal_lcd_read,
933 musicpal_lcd_read,
934 musicpal_lcd_read
935};
936
937static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
938 musicpal_lcd_write,
939 musicpal_lcd_write,
940 musicpal_lcd_write
941};
942
718ec0be 943static void musicpal_lcd_init(void)
24859b68
AZ		 944{
945 musicpal_lcd_state *s;
946 int iomemtype;
947
948 s = qemu_mallocz(sizeof(musicpal_lcd_state));
24859b68
AZ		 949 iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
950 musicpal_lcd_writefn, s);
718ec0be 951 cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype);
24859b68 952
3023f332
AL		 953 s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
954 NULL, NULL, s);
955 qemu_console_resize(s->ds, 128*3, 64*3);
24859b68
AZ		 956}
957
958/* PIC register offsets */
959#define MP_PIC_STATUS 0x00
960#define MP_PIC_ENABLE_SET 0x08
961#define MP_PIC_ENABLE_CLR 0x0C
962
963typedef struct mv88w8618_pic_state
964{
24859b68
AZ		 965 uint32_t level;
966 uint32_t enabled;
967 qemu_irq parent_irq;
968} mv88w8618_pic_state;
969
970static void mv88w8618_pic_update(mv88w8618_pic_state *s)
971{
972 qemu_set_irq(s->parent_irq, (s->level & s->enabled));
973}
974
975static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
976{
977 mv88w8618_pic_state *s = opaque;
978
979 if (level)
980 s->level |= 1 << irq;
981 else
982 s->level &= ~(1 << irq);
983 mv88w8618_pic_update(s);
984}
985
986static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
987{
988 mv88w8618_pic_state *s = opaque;
989
24859b68
AZ		 990 switch (offset) {
991 case MP_PIC_STATUS:
992 return s->level & s->enabled;
993
994 default:
995 return 0;
996 }
997}
998
999static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
1000 uint32_t value)
1001{
1002 mv88w8618_pic_state *s = opaque;
1003
24859b68
AZ		 1004 switch (offset) {
1005 case MP_PIC_ENABLE_SET:
1006 s->enabled |= value;
1007 break;
1008
1009 case MP_PIC_ENABLE_CLR:
1010 s->enabled &= ~value;
1011 s->level &= ~value;
1012 break;
1013 }
1014 mv88w8618_pic_update(s);
1015}
1016
1017static void mv88w8618_pic_reset(void *opaque)
1018{
1019 mv88w8618_pic_state *s = opaque;
1020
1021 s->level = 0;
1022 s->enabled = 0;
1023}
1024
1025static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
1026 mv88w8618_pic_read,
1027 mv88w8618_pic_read,
1028 mv88w8618_pic_read
1029};
1030
1031static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
1032 mv88w8618_pic_write,
1033 mv88w8618_pic_write,
1034 mv88w8618_pic_write
1035};
1036
1037static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
1038{
1039 mv88w8618_pic_state *s;
1040 int iomemtype;
1041 qemu_irq *qi;
1042
1043 s = qemu_mallocz(sizeof(mv88w8618_pic_state));
24859b68 1044 qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
24859b68
AZ		 1045 s->parent_irq = parent_irq;
1046 iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1047 mv88w8618_pic_writefn, s);
1048 cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1049
1050 qemu_register_reset(mv88w8618_pic_reset, s);
1051
1052 return qi;
1053}
1054
1055/* PIT register offsets */
1056#define MP_PIT_TIMER1_LENGTH 0x00
1057/* ... */
1058#define MP_PIT_TIMER4_LENGTH 0x0C
1059#define MP_PIT_CONTROL 0x10
1060#define MP_PIT_TIMER1_VALUE 0x14
1061/* ... */
1062#define MP_PIT_TIMER4_VALUE 0x20
1063#define MP_BOARD_RESET 0x34
1064
1065/* Magic board reset value (probably some watchdog behind it) */
1066#define MP_BOARD_RESET_MAGIC 0x10000
1067
1068typedef struct mv88w8618_timer_state {
1069 ptimer_state *timer;
1070 uint32_t limit;
1071 int freq;
1072 qemu_irq irq;
1073} mv88w8618_timer_state;
1074
1075typedef struct mv88w8618_pit_state {
1076 void *timer[4];
1077 uint32_t control;
24859b68
AZ		 1078} mv88w8618_pit_state;
1079
1080static void mv88w8618_timer_tick(void *opaque)
1081{
1082 mv88w8618_timer_state *s = opaque;
1083
1084 qemu_irq_raise(s->irq);
1085}
1086
1087static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1088{
1089 mv88w8618_timer_state *s;
1090 QEMUBH *bh;
1091
1092 s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1093 s->irq = irq;
1094 s->freq = freq;
1095
1096 bh = qemu_bh_new(mv88w8618_timer_tick, s);
1097 s->timer = ptimer_init(bh);
1098
1099 return s;
1100}
1101
1102static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1103{
1104 mv88w8618_pit_state *s = opaque;
1105 mv88w8618_timer_state *t;
1106
24859b68
AZ		 1107 switch (offset) {
1108 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1109 t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1110 return ptimer_get_count(t->timer);
1111
1112 default:
1113 return 0;
1114 }
1115}
1116
1117static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1118 uint32_t value)
1119{
1120 mv88w8618_pit_state *s = opaque;
1121 mv88w8618_timer_state *t;
1122 int i;
1123
24859b68
AZ		 1124 switch (offset) {
1125 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1126 t = s->timer[offset >> 2];
1127 t->limit = value;
1128 ptimer_set_limit(t->timer, t->limit, 1);
1129 break;
1130
1131 case MP_PIT_CONTROL:
1132 for (i = 0; i < 4; i++) {
1133 if (value & 0xf) {
1134 t = s->timer[i];
1135 ptimer_set_limit(t->timer, t->limit, 0);
1136 ptimer_set_freq(t->timer, t->freq);
1137 ptimer_run(t->timer, 0);
1138 }
1139 value >>= 4;
1140 }
1141 break;
1142
1143 case MP_BOARD_RESET:
1144 if (value == MP_BOARD_RESET_MAGIC)
1145 qemu_system_reset_request();
1146 break;
1147 }
1148}
1149
1150static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1151 mv88w8618_pit_read,
1152 mv88w8618_pit_read,
1153 mv88w8618_pit_read
1154};
1155
1156static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1157 mv88w8618_pit_write,
1158 mv88w8618_pit_write,
1159 mv88w8618_pit_write
1160};
1161
1162static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1163{
1164 int iomemtype;
1165 mv88w8618_pit_state *s;
1166
1167 s = qemu_mallocz(sizeof(mv88w8618_pit_state));
24859b68 1168
24859b68
AZ		 1169 /* Letting them all run at 1 MHz is likely just a pragmatic
1170 * simplification. */
1171 s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1172 s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1173 s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1174 s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1175
1176 iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1177 mv88w8618_pit_writefn, s);
1178 cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1179}
1180
1181/* Flash config register offsets */
1182#define MP_FLASHCFG_CFGR0 0x04
1183
1184typedef struct mv88w8618_flashcfg_state {
24859b68
AZ		 1185 uint32_t cfgr0;
1186} mv88w8618_flashcfg_state;
1187
1188static uint32_t mv88w8618_flashcfg_read(void *opaque,
1189 target_phys_addr_t offset)
1190{
1191 mv88w8618_flashcfg_state *s = opaque;
1192
24859b68
AZ		 1193 switch (offset) {
1194 case MP_FLASHCFG_CFGR0:
1195 return s->cfgr0;
1196
1197 default:
1198 return 0;
1199 }
1200}
1201
1202static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1203 uint32_t value)
1204{
1205 mv88w8618_flashcfg_state *s = opaque;
1206
24859b68
AZ		 1207 switch (offset) {
1208 case MP_FLASHCFG_CFGR0:
1209 s->cfgr0 = value;
1210 break;
1211 }
1212}
1213
1214static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1215 mv88w8618_flashcfg_read,
1216 mv88w8618_flashcfg_read,
1217 mv88w8618_flashcfg_read
1218};
1219
1220static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1221 mv88w8618_flashcfg_write,
1222 mv88w8618_flashcfg_write,
1223 mv88w8618_flashcfg_write
1224};
1225
1226static void mv88w8618_flashcfg_init(uint32_t base)
1227{
1228 int iomemtype;
1229 mv88w8618_flashcfg_state *s;
1230
1231 s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
24859b68 1232
24859b68
AZ		 1233 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1234 iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1235 mv88w8618_flashcfg_writefn, s);
1236 cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1237}
1238
718ec0be 1239/* Misc register offsets */
1240#define MP_MISC_BOARD_REVISION 0x18
1241
1242#define MP_BOARD_REVISION 0x31
1243
1244static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
1245{
1246 switch (offset) {
1247 case MP_MISC_BOARD_REVISION:
1248 return MP_BOARD_REVISION;
1249
1250 default:
1251 return 0;
1252 }
1253}
1254
1255static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1256 uint32_t value)
1257{
1258}
1259
1260static CPUReadMemoryFunc *musicpal_misc_readfn[] = {
1261 musicpal_misc_read,
1262 musicpal_misc_read,
1263 musicpal_misc_read,
1264};
1265
1266static CPUWriteMemoryFunc *musicpal_misc_writefn[] = {
1267 musicpal_misc_write,
1268 musicpal_misc_write,
1269 musicpal_misc_write,
1270};
1271
1272static void musicpal_misc_init(void)
1273{
1274 int iomemtype;
1275
1276 iomemtype = cpu_register_io_memory(0, musicpal_misc_readfn,
1277 musicpal_misc_writefn, NULL);
1278 cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
1279}
1280
1281/* WLAN register offsets */
1282#define MP_WLAN_MAGIC1 0x11c
1283#define MP_WLAN_MAGIC2 0x124
1284
1285static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
1286{
1287 switch (offset) {
1288 /* Workaround to allow loading the binary-only wlandrv.ko crap
1289 * from the original Freecom firmware. */
1290 case MP_WLAN_MAGIC1:
1291 return ~3;
1292 case MP_WLAN_MAGIC2:
1293 return -1;
1294
1295 default:
1296 return 0;
1297 }
1298}
1299
1300static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1301 uint32_t value)
1302{
1303}
1304
1305static CPUReadMemoryFunc *mv88w8618_wlan_readfn[] = {
1306 mv88w8618_wlan_read,
1307 mv88w8618_wlan_read,
1308 mv88w8618_wlan_read,
1309};
1310
1311static CPUWriteMemoryFunc *mv88w8618_wlan_writefn[] = {
1312 mv88w8618_wlan_write,
1313 mv88w8618_wlan_write,
1314 mv88w8618_wlan_write,
1315};
1316
1317static void mv88w8618_wlan_init(uint32_t base)
1318{
1319 int iomemtype;
24859b68 1320
718ec0be 1321 iomemtype = cpu_register_io_memory(0, mv88w8618_wlan_readfn,
1322 mv88w8618_wlan_writefn, NULL);
1323 cpu_register_physical_memory(base, MP_WLAN_SIZE, iomemtype);
1324}
24859b68 1325
718ec0be 1326/* GPIO register offsets */
1327#define MP_GPIO_OE_LO 0x008
1328#define MP_GPIO_OUT_LO 0x00c
1329#define MP_GPIO_IN_LO 0x010
1330#define MP_GPIO_ISR_LO 0x020
1331#define MP_GPIO_OE_HI 0x508
1332#define MP_GPIO_OUT_HI 0x50c
1333#define MP_GPIO_IN_HI 0x510
1334#define MP_GPIO_ISR_HI 0x520
24859b68
AZ		 1335
1336/* GPIO bits & masks */
1337#define MP_GPIO_WHEEL_VOL (1 << 8)
1338#define MP_GPIO_WHEEL_VOL_INV (1 << 9)
1339#define MP_GPIO_WHEEL_NAV (1 << 10)
1340#define MP_GPIO_WHEEL_NAV_INV (1 << 11)
1341#define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1342#define MP_GPIO_BTN_FAVORITS (1 << 19)
1343#define MP_GPIO_BTN_MENU (1 << 20)
1344#define MP_GPIO_BTN_VOLUME (1 << 21)
1345#define MP_GPIO_BTN_NAVIGATION (1 << 22)
1346#define MP_GPIO_I2C_DATA_BIT 29
1347#define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT)
1348#define MP_GPIO_I2C_CLOCK_BIT 30
1349
1350/* LCD brightness bits in GPIO_OE_HI */
1351#define MP_OE_LCD_BRIGHTNESS 0x0007
1352
718ec0be 1353static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
24859b68 1354{
24859b68 1355 switch (offset) {
24859b68
AZ		 1356 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1357 return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1358
1359 case MP_GPIO_OUT_LO:
1360 return gpio_out_state & 0xFFFF;
1361 case MP_GPIO_OUT_HI:
1362 return gpio_out_state >> 16;
1363
1364 case MP_GPIO_IN_LO:
1365 return gpio_in_state & 0xFFFF;
1366 case MP_GPIO_IN_HI:
1367 /* Update received I2C data */
1368 gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1369 (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1370 return gpio_in_state >> 16;
1371
24859b68 1372 case MP_GPIO_ISR_LO:
7c6ce4ba 1373 return gpio_isr & 0xFFFF;
24859b68 1374 case MP_GPIO_ISR_HI:
7c6ce4ba 1375 return gpio_isr >> 16;
24859b68 1376
24859b68
AZ		 1377 default:
1378 return 0;
1379 }
1380}
1381
718ec0be 1382static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1383 uint32_t value)
24859b68 1384{
24859b68
AZ		 1385 switch (offset) {
1386 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1387 lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1388 (value & MP_OE_LCD_BRIGHTNESS);
1389 break;
1390
1391 case MP_GPIO_OUT_LO:
1392 gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1393 break;
1394 case MP_GPIO_OUT_HI:
1395 gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1396 lcd_brightness = (lcd_brightness & 0xFFFF) |
1397 (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1398 i2c_state_update(mixer_i2c,
1399 (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1400 (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1401 break;
1402
1403 }
1404}
1405
718ec0be 1406static CPUReadMemoryFunc *musicpal_gpio_readfn[] = {
1407 musicpal_gpio_read,
1408 musicpal_gpio_read,
1409 musicpal_gpio_read,
1410};
1411
1412static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = {
1413 musicpal_gpio_write,
1414 musicpal_gpio_write,
1415 musicpal_gpio_write,
1416};
1417
1418static void musicpal_gpio_init(void)
1419{
1420 int iomemtype;
1421
1422 iomemtype = cpu_register_io_memory(0, musicpal_gpio_readfn,
1423 musicpal_gpio_writefn, NULL);
1424 cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype);
1425}
1426
24859b68 1427/* Keyboard codes & masks */
7c6ce4ba 1428#define KEY_RELEASED 0x80
24859b68
AZ		 1429#define KEY_CODE 0x7f
1430
1431#define KEYCODE_TAB 0x0f
1432#define KEYCODE_ENTER 0x1c
1433#define KEYCODE_F 0x21
1434#define KEYCODE_M 0x32
1435
1436#define KEYCODE_EXTENDED 0xe0
1437#define KEYCODE_UP 0x48
1438#define KEYCODE_DOWN 0x50
1439#define KEYCODE_LEFT 0x4b
1440#define KEYCODE_RIGHT 0x4d
1441
1442static void musicpal_key_event(void *opaque, int keycode)
1443{
1444 qemu_irq irq = opaque;
1445 uint32_t event = 0;
1446 static int kbd_extended;
1447
1448 if (keycode == KEYCODE_EXTENDED) {
1449 kbd_extended = 1;
1450 return;
1451 }
1452
1453 if (kbd_extended)
1454 switch (keycode & KEY_CODE) {
1455 case KEYCODE_UP:
1456 event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1457 break;
1458
1459 case KEYCODE_DOWN:
1460 event = MP_GPIO_WHEEL_NAV;
1461 break;
1462
1463 case KEYCODE_LEFT:
1464 event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1465 break;
1466
1467 case KEYCODE_RIGHT:
1468 event = MP_GPIO_WHEEL_VOL;
1469 break;
1470 }
7c6ce4ba 1471 else {
24859b68
AZ		 1472 switch (keycode & KEY_CODE) {
1473 case KEYCODE_F:
1474 event = MP_GPIO_BTN_FAVORITS;
1475 break;
1476
1477 case KEYCODE_TAB:
1478 event = MP_GPIO_BTN_VOLUME;
1479 break;
1480
1481 case KEYCODE_ENTER:
1482 event = MP_GPIO_BTN_NAVIGATION;
1483 break;
1484
1485 case KEYCODE_M:
1486 event = MP_GPIO_BTN_MENU;
1487 break;
1488 }
7c6ce4ba
AZ		 1489 /* Do not repeat already pressed buttons */
1490 if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
1491 event = 0;
1492 }
24859b68 1493
7c6ce4ba
AZ		 1494 if (event) {
1495 if (keycode & KEY_RELEASED) {
1496 gpio_in_state |= event;
1497 } else {
1498 gpio_in_state &= ~event;
1499 gpio_isr = event;
1500 qemu_irq_raise(irq);
1501 }
24859b68
AZ		 1502 }
1503
1504 kbd_extended = 0;
1505}
1506
24859b68
AZ		 1507static struct arm_boot_info musicpal_binfo = {
1508 .loader_start = 0x0,
1509 .board_id = 0x20e,
1510};
1511
b0f6edb1 1512static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
3023f332 1513 const char *boot_device,
24859b68
AZ		 1514 const char *kernel_filename, const char *kernel_cmdline,
1515 const char *initrd_filename, const char *cpu_model)
1516{
1517 CPUState *env;
1518 qemu_irq *pic;
1519 int index;
24859b68
AZ		 1520 unsigned long flash_size;
1521
1522 if (!cpu_model)
1523 cpu_model = "arm926";
1524
1525 env = cpu_init(cpu_model);
1526 if (!env) {
1527 fprintf(stderr, "Unable to find CPU definition\n");
1528 exit(1);
1529 }
1530 pic = arm_pic_init_cpu(env);
1531
1532 /* For now we use a fixed - the original - RAM size */
1533 cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1534 qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1535
1536 sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1537 cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1538
24859b68
AZ		 1539 pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1540 mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1541
1542 if (serial_hds[0])
b6cd0ea1 1543 serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
24859b68
AZ		 1544 serial_hds[0], 1);
1545 if (serial_hds[1])
b6cd0ea1 1546 serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
24859b68
AZ		 1547 serial_hds[1], 1);
1548
1549 /* Register flash */
1550 index = drive_get_index(IF_PFLASH, 0, 0);
1551 if (index != -1) {
1552 flash_size = bdrv_getlength(drives_table[index].bdrv);
1553 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1554 flash_size != 32*1024*1024) {
1555 fprintf(stderr, "Invalid flash image size\n");
1556 exit(1);
1557 }
1558
1559 /*
1560 * The original U-Boot accesses the flash at 0xFE000000 instead of
1561 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1562 * image is smaller than 32 MB.
1563 */
1564 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1565 drives_table[index].bdrv, 0x10000,
1566 (flash_size + 0xffff) >> 16,
1567 MP_FLASH_SIZE_MAX / flash_size,
1568 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1569 0x5555, 0x2AAA);
1570 }
1571 mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1572
718ec0be 1573 musicpal_lcd_init();
24859b68
AZ		 1574
1575 qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1576
24859b68
AZ		 1577 mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1578
718ec0be 1579 mixer_i2c = musicpal_audio_init(pic[MP_AUDIO_IRQ]);
1580
1581 mv88w8618_wlan_init(MP_WLAN_BASE);
1582
1583 musicpal_misc_init();
1584 musicpal_gpio_init();
24859b68
AZ		 1585
1586 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1587 musicpal_binfo.kernel_filename = kernel_filename;
1588 musicpal_binfo.kernel_cmdline = kernel_cmdline;
1589 musicpal_binfo.initrd_filename = initrd_filename;
b0f6edb1 1590 arm_load_kernel(env, &musicpal_binfo);
24859b68
AZ		 1591}
1592
1593QEMUMachine musicpal_machine = {
4b32e168
AL		 1594 .name = "musicpal",
1595 .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1596 .init = musicpal_init,
24859b68 1597};
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