]>
Commit | Line | Data |
---|---|---|
24859b68 AZ |
1 | /* |
2 | * Marvell MV88W8618 / Freecom MusicPal emulation. | |
3 | * | |
4 | * Copyright (c) 2008 Jan Kiszka | |
5 | * | |
6 | * This code is licenced under the GNU GPL v2. | |
7 | */ | |
8 | ||
b47b50fa | 9 | #include "sysbus.h" |
24859b68 AZ |
10 | #include "arm-misc.h" |
11 | #include "devices.h" | |
12 | #include "net.h" | |
13 | #include "sysemu.h" | |
14 | #include "boards.h" | |
15 | #include "pc.h" | |
16 | #include "qemu-timer.h" | |
17 | #include "block.h" | |
18 | #include "flash.h" | |
19 | #include "console.h" | |
24859b68 AZ |
20 | #include "i2c.h" |
21 | ||
718ec0be | 22 | #define MP_MISC_BASE 0x80002000 |
23 | #define MP_MISC_SIZE 0x00001000 | |
24 | ||
24859b68 AZ |
25 | #define MP_ETH_BASE 0x80008000 |
26 | #define MP_ETH_SIZE 0x00001000 | |
27 | ||
718ec0be | 28 | #define MP_WLAN_BASE 0x8000C000 |
29 | #define MP_WLAN_SIZE 0x00000800 | |
30 | ||
24859b68 AZ |
31 | #define MP_UART1_BASE 0x8000C840 |
32 | #define MP_UART2_BASE 0x8000C940 | |
33 | ||
718ec0be | 34 | #define MP_GPIO_BASE 0x8000D000 |
35 | #define MP_GPIO_SIZE 0x00001000 | |
36 | ||
24859b68 AZ |
37 | #define MP_FLASHCFG_BASE 0x90006000 |
38 | #define MP_FLASHCFG_SIZE 0x00001000 | |
39 | ||
40 | #define MP_AUDIO_BASE 0x90007000 | |
24859b68 AZ |
41 | |
42 | #define MP_PIC_BASE 0x90008000 | |
43 | #define MP_PIC_SIZE 0x00001000 | |
44 | ||
45 | #define MP_PIT_BASE 0x90009000 | |
46 | #define MP_PIT_SIZE 0x00001000 | |
47 | ||
48 | #define MP_LCD_BASE 0x9000c000 | |
49 | #define MP_LCD_SIZE 0x00001000 | |
50 | ||
51 | #define MP_SRAM_BASE 0xC0000000 | |
52 | #define MP_SRAM_SIZE 0x00020000 | |
53 | ||
54 | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 | |
55 | #define MP_FLASH_SIZE_MAX 32*1024*1024 | |
56 | ||
57 | #define MP_TIMER1_IRQ 4 | |
b47b50fa PB |
58 | #define MP_TIMER2_IRQ 5 |
59 | #define MP_TIMER3_IRQ 6 | |
24859b68 AZ |
60 | #define MP_TIMER4_IRQ 7 |
61 | #define MP_EHCI_IRQ 8 | |
62 | #define MP_ETH_IRQ 9 | |
63 | #define MP_UART1_IRQ 11 | |
64 | #define MP_UART2_IRQ 11 | |
65 | #define MP_GPIO_IRQ 12 | |
66 | #define MP_RTC_IRQ 28 | |
67 | #define MP_AUDIO_IRQ 30 | |
68 | ||
24859b68 AZ |
69 | /* Wolfson 8750 I2C address */ |
70 | #define MP_WM_ADDR 0x34 | |
71 | ||
24859b68 AZ |
72 | /* Ethernet register offsets */ |
73 | #define MP_ETH_SMIR 0x010 | |
74 | #define MP_ETH_PCXR 0x408 | |
75 | #define MP_ETH_SDCMR 0x448 | |
76 | #define MP_ETH_ICR 0x450 | |
77 | #define MP_ETH_IMR 0x458 | |
78 | #define MP_ETH_FRDP0 0x480 | |
79 | #define MP_ETH_FRDP1 0x484 | |
80 | #define MP_ETH_FRDP2 0x488 | |
81 | #define MP_ETH_FRDP3 0x48C | |
82 | #define MP_ETH_CRDP0 0x4A0 | |
83 | #define MP_ETH_CRDP1 0x4A4 | |
84 | #define MP_ETH_CRDP2 0x4A8 | |
85 | #define MP_ETH_CRDP3 0x4AC | |
86 | #define MP_ETH_CTDP0 0x4E0 | |
87 | #define MP_ETH_CTDP1 0x4E4 | |
88 | #define MP_ETH_CTDP2 0x4E8 | |
89 | #define MP_ETH_CTDP3 0x4EC | |
90 | ||
91 | /* MII PHY access */ | |
92 | #define MP_ETH_SMIR_DATA 0x0000FFFF | |
93 | #define MP_ETH_SMIR_ADDR 0x03FF0000 | |
94 | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ | |
95 | #define MP_ETH_SMIR_RDVALID (1 << 27) | |
96 | ||
97 | /* PHY registers */ | |
98 | #define MP_ETH_PHY1_BMSR 0x00210000 | |
99 | #define MP_ETH_PHY1_PHYSID1 0x00410000 | |
100 | #define MP_ETH_PHY1_PHYSID2 0x00610000 | |
101 | ||
102 | #define MP_PHY_BMSR_LINK 0x0004 | |
103 | #define MP_PHY_BMSR_AUTONEG 0x0008 | |
104 | ||
105 | #define MP_PHY_88E3015 0x01410E20 | |
106 | ||
107 | /* TX descriptor status */ | |
108 | #define MP_ETH_TX_OWN (1 << 31) | |
109 | ||
110 | /* RX descriptor status */ | |
111 | #define MP_ETH_RX_OWN (1 << 31) | |
112 | ||
113 | /* Interrupt cause/mask bits */ | |
114 | #define MP_ETH_IRQ_RX_BIT 0 | |
115 | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) | |
116 | #define MP_ETH_IRQ_TXHI_BIT 2 | |
117 | #define MP_ETH_IRQ_TXLO_BIT 3 | |
118 | ||
119 | /* Port config bits */ | |
120 | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ | |
121 | ||
122 | /* SDMA command bits */ | |
123 | #define MP_ETH_CMD_TXHI (1 << 23) | |
124 | #define MP_ETH_CMD_TXLO (1 << 22) | |
125 | ||
126 | typedef struct mv88w8618_tx_desc { | |
127 | uint32_t cmdstat; | |
128 | uint16_t res; | |
129 | uint16_t bytes; | |
130 | uint32_t buffer; | |
131 | uint32_t next; | |
132 | } mv88w8618_tx_desc; | |
133 | ||
134 | typedef struct mv88w8618_rx_desc { | |
135 | uint32_t cmdstat; | |
136 | uint16_t bytes; | |
137 | uint16_t buffer_size; | |
138 | uint32_t buffer; | |
139 | uint32_t next; | |
140 | } mv88w8618_rx_desc; | |
141 | ||
142 | typedef struct mv88w8618_eth_state { | |
b47b50fa | 143 | SysBusDevice busdev; |
24859b68 AZ |
144 | qemu_irq irq; |
145 | uint32_t smir; | |
146 | uint32_t icr; | |
147 | uint32_t imr; | |
b946a153 | 148 | int mmio_index; |
24859b68 | 149 | int vlan_header; |
930c8682 PB |
150 | uint32_t tx_queue[2]; |
151 | uint32_t rx_queue[4]; | |
152 | uint32_t frx_queue[4]; | |
153 | uint32_t cur_rx[4]; | |
24859b68 AZ |
154 | VLANClientState *vc; |
155 | } mv88w8618_eth_state; | |
156 | ||
930c8682 PB |
157 | static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
158 | { | |
159 | cpu_to_le32s(&desc->cmdstat); | |
160 | cpu_to_le16s(&desc->bytes); | |
161 | cpu_to_le16s(&desc->buffer_size); | |
162 | cpu_to_le32s(&desc->buffer); | |
163 | cpu_to_le32s(&desc->next); | |
164 | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); | |
165 | } | |
166 | ||
167 | static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) | |
168 | { | |
169 | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); | |
170 | le32_to_cpus(&desc->cmdstat); | |
171 | le16_to_cpus(&desc->bytes); | |
172 | le16_to_cpus(&desc->buffer_size); | |
173 | le32_to_cpus(&desc->buffer); | |
174 | le32_to_cpus(&desc->next); | |
175 | } | |
176 | ||
e3f5ec2b | 177 | static int eth_can_receive(VLANClientState *vc) |
24859b68 AZ |
178 | { |
179 | return 1; | |
180 | } | |
181 | ||
4f1c942b | 182 | static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size) |
24859b68 | 183 | { |
e3f5ec2b | 184 | mv88w8618_eth_state *s = vc->opaque; |
930c8682 PB |
185 | uint32_t desc_addr; |
186 | mv88w8618_rx_desc desc; | |
24859b68 AZ |
187 | int i; |
188 | ||
189 | for (i = 0; i < 4; i++) { | |
930c8682 | 190 | desc_addr = s->cur_rx[i]; |
49fedd0d | 191 | if (!desc_addr) { |
24859b68 | 192 | continue; |
49fedd0d | 193 | } |
24859b68 | 194 | do { |
930c8682 PB |
195 | eth_rx_desc_get(desc_addr, &desc); |
196 | if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { | |
197 | cpu_physical_memory_write(desc.buffer + s->vlan_header, | |
198 | buf, size); | |
199 | desc.bytes = size + s->vlan_header; | |
200 | desc.cmdstat &= ~MP_ETH_RX_OWN; | |
201 | s->cur_rx[i] = desc.next; | |
24859b68 AZ |
202 | |
203 | s->icr |= MP_ETH_IRQ_RX; | |
49fedd0d | 204 | if (s->icr & s->imr) { |
24859b68 | 205 | qemu_irq_raise(s->irq); |
49fedd0d | 206 | } |
930c8682 | 207 | eth_rx_desc_put(desc_addr, &desc); |
4f1c942b | 208 | return size; |
24859b68 | 209 | } |
930c8682 PB |
210 | desc_addr = desc.next; |
211 | } while (desc_addr != s->rx_queue[i]); | |
24859b68 | 212 | } |
4f1c942b | 213 | return size; |
24859b68 AZ |
214 | } |
215 | ||
930c8682 PB |
216 | static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
217 | { | |
218 | cpu_to_le32s(&desc->cmdstat); | |
219 | cpu_to_le16s(&desc->res); | |
220 | cpu_to_le16s(&desc->bytes); | |
221 | cpu_to_le32s(&desc->buffer); | |
222 | cpu_to_le32s(&desc->next); | |
223 | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); | |
224 | } | |
225 | ||
226 | static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) | |
227 | { | |
228 | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); | |
229 | le32_to_cpus(&desc->cmdstat); | |
230 | le16_to_cpus(&desc->res); | |
231 | le16_to_cpus(&desc->bytes); | |
232 | le32_to_cpus(&desc->buffer); | |
233 | le32_to_cpus(&desc->next); | |
234 | } | |
235 | ||
24859b68 AZ |
236 | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
237 | { | |
930c8682 PB |
238 | uint32_t desc_addr = s->tx_queue[queue_index]; |
239 | mv88w8618_tx_desc desc; | |
240 | uint8_t buf[2048]; | |
241 | int len; | |
242 | ||
2e87c5b9 JK |
243 | if (!desc_addr) { |
244 | return; | |
245 | } | |
24859b68 | 246 | do { |
930c8682 PB |
247 | eth_tx_desc_get(desc_addr, &desc); |
248 | if (desc.cmdstat & MP_ETH_TX_OWN) { | |
249 | len = desc.bytes; | |
250 | if (len < 2048) { | |
251 | cpu_physical_memory_read(desc.buffer, buf, len); | |
252 | qemu_send_packet(s->vc, buf, len); | |
253 | } | |
254 | desc.cmdstat &= ~MP_ETH_TX_OWN; | |
24859b68 | 255 | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); |
930c8682 | 256 | eth_tx_desc_put(desc_addr, &desc); |
24859b68 | 257 | } |
930c8682 PB |
258 | desc_addr = desc.next; |
259 | } while (desc_addr != s->tx_queue[queue_index]); | |
24859b68 AZ |
260 | } |
261 | ||
c227f099 | 262 | static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) |
24859b68 AZ |
263 | { |
264 | mv88w8618_eth_state *s = opaque; | |
265 | ||
24859b68 AZ |
266 | switch (offset) { |
267 | case MP_ETH_SMIR: | |
268 | if (s->smir & MP_ETH_SMIR_OPCODE) { | |
269 | switch (s->smir & MP_ETH_SMIR_ADDR) { | |
270 | case MP_ETH_PHY1_BMSR: | |
271 | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | | |
272 | MP_ETH_SMIR_RDVALID; | |
273 | case MP_ETH_PHY1_PHYSID1: | |
274 | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; | |
275 | case MP_ETH_PHY1_PHYSID2: | |
276 | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; | |
277 | default: | |
278 | return MP_ETH_SMIR_RDVALID; | |
279 | } | |
280 | } | |
281 | return 0; | |
282 | ||
283 | case MP_ETH_ICR: | |
284 | return s->icr; | |
285 | ||
286 | case MP_ETH_IMR: | |
287 | return s->imr; | |
288 | ||
289 | case MP_ETH_FRDP0 ... MP_ETH_FRDP3: | |
930c8682 | 290 | return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
24859b68 AZ |
291 | |
292 | case MP_ETH_CRDP0 ... MP_ETH_CRDP3: | |
930c8682 | 293 | return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
24859b68 AZ |
294 | |
295 | case MP_ETH_CTDP0 ... MP_ETH_CTDP3: | |
930c8682 | 296 | return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
24859b68 AZ |
297 | |
298 | default: | |
299 | return 0; | |
300 | } | |
301 | } | |
302 | ||
c227f099 | 303 | static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, |
24859b68 AZ |
304 | uint32_t value) |
305 | { | |
306 | mv88w8618_eth_state *s = opaque; | |
307 | ||
24859b68 AZ |
308 | switch (offset) { |
309 | case MP_ETH_SMIR: | |
310 | s->smir = value; | |
311 | break; | |
312 | ||
313 | case MP_ETH_PCXR: | |
314 | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; | |
315 | break; | |
316 | ||
317 | case MP_ETH_SDCMR: | |
49fedd0d | 318 | if (value & MP_ETH_CMD_TXHI) { |
24859b68 | 319 | eth_send(s, 1); |
49fedd0d JK |
320 | } |
321 | if (value & MP_ETH_CMD_TXLO) { | |
24859b68 | 322 | eth_send(s, 0); |
49fedd0d JK |
323 | } |
324 | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { | |
24859b68 | 325 | qemu_irq_raise(s->irq); |
49fedd0d | 326 | } |
24859b68 AZ |
327 | break; |
328 | ||
329 | case MP_ETH_ICR: | |
330 | s->icr &= value; | |
331 | break; | |
332 | ||
333 | case MP_ETH_IMR: | |
334 | s->imr = value; | |
49fedd0d | 335 | if (s->icr & s->imr) { |
24859b68 | 336 | qemu_irq_raise(s->irq); |
49fedd0d | 337 | } |
24859b68 AZ |
338 | break; |
339 | ||
340 | case MP_ETH_FRDP0 ... MP_ETH_FRDP3: | |
930c8682 | 341 | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; |
24859b68 AZ |
342 | break; |
343 | ||
344 | case MP_ETH_CRDP0 ... MP_ETH_CRDP3: | |
345 | s->rx_queue[(offset - MP_ETH_CRDP0)/4] = | |
930c8682 | 346 | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; |
24859b68 AZ |
347 | break; |
348 | ||
349 | case MP_ETH_CTDP0 ... MP_ETH_CTDP3: | |
930c8682 | 350 | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; |
24859b68 AZ |
351 | break; |
352 | } | |
353 | } | |
354 | ||
d60efc6b | 355 | static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = { |
24859b68 AZ |
356 | mv88w8618_eth_read, |
357 | mv88w8618_eth_read, | |
358 | mv88w8618_eth_read | |
359 | }; | |
360 | ||
d60efc6b | 361 | static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = { |
24859b68 AZ |
362 | mv88w8618_eth_write, |
363 | mv88w8618_eth_write, | |
364 | mv88w8618_eth_write | |
365 | }; | |
366 | ||
b946a153 AL |
367 | static void eth_cleanup(VLANClientState *vc) |
368 | { | |
369 | mv88w8618_eth_state *s = vc->opaque; | |
370 | ||
371 | cpu_unregister_io_memory(s->mmio_index); | |
372 | ||
373 | qemu_free(s); | |
374 | } | |
375 | ||
81a322d4 | 376 | static int mv88w8618_eth_init(SysBusDevice *dev) |
24859b68 | 377 | { |
b47b50fa | 378 | mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev); |
0ae18cee | 379 | |
b47b50fa PB |
380 | sysbus_init_irq(dev, &s->irq); |
381 | s->vc = qdev_get_vlan_client(&dev->qdev, | |
463af534 | 382 | eth_can_receive, eth_receive, NULL, |
b946a153 | 383 | eth_cleanup, s); |
1eed09cb | 384 | s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn, |
b946a153 | 385 | mv88w8618_eth_writefn, s); |
b47b50fa | 386 | sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index); |
81a322d4 | 387 | return 0; |
24859b68 AZ |
388 | } |
389 | ||
390 | /* LCD register offsets */ | |
391 | #define MP_LCD_IRQCTRL 0x180 | |
392 | #define MP_LCD_IRQSTAT 0x184 | |
393 | #define MP_LCD_SPICTRL 0x1ac | |
394 | #define MP_LCD_INST 0x1bc | |
395 | #define MP_LCD_DATA 0x1c0 | |
396 | ||
397 | /* Mode magics */ | |
398 | #define MP_LCD_SPI_DATA 0x00100011 | |
399 | #define MP_LCD_SPI_CMD 0x00104011 | |
400 | #define MP_LCD_SPI_INVALID 0x00000000 | |
401 | ||
402 | /* Commmands */ | |
403 | #define MP_LCD_INST_SETPAGE0 0xB0 | |
404 | /* ... */ | |
405 | #define MP_LCD_INST_SETPAGE7 0xB7 | |
406 | ||
407 | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ | |
408 | ||
409 | typedef struct musicpal_lcd_state { | |
b47b50fa | 410 | SysBusDevice busdev; |
343ec8e4 | 411 | uint32_t brightness; |
24859b68 AZ |
412 | uint32_t mode; |
413 | uint32_t irqctrl; | |
414 | int page; | |
415 | int page_off; | |
416 | DisplayState *ds; | |
417 | uint8_t video_ram[128*64/8]; | |
418 | } musicpal_lcd_state; | |
419 | ||
343ec8e4 | 420 | static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) |
24859b68 | 421 | { |
343ec8e4 BC |
422 | switch (s->brightness) { |
423 | case 7: | |
424 | return col; | |
425 | case 0: | |
24859b68 | 426 | return 0; |
24859b68 | 427 | default: |
343ec8e4 | 428 | return (col * s->brightness) / 7; |
24859b68 AZ |
429 | } |
430 | } | |
431 | ||
0266f2c7 AZ |
432 | #define SET_LCD_PIXEL(depth, type) \ |
433 | static inline void glue(set_lcd_pixel, depth) \ | |
434 | (musicpal_lcd_state *s, int x, int y, type col) \ | |
435 | { \ | |
436 | int dx, dy; \ | |
0e1f5a0c | 437 | type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \ |
0266f2c7 AZ |
438 | \ |
439 | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ | |
440 | for (dx = 0; dx < 3; dx++, pixel++) \ | |
441 | *pixel = col; \ | |
24859b68 | 442 | } |
0266f2c7 AZ |
443 | SET_LCD_PIXEL(8, uint8_t) |
444 | SET_LCD_PIXEL(16, uint16_t) | |
445 | SET_LCD_PIXEL(32, uint32_t) | |
446 | ||
447 | #include "pixel_ops.h" | |
24859b68 AZ |
448 | |
449 | static void lcd_refresh(void *opaque) | |
450 | { | |
451 | musicpal_lcd_state *s = opaque; | |
0266f2c7 | 452 | int x, y, col; |
24859b68 | 453 | |
0e1f5a0c | 454 | switch (ds_get_bits_per_pixel(s->ds)) { |
0266f2c7 AZ |
455 | case 0: |
456 | return; | |
457 | #define LCD_REFRESH(depth, func) \ | |
458 | case depth: \ | |
343ec8e4 BC |
459 | col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
460 | scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ | |
461 | scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ | |
49fedd0d JK |
462 | for (x = 0; x < 128; x++) { \ |
463 | for (y = 0; y < 64; y++) { \ | |
464 | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ | |
0266f2c7 | 465 | glue(set_lcd_pixel, depth)(s, x, y, col); \ |
49fedd0d | 466 | } else { \ |
0266f2c7 | 467 | glue(set_lcd_pixel, depth)(s, x, y, 0); \ |
49fedd0d JK |
468 | } \ |
469 | } \ | |
470 | } \ | |
0266f2c7 AZ |
471 | break; |
472 | LCD_REFRESH(8, rgb_to_pixel8) | |
473 | LCD_REFRESH(16, rgb_to_pixel16) | |
bf9b48af AL |
474 | LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ? |
475 | rgb_to_pixel32bgr : rgb_to_pixel32)) | |
0266f2c7 | 476 | default: |
2ac71179 | 477 | hw_error("unsupported colour depth %i\n", |
0e1f5a0c | 478 | ds_get_bits_per_pixel(s->ds)); |
0266f2c7 | 479 | } |
24859b68 AZ |
480 | |
481 | dpy_update(s->ds, 0, 0, 128*3, 64*3); | |
482 | } | |
483 | ||
167bc3d2 AZ |
484 | static void lcd_invalidate(void *opaque) |
485 | { | |
167bc3d2 AZ |
486 | } |
487 | ||
343ec8e4 BC |
488 | static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level) |
489 | { | |
243cd13c | 490 | musicpal_lcd_state *s = opaque; |
343ec8e4 BC |
491 | s->brightness &= ~(1 << irq); |
492 | s->brightness |= level << irq; | |
493 | } | |
494 | ||
c227f099 | 495 | static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
24859b68 AZ |
496 | { |
497 | musicpal_lcd_state *s = opaque; | |
498 | ||
24859b68 AZ |
499 | switch (offset) { |
500 | case MP_LCD_IRQCTRL: | |
501 | return s->irqctrl; | |
502 | ||
503 | default: | |
504 | return 0; | |
505 | } | |
506 | } | |
507 | ||
c227f099 | 508 | static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, |
24859b68 AZ |
509 | uint32_t value) |
510 | { | |
511 | musicpal_lcd_state *s = opaque; | |
512 | ||
24859b68 AZ |
513 | switch (offset) { |
514 | case MP_LCD_IRQCTRL: | |
515 | s->irqctrl = value; | |
516 | break; | |
517 | ||
518 | case MP_LCD_SPICTRL: | |
49fedd0d | 519 | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) { |
24859b68 | 520 | s->mode = value; |
49fedd0d | 521 | } else { |
24859b68 | 522 | s->mode = MP_LCD_SPI_INVALID; |
49fedd0d | 523 | } |
24859b68 AZ |
524 | break; |
525 | ||
526 | case MP_LCD_INST: | |
527 | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { | |
528 | s->page = value - MP_LCD_INST_SETPAGE0; | |
529 | s->page_off = 0; | |
530 | } | |
531 | break; | |
532 | ||
533 | case MP_LCD_DATA: | |
534 | if (s->mode == MP_LCD_SPI_CMD) { | |
535 | if (value >= MP_LCD_INST_SETPAGE0 && | |
536 | value <= MP_LCD_INST_SETPAGE7) { | |
537 | s->page = value - MP_LCD_INST_SETPAGE0; | |
538 | s->page_off = 0; | |
539 | } | |
540 | } else if (s->mode == MP_LCD_SPI_DATA) { | |
541 | s->video_ram[s->page*128 + s->page_off] = value; | |
542 | s->page_off = (s->page_off + 1) & 127; | |
543 | } | |
544 | break; | |
545 | } | |
546 | } | |
547 | ||
d60efc6b | 548 | static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = { |
24859b68 AZ |
549 | musicpal_lcd_read, |
550 | musicpal_lcd_read, | |
551 | musicpal_lcd_read | |
552 | }; | |
553 | ||
d60efc6b | 554 | static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = { |
24859b68 AZ |
555 | musicpal_lcd_write, |
556 | musicpal_lcd_write, | |
557 | musicpal_lcd_write | |
558 | }; | |
559 | ||
81a322d4 | 560 | static int musicpal_lcd_init(SysBusDevice *dev) |
24859b68 | 561 | { |
b47b50fa | 562 | musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev); |
24859b68 AZ |
563 | int iomemtype; |
564 | ||
343ec8e4 BC |
565 | s->brightness = 7; |
566 | ||
1eed09cb | 567 | iomemtype = cpu_register_io_memory(musicpal_lcd_readfn, |
24859b68 | 568 | musicpal_lcd_writefn, s); |
b47b50fa | 569 | sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype); |
24859b68 | 570 | |
3023f332 AL |
571 | s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, |
572 | NULL, NULL, s); | |
573 | qemu_console_resize(s->ds, 128*3, 64*3); | |
343ec8e4 BC |
574 | |
575 | qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3); | |
81a322d4 GH |
576 | |
577 | return 0; | |
24859b68 AZ |
578 | } |
579 | ||
580 | /* PIC register offsets */ | |
581 | #define MP_PIC_STATUS 0x00 | |
582 | #define MP_PIC_ENABLE_SET 0x08 | |
583 | #define MP_PIC_ENABLE_CLR 0x0C | |
584 | ||
585 | typedef struct mv88w8618_pic_state | |
586 | { | |
b47b50fa | 587 | SysBusDevice busdev; |
24859b68 AZ |
588 | uint32_t level; |
589 | uint32_t enabled; | |
590 | qemu_irq parent_irq; | |
591 | } mv88w8618_pic_state; | |
592 | ||
593 | static void mv88w8618_pic_update(mv88w8618_pic_state *s) | |
594 | { | |
595 | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); | |
596 | } | |
597 | ||
598 | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) | |
599 | { | |
600 | mv88w8618_pic_state *s = opaque; | |
601 | ||
49fedd0d | 602 | if (level) { |
24859b68 | 603 | s->level |= 1 << irq; |
49fedd0d | 604 | } else { |
24859b68 | 605 | s->level &= ~(1 << irq); |
49fedd0d | 606 | } |
24859b68 AZ |
607 | mv88w8618_pic_update(s); |
608 | } | |
609 | ||
c227f099 | 610 | static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) |
24859b68 AZ |
611 | { |
612 | mv88w8618_pic_state *s = opaque; | |
613 | ||
24859b68 AZ |
614 | switch (offset) { |
615 | case MP_PIC_STATUS: | |
616 | return s->level & s->enabled; | |
617 | ||
618 | default: | |
619 | return 0; | |
620 | } | |
621 | } | |
622 | ||
c227f099 | 623 | static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, |
24859b68 AZ |
624 | uint32_t value) |
625 | { | |
626 | mv88w8618_pic_state *s = opaque; | |
627 | ||
24859b68 AZ |
628 | switch (offset) { |
629 | case MP_PIC_ENABLE_SET: | |
630 | s->enabled |= value; | |
631 | break; | |
632 | ||
633 | case MP_PIC_ENABLE_CLR: | |
634 | s->enabled &= ~value; | |
635 | s->level &= ~value; | |
636 | break; | |
637 | } | |
638 | mv88w8618_pic_update(s); | |
639 | } | |
640 | ||
641 | static void mv88w8618_pic_reset(void *opaque) | |
642 | { | |
643 | mv88w8618_pic_state *s = opaque; | |
644 | ||
645 | s->level = 0; | |
646 | s->enabled = 0; | |
647 | } | |
648 | ||
d60efc6b | 649 | static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = { |
24859b68 AZ |
650 | mv88w8618_pic_read, |
651 | mv88w8618_pic_read, | |
652 | mv88w8618_pic_read | |
653 | }; | |
654 | ||
d60efc6b | 655 | static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = { |
24859b68 AZ |
656 | mv88w8618_pic_write, |
657 | mv88w8618_pic_write, | |
658 | mv88w8618_pic_write | |
659 | }; | |
660 | ||
81a322d4 | 661 | static int mv88w8618_pic_init(SysBusDevice *dev) |
24859b68 | 662 | { |
b47b50fa | 663 | mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev); |
24859b68 | 664 | int iomemtype; |
24859b68 | 665 | |
067a3ddc | 666 | qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32); |
b47b50fa | 667 | sysbus_init_irq(dev, &s->parent_irq); |
1eed09cb | 668 | iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn, |
24859b68 | 669 | mv88w8618_pic_writefn, s); |
b47b50fa | 670 | sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); |
24859b68 | 671 | |
a08d4367 | 672 | qemu_register_reset(mv88w8618_pic_reset, s); |
81a322d4 | 673 | return 0; |
24859b68 AZ |
674 | } |
675 | ||
676 | /* PIT register offsets */ | |
677 | #define MP_PIT_TIMER1_LENGTH 0x00 | |
678 | /* ... */ | |
679 | #define MP_PIT_TIMER4_LENGTH 0x0C | |
680 | #define MP_PIT_CONTROL 0x10 | |
681 | #define MP_PIT_TIMER1_VALUE 0x14 | |
682 | /* ... */ | |
683 | #define MP_PIT_TIMER4_VALUE 0x20 | |
684 | #define MP_BOARD_RESET 0x34 | |
685 | ||
686 | /* Magic board reset value (probably some watchdog behind it) */ | |
687 | #define MP_BOARD_RESET_MAGIC 0x10000 | |
688 | ||
689 | typedef struct mv88w8618_timer_state { | |
b47b50fa | 690 | ptimer_state *ptimer; |
24859b68 AZ |
691 | uint32_t limit; |
692 | int freq; | |
693 | qemu_irq irq; | |
694 | } mv88w8618_timer_state; | |
695 | ||
696 | typedef struct mv88w8618_pit_state { | |
b47b50fa PB |
697 | SysBusDevice busdev; |
698 | mv88w8618_timer_state timer[4]; | |
24859b68 | 699 | uint32_t control; |
24859b68 AZ |
700 | } mv88w8618_pit_state; |
701 | ||
702 | static void mv88w8618_timer_tick(void *opaque) | |
703 | { | |
704 | mv88w8618_timer_state *s = opaque; | |
705 | ||
706 | qemu_irq_raise(s->irq); | |
707 | } | |
708 | ||
b47b50fa PB |
709 | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
710 | uint32_t freq) | |
24859b68 | 711 | { |
24859b68 AZ |
712 | QEMUBH *bh; |
713 | ||
b47b50fa | 714 | sysbus_init_irq(dev, &s->irq); |
24859b68 AZ |
715 | s->freq = freq; |
716 | ||
717 | bh = qemu_bh_new(mv88w8618_timer_tick, s); | |
b47b50fa | 718 | s->ptimer = ptimer_init(bh); |
24859b68 AZ |
719 | } |
720 | ||
c227f099 | 721 | static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) |
24859b68 AZ |
722 | { |
723 | mv88w8618_pit_state *s = opaque; | |
724 | mv88w8618_timer_state *t; | |
725 | ||
24859b68 AZ |
726 | switch (offset) { |
727 | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: | |
b47b50fa PB |
728 | t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; |
729 | return ptimer_get_count(t->ptimer); | |
24859b68 AZ |
730 | |
731 | default: | |
732 | return 0; | |
733 | } | |
734 | } | |
735 | ||
c227f099 | 736 | static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, |
24859b68 AZ |
737 | uint32_t value) |
738 | { | |
739 | mv88w8618_pit_state *s = opaque; | |
740 | mv88w8618_timer_state *t; | |
741 | int i; | |
742 | ||
24859b68 AZ |
743 | switch (offset) { |
744 | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: | |
b47b50fa | 745 | t = &s->timer[offset >> 2]; |
24859b68 | 746 | t->limit = value; |
b47b50fa | 747 | ptimer_set_limit(t->ptimer, t->limit, 1); |
24859b68 AZ |
748 | break; |
749 | ||
750 | case MP_PIT_CONTROL: | |
751 | for (i = 0; i < 4; i++) { | |
752 | if (value & 0xf) { | |
b47b50fa PB |
753 | t = &s->timer[i]; |
754 | ptimer_set_limit(t->ptimer, t->limit, 0); | |
755 | ptimer_set_freq(t->ptimer, t->freq); | |
756 | ptimer_run(t->ptimer, 0); | |
24859b68 AZ |
757 | } |
758 | value >>= 4; | |
759 | } | |
760 | break; | |
761 | ||
762 | case MP_BOARD_RESET: | |
49fedd0d | 763 | if (value == MP_BOARD_RESET_MAGIC) { |
24859b68 | 764 | qemu_system_reset_request(); |
49fedd0d | 765 | } |
24859b68 AZ |
766 | break; |
767 | } | |
768 | } | |
769 | ||
d60efc6b | 770 | static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = { |
24859b68 AZ |
771 | mv88w8618_pit_read, |
772 | mv88w8618_pit_read, | |
773 | mv88w8618_pit_read | |
774 | }; | |
775 | ||
d60efc6b | 776 | static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = { |
24859b68 AZ |
777 | mv88w8618_pit_write, |
778 | mv88w8618_pit_write, | |
779 | mv88w8618_pit_write | |
780 | }; | |
781 | ||
81a322d4 | 782 | static int mv88w8618_pit_init(SysBusDevice *dev) |
24859b68 AZ |
783 | { |
784 | int iomemtype; | |
b47b50fa PB |
785 | mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev); |
786 | int i; | |
24859b68 | 787 | |
24859b68 AZ |
788 | /* Letting them all run at 1 MHz is likely just a pragmatic |
789 | * simplification. */ | |
b47b50fa PB |
790 | for (i = 0; i < 4; i++) { |
791 | mv88w8618_timer_init(dev, &s->timer[i], 1000000); | |
792 | } | |
24859b68 | 793 | |
1eed09cb | 794 | iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn, |
24859b68 | 795 | mv88w8618_pit_writefn, s); |
b47b50fa | 796 | sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype); |
81a322d4 | 797 | return 0; |
24859b68 AZ |
798 | } |
799 | ||
800 | /* Flash config register offsets */ | |
801 | #define MP_FLASHCFG_CFGR0 0x04 | |
802 | ||
803 | typedef struct mv88w8618_flashcfg_state { | |
b47b50fa | 804 | SysBusDevice busdev; |
24859b68 AZ |
805 | uint32_t cfgr0; |
806 | } mv88w8618_flashcfg_state; | |
807 | ||
808 | static uint32_t mv88w8618_flashcfg_read(void *opaque, | |
c227f099 | 809 | target_phys_addr_t offset) |
24859b68 AZ |
810 | { |
811 | mv88w8618_flashcfg_state *s = opaque; | |
812 | ||
24859b68 AZ |
813 | switch (offset) { |
814 | case MP_FLASHCFG_CFGR0: | |
815 | return s->cfgr0; | |
816 | ||
817 | default: | |
818 | return 0; | |
819 | } | |
820 | } | |
821 | ||
c227f099 | 822 | static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, |
24859b68 AZ |
823 | uint32_t value) |
824 | { | |
825 | mv88w8618_flashcfg_state *s = opaque; | |
826 | ||
24859b68 AZ |
827 | switch (offset) { |
828 | case MP_FLASHCFG_CFGR0: | |
829 | s->cfgr0 = value; | |
830 | break; | |
831 | } | |
832 | } | |
833 | ||
d60efc6b | 834 | static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = { |
24859b68 AZ |
835 | mv88w8618_flashcfg_read, |
836 | mv88w8618_flashcfg_read, | |
837 | mv88w8618_flashcfg_read | |
838 | }; | |
839 | ||
d60efc6b | 840 | static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = { |
24859b68 AZ |
841 | mv88w8618_flashcfg_write, |
842 | mv88w8618_flashcfg_write, | |
843 | mv88w8618_flashcfg_write | |
844 | }; | |
845 | ||
81a322d4 | 846 | static int mv88w8618_flashcfg_init(SysBusDevice *dev) |
24859b68 AZ |
847 | { |
848 | int iomemtype; | |
b47b50fa | 849 | mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev); |
24859b68 | 850 | |
24859b68 | 851 | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
1eed09cb | 852 | iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn, |
49fedd0d | 853 | mv88w8618_flashcfg_writefn, s); |
b47b50fa | 854 | sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype); |
81a322d4 | 855 | return 0; |
24859b68 AZ |
856 | } |
857 | ||
718ec0be | 858 | /* Misc register offsets */ |
859 | #define MP_MISC_BOARD_REVISION 0x18 | |
860 | ||
861 | #define MP_BOARD_REVISION 0x31 | |
862 | ||
c227f099 | 863 | static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) |
718ec0be | 864 | { |
865 | switch (offset) { | |
866 | case MP_MISC_BOARD_REVISION: | |
867 | return MP_BOARD_REVISION; | |
868 | ||
869 | default: | |
870 | return 0; | |
871 | } | |
872 | } | |
873 | ||
c227f099 | 874 | static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, |
718ec0be | 875 | uint32_t value) |
876 | { | |
877 | } | |
878 | ||
d60efc6b | 879 | static CPUReadMemoryFunc * const musicpal_misc_readfn[] = { |
718ec0be | 880 | musicpal_misc_read, |
881 | musicpal_misc_read, | |
882 | musicpal_misc_read, | |
883 | }; | |
884 | ||
d60efc6b | 885 | static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = { |
718ec0be | 886 | musicpal_misc_write, |
887 | musicpal_misc_write, | |
888 | musicpal_misc_write, | |
889 | }; | |
890 | ||
891 | static void musicpal_misc_init(void) | |
892 | { | |
893 | int iomemtype; | |
894 | ||
1eed09cb | 895 | iomemtype = cpu_register_io_memory(musicpal_misc_readfn, |
718ec0be | 896 | musicpal_misc_writefn, NULL); |
897 | cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); | |
898 | } | |
899 | ||
900 | /* WLAN register offsets */ | |
901 | #define MP_WLAN_MAGIC1 0x11c | |
902 | #define MP_WLAN_MAGIC2 0x124 | |
903 | ||
c227f099 | 904 | static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) |
718ec0be | 905 | { |
906 | switch (offset) { | |
907 | /* Workaround to allow loading the binary-only wlandrv.ko crap | |
908 | * from the original Freecom firmware. */ | |
909 | case MP_WLAN_MAGIC1: | |
910 | return ~3; | |
911 | case MP_WLAN_MAGIC2: | |
912 | return -1; | |
913 | ||
914 | default: | |
915 | return 0; | |
916 | } | |
917 | } | |
918 | ||
c227f099 | 919 | static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, |
718ec0be | 920 | uint32_t value) |
921 | { | |
922 | } | |
923 | ||
d60efc6b | 924 | static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = { |
718ec0be | 925 | mv88w8618_wlan_read, |
926 | mv88w8618_wlan_read, | |
927 | mv88w8618_wlan_read, | |
928 | }; | |
929 | ||
d60efc6b | 930 | static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = { |
718ec0be | 931 | mv88w8618_wlan_write, |
932 | mv88w8618_wlan_write, | |
933 | mv88w8618_wlan_write, | |
934 | }; | |
935 | ||
81a322d4 | 936 | static int mv88w8618_wlan_init(SysBusDevice *dev) |
718ec0be | 937 | { |
938 | int iomemtype; | |
24859b68 | 939 | |
1eed09cb | 940 | iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn, |
718ec0be | 941 | mv88w8618_wlan_writefn, NULL); |
b47b50fa | 942 | sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype); |
81a322d4 | 943 | return 0; |
718ec0be | 944 | } |
24859b68 | 945 | |
718ec0be | 946 | /* GPIO register offsets */ |
947 | #define MP_GPIO_OE_LO 0x008 | |
948 | #define MP_GPIO_OUT_LO 0x00c | |
949 | #define MP_GPIO_IN_LO 0x010 | |
708afdf3 JK |
950 | #define MP_GPIO_IER_LO 0x014 |
951 | #define MP_GPIO_IMR_LO 0x018 | |
718ec0be | 952 | #define MP_GPIO_ISR_LO 0x020 |
953 | #define MP_GPIO_OE_HI 0x508 | |
954 | #define MP_GPIO_OUT_HI 0x50c | |
955 | #define MP_GPIO_IN_HI 0x510 | |
708afdf3 JK |
956 | #define MP_GPIO_IER_HI 0x514 |
957 | #define MP_GPIO_IMR_HI 0x518 | |
718ec0be | 958 | #define MP_GPIO_ISR_HI 0x520 |
24859b68 AZ |
959 | |
960 | /* GPIO bits & masks */ | |
24859b68 | 961 | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
24859b68 | 962 | #define MP_GPIO_I2C_DATA_BIT 29 |
24859b68 AZ |
963 | #define MP_GPIO_I2C_CLOCK_BIT 30 |
964 | ||
965 | /* LCD brightness bits in GPIO_OE_HI */ | |
966 | #define MP_OE_LCD_BRIGHTNESS 0x0007 | |
967 | ||
343ec8e4 BC |
968 | typedef struct musicpal_gpio_state { |
969 | SysBusDevice busdev; | |
970 | uint32_t lcd_brightness; | |
971 | uint32_t out_state; | |
972 | uint32_t in_state; | |
708afdf3 JK |
973 | uint32_t ier; |
974 | uint32_t imr; | |
343ec8e4 | 975 | uint32_t isr; |
343ec8e4 | 976 | qemu_irq irq; |
708afdf3 | 977 | qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ |
343ec8e4 BC |
978 | } musicpal_gpio_state; |
979 | ||
980 | static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { | |
981 | int i; | |
982 | uint32_t brightness; | |
983 | ||
984 | /* compute brightness ratio */ | |
985 | switch (s->lcd_brightness) { | |
986 | case 0x00000007: | |
987 | brightness = 0; | |
988 | break; | |
989 | ||
990 | case 0x00020000: | |
991 | brightness = 1; | |
992 | break; | |
993 | ||
994 | case 0x00020001: | |
995 | brightness = 2; | |
996 | break; | |
997 | ||
998 | case 0x00040000: | |
999 | brightness = 3; | |
1000 | break; | |
1001 | ||
1002 | case 0x00010006: | |
1003 | brightness = 4; | |
1004 | break; | |
1005 | ||
1006 | case 0x00020005: | |
1007 | brightness = 5; | |
1008 | break; | |
1009 | ||
1010 | case 0x00040003: | |
1011 | brightness = 6; | |
1012 | break; | |
1013 | ||
1014 | case 0x00030004: | |
1015 | default: | |
1016 | brightness = 7; | |
1017 | } | |
1018 | ||
1019 | /* set lcd brightness GPIOs */ | |
49fedd0d | 1020 | for (i = 0; i <= 2; i++) { |
343ec8e4 | 1021 | qemu_set_irq(s->out[i], (brightness >> i) & 1); |
49fedd0d | 1022 | } |
343ec8e4 BC |
1023 | } |
1024 | ||
708afdf3 | 1025 | static void musicpal_gpio_pin_event(void *opaque, int pin, int level) |
343ec8e4 | 1026 | { |
243cd13c | 1027 | musicpal_gpio_state *s = opaque; |
708afdf3 JK |
1028 | uint32_t mask = 1 << pin; |
1029 | uint32_t delta = level << pin; | |
1030 | uint32_t old = s->in_state & mask; | |
343ec8e4 | 1031 | |
708afdf3 JK |
1032 | s->in_state &= ~mask; |
1033 | s->in_state |= delta; | |
343ec8e4 | 1034 | |
708afdf3 JK |
1035 | if ((old ^ delta) && |
1036 | ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { | |
1037 | s->isr = mask; | |
1038 | qemu_irq_raise(s->irq); | |
343ec8e4 | 1039 | } |
343ec8e4 BC |
1040 | } |
1041 | ||
c227f099 | 1042 | static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) |
24859b68 | 1043 | { |
243cd13c | 1044 | musicpal_gpio_state *s = opaque; |
343ec8e4 | 1045 | |
24859b68 | 1046 | switch (offset) { |
24859b68 | 1047 | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
343ec8e4 | 1048 | return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; |
24859b68 AZ |
1049 | |
1050 | case MP_GPIO_OUT_LO: | |
343ec8e4 | 1051 | return s->out_state & 0xFFFF; |
24859b68 | 1052 | case MP_GPIO_OUT_HI: |
343ec8e4 | 1053 | return s->out_state >> 16; |
24859b68 AZ |
1054 | |
1055 | case MP_GPIO_IN_LO: | |
343ec8e4 | 1056 | return s->in_state & 0xFFFF; |
24859b68 | 1057 | case MP_GPIO_IN_HI: |
343ec8e4 | 1058 | return s->in_state >> 16; |
24859b68 | 1059 | |
708afdf3 JK |
1060 | case MP_GPIO_IER_LO: |
1061 | return s->ier & 0xFFFF; | |
1062 | case MP_GPIO_IER_HI: | |
1063 | return s->ier >> 16; | |
1064 | ||
1065 | case MP_GPIO_IMR_LO: | |
1066 | return s->imr & 0xFFFF; | |
1067 | case MP_GPIO_IMR_HI: | |
1068 | return s->imr >> 16; | |
1069 | ||
24859b68 | 1070 | case MP_GPIO_ISR_LO: |
343ec8e4 | 1071 | return s->isr & 0xFFFF; |
24859b68 | 1072 | case MP_GPIO_ISR_HI: |
343ec8e4 | 1073 | return s->isr >> 16; |
24859b68 | 1074 | |
24859b68 AZ |
1075 | default: |
1076 | return 0; | |
1077 | } | |
1078 | } | |
1079 | ||
c227f099 | 1080 | static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, |
718ec0be | 1081 | uint32_t value) |
24859b68 | 1082 | { |
243cd13c | 1083 | musicpal_gpio_state *s = opaque; |
24859b68 AZ |
1084 | switch (offset) { |
1085 | case MP_GPIO_OE_HI: /* used for LCD brightness control */ | |
343ec8e4 | 1086 | s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
24859b68 | 1087 | (value & MP_OE_LCD_BRIGHTNESS); |
343ec8e4 | 1088 | musicpal_gpio_brightness_update(s); |
24859b68 AZ |
1089 | break; |
1090 | ||
1091 | case MP_GPIO_OUT_LO: | |
343ec8e4 | 1092 | s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
24859b68 AZ |
1093 | break; |
1094 | case MP_GPIO_OUT_HI: | |
343ec8e4 BC |
1095 | s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1096 | s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | | |
1097 | (s->out_state & MP_GPIO_LCD_BRIGHTNESS); | |
1098 | musicpal_gpio_brightness_update(s); | |
d074769c AZ |
1099 | qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); |
1100 | qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); | |
24859b68 AZ |
1101 | break; |
1102 | ||
708afdf3 JK |
1103 | case MP_GPIO_IER_LO: |
1104 | s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); | |
1105 | break; | |
1106 | case MP_GPIO_IER_HI: | |
1107 | s->ier = (s->ier & 0xFFFF) | (value << 16); | |
1108 | break; | |
1109 | ||
1110 | case MP_GPIO_IMR_LO: | |
1111 | s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); | |
1112 | break; | |
1113 | case MP_GPIO_IMR_HI: | |
1114 | s->imr = (s->imr & 0xFFFF) | (value << 16); | |
1115 | break; | |
24859b68 AZ |
1116 | } |
1117 | } | |
1118 | ||
d60efc6b | 1119 | static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = { |
718ec0be | 1120 | musicpal_gpio_read, |
1121 | musicpal_gpio_read, | |
1122 | musicpal_gpio_read, | |
1123 | }; | |
1124 | ||
d60efc6b | 1125 | static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = { |
718ec0be | 1126 | musicpal_gpio_write, |
1127 | musicpal_gpio_write, | |
1128 | musicpal_gpio_write, | |
1129 | }; | |
1130 | ||
343ec8e4 | 1131 | static void musicpal_gpio_reset(musicpal_gpio_state *s) |
718ec0be | 1132 | { |
343ec8e4 | 1133 | s->in_state = 0xffffffff; |
708afdf3 JK |
1134 | s->ier = 0; |
1135 | s->imr = 0; | |
343ec8e4 BC |
1136 | s->isr = 0; |
1137 | } | |
1138 | ||
81a322d4 | 1139 | static int musicpal_gpio_init(SysBusDevice *dev) |
343ec8e4 BC |
1140 | { |
1141 | musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev); | |
718ec0be | 1142 | int iomemtype; |
1143 | ||
343ec8e4 BC |
1144 | sysbus_init_irq(dev, &s->irq); |
1145 | ||
1eed09cb | 1146 | iomemtype = cpu_register_io_memory(musicpal_gpio_readfn, |
343ec8e4 BC |
1147 | musicpal_gpio_writefn, s); |
1148 | sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype); | |
1149 | ||
1150 | musicpal_gpio_reset(s); | |
1151 | ||
708afdf3 JK |
1152 | qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1153 | ||
1154 | qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32); | |
81a322d4 GH |
1155 | |
1156 | return 0; | |
718ec0be | 1157 | } |
1158 | ||
24859b68 | 1159 | /* Keyboard codes & masks */ |
7c6ce4ba | 1160 | #define KEY_RELEASED 0x80 |
24859b68 AZ |
1161 | #define KEY_CODE 0x7f |
1162 | ||
1163 | #define KEYCODE_TAB 0x0f | |
1164 | #define KEYCODE_ENTER 0x1c | |
1165 | #define KEYCODE_F 0x21 | |
1166 | #define KEYCODE_M 0x32 | |
1167 | ||
1168 | #define KEYCODE_EXTENDED 0xe0 | |
1169 | #define KEYCODE_UP 0x48 | |
1170 | #define KEYCODE_DOWN 0x50 | |
1171 | #define KEYCODE_LEFT 0x4b | |
1172 | #define KEYCODE_RIGHT 0x4d | |
1173 | ||
708afdf3 | 1174 | #define MP_KEY_WHEEL_VOL (1 << 0) |
343ec8e4 BC |
1175 | #define MP_KEY_WHEEL_VOL_INV (1 << 1) |
1176 | #define MP_KEY_WHEEL_NAV (1 << 2) | |
1177 | #define MP_KEY_WHEEL_NAV_INV (1 << 3) | |
1178 | #define MP_KEY_BTN_FAVORITS (1 << 4) | |
1179 | #define MP_KEY_BTN_MENU (1 << 5) | |
1180 | #define MP_KEY_BTN_VOLUME (1 << 6) | |
1181 | #define MP_KEY_BTN_NAVIGATION (1 << 7) | |
1182 | ||
1183 | typedef struct musicpal_key_state { | |
1184 | SysBusDevice busdev; | |
1185 | uint32_t kbd_extended; | |
708afdf3 JK |
1186 | uint32_t pressed_keys; |
1187 | qemu_irq out[8]; | |
343ec8e4 BC |
1188 | } musicpal_key_state; |
1189 | ||
24859b68 AZ |
1190 | static void musicpal_key_event(void *opaque, int keycode) |
1191 | { | |
243cd13c | 1192 | musicpal_key_state *s = opaque; |
24859b68 | 1193 | uint32_t event = 0; |
343ec8e4 | 1194 | int i; |
24859b68 AZ |
1195 | |
1196 | if (keycode == KEYCODE_EXTENDED) { | |
343ec8e4 | 1197 | s->kbd_extended = 1; |
24859b68 AZ |
1198 | return; |
1199 | } | |
1200 | ||
49fedd0d | 1201 | if (s->kbd_extended) { |
24859b68 AZ |
1202 | switch (keycode & KEY_CODE) { |
1203 | case KEYCODE_UP: | |
343ec8e4 | 1204 | event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
24859b68 AZ |
1205 | break; |
1206 | ||
1207 | case KEYCODE_DOWN: | |
343ec8e4 | 1208 | event = MP_KEY_WHEEL_NAV; |
24859b68 AZ |
1209 | break; |
1210 | ||
1211 | case KEYCODE_LEFT: | |
343ec8e4 | 1212 | event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
24859b68 AZ |
1213 | break; |
1214 | ||
1215 | case KEYCODE_RIGHT: | |
343ec8e4 | 1216 | event = MP_KEY_WHEEL_VOL; |
24859b68 AZ |
1217 | break; |
1218 | } | |
49fedd0d | 1219 | } else { |
24859b68 AZ |
1220 | switch (keycode & KEY_CODE) { |
1221 | case KEYCODE_F: | |
343ec8e4 | 1222 | event = MP_KEY_BTN_FAVORITS; |
24859b68 AZ |
1223 | break; |
1224 | ||
1225 | case KEYCODE_TAB: | |
343ec8e4 | 1226 | event = MP_KEY_BTN_VOLUME; |
24859b68 AZ |
1227 | break; |
1228 | ||
1229 | case KEYCODE_ENTER: | |
343ec8e4 | 1230 | event = MP_KEY_BTN_NAVIGATION; |
24859b68 AZ |
1231 | break; |
1232 | ||
1233 | case KEYCODE_M: | |
343ec8e4 | 1234 | event = MP_KEY_BTN_MENU; |
24859b68 AZ |
1235 | break; |
1236 | } | |
7c6ce4ba | 1237 | /* Do not repeat already pressed buttons */ |
708afdf3 | 1238 | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { |
7c6ce4ba | 1239 | event = 0; |
708afdf3 | 1240 | } |
7c6ce4ba | 1241 | } |
24859b68 | 1242 | |
7c6ce4ba | 1243 | if (event) { |
708afdf3 JK |
1244 | /* Raise GPIO pin first if repeating a key */ |
1245 | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { | |
1246 | for (i = 0; i <= 7; i++) { | |
1247 | if (event & (1 << i)) { | |
1248 | qemu_set_irq(s->out[i], 1); | |
1249 | } | |
1250 | } | |
1251 | } | |
1252 | for (i = 0; i <= 7; i++) { | |
1253 | if (event & (1 << i)) { | |
1254 | qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); | |
1255 | } | |
1256 | } | |
7c6ce4ba | 1257 | if (keycode & KEY_RELEASED) { |
708afdf3 | 1258 | s->pressed_keys &= ~event; |
7c6ce4ba | 1259 | } else { |
708afdf3 | 1260 | s->pressed_keys |= event; |
7c6ce4ba | 1261 | } |
24859b68 AZ |
1262 | } |
1263 | ||
343ec8e4 BC |
1264 | s->kbd_extended = 0; |
1265 | } | |
1266 | ||
81a322d4 | 1267 | static int musicpal_key_init(SysBusDevice *dev) |
343ec8e4 BC |
1268 | { |
1269 | musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev); | |
1270 | ||
1271 | sysbus_init_mmio(dev, 0x0, 0); | |
1272 | ||
1273 | s->kbd_extended = 0; | |
708afdf3 | 1274 | s->pressed_keys = 0; |
343ec8e4 | 1275 | |
708afdf3 | 1276 | qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
343ec8e4 BC |
1277 | |
1278 | qemu_add_kbd_event_handler(musicpal_key_event, s); | |
81a322d4 GH |
1279 | |
1280 | return 0; | |
24859b68 AZ |
1281 | } |
1282 | ||
24859b68 AZ |
1283 | static struct arm_boot_info musicpal_binfo = { |
1284 | .loader_start = 0x0, | |
1285 | .board_id = 0x20e, | |
1286 | }; | |
1287 | ||
c227f099 | 1288 | static void musicpal_init(ram_addr_t ram_size, |
3023f332 | 1289 | const char *boot_device, |
24859b68 AZ |
1290 | const char *kernel_filename, const char *kernel_cmdline, |
1291 | const char *initrd_filename, const char *cpu_model) | |
1292 | { | |
1293 | CPUState *env; | |
b47b50fa PB |
1294 | qemu_irq *cpu_pic; |
1295 | qemu_irq pic[32]; | |
1296 | DeviceState *dev; | |
d074769c | 1297 | DeviceState *i2c_dev; |
343ec8e4 BC |
1298 | DeviceState *lcd_dev; |
1299 | DeviceState *key_dev; | |
d074769c AZ |
1300 | #ifdef HAS_AUDIO |
1301 | DeviceState *wm8750_dev; | |
1302 | SysBusDevice *s; | |
1303 | #endif | |
1304 | i2c_bus *i2c; | |
b47b50fa | 1305 | int i; |
24859b68 | 1306 | unsigned long flash_size; |
751c6a17 | 1307 | DriveInfo *dinfo; |
c227f099 | 1308 | ram_addr_t sram_off; |
24859b68 | 1309 | |
49fedd0d | 1310 | if (!cpu_model) { |
24859b68 | 1311 | cpu_model = "arm926"; |
49fedd0d | 1312 | } |
24859b68 AZ |
1313 | env = cpu_init(cpu_model); |
1314 | if (!env) { | |
1315 | fprintf(stderr, "Unable to find CPU definition\n"); | |
1316 | exit(1); | |
1317 | } | |
b47b50fa | 1318 | cpu_pic = arm_pic_init_cpu(env); |
24859b68 AZ |
1319 | |
1320 | /* For now we use a fixed - the original - RAM size */ | |
1321 | cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE, | |
1322 | qemu_ram_alloc(MP_RAM_DEFAULT_SIZE)); | |
1323 | ||
1324 | sram_off = qemu_ram_alloc(MP_SRAM_SIZE); | |
1325 | cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); | |
1326 | ||
b47b50fa PB |
1327 | dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE, |
1328 | cpu_pic[ARM_PIC_CPU_IRQ]); | |
1329 | for (i = 0; i < 32; i++) { | |
067a3ddc | 1330 | pic[i] = qdev_get_gpio_in(dev, i); |
b47b50fa PB |
1331 | } |
1332 | sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ], | |
1333 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | |
1334 | pic[MP_TIMER4_IRQ], NULL); | |
24859b68 | 1335 | |
49fedd0d | 1336 | if (serial_hds[0]) { |
b6cd0ea1 | 1337 | serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
24859b68 | 1338 | serial_hds[0], 1); |
49fedd0d JK |
1339 | } |
1340 | if (serial_hds[1]) { | |
b6cd0ea1 | 1341 | serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
24859b68 | 1342 | serial_hds[1], 1); |
49fedd0d | 1343 | } |
24859b68 AZ |
1344 | |
1345 | /* Register flash */ | |
751c6a17 GH |
1346 | dinfo = drive_get(IF_PFLASH, 0, 0); |
1347 | if (dinfo) { | |
1348 | flash_size = bdrv_getlength(dinfo->bdrv); | |
24859b68 AZ |
1349 | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1350 | flash_size != 32*1024*1024) { | |
1351 | fprintf(stderr, "Invalid flash image size\n"); | |
1352 | exit(1); | |
1353 | } | |
1354 | ||
1355 | /* | |
1356 | * The original U-Boot accesses the flash at 0xFE000000 instead of | |
1357 | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the | |
1358 | * image is smaller than 32 MB. | |
1359 | */ | |
1360 | pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size), | |
751c6a17 | 1361 | dinfo->bdrv, 0x10000, |
24859b68 AZ |
1362 | (flash_size + 0xffff) >> 16, |
1363 | MP_FLASH_SIZE_MAX / flash_size, | |
1364 | 2, 0x00BF, 0x236D, 0x0000, 0x0000, | |
1365 | 0x5555, 0x2AAA); | |
1366 | } | |
b47b50fa | 1367 | sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL); |
24859b68 | 1368 | |
b47b50fa PB |
1369 | qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
1370 | dev = qdev_create(NULL, "mv88w8618_eth"); | |
ee6847d1 | 1371 | dev->nd = &nd_table[0]; |
b47b50fa PB |
1372 | qdev_init(dev); |
1373 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE); | |
1374 | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]); | |
24859b68 | 1375 | |
b47b50fa | 1376 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
718ec0be | 1377 | |
1378 | musicpal_misc_init(); | |
343ec8e4 BC |
1379 | |
1380 | dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]); | |
d074769c AZ |
1381 | i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL); |
1382 | i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c"); | |
1383 | ||
343ec8e4 BC |
1384 | lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL); |
1385 | key_dev = sysbus_create_simple("musicpal_key", 0, NULL); | |
1386 | ||
d074769c | 1387 | /* I2C read data */ |
708afdf3 JK |
1388 | qdev_connect_gpio_out(i2c_dev, 0, |
1389 | qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); | |
d074769c AZ |
1390 | /* I2C data */ |
1391 | qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); | |
1392 | /* I2C clock */ | |
1393 | qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); | |
1394 | ||
49fedd0d | 1395 | for (i = 0; i < 3; i++) { |
343ec8e4 | 1396 | qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); |
49fedd0d | 1397 | } |
708afdf3 JK |
1398 | for (i = 0; i < 4; i++) { |
1399 | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); | |
1400 | } | |
1401 | for (i = 4; i < 8; i++) { | |
1402 | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); | |
1403 | } | |
24859b68 | 1404 | |
d074769c AZ |
1405 | #ifdef HAS_AUDIO |
1406 | wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR); | |
1407 | dev = qdev_create(NULL, "mv88w8618_audio"); | |
1408 | s = sysbus_from_qdev(dev); | |
1409 | qdev_prop_set_ptr(dev, "wm8750", wm8750_dev); | |
1410 | qdev_init(dev); | |
1411 | sysbus_mmio_map(s, 0, MP_AUDIO_BASE); | |
1412 | sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); | |
1413 | #endif | |
1414 | ||
24859b68 AZ |
1415 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1416 | musicpal_binfo.kernel_filename = kernel_filename; | |
1417 | musicpal_binfo.kernel_cmdline = kernel_cmdline; | |
1418 | musicpal_binfo.initrd_filename = initrd_filename; | |
b0f6edb1 | 1419 | arm_load_kernel(env, &musicpal_binfo); |
24859b68 AZ |
1420 | } |
1421 | ||
f80f9ec9 | 1422 | static QEMUMachine musicpal_machine = { |
4b32e168 AL |
1423 | .name = "musicpal", |
1424 | .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)", | |
1425 | .init = musicpal_init, | |
24859b68 | 1426 | }; |
b47b50fa | 1427 | |
f80f9ec9 AL |
1428 | static void musicpal_machine_init(void) |
1429 | { | |
1430 | qemu_register_machine(&musicpal_machine); | |
1431 | } | |
1432 | ||
1433 | machine_init(musicpal_machine_init); | |
1434 | ||
b47b50fa PB |
1435 | static void musicpal_register_devices(void) |
1436 | { | |
1437 | sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state), | |
1438 | mv88w8618_pic_init); | |
1439 | sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state), | |
1440 | mv88w8618_pit_init); | |
1441 | sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state), | |
1442 | mv88w8618_flashcfg_init); | |
1443 | sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state), | |
1444 | mv88w8618_eth_init); | |
1445 | sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice), | |
1446 | mv88w8618_wlan_init); | |
1447 | sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state), | |
1448 | musicpal_lcd_init); | |
343ec8e4 BC |
1449 | sysbus_register_dev("musicpal_gpio", sizeof(musicpal_gpio_state), |
1450 | musicpal_gpio_init); | |
1451 | sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state), | |
1452 | musicpal_key_init); | |
b47b50fa PB |
1453 | } |
1454 | ||
1455 | device_init(musicpal_register_devices) |