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Remove arm's local not_i32 tcg op now that there's one in tcg.
[mirror_qemu.git] / hw / musicpal.c
CommitLineData
24859b68
AZ		 1/*
2 * Marvell MV88W8618 / Freecom MusicPal emulation.
3 *
4 * Copyright (c) 2008 Jan Kiszka
5 *
6 * This code is licenced under the GNU GPL v2.
7 */
8
9#include "hw.h"
10#include "arm-misc.h"
11#include "devices.h"
12#include "net.h"
13#include "sysemu.h"
14#include "boards.h"
15#include "pc.h"
16#include "qemu-timer.h"
17#include "block.h"
18#include "flash.h"
19#include "console.h"
20#include "audio/audio.h"
21#include "i2c.h"
22
23#define MP_ETH_BASE 0x80008000
24#define MP_ETH_SIZE 0x00001000
25
26#define MP_UART1_BASE 0x8000C840
27#define MP_UART2_BASE 0x8000C940
28
29#define MP_FLASHCFG_BASE 0x90006000
30#define MP_FLASHCFG_SIZE 0x00001000
31
32#define MP_AUDIO_BASE 0x90007000
33#define MP_AUDIO_SIZE 0x00001000
34
35#define MP_PIC_BASE 0x90008000
36#define MP_PIC_SIZE 0x00001000
37
38#define MP_PIT_BASE 0x90009000
39#define MP_PIT_SIZE 0x00001000
40
41#define MP_LCD_BASE 0x9000c000
42#define MP_LCD_SIZE 0x00001000
43
44#define MP_SRAM_BASE 0xC0000000
45#define MP_SRAM_SIZE 0x00020000
46
47#define MP_RAM_DEFAULT_SIZE 32*1024*1024
48#define MP_FLASH_SIZE_MAX 32*1024*1024
49
50#define MP_TIMER1_IRQ 4
51/* ... */
52#define MP_TIMER4_IRQ 7
53#define MP_EHCI_IRQ 8
54#define MP_ETH_IRQ 9
55#define MP_UART1_IRQ 11
56#define MP_UART2_IRQ 11
57#define MP_GPIO_IRQ 12
58#define MP_RTC_IRQ 28
59#define MP_AUDIO_IRQ 30
60
61static uint32_t gpio_in_state = 0xffffffff;
62static uint32_t gpio_out_state;
63static ram_addr_t sram_off;
64
65/* Address conversion helpers */
66static void *target2host_addr(uint32_t addr)
67{
68 if (addr < MP_SRAM_BASE) {
69 if (addr >= MP_RAM_DEFAULT_SIZE)
70 return NULL;
71 return (void *)(phys_ram_base + addr);
72 } else {
73 if (addr >= MP_SRAM_BASE + MP_SRAM_SIZE)
74 return NULL;
75 return (void *)(phys_ram_base + sram_off + addr - MP_SRAM_BASE);
76 }
77}
78
79static uint32_t host2target_addr(void *addr)
80{
81 if (addr < ((void *)phys_ram_base) + sram_off)
82 return (unsigned long)addr - (unsigned long)phys_ram_base;
83 else
84 return (unsigned long)addr - (unsigned long)phys_ram_base -
85 sram_off + MP_SRAM_BASE;
86}
87
88
89typedef enum i2c_state {
90 STOPPED = 0,
91 INITIALIZING,
92 SENDING_BIT7,
93 SENDING_BIT6,
94 SENDING_BIT5,
95 SENDING_BIT4,
96 SENDING_BIT3,
97 SENDING_BIT2,
98 SENDING_BIT1,
99 SENDING_BIT0,
100 WAITING_FOR_ACK,
101 RECEIVING_BIT7,
102 RECEIVING_BIT6,
103 RECEIVING_BIT5,
104 RECEIVING_BIT4,
105 RECEIVING_BIT3,
106 RECEIVING_BIT2,
107 RECEIVING_BIT1,
108 RECEIVING_BIT0,
109 SENDING_ACK
110} i2c_state;
111
112typedef struct i2c_interface {
113 i2c_bus *bus;
114 i2c_state state;
115 int last_data;
116 int last_clock;
117 uint8_t buffer;
118 int current_addr;
119} i2c_interface;
120
121static void i2c_enter_stop(i2c_interface *i2c)
122{
123 if (i2c->current_addr >= 0)
124 i2c_end_transfer(i2c->bus);
125 i2c->current_addr = -1;
126 i2c->state = STOPPED;
127}
128
129static void i2c_state_update(i2c_interface *i2c, int data, int clock)
130{
131 if (!i2c)
132 return;
133
134 switch (i2c->state) {
135 case STOPPED:
136 if (data == 0 && i2c->last_data == 1 && clock == 1)
137 i2c->state = INITIALIZING;
138 break;
139
140 case INITIALIZING:
141 if (clock == 0 && i2c->last_clock == 1 && data == 0)
142 i2c->state = SENDING_BIT7;
143 else
144 i2c_enter_stop(i2c);
145 break;
146
147 case SENDING_BIT7 ... SENDING_BIT0:
148 if (clock == 0 && i2c->last_clock == 1) {
149 i2c->buffer = (i2c->buffer << 1) | data;
150 i2c->state++; /* will end up in WAITING_FOR_ACK */
151 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
152 i2c_enter_stop(i2c);
153 break;
154
155 case WAITING_FOR_ACK:
156 if (clock == 0 && i2c->last_clock == 1) {
157 if (i2c->current_addr < 0) {
158 i2c->current_addr = i2c->buffer;
159 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
160 i2c->buffer & 1);
161 } else
162 i2c_send(i2c->bus, i2c->buffer);
163 if (i2c->current_addr & 1) {
164 i2c->state = RECEIVING_BIT7;
165 i2c->buffer = i2c_recv(i2c->bus);
166 } else
167 i2c->state = SENDING_BIT7;
168 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
169 i2c_enter_stop(i2c);
170 break;
171
172 case RECEIVING_BIT7 ... RECEIVING_BIT0:
173 if (clock == 0 && i2c->last_clock == 1) {
174 i2c->state++; /* will end up in SENDING_ACK */
175 i2c->buffer <<= 1;
176 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
177 i2c_enter_stop(i2c);
178 break;
179
180 case SENDING_ACK:
181 if (clock == 0 && i2c->last_clock == 1) {
182 i2c->state = RECEIVING_BIT7;
183 if (data == 0)
184 i2c->buffer = i2c_recv(i2c->bus);
185 else
186 i2c_nack(i2c->bus);
187 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
188 i2c_enter_stop(i2c);
189 break;
190 }
191
192 i2c->last_data = data;
193 i2c->last_clock = clock;
194}
195
196static int i2c_get_data(i2c_interface *i2c)
197{
198 if (!i2c)
199 return 0;
200
201 switch (i2c->state) {
202 case RECEIVING_BIT7 ... RECEIVING_BIT0:
203 return (i2c->buffer >> 7);
204
205 case WAITING_FOR_ACK:
206 default:
207 return 0;
208 }
209}
210
211static i2c_interface *mixer_i2c;
212
213#ifdef HAS_AUDIO
214
215/* Audio register offsets */
216#define MP_AUDIO_PLAYBACK_MODE 0x00
217#define MP_AUDIO_CLOCK_DIV 0x18
218#define MP_AUDIO_IRQ_STATUS 0x20
219#define MP_AUDIO_IRQ_ENABLE 0x24
220#define MP_AUDIO_TX_START_LO 0x28
221#define MP_AUDIO_TX_THRESHOLD 0x2C
222#define MP_AUDIO_TX_STATUS 0x38
223#define MP_AUDIO_TX_START_HI 0x40
224
225/* Status register and IRQ enable bits */
226#define MP_AUDIO_TX_HALF (1 << 6)
227#define MP_AUDIO_TX_FULL (1 << 7)
228
229/* Playback mode bits */
230#define MP_AUDIO_16BIT_SAMPLE (1 << 0)
231#define MP_AUDIO_PLAYBACK_EN (1 << 7)
232#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
4001a81e 233#define MP_AUDIO_MONO (1 << 14)
24859b68
AZ		 234
235/* Wolfson 8750 I2C address */
236#define MP_WM_ADDR 0x34
237
238const char audio_name[] = "mv88w8618";
239
240typedef struct musicpal_audio_state {
241 uint32_t base;
242 qemu_irq irq;
243 uint32_t playback_mode;
244 uint32_t status;
245 uint32_t irq_enable;
246 unsigned long phys_buf;
a350e694 247 int8_t *target_buffer;
24859b68
AZ		 248 unsigned int threshold;
249 unsigned int play_pos;
250 unsigned int last_free;
251 uint32_t clock_div;
252 i2c_slave *wm;
253} musicpal_audio_state;
254
255static void audio_callback(void *opaque, int free_out, int free_in)
256{
257 musicpal_audio_state *s = opaque;
4f3cb3be 258 int16_t *codec_buffer;
a350e694 259 int8_t *mem_buffer;
24859b68
AZ		 260 int pos, block_size;
261
262 if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
263 return;
264
265 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
4001a81e
AZ		 266 free_out <<= 1;
267
268 if (!(s->playback_mode & MP_AUDIO_MONO))
24859b68
AZ		 269 free_out <<= 1;
270
271 block_size = s->threshold/2;
272 if (free_out - s->last_free < block_size)
273 return;
274
4001a81e
AZ		 275 mem_buffer = s->target_buffer + s->play_pos;
276 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
277 if (s->playback_mode & MP_AUDIO_MONO) {
278 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
279 for (pos = 0; pos < block_size; pos += 2) {
a350e694
AZ		 280 *codec_buffer++ = *(int16_t *)mem_buffer;
281 *codec_buffer++ = *(int16_t *)mem_buffer;
4f3cb3be 282 mem_buffer += 2;
4001a81e
AZ		 283 }
284 } else
285 memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
286 (uint32_t *)mem_buffer, block_size);
287 } else {
288 if (s->playback_mode & MP_AUDIO_MONO) {
289 codec_buffer = wm8750_dac_buffer(s->wm, block_size);
290 for (pos = 0; pos < block_size; pos++) {
a350e694
AZ		 291 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
292 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
4001a81e
AZ		 293 }
294 } else {
295 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
296 for (pos = 0; pos < block_size; pos += 2) {
a350e694
AZ		 297 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
298 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
4001a81e 299 }
24859b68 300 }
662caa6f
AZ		 301 }
302 wm8750_dac_commit(s->wm);
24859b68
AZ		 303
304 s->last_free = free_out - block_size;
305
306 if (s->play_pos == 0) {
307 s->status |= MP_AUDIO_TX_HALF;
308 s->play_pos = block_size;
309 } else {
310 s->status |= MP_AUDIO_TX_FULL;
311 s->play_pos = 0;
312 }
313
314 if (s->status & s->irq_enable)
315 qemu_irq_raise(s->irq);
316}
317
af83e09e
AZ		 318static void musicpal_audio_clock_update(musicpal_audio_state *s)
319{
320 int rate;
321
322 if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
323 rate = 24576000 / 64; /* 24.576MHz */
324 else
325 rate = 11289600 / 64; /* 11.2896MHz */
326
327 rate /= ((s->clock_div >> 8) & 0xff) + 1;
328
91834991 329 wm8750_set_bclk_in(s->wm, rate);
af83e09e
AZ		 330}
331
24859b68
AZ		 332static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
333{
334 musicpal_audio_state *s = opaque;
335
336 offset -= s->base;
337 switch (offset) {
338 case MP_AUDIO_PLAYBACK_MODE:
339 return s->playback_mode;
340
341 case MP_AUDIO_CLOCK_DIV:
342 return s->clock_div;
343
344 case MP_AUDIO_IRQ_STATUS:
345 return s->status;
346
347 case MP_AUDIO_IRQ_ENABLE:
348 return s->irq_enable;
349
350 case MP_AUDIO_TX_STATUS:
351 return s->play_pos >> 2;
352
353 default:
354 return 0;
355 }
356}
357
358static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
359 uint32_t value)
360{
361 musicpal_audio_state *s = opaque;
362
363 offset -= s->base;
364 switch (offset) {
365 case MP_AUDIO_PLAYBACK_MODE:
366 if (value & MP_AUDIO_PLAYBACK_EN &&
367 !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
368 s->status = 0;
369 s->last_free = 0;
370 s->play_pos = 0;
371 }
372 s->playback_mode = value;
af83e09e 373 musicpal_audio_clock_update(s);
24859b68
AZ		 374 break;
375
376 case MP_AUDIO_CLOCK_DIV:
377 s->clock_div = value;
378 s->last_free = 0;
379 s->play_pos = 0;
af83e09e 380 musicpal_audio_clock_update(s);
24859b68
AZ		 381 break;
382
383 case MP_AUDIO_IRQ_STATUS:
384 s->status &= ~value;
385 break;
386
387 case MP_AUDIO_IRQ_ENABLE:
388 s->irq_enable = value;
389 if (s->status & s->irq_enable)
390 qemu_irq_raise(s->irq);
391 break;
392
393 case MP_AUDIO_TX_START_LO:
394 s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
395 s->target_buffer = target2host_addr(s->phys_buf);
396 s->play_pos = 0;
397 s->last_free = 0;
398 break;
399
400 case MP_AUDIO_TX_THRESHOLD:
401 s->threshold = (value + 1) * 4;
402 break;
403
404 case MP_AUDIO_TX_START_HI:
405 s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
406 s->target_buffer = target2host_addr(s->phys_buf);
407 s->play_pos = 0;
408 s->last_free = 0;
409 break;
410 }
411}
412
413static void musicpal_audio_reset(void *opaque)
414{
415 musicpal_audio_state *s = opaque;
416
417 s->playback_mode = 0;
418 s->status = 0;
419 s->irq_enable = 0;
420}
421
422static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
423 musicpal_audio_read,
424 musicpal_audio_read,
425 musicpal_audio_read
426};
427
428static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
429 musicpal_audio_write,
430 musicpal_audio_write,
431 musicpal_audio_write
432};
433
434static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
435{
436 AudioState *audio;
437 musicpal_audio_state *s;
438 i2c_interface *i2c;
439 int iomemtype;
440
441 audio = AUD_init();
442 if (!audio) {
443 AUD_log(audio_name, "No audio state\n");
444 return NULL;
445 }
446
447 s = qemu_mallocz(sizeof(musicpal_audio_state));
448 if (!s)
449 return NULL;
450 s->base = base;
451 s->irq = irq;
452
453 i2c = qemu_mallocz(sizeof(i2c_interface));
454 if (!i2c)
455 return NULL;
456 i2c->bus = i2c_init_bus();
457 i2c->current_addr = -1;
458
459 s->wm = wm8750_init(i2c->bus, audio);
460 if (!s->wm)
461 return NULL;
462 i2c_set_slave_address(s->wm, MP_WM_ADDR);
463 wm8750_data_req_set(s->wm, audio_callback, s);
464
465 iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
466 musicpal_audio_writefn, s);
467 cpu_register_physical_memory(base, MP_AUDIO_SIZE, iomemtype);
468
469 qemu_register_reset(musicpal_audio_reset, s);
470
471 return i2c;
472}
473#else /* !HAS_AUDIO */
474static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
475{
476 return NULL;
477}
478#endif /* !HAS_AUDIO */
479
480/* Ethernet register offsets */
481#define MP_ETH_SMIR 0x010
482#define MP_ETH_PCXR 0x408
483#define MP_ETH_SDCMR 0x448
484#define MP_ETH_ICR 0x450
485#define MP_ETH_IMR 0x458
486#define MP_ETH_FRDP0 0x480
487#define MP_ETH_FRDP1 0x484
488#define MP_ETH_FRDP2 0x488
489#define MP_ETH_FRDP3 0x48C
490#define MP_ETH_CRDP0 0x4A0
491#define MP_ETH_CRDP1 0x4A4
492#define MP_ETH_CRDP2 0x4A8
493#define MP_ETH_CRDP3 0x4AC
494#define MP_ETH_CTDP0 0x4E0
495#define MP_ETH_CTDP1 0x4E4
496#define MP_ETH_CTDP2 0x4E8
497#define MP_ETH_CTDP3 0x4EC
498
499/* MII PHY access */
500#define MP_ETH_SMIR_DATA 0x0000FFFF
501#define MP_ETH_SMIR_ADDR 0x03FF0000
502#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
503#define MP_ETH_SMIR_RDVALID (1 << 27)
504
505/* PHY registers */
506#define MP_ETH_PHY1_BMSR 0x00210000
507#define MP_ETH_PHY1_PHYSID1 0x00410000
508#define MP_ETH_PHY1_PHYSID2 0x00610000
509
510#define MP_PHY_BMSR_LINK 0x0004
511#define MP_PHY_BMSR_AUTONEG 0x0008
512
513#define MP_PHY_88E3015 0x01410E20
514
515/* TX descriptor status */
516#define MP_ETH_TX_OWN (1 << 31)
517
518/* RX descriptor status */
519#define MP_ETH_RX_OWN (1 << 31)
520
521/* Interrupt cause/mask bits */
522#define MP_ETH_IRQ_RX_BIT 0
523#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
524#define MP_ETH_IRQ_TXHI_BIT 2
525#define MP_ETH_IRQ_TXLO_BIT 3
526
527/* Port config bits */
528#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
529
530/* SDMA command bits */
531#define MP_ETH_CMD_TXHI (1 << 23)
532#define MP_ETH_CMD_TXLO (1 << 22)
533
534typedef struct mv88w8618_tx_desc {
535 uint32_t cmdstat;
536 uint16_t res;
537 uint16_t bytes;
538 uint32_t buffer;
539 uint32_t next;
540} mv88w8618_tx_desc;
541
542typedef struct mv88w8618_rx_desc {
543 uint32_t cmdstat;
544 uint16_t bytes;
545 uint16_t buffer_size;
546 uint32_t buffer;
547 uint32_t next;
548} mv88w8618_rx_desc;
549
550typedef struct mv88w8618_eth_state {
551 uint32_t base;
552 qemu_irq irq;
553 uint32_t smir;
554 uint32_t icr;
555 uint32_t imr;
556 int vlan_header;
557 mv88w8618_tx_desc *tx_queue[2];
558 mv88w8618_rx_desc *rx_queue[4];
559 mv88w8618_rx_desc *frx_queue[4];
560 mv88w8618_rx_desc *cur_rx[4];
561 VLANClientState *vc;
562} mv88w8618_eth_state;
563
564static int eth_can_receive(void *opaque)
565{
566 return 1;
567}
568
569static void eth_receive(void *opaque, const uint8_t *buf, int size)
570{
571 mv88w8618_eth_state *s = opaque;
572 mv88w8618_rx_desc *desc;
573 int i;
574
575 for (i = 0; i < 4; i++) {
576 desc = s->cur_rx[i];
577 if (!desc)
578 continue;
579 do {
580 if (le32_to_cpu(desc->cmdstat) & MP_ETH_RX_OWN &&
581 le16_to_cpu(desc->buffer_size) >= size) {
582 memcpy(target2host_addr(le32_to_cpu(desc->buffer) +
583 s->vlan_header),
584 buf, size);
585 desc->bytes = cpu_to_le16(size + s->vlan_header);
586 desc->cmdstat &= cpu_to_le32(~MP_ETH_RX_OWN);
587 s->cur_rx[i] = target2host_addr(le32_to_cpu(desc->next));
588
589 s->icr |= MP_ETH_IRQ_RX;
590 if (s->icr & s->imr)
591 qemu_irq_raise(s->irq);
592 return;
593 }
594 desc = target2host_addr(le32_to_cpu(desc->next));
595 } while (desc != s->rx_queue[i]);
596 }
597}
598
599static void eth_send(mv88w8618_eth_state *s, int queue_index)
600{
601 mv88w8618_tx_desc *desc = s->tx_queue[queue_index];
602
603 do {
604 if (le32_to_cpu(desc->cmdstat) & MP_ETH_TX_OWN) {
605 qemu_send_packet(s->vc,
606 target2host_addr(le32_to_cpu(desc->buffer)),
607 le16_to_cpu(desc->bytes));
608 desc->cmdstat &= cpu_to_le32(~MP_ETH_TX_OWN);
609 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
610 }
611 desc = target2host_addr(le32_to_cpu(desc->next));
612 } while (desc != s->tx_queue[queue_index]);
613}
614
615static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
616{
617 mv88w8618_eth_state *s = opaque;
618
619 offset -= s->base;
620 switch (offset) {
621 case MP_ETH_SMIR:
622 if (s->smir & MP_ETH_SMIR_OPCODE) {
623 switch (s->smir & MP_ETH_SMIR_ADDR) {
624 case MP_ETH_PHY1_BMSR:
625 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
626 MP_ETH_SMIR_RDVALID;
627 case MP_ETH_PHY1_PHYSID1:
628 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
629 case MP_ETH_PHY1_PHYSID2:
630 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
631 default:
632 return MP_ETH_SMIR_RDVALID;
633 }
634 }
635 return 0;
636
637 case MP_ETH_ICR:
638 return s->icr;
639
640 case MP_ETH_IMR:
641 return s->imr;
642
643 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
644 return host2target_addr(s->frx_queue[(offset - MP_ETH_FRDP0)/4]);
645
646 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
647 return host2target_addr(s->rx_queue[(offset - MP_ETH_CRDP0)/4]);
648
649 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
650 return host2target_addr(s->tx_queue[(offset - MP_ETH_CTDP0)/4]);
651
652 default:
653 return 0;
654 }
655}
656
657static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
658 uint32_t value)
659{
660 mv88w8618_eth_state *s = opaque;
661
662 offset -= s->base;
663 switch (offset) {
664 case MP_ETH_SMIR:
665 s->smir = value;
666 break;
667
668 case MP_ETH_PCXR:
669 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
670 break;
671
672 case MP_ETH_SDCMR:
673 if (value & MP_ETH_CMD_TXHI)
674 eth_send(s, 1);
675 if (value & MP_ETH_CMD_TXLO)
676 eth_send(s, 0);
677 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
678 qemu_irq_raise(s->irq);
679 break;
680
681 case MP_ETH_ICR:
682 s->icr &= value;
683 break;
684
685 case MP_ETH_IMR:
686 s->imr = value;
687 if (s->icr & s->imr)
688 qemu_irq_raise(s->irq);
689 break;
690
691 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
692 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = target2host_addr(value);
693 break;
694
695 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
696 s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
697 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = target2host_addr(value);
698 break;
699
700 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
701 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = target2host_addr(value);
702 break;
703 }
704}
705
706static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
707 mv88w8618_eth_read,
708 mv88w8618_eth_read,
709 mv88w8618_eth_read
710};
711
712static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
713 mv88w8618_eth_write,
714 mv88w8618_eth_write,
715 mv88w8618_eth_write
716};
717
718static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
719{
720 mv88w8618_eth_state *s;
721 int iomemtype;
722
723 s = qemu_mallocz(sizeof(mv88w8618_eth_state));
724 if (!s)
725 return;
726 s->base = base;
727 s->irq = irq;
728 s->vc = qemu_new_vlan_client(nd->vlan, eth_receive, eth_can_receive, s);
729 iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
730 mv88w8618_eth_writefn, s);
731 cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype);
732}
733
734/* LCD register offsets */
735#define MP_LCD_IRQCTRL 0x180
736#define MP_LCD_IRQSTAT 0x184
737#define MP_LCD_SPICTRL 0x1ac
738#define MP_LCD_INST 0x1bc
739#define MP_LCD_DATA 0x1c0
740
741/* Mode magics */
742#define MP_LCD_SPI_DATA 0x00100011
743#define MP_LCD_SPI_CMD 0x00104011
744#define MP_LCD_SPI_INVALID 0x00000000
745
746/* Commmands */
747#define MP_LCD_INST_SETPAGE0 0xB0
748/* ... */
749#define MP_LCD_INST_SETPAGE7 0xB7
750
751#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
752
753typedef struct musicpal_lcd_state {
754 uint32_t base;
755 uint32_t mode;
756 uint32_t irqctrl;
757 int page;
758 int page_off;
759 DisplayState *ds;
760 uint8_t video_ram[128*64/8];
761} musicpal_lcd_state;
762
763static uint32_t lcd_brightness;
764
765static uint8_t scale_lcd_color(uint8_t col)
766{
767 int tmp = col;
768
769 switch (lcd_brightness) {
770 case 0x00000007: /* 0 */
771 return 0;
772
773 case 0x00020000: /* 1 */
774 return (tmp * 1) / 7;
775
776 case 0x00020001: /* 2 */
777 return (tmp * 2) / 7;
778
779 case 0x00040000: /* 3 */
780 return (tmp * 3) / 7;
781
782 case 0x00010006: /* 4 */
783 return (tmp * 4) / 7;
784
785 case 0x00020005: /* 5 */
786 return (tmp * 5) / 7;
787
788 case 0x00040003: /* 6 */
789 return (tmp * 6) / 7;
790
791 case 0x00030004: /* 7 */
792 default:
793 return col;
794 }
795}
796
0266f2c7
AZ		 797#define SET_LCD_PIXEL(depth, type) \
798static inline void glue(set_lcd_pixel, depth) \
799 (musicpal_lcd_state *s, int x, int y, type col) \
800{ \
801 int dx, dy; \
802 type *pixel = &((type *) s->ds->data)[(y * 128 * 3 + x) * 3]; \
803\
804 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
805 for (dx = 0; dx < 3; dx++, pixel++) \
806 *pixel = col; \
24859b68 807}
0266f2c7
AZ		 808SET_LCD_PIXEL(8, uint8_t)
809SET_LCD_PIXEL(16, uint16_t)
810SET_LCD_PIXEL(32, uint32_t)
811
812#include "pixel_ops.h"
24859b68
AZ		 813
814static void lcd_refresh(void *opaque)
815{
816 musicpal_lcd_state *s = opaque;
0266f2c7 817 int x, y, col;
24859b68 818
0266f2c7
AZ		 819 switch (s->ds->depth) {
820 case 0:
821 return;
822#define LCD_REFRESH(depth, func) \
823 case depth: \
824 col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
825 scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
826 scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
827 for (x = 0; x < 128; x++) \
828 for (y = 0; y < 64; y++) \
829 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
830 glue(set_lcd_pixel, depth)(s, x, y, col); \
831 else \
832 glue(set_lcd_pixel, depth)(s, x, y, 0); \
833 break;
834 LCD_REFRESH(8, rgb_to_pixel8)
835 LCD_REFRESH(16, rgb_to_pixel16)
836 LCD_REFRESH(32, (s->ds->bgr ? rgb_to_pixel32bgr : rgb_to_pixel32))
837 default:
838 cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
839 s->ds->depth);
840 }
24859b68
AZ		 841
842 dpy_update(s->ds, 0, 0, 128*3, 64*3);
843}
844
845static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
846{
847 musicpal_lcd_state *s = opaque;
848
849 offset -= s->base;
850 switch (offset) {
851 case MP_LCD_IRQCTRL:
852 return s->irqctrl;
853
854 default:
855 return 0;
856 }
857}
858
859static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
860 uint32_t value)
861{
862 musicpal_lcd_state *s = opaque;
863
864 offset -= s->base;
865 switch (offset) {
866 case MP_LCD_IRQCTRL:
867 s->irqctrl = value;
868 break;
869
870 case MP_LCD_SPICTRL:
871 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
872 s->mode = value;
873 else
874 s->mode = MP_LCD_SPI_INVALID;
875 break;
876
877 case MP_LCD_INST:
878 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
879 s->page = value - MP_LCD_INST_SETPAGE0;
880 s->page_off = 0;
881 }
882 break;
883
884 case MP_LCD_DATA:
885 if (s->mode == MP_LCD_SPI_CMD) {
886 if (value >= MP_LCD_INST_SETPAGE0 &&
887 value <= MP_LCD_INST_SETPAGE7) {
888 s->page = value - MP_LCD_INST_SETPAGE0;
889 s->page_off = 0;
890 }
891 } else if (s->mode == MP_LCD_SPI_DATA) {
892 s->video_ram[s->page*128 + s->page_off] = value;
893 s->page_off = (s->page_off + 1) & 127;
894 }
895 break;
896 }
897}
898
899static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
900 musicpal_lcd_read,
901 musicpal_lcd_read,
902 musicpal_lcd_read
903};
904
905static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
906 musicpal_lcd_write,
907 musicpal_lcd_write,
908 musicpal_lcd_write
909};
910
911static void musicpal_lcd_init(DisplayState *ds, uint32_t base)
912{
913 musicpal_lcd_state *s;
914 int iomemtype;
915
916 s = qemu_mallocz(sizeof(musicpal_lcd_state));
917 if (!s)
918 return;
919 s->base = base;
920 s->ds = ds;
921 iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
922 musicpal_lcd_writefn, s);
923 cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
924
925 graphic_console_init(ds, lcd_refresh, NULL, NULL, NULL, s);
926 dpy_resize(ds, 128*3, 64*3);
927}
928
929/* PIC register offsets */
930#define MP_PIC_STATUS 0x00
931#define MP_PIC_ENABLE_SET 0x08
932#define MP_PIC_ENABLE_CLR 0x0C
933
934typedef struct mv88w8618_pic_state
935{
936 uint32_t base;
937 uint32_t level;
938 uint32_t enabled;
939 qemu_irq parent_irq;
940} mv88w8618_pic_state;
941
942static void mv88w8618_pic_update(mv88w8618_pic_state *s)
943{
944 qemu_set_irq(s->parent_irq, (s->level & s->enabled));
945}
946
947static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
948{
949 mv88w8618_pic_state *s = opaque;
950
951 if (level)
952 s->level |= 1 << irq;
953 else
954 s->level &= ~(1 << irq);
955 mv88w8618_pic_update(s);
956}
957
958static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
959{
960 mv88w8618_pic_state *s = opaque;
961
962 offset -= s->base;
963 switch (offset) {
964 case MP_PIC_STATUS:
965 return s->level & s->enabled;
966
967 default:
968 return 0;
969 }
970}
971
972static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
973 uint32_t value)
974{
975 mv88w8618_pic_state *s = opaque;
976
977 offset -= s->base;
978 switch (offset) {
979 case MP_PIC_ENABLE_SET:
980 s->enabled |= value;
981 break;
982
983 case MP_PIC_ENABLE_CLR:
984 s->enabled &= ~value;
985 s->level &= ~value;
986 break;
987 }
988 mv88w8618_pic_update(s);
989}
990
991static void mv88w8618_pic_reset(void *opaque)
992{
993 mv88w8618_pic_state *s = opaque;
994
995 s->level = 0;
996 s->enabled = 0;
997}
998
999static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
1000 mv88w8618_pic_read,
1001 mv88w8618_pic_read,
1002 mv88w8618_pic_read
1003};
1004
1005static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
1006 mv88w8618_pic_write,
1007 mv88w8618_pic_write,
1008 mv88w8618_pic_write
1009};
1010
1011static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
1012{
1013 mv88w8618_pic_state *s;
1014 int iomemtype;
1015 qemu_irq *qi;
1016
1017 s = qemu_mallocz(sizeof(mv88w8618_pic_state));
1018 if (!s)
1019 return NULL;
1020 qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
1021 s->base = base;
1022 s->parent_irq = parent_irq;
1023 iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1024 mv88w8618_pic_writefn, s);
1025 cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1026
1027 qemu_register_reset(mv88w8618_pic_reset, s);
1028
1029 return qi;
1030}
1031
1032/* PIT register offsets */
1033#define MP_PIT_TIMER1_LENGTH 0x00
1034/* ... */
1035#define MP_PIT_TIMER4_LENGTH 0x0C
1036#define MP_PIT_CONTROL 0x10
1037#define MP_PIT_TIMER1_VALUE 0x14
1038/* ... */
1039#define MP_PIT_TIMER4_VALUE 0x20
1040#define MP_BOARD_RESET 0x34
1041
1042/* Magic board reset value (probably some watchdog behind it) */
1043#define MP_BOARD_RESET_MAGIC 0x10000
1044
1045typedef struct mv88w8618_timer_state {
1046 ptimer_state *timer;
1047 uint32_t limit;
1048 int freq;
1049 qemu_irq irq;
1050} mv88w8618_timer_state;
1051
1052typedef struct mv88w8618_pit_state {
1053 void *timer[4];
1054 uint32_t control;
1055 uint32_t base;
1056} mv88w8618_pit_state;
1057
1058static void mv88w8618_timer_tick(void *opaque)
1059{
1060 mv88w8618_timer_state *s = opaque;
1061
1062 qemu_irq_raise(s->irq);
1063}
1064
1065static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1066{
1067 mv88w8618_timer_state *s;
1068 QEMUBH *bh;
1069
1070 s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1071 s->irq = irq;
1072 s->freq = freq;
1073
1074 bh = qemu_bh_new(mv88w8618_timer_tick, s);
1075 s->timer = ptimer_init(bh);
1076
1077 return s;
1078}
1079
1080static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1081{
1082 mv88w8618_pit_state *s = opaque;
1083 mv88w8618_timer_state *t;
1084
1085 offset -= s->base;
1086 switch (offset) {
1087 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1088 t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1089 return ptimer_get_count(t->timer);
1090
1091 default:
1092 return 0;
1093 }
1094}
1095
1096static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1097 uint32_t value)
1098{
1099 mv88w8618_pit_state *s = opaque;
1100 mv88w8618_timer_state *t;
1101 int i;
1102
1103 offset -= s->base;
1104 switch (offset) {
1105 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1106 t = s->timer[offset >> 2];
1107 t->limit = value;
1108 ptimer_set_limit(t->timer, t->limit, 1);
1109 break;
1110
1111 case MP_PIT_CONTROL:
1112 for (i = 0; i < 4; i++) {
1113 if (value & 0xf) {
1114 t = s->timer[i];
1115 ptimer_set_limit(t->timer, t->limit, 0);
1116 ptimer_set_freq(t->timer, t->freq);
1117 ptimer_run(t->timer, 0);
1118 }
1119 value >>= 4;
1120 }
1121 break;
1122
1123 case MP_BOARD_RESET:
1124 if (value == MP_BOARD_RESET_MAGIC)
1125 qemu_system_reset_request();
1126 break;
1127 }
1128}
1129
1130static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1131 mv88w8618_pit_read,
1132 mv88w8618_pit_read,
1133 mv88w8618_pit_read
1134};
1135
1136static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1137 mv88w8618_pit_write,
1138 mv88w8618_pit_write,
1139 mv88w8618_pit_write
1140};
1141
1142static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1143{
1144 int iomemtype;
1145 mv88w8618_pit_state *s;
1146
1147 s = qemu_mallocz(sizeof(mv88w8618_pit_state));
1148 if (!s)
1149 return;
1150
1151 s->base = base;
1152 /* Letting them all run at 1 MHz is likely just a pragmatic
1153 * simplification. */
1154 s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1155 s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1156 s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1157 s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1158
1159 iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1160 mv88w8618_pit_writefn, s);
1161 cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1162}
1163
1164/* Flash config register offsets */
1165#define MP_FLASHCFG_CFGR0 0x04
1166
1167typedef struct mv88w8618_flashcfg_state {
1168 uint32_t base;
1169 uint32_t cfgr0;
1170} mv88w8618_flashcfg_state;
1171
1172static uint32_t mv88w8618_flashcfg_read(void *opaque,
1173 target_phys_addr_t offset)
1174{
1175 mv88w8618_flashcfg_state *s = opaque;
1176
1177 offset -= s->base;
1178 switch (offset) {
1179 case MP_FLASHCFG_CFGR0:
1180 return s->cfgr0;
1181
1182 default:
1183 return 0;
1184 }
1185}
1186
1187static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1188 uint32_t value)
1189{
1190 mv88w8618_flashcfg_state *s = opaque;
1191
1192 offset -= s->base;
1193 switch (offset) {
1194 case MP_FLASHCFG_CFGR0:
1195 s->cfgr0 = value;
1196 break;
1197 }
1198}
1199
1200static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1201 mv88w8618_flashcfg_read,
1202 mv88w8618_flashcfg_read,
1203 mv88w8618_flashcfg_read
1204};
1205
1206static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1207 mv88w8618_flashcfg_write,
1208 mv88w8618_flashcfg_write,
1209 mv88w8618_flashcfg_write
1210};
1211
1212static void mv88w8618_flashcfg_init(uint32_t base)
1213{
1214 int iomemtype;
1215 mv88w8618_flashcfg_state *s;
1216
1217 s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
1218 if (!s)
1219 return;
1220
1221 s->base = base;
1222 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1223 iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1224 mv88w8618_flashcfg_writefn, s);
1225 cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1226}
1227
1228/* Various registers in the 0x80000000 domain */
1229#define MP_BOARD_REVISION 0x2018
1230
1231#define MP_WLAN_MAGIC1 0xc11c
1232#define MP_WLAN_MAGIC2 0xc124
1233
1234#define MP_GPIO_OE_LO 0xd008
1235#define MP_GPIO_OUT_LO 0xd00c
1236#define MP_GPIO_IN_LO 0xd010
1237#define MP_GPIO_ISR_LO 0xd020
1238#define MP_GPIO_OE_HI 0xd508
1239#define MP_GPIO_OUT_HI 0xd50c
1240#define MP_GPIO_IN_HI 0xd510
1241#define MP_GPIO_ISR_HI 0xd520
1242
1243/* GPIO bits & masks */
1244#define MP_GPIO_WHEEL_VOL (1 << 8)
1245#define MP_GPIO_WHEEL_VOL_INV (1 << 9)
1246#define MP_GPIO_WHEEL_NAV (1 << 10)
1247#define MP_GPIO_WHEEL_NAV_INV (1 << 11)
1248#define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1249#define MP_GPIO_BTN_FAVORITS (1 << 19)
1250#define MP_GPIO_BTN_MENU (1 << 20)
1251#define MP_GPIO_BTN_VOLUME (1 << 21)
1252#define MP_GPIO_BTN_NAVIGATION (1 << 22)
1253#define MP_GPIO_I2C_DATA_BIT 29
1254#define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT)
1255#define MP_GPIO_I2C_CLOCK_BIT 30
1256
1257/* LCD brightness bits in GPIO_OE_HI */
1258#define MP_OE_LCD_BRIGHTNESS 0x0007
1259
1260static uint32_t musicpal_read(void *opaque, target_phys_addr_t offset)
1261{
1262 offset -= 0x80000000;
1263 switch (offset) {
1264 case MP_BOARD_REVISION:
1265 return 0x0031;
1266
1267 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1268 return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1269
1270 case MP_GPIO_OUT_LO:
1271 return gpio_out_state & 0xFFFF;
1272 case MP_GPIO_OUT_HI:
1273 return gpio_out_state >> 16;
1274
1275 case MP_GPIO_IN_LO:
1276 return gpio_in_state & 0xFFFF;
1277 case MP_GPIO_IN_HI:
1278 /* Update received I2C data */
1279 gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1280 (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1281 return gpio_in_state >> 16;
1282
1283 /* This is a simplification of reality */
1284 case MP_GPIO_ISR_LO:
1285 return ~gpio_in_state & 0xFFFF;
1286 case MP_GPIO_ISR_HI:
1287 return ~gpio_in_state >> 16;
1288
1289 /* Workaround to allow loading the binary-only wlandrv.ko crap
1290 * from the original Freecom firmware. */
1291 case MP_WLAN_MAGIC1:
1292 return ~3;
1293 case MP_WLAN_MAGIC2:
1294 return -1;
1295
1296 default:
1297 return 0;
1298 }
1299}
1300
1301static void musicpal_write(void *opaque, target_phys_addr_t offset,
1302 uint32_t value)
1303{
1304 offset -= 0x80000000;
1305 switch (offset) {
1306 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1307 lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1308 (value & MP_OE_LCD_BRIGHTNESS);
1309 break;
1310
1311 case MP_GPIO_OUT_LO:
1312 gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1313 break;
1314 case MP_GPIO_OUT_HI:
1315 gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1316 lcd_brightness = (lcd_brightness & 0xFFFF) |
1317 (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1318 i2c_state_update(mixer_i2c,
1319 (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1320 (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1321 break;
1322
1323 }
1324}
1325
1326/* Keyboard codes & masks */
1327#define KEY_PRESSED 0x80
1328#define KEY_CODE 0x7f
1329
1330#define KEYCODE_TAB 0x0f
1331#define KEYCODE_ENTER 0x1c
1332#define KEYCODE_F 0x21
1333#define KEYCODE_M 0x32
1334
1335#define KEYCODE_EXTENDED 0xe0
1336#define KEYCODE_UP 0x48
1337#define KEYCODE_DOWN 0x50
1338#define KEYCODE_LEFT 0x4b
1339#define KEYCODE_RIGHT 0x4d
1340
1341static void musicpal_key_event(void *opaque, int keycode)
1342{
1343 qemu_irq irq = opaque;
1344 uint32_t event = 0;
1345 static int kbd_extended;
1346
1347 if (keycode == KEYCODE_EXTENDED) {
1348 kbd_extended = 1;
1349 return;
1350 }
1351
1352 if (kbd_extended)
1353 switch (keycode & KEY_CODE) {
1354 case KEYCODE_UP:
1355 event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1356 break;
1357
1358 case KEYCODE_DOWN:
1359 event = MP_GPIO_WHEEL_NAV;
1360 break;
1361
1362 case KEYCODE_LEFT:
1363 event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1364 break;
1365
1366 case KEYCODE_RIGHT:
1367 event = MP_GPIO_WHEEL_VOL;
1368 break;
1369 }
1370 else
1371 switch (keycode & KEY_CODE) {
1372 case KEYCODE_F:
1373 event = MP_GPIO_BTN_FAVORITS;
1374 break;
1375
1376 case KEYCODE_TAB:
1377 event = MP_GPIO_BTN_VOLUME;
1378 break;
1379
1380 case KEYCODE_ENTER:
1381 event = MP_GPIO_BTN_NAVIGATION;
1382 break;
1383
1384 case KEYCODE_M:
1385 event = MP_GPIO_BTN_MENU;
1386 break;
1387 }
1388
1389 if (keycode & KEY_PRESSED)
1390 gpio_in_state |= event;
1391 else if (gpio_in_state & event) {
1392 gpio_in_state &= ~event;
1393 qemu_irq_raise(irq);
1394 }
1395
1396 kbd_extended = 0;
1397}
1398
1399static CPUReadMemoryFunc *musicpal_readfn[] = {
1400 musicpal_read,
1401 musicpal_read,
1402 musicpal_read,
1403};
1404
1405static CPUWriteMemoryFunc *musicpal_writefn[] = {
1406 musicpal_write,
1407 musicpal_write,
1408 musicpal_write,
1409};
1410
1411static struct arm_boot_info musicpal_binfo = {
1412 .loader_start = 0x0,
1413 .board_id = 0x20e,
1414};
1415
b0f6edb1 1416static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
24859b68
AZ		 1417 const char *boot_device, DisplayState *ds,
1418 const char *kernel_filename, const char *kernel_cmdline,
1419 const char *initrd_filename, const char *cpu_model)
1420{
1421 CPUState *env;
1422 qemu_irq *pic;
1423 int index;
1424 int iomemtype;
1425 unsigned long flash_size;
1426
1427 if (!cpu_model)
1428 cpu_model = "arm926";
1429
1430 env = cpu_init(cpu_model);
1431 if (!env) {
1432 fprintf(stderr, "Unable to find CPU definition\n");
1433 exit(1);
1434 }
1435 pic = arm_pic_init_cpu(env);
1436
1437 /* For now we use a fixed - the original - RAM size */
1438 cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1439 qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1440
1441 sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1442 cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1443
1444 /* Catch various stuff not handled by separate subsystems */
1445 iomemtype = cpu_register_io_memory(0, musicpal_readfn,
b0f6edb1 1446 musicpal_writefn, env);
24859b68
AZ		 1447 cpu_register_physical_memory(0x80000000, 0x10000, iomemtype);
1448
1449 pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1450 mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1451
1452 if (serial_hds[0])
b6cd0ea1 1453 serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
24859b68
AZ		 1454 serial_hds[0], 1);
1455 if (serial_hds[1])
b6cd0ea1 1456 serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
24859b68
AZ		 1457 serial_hds[1], 1);
1458
1459 /* Register flash */
1460 index = drive_get_index(IF_PFLASH, 0, 0);
1461 if (index != -1) {
1462 flash_size = bdrv_getlength(drives_table[index].bdrv);
1463 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1464 flash_size != 32*1024*1024) {
1465 fprintf(stderr, "Invalid flash image size\n");
1466 exit(1);
1467 }
1468
1469 /*
1470 * The original U-Boot accesses the flash at 0xFE000000 instead of
1471 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1472 * image is smaller than 32 MB.
1473 */
1474 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1475 drives_table[index].bdrv, 0x10000,
1476 (flash_size + 0xffff) >> 16,
1477 MP_FLASH_SIZE_MAX / flash_size,
1478 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1479 0x5555, 0x2AAA);
1480 }
1481 mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1482
1483 musicpal_lcd_init(ds, MP_LCD_BASE);
1484
1485 qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1486
1487 /*
1488 * Wait a bit to catch menu button during U-Boot start-up
1489 * (to trigger emergency update).
1490 */
1491 sleep(1);
1492
1493 mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1494
1495 mixer_i2c = musicpal_audio_init(MP_AUDIO_BASE, pic[MP_AUDIO_IRQ]);
1496
1497 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1498 musicpal_binfo.kernel_filename = kernel_filename;
1499 musicpal_binfo.kernel_cmdline = kernel_cmdline;
1500 musicpal_binfo.initrd_filename = initrd_filename;
b0f6edb1 1501 arm_load_kernel(env, &musicpal_binfo);
24859b68
AZ		 1502}
1503
1504QEMUMachine musicpal_machine = {
1505 "musicpal",
1506 "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1507 musicpal_init,
1508 MP_RAM_DEFAULT_SIZE + MP_SRAM_SIZE + MP_FLASH_SIZE_MAX + RAMSIZE_FIXED
1509};
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