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Commit | Line | Data |
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e9f186e5 | 1 | /* |
116d5546 | 2 | * QEMU Cadence GEM emulation |
e9f186e5 PC |
3 | * |
4 | * Copyright (c) 2011 Xilinx, Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
8ef94f0b | 25 | #include "qemu/osdep.h" |
e9f186e5 PC |
26 | #include <zlib.h> /* For crc32 */ |
27 | ||
f49856d4 | 28 | #include "hw/net/cadence_gem.h" |
2bf57f73 | 29 | #include "qapi/error.h" |
e8e49943 | 30 | #include "qemu/log.h" |
e9f186e5 PC |
31 | #include "net/checksum.h" |
32 | ||
33 | #ifdef CADENCE_GEM_ERR_DEBUG | |
34 | #define DB_PRINT(...) do { \ | |
35 | fprintf(stderr, ": %s: ", __func__); \ | |
36 | fprintf(stderr, ## __VA_ARGS__); \ | |
2562755e | 37 | } while (0) |
e9f186e5 PC |
38 | #else |
39 | #define DB_PRINT(...) | |
40 | #endif | |
41 | ||
42 | #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ | |
43 | #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ | |
44 | #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ | |
45 | #define GEM_USERIO (0x0000000C/4) /* User IO reg */ | |
46 | #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ | |
47 | #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ | |
48 | #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ | |
49 | #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ | |
50 | #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ | |
51 | #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ | |
52 | #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ | |
53 | #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ | |
54 | #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ | |
3048ed6a | 55 | #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ |
e9f186e5 PC |
56 | #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ |
57 | #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ | |
58 | #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ | |
59 | #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ | |
60 | #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ | |
61 | #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ | |
62 | #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ | |
63 | #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ | |
64 | #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ | |
65 | #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ | |
66 | #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ | |
67 | #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ | |
68 | #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ | |
69 | #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ | |
70 | #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ | |
71 | #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ | |
72 | #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ | |
73 | #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ | |
74 | #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ | |
75 | #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ | |
76 | #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ | |
77 | #define GEM_MODID (0x000000FC/4) /* Module ID reg */ | |
78 | #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ | |
79 | #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ | |
80 | #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ | |
81 | #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ | |
82 | #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ | |
83 | #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ | |
84 | #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ | |
85 | #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ | |
86 | #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ | |
87 | #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ | |
88 | #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ | |
89 | #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ | |
90 | #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ | |
91 | #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ | |
92 | #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ | |
93 | #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ | |
94 | #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ | |
95 | #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ | |
96 | #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ | |
97 | #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ | |
98 | #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ | |
99 | #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ | |
100 | #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ | |
101 | #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ | |
102 | #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ | |
103 | #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ | |
104 | #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ | |
105 | #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ | |
106 | #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ | |
107 | #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ | |
108 | #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ | |
109 | #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ | |
110 | #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ | |
111 | #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ | |
112 | #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ | |
113 | #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ | |
114 | #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ | |
115 | #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ | |
116 | #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ | |
117 | #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ | |
118 | #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ | |
119 | #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ | |
120 | #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ | |
121 | #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ | |
122 | #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ | |
123 | ||
124 | #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ | |
125 | #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ | |
126 | #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ | |
127 | #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ | |
128 | #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ | |
129 | #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ | |
130 | #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ | |
131 | #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ | |
132 | #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ | |
133 | #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ | |
134 | #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ | |
135 | #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ | |
136 | ||
137 | /* Design Configuration Registers */ | |
138 | #define GEM_DESCONF (0x00000280/4) | |
139 | #define GEM_DESCONF2 (0x00000284/4) | |
140 | #define GEM_DESCONF3 (0x00000288/4) | |
141 | #define GEM_DESCONF4 (0x0000028C/4) | |
142 | #define GEM_DESCONF5 (0x00000290/4) | |
143 | #define GEM_DESCONF6 (0x00000294/4) | |
144 | #define GEM_DESCONF7 (0x00000298/4) | |
145 | ||
67101725 AF |
146 | #define GEM_INT_Q1_STATUS (0x00000400 / 4) |
147 | #define GEM_INT_Q1_MASK (0x00000640 / 4) | |
148 | ||
149 | #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) | |
79b2ac8f | 150 | #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) |
67101725 AF |
151 | |
152 | #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) | |
79b2ac8f | 153 | #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) |
67101725 AF |
154 | |
155 | #define GEM_INT_Q1_ENABLE (0x00000600 / 4) | |
156 | #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) | |
67101725 AF |
157 | |
158 | #define GEM_INT_Q1_DISABLE (0x00000620 / 4) | |
159 | #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) | |
67101725 AF |
160 | |
161 | #define GEM_INT_Q1_MASK (0x00000640 / 4) | |
162 | #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) | |
67101725 | 163 | |
e8e49943 AF |
164 | #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) |
165 | ||
166 | #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) | |
167 | #define GEM_ST1R_DSTC_ENABLE (1 << 28) | |
168 | #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) | |
169 | #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) | |
170 | #define GEM_ST1R_DSTC_MATCH_SHIFT (4) | |
171 | #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) | |
172 | #define GEM_ST1R_QUEUE_SHIFT (0) | |
173 | #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) | |
174 | ||
175 | #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) | |
176 | ||
177 | #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) | |
178 | #define GEM_ST2R_COMPARE_A_SHIFT (13) | |
179 | #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) | |
180 | #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) | |
181 | #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) | |
182 | #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ | |
183 | + 1) | |
184 | #define GEM_ST2R_QUEUE_SHIFT (0) | |
185 | #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) | |
186 | ||
187 | #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) | |
188 | #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) | |
189 | ||
190 | #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) | |
191 | #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) | |
192 | #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) | |
193 | #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) | |
194 | ||
e9f186e5 PC |
195 | /*****************************************/ |
196 | #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ | |
197 | #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ | |
198 | #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ | |
199 | #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ | |
200 | ||
201 | #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ | |
3048ed6a | 202 | #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ |
e9f186e5 PC |
203 | #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ |
204 | #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ | |
205 | #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ | |
206 | #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ | |
207 | #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ | |
208 | #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ | |
209 | ||
e48fdd9d EI |
210 | #define GEM_DMACFG_ADDR_64B (1U << 30) |
211 | #define GEM_DMACFG_TX_BD_EXT (1U << 29) | |
212 | #define GEM_DMACFG_RX_BD_EXT (1U << 28) | |
2801339f | 213 | #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ |
e9f186e5 PC |
214 | #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ |
215 | #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ | |
216 | #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ | |
217 | ||
218 | #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ | |
219 | #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ | |
220 | ||
221 | #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ | |
222 | #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ | |
223 | ||
224 | /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ | |
225 | #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ | |
226 | #define GEM_INT_TXUSED 0x00000008 | |
227 | #define GEM_INT_RXUSED 0x00000004 | |
228 | #define GEM_INT_RXCMPL 0x00000002 | |
229 | ||
230 | #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ | |
231 | #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ | |
232 | #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ | |
233 | #define GEM_PHYMNTNC_ADDR_SHFT 23 | |
234 | #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ | |
235 | #define GEM_PHYMNTNC_REG_SHIFT 18 | |
236 | ||
237 | /* Marvell PHY definitions */ | |
238 | #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ | |
239 | ||
240 | #define PHY_REG_CONTROL 0 | |
241 | #define PHY_REG_STATUS 1 | |
242 | #define PHY_REG_PHYID1 2 | |
243 | #define PHY_REG_PHYID2 3 | |
244 | #define PHY_REG_ANEGADV 4 | |
245 | #define PHY_REG_LINKPABIL 5 | |
246 | #define PHY_REG_ANEGEXP 6 | |
247 | #define PHY_REG_NEXTP 7 | |
248 | #define PHY_REG_LINKPNEXTP 8 | |
249 | #define PHY_REG_100BTCTRL 9 | |
250 | #define PHY_REG_1000BTSTAT 10 | |
251 | #define PHY_REG_EXTSTAT 15 | |
252 | #define PHY_REG_PHYSPCFC_CTL 16 | |
253 | #define PHY_REG_PHYSPCFC_ST 17 | |
254 | #define PHY_REG_INT_EN 18 | |
255 | #define PHY_REG_INT_ST 19 | |
256 | #define PHY_REG_EXT_PHYSPCFC_CTL 20 | |
257 | #define PHY_REG_RXERR 21 | |
258 | #define PHY_REG_EACD 22 | |
259 | #define PHY_REG_LED 24 | |
260 | #define PHY_REG_LED_OVRD 25 | |
261 | #define PHY_REG_EXT_PHYSPCFC_CTL2 26 | |
262 | #define PHY_REG_EXT_PHYSPCFC_ST 27 | |
263 | #define PHY_REG_CABLE_DIAG 28 | |
264 | ||
265 | #define PHY_REG_CONTROL_RST 0x8000 | |
266 | #define PHY_REG_CONTROL_LOOP 0x4000 | |
267 | #define PHY_REG_CONTROL_ANEG 0x1000 | |
268 | ||
269 | #define PHY_REG_STATUS_LINK 0x0004 | |
270 | #define PHY_REG_STATUS_ANEGCMPL 0x0020 | |
271 | ||
272 | #define PHY_REG_INT_ST_ANEGCMPL 0x0800 | |
273 | #define PHY_REG_INT_ST_LINKC 0x0400 | |
274 | #define PHY_REG_INT_ST_ENERGY 0x0010 | |
275 | ||
276 | /***********************************************************************/ | |
63af1e0c PC |
277 | #define GEM_RX_REJECT (-1) |
278 | #define GEM_RX_PROMISCUOUS_ACCEPT (-2) | |
279 | #define GEM_RX_BROADCAST_ACCEPT (-3) | |
280 | #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) | |
281 | #define GEM_RX_UNICAST_HASH_ACCEPT (-5) | |
282 | ||
283 | #define GEM_RX_SAR_ACCEPT 0 | |
e9f186e5 PC |
284 | |
285 | /***********************************************************************/ | |
286 | ||
287 | #define DESC_1_USED 0x80000000 | |
288 | #define DESC_1_LENGTH 0x00001FFF | |
289 | ||
290 | #define DESC_1_TX_WRAP 0x40000000 | |
291 | #define DESC_1_TX_LAST 0x00008000 | |
292 | ||
293 | #define DESC_0_RX_WRAP 0x00000002 | |
294 | #define DESC_0_RX_OWNERSHIP 0x00000001 | |
295 | ||
63af1e0c PC |
296 | #define R_DESC_1_RX_SAR_SHIFT 25 |
297 | #define R_DESC_1_RX_SAR_LENGTH 2 | |
a03f7429 | 298 | #define R_DESC_1_RX_SAR_MATCH (1 << 27) |
63af1e0c PC |
299 | #define R_DESC_1_RX_UNICAST_HASH (1 << 29) |
300 | #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) | |
301 | #define R_DESC_1_RX_BROADCAST (1 << 31) | |
302 | ||
e9f186e5 PC |
303 | #define DESC_1_RX_SOF 0x00004000 |
304 | #define DESC_1_RX_EOF 0x00008000 | |
305 | ||
a5517666 AF |
306 | #define GEM_MODID_VALUE 0x00020118 |
307 | ||
e48fdd9d | 308 | static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) |
e9f186e5 | 309 | { |
e48fdd9d EI |
310 | uint64_t ret = desc[0]; |
311 | ||
312 | if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | |
313 | ret |= (uint64_t)desc[2] << 32; | |
314 | } | |
315 | return ret; | |
e9f186e5 PC |
316 | } |
317 | ||
f0236182 | 318 | static inline unsigned tx_desc_get_used(uint32_t *desc) |
e9f186e5 PC |
319 | { |
320 | return (desc[1] & DESC_1_USED) ? 1 : 0; | |
321 | } | |
322 | ||
f0236182 | 323 | static inline void tx_desc_set_used(uint32_t *desc) |
e9f186e5 PC |
324 | { |
325 | desc[1] |= DESC_1_USED; | |
326 | } | |
327 | ||
f0236182 | 328 | static inline unsigned tx_desc_get_wrap(uint32_t *desc) |
e9f186e5 PC |
329 | { |
330 | return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; | |
331 | } | |
332 | ||
f0236182 | 333 | static inline unsigned tx_desc_get_last(uint32_t *desc) |
e9f186e5 PC |
334 | { |
335 | return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; | |
336 | } | |
337 | ||
f0236182 | 338 | static inline void tx_desc_set_last(uint32_t *desc) |
cbdab58d AF |
339 | { |
340 | desc[1] |= DESC_1_TX_LAST; | |
341 | } | |
342 | ||
f0236182 | 343 | static inline unsigned tx_desc_get_length(uint32_t *desc) |
e9f186e5 PC |
344 | { |
345 | return desc[1] & DESC_1_LENGTH; | |
346 | } | |
347 | ||
f0236182 | 348 | static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) |
e9f186e5 | 349 | { |
67101725 | 350 | DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); |
e9f186e5 PC |
351 | DB_PRINT("bufaddr: 0x%08x\n", *desc); |
352 | DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); | |
353 | DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); | |
354 | DB_PRINT("last: %d\n", tx_desc_get_last(desc)); | |
355 | DB_PRINT("length: %d\n", tx_desc_get_length(desc)); | |
356 | } | |
357 | ||
e48fdd9d | 358 | static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) |
e9f186e5 | 359 | { |
e48fdd9d EI |
360 | uint64_t ret = desc[0] & ~0x3UL; |
361 | ||
362 | if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | |
363 | ret |= (uint64_t)desc[2] << 32; | |
364 | } | |
365 | return ret; | |
366 | } | |
367 | ||
368 | static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) | |
369 | { | |
370 | int ret = 2; | |
371 | ||
372 | if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | |
373 | ret += 2; | |
374 | } | |
375 | if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT | |
376 | : GEM_DMACFG_TX_BD_EXT)) { | |
377 | ret += 2; | |
378 | } | |
379 | ||
380 | assert(ret <= DESC_MAX_NUM_WORDS); | |
381 | return ret; | |
e9f186e5 PC |
382 | } |
383 | ||
f0236182 | 384 | static inline unsigned rx_desc_get_wrap(uint32_t *desc) |
e9f186e5 PC |
385 | { |
386 | return desc[0] & DESC_0_RX_WRAP ? 1 : 0; | |
387 | } | |
388 | ||
f0236182 | 389 | static inline unsigned rx_desc_get_ownership(uint32_t *desc) |
e9f186e5 PC |
390 | { |
391 | return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; | |
392 | } | |
393 | ||
f0236182 | 394 | static inline void rx_desc_set_ownership(uint32_t *desc) |
e9f186e5 PC |
395 | { |
396 | desc[0] |= DESC_0_RX_OWNERSHIP; | |
397 | } | |
398 | ||
f0236182 | 399 | static inline void rx_desc_set_sof(uint32_t *desc) |
e9f186e5 PC |
400 | { |
401 | desc[1] |= DESC_1_RX_SOF; | |
402 | } | |
403 | ||
f0236182 | 404 | static inline void rx_desc_set_eof(uint32_t *desc) |
e9f186e5 PC |
405 | { |
406 | desc[1] |= DESC_1_RX_EOF; | |
407 | } | |
408 | ||
f0236182 | 409 | static inline void rx_desc_set_length(uint32_t *desc, unsigned len) |
e9f186e5 PC |
410 | { |
411 | desc[1] &= ~DESC_1_LENGTH; | |
412 | desc[1] |= len; | |
413 | } | |
414 | ||
f0236182 | 415 | static inline void rx_desc_set_broadcast(uint32_t *desc) |
63af1e0c PC |
416 | { |
417 | desc[1] |= R_DESC_1_RX_BROADCAST; | |
418 | } | |
419 | ||
f0236182 | 420 | static inline void rx_desc_set_unicast_hash(uint32_t *desc) |
63af1e0c PC |
421 | { |
422 | desc[1] |= R_DESC_1_RX_UNICAST_HASH; | |
423 | } | |
424 | ||
f0236182 | 425 | static inline void rx_desc_set_multicast_hash(uint32_t *desc) |
63af1e0c PC |
426 | { |
427 | desc[1] |= R_DESC_1_RX_MULTICAST_HASH; | |
428 | } | |
429 | ||
f0236182 | 430 | static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) |
63af1e0c PC |
431 | { |
432 | desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, | |
433 | sar_idx); | |
a03f7429 | 434 | desc[1] |= R_DESC_1_RX_SAR_MATCH; |
63af1e0c PC |
435 | } |
436 | ||
e9f186e5 | 437 | /* The broadcast MAC address: 0xFFFFFFFFFFFF */ |
6a0a70b0 | 438 | static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
e9f186e5 PC |
439 | |
440 | /* | |
441 | * gem_init_register_masks: | |
442 | * One time initialization. | |
443 | * Set masks to identify which register bits have magical clear properties | |
444 | */ | |
448f19e2 | 445 | static void gem_init_register_masks(CadenceGEMState *s) |
e9f186e5 | 446 | { |
3048ed6a | 447 | /* Mask of register bits which are read only */ |
e9f186e5 PC |
448 | memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); |
449 | s->regs_ro[GEM_NWCTRL] = 0xFFF80000; | |
450 | s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; | |
e48fdd9d | 451 | s->regs_ro[GEM_DMACFG] = 0x8E00F000; |
e9f186e5 PC |
452 | s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; |
453 | s->regs_ro[GEM_RXQBASE] = 0x00000003; | |
454 | s->regs_ro[GEM_TXQBASE] = 0x00000003; | |
455 | s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; | |
456 | s->regs_ro[GEM_ISR] = 0xFFFFFFFF; | |
457 | s->regs_ro[GEM_IMR] = 0xFFFFFFFF; | |
458 | s->regs_ro[GEM_MODID] = 0xFFFFFFFF; | |
459 | ||
460 | /* Mask of register bits which are clear on read */ | |
461 | memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); | |
462 | s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; | |
463 | ||
464 | /* Mask of register bits which are write 1 to clear */ | |
465 | memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); | |
466 | s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; | |
467 | s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; | |
468 | ||
469 | /* Mask of register bits which are write only */ | |
470 | memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); | |
471 | s->regs_wo[GEM_NWCTRL] = 0x00073E60; | |
472 | s->regs_wo[GEM_IER] = 0x07FFFFFF; | |
473 | s->regs_wo[GEM_IDR] = 0x07FFFFFF; | |
474 | } | |
475 | ||
476 | /* | |
477 | * phy_update_link: | |
478 | * Make the emulated PHY link state match the QEMU "interface" state. | |
479 | */ | |
448f19e2 | 480 | static void phy_update_link(CadenceGEMState *s) |
e9f186e5 | 481 | { |
b356f76d | 482 | DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); |
e9f186e5 PC |
483 | |
484 | /* Autonegotiation status mirrors link status. */ | |
b356f76d | 485 | if (qemu_get_queue(s->nic)->link_down) { |
e9f186e5 PC |
486 | s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | |
487 | PHY_REG_STATUS_LINK); | |
488 | s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; | |
489 | } else { | |
490 | s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | | |
491 | PHY_REG_STATUS_LINK); | |
492 | s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | | |
493 | PHY_REG_INT_ST_ANEGCMPL | | |
494 | PHY_REG_INT_ST_ENERGY); | |
495 | } | |
496 | } | |
497 | ||
4e68f7a0 | 498 | static int gem_can_receive(NetClientState *nc) |
e9f186e5 | 499 | { |
448f19e2 | 500 | CadenceGEMState *s; |
67101725 | 501 | int i; |
e9f186e5 | 502 | |
cc1f0f45 | 503 | s = qemu_get_nic_opaque(nc); |
e9f186e5 | 504 | |
e9f186e5 PC |
505 | /* Do nothing if receive is not enabled. */ |
506 | if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { | |
3ae5725f PC |
507 | if (s->can_rx_state != 1) { |
508 | s->can_rx_state = 1; | |
509 | DB_PRINT("can't receive - no enable\n"); | |
510 | } | |
e9f186e5 PC |
511 | return 0; |
512 | } | |
513 | ||
67101725 | 514 | for (i = 0; i < s->num_priority_queues; i++) { |
dacc0566 AF |
515 | if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { |
516 | break; | |
8202aa53 | 517 | } |
dacc0566 AF |
518 | }; |
519 | ||
520 | if (i == s->num_priority_queues) { | |
521 | if (s->can_rx_state != 2) { | |
522 | s->can_rx_state = 2; | |
523 | DB_PRINT("can't receive - all the buffer descriptors are busy\n"); | |
524 | } | |
525 | return 0; | |
8202aa53 PC |
526 | } |
527 | ||
3ae5725f PC |
528 | if (s->can_rx_state != 0) { |
529 | s->can_rx_state = 0; | |
67101725 | 530 | DB_PRINT("can receive\n"); |
3ae5725f | 531 | } |
e9f186e5 PC |
532 | return 1; |
533 | } | |
534 | ||
535 | /* | |
536 | * gem_update_int_status: | |
537 | * Raise or lower interrupt based on current status. | |
538 | */ | |
448f19e2 | 539 | static void gem_update_int_status(CadenceGEMState *s) |
e9f186e5 | 540 | { |
67101725 AF |
541 | int i; |
542 | ||
596b6f51 AF |
543 | if (!s->regs[GEM_ISR]) { |
544 | /* ISR isn't set, clear all the interrupts */ | |
545 | for (i = 0; i < s->num_priority_queues; ++i) { | |
546 | qemu_set_irq(s->irq[i], 0); | |
547 | } | |
548 | return; | |
549 | } | |
550 | ||
551 | /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to | |
552 | * check it again. | |
553 | */ | |
554 | if (s->num_priority_queues == 1) { | |
67101725 | 555 | /* No priority queues, just trigger the interrupt */ |
8ea1d056 | 556 | DB_PRINT("asserting int.\n"); |
2bf57f73 | 557 | qemu_set_irq(s->irq[0], 1); |
67101725 AF |
558 | return; |
559 | } | |
560 | ||
561 | for (i = 0; i < s->num_priority_queues; ++i) { | |
562 | if (s->regs[GEM_INT_Q1_STATUS + i]) { | |
563 | DB_PRINT("asserting int. (q=%d)\n", i); | |
564 | qemu_set_irq(s->irq[i], 1); | |
565 | } | |
e9f186e5 PC |
566 | } |
567 | } | |
568 | ||
569 | /* | |
570 | * gem_receive_updatestats: | |
571 | * Increment receive statistics. | |
572 | */ | |
448f19e2 | 573 | static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, |
e9f186e5 PC |
574 | unsigned bytes) |
575 | { | |
576 | uint64_t octets; | |
577 | ||
578 | /* Total octets (bytes) received */ | |
579 | octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | | |
580 | s->regs[GEM_OCTRXHI]; | |
581 | octets += bytes; | |
582 | s->regs[GEM_OCTRXLO] = octets >> 32; | |
583 | s->regs[GEM_OCTRXHI] = octets; | |
584 | ||
585 | /* Error-free Frames received */ | |
586 | s->regs[GEM_RXCNT]++; | |
587 | ||
588 | /* Error-free Broadcast Frames counter */ | |
589 | if (!memcmp(packet, broadcast_addr, 6)) { | |
590 | s->regs[GEM_RXBROADCNT]++; | |
591 | } | |
592 | ||
593 | /* Error-free Multicast Frames counter */ | |
594 | if (packet[0] == 0x01) { | |
595 | s->regs[GEM_RXMULTICNT]++; | |
596 | } | |
597 | ||
598 | if (bytes <= 64) { | |
599 | s->regs[GEM_RX64CNT]++; | |
600 | } else if (bytes <= 127) { | |
601 | s->regs[GEM_RX65CNT]++; | |
602 | } else if (bytes <= 255) { | |
603 | s->regs[GEM_RX128CNT]++; | |
604 | } else if (bytes <= 511) { | |
605 | s->regs[GEM_RX256CNT]++; | |
606 | } else if (bytes <= 1023) { | |
607 | s->regs[GEM_RX512CNT]++; | |
608 | } else if (bytes <= 1518) { | |
609 | s->regs[GEM_RX1024CNT]++; | |
610 | } else { | |
611 | s->regs[GEM_RX1519CNT]++; | |
612 | } | |
613 | } | |
614 | ||
615 | /* | |
616 | * Get the MAC Address bit from the specified position | |
617 | */ | |
618 | static unsigned get_bit(const uint8_t *mac, unsigned bit) | |
619 | { | |
620 | unsigned byte; | |
621 | ||
622 | byte = mac[bit / 8]; | |
623 | byte >>= (bit & 0x7); | |
624 | byte &= 1; | |
625 | ||
626 | return byte; | |
627 | } | |
628 | ||
629 | /* | |
630 | * Calculate a GEM MAC Address hash index | |
631 | */ | |
632 | static unsigned calc_mac_hash(const uint8_t *mac) | |
633 | { | |
634 | int index_bit, mac_bit; | |
635 | unsigned hash_index; | |
636 | ||
637 | hash_index = 0; | |
638 | mac_bit = 5; | |
639 | for (index_bit = 5; index_bit >= 0; index_bit--) { | |
640 | hash_index |= (get_bit(mac, mac_bit) ^ | |
641 | get_bit(mac, mac_bit + 6) ^ | |
642 | get_bit(mac, mac_bit + 12) ^ | |
643 | get_bit(mac, mac_bit + 18) ^ | |
644 | get_bit(mac, mac_bit + 24) ^ | |
645 | get_bit(mac, mac_bit + 30) ^ | |
646 | get_bit(mac, mac_bit + 36) ^ | |
647 | get_bit(mac, mac_bit + 42)) << index_bit; | |
648 | mac_bit--; | |
649 | } | |
650 | ||
651 | return hash_index; | |
652 | } | |
653 | ||
654 | /* | |
655 | * gem_mac_address_filter: | |
656 | * Accept or reject this destination address? | |
657 | * Returns: | |
658 | * GEM_RX_REJECT: reject | |
63af1e0c PC |
659 | * >= 0: Specific address accept (which matched SAR is returned) |
660 | * others for various other modes of accept: | |
661 | * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, | |
662 | * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT | |
e9f186e5 | 663 | */ |
448f19e2 | 664 | static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) |
e9f186e5 PC |
665 | { |
666 | uint8_t *gem_spaddr; | |
667 | int i; | |
668 | ||
669 | /* Promiscuous mode? */ | |
670 | if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { | |
63af1e0c | 671 | return GEM_RX_PROMISCUOUS_ACCEPT; |
e9f186e5 PC |
672 | } |
673 | ||
674 | if (!memcmp(packet, broadcast_addr, 6)) { | |
675 | /* Reject broadcast packets? */ | |
676 | if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { | |
677 | return GEM_RX_REJECT; | |
678 | } | |
63af1e0c | 679 | return GEM_RX_BROADCAST_ACCEPT; |
e9f186e5 PC |
680 | } |
681 | ||
682 | /* Accept packets -w- hash match? */ | |
683 | if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || | |
684 | (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { | |
685 | unsigned hash_index; | |
686 | ||
687 | hash_index = calc_mac_hash(packet); | |
688 | if (hash_index < 32) { | |
689 | if (s->regs[GEM_HASHLO] & (1<<hash_index)) { | |
63af1e0c PC |
690 | return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : |
691 | GEM_RX_UNICAST_HASH_ACCEPT; | |
e9f186e5 PC |
692 | } |
693 | } else { | |
694 | hash_index -= 32; | |
695 | if (s->regs[GEM_HASHHI] & (1<<hash_index)) { | |
63af1e0c PC |
696 | return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : |
697 | GEM_RX_UNICAST_HASH_ACCEPT; | |
e9f186e5 PC |
698 | } |
699 | } | |
700 | } | |
701 | ||
702 | /* Check all 4 specific addresses */ | |
703 | gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); | |
63af1e0c | 704 | for (i = 3; i >= 0; i--) { |
64eb9301 | 705 | if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { |
63af1e0c | 706 | return GEM_RX_SAR_ACCEPT + i; |
e9f186e5 | 707 | } |
e9f186e5 PC |
708 | } |
709 | ||
710 | /* No address match; reject the packet */ | |
711 | return GEM_RX_REJECT; | |
712 | } | |
713 | ||
e8e49943 AF |
714 | /* Figure out which queue the received data should be sent to */ |
715 | static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, | |
716 | unsigned rxbufsize) | |
717 | { | |
718 | uint32_t reg; | |
719 | bool matched, mismatched; | |
720 | int i, j; | |
721 | ||
722 | for (i = 0; i < s->num_type1_screeners; i++) { | |
723 | reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; | |
724 | matched = false; | |
725 | mismatched = false; | |
726 | ||
727 | /* Screening is based on UDP Port */ | |
728 | if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { | |
729 | uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; | |
730 | if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, | |
731 | GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { | |
732 | matched = true; | |
733 | } else { | |
734 | mismatched = true; | |
735 | } | |
736 | } | |
737 | ||
738 | /* Screening is based on DS/TC */ | |
739 | if (reg & GEM_ST1R_DSTC_ENABLE) { | |
740 | uint8_t dscp = rxbuf_ptr[14 + 1]; | |
741 | if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, | |
742 | GEM_ST1R_DSTC_MATCH_WIDTH)) { | |
743 | matched = true; | |
744 | } else { | |
745 | mismatched = true; | |
746 | } | |
747 | } | |
748 | ||
749 | if (matched && !mismatched) { | |
750 | return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); | |
751 | } | |
752 | } | |
753 | ||
754 | for (i = 0; i < s->num_type2_screeners; i++) { | |
755 | reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; | |
756 | matched = false; | |
757 | mismatched = false; | |
758 | ||
759 | if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { | |
760 | uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; | |
761 | int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, | |
762 | GEM_ST2R_ETHERTYPE_INDEX_WIDTH); | |
763 | ||
764 | if (et_idx > s->num_type2_screeners) { | |
765 | qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " | |
766 | "register index: %d\n", et_idx); | |
767 | } | |
768 | if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + | |
769 | et_idx]) { | |
770 | matched = true; | |
771 | } else { | |
772 | mismatched = true; | |
773 | } | |
774 | } | |
775 | ||
776 | /* Compare A, B, C */ | |
777 | for (j = 0; j < 3; j++) { | |
778 | uint32_t cr0, cr1, mask; | |
779 | uint16_t rx_cmp; | |
780 | int offset; | |
781 | int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, | |
782 | GEM_ST2R_COMPARE_WIDTH); | |
783 | ||
784 | if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { | |
785 | continue; | |
786 | } | |
787 | if (cr_idx > s->num_type2_screeners) { | |
788 | qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " | |
789 | "register index: %d\n", cr_idx); | |
790 | } | |
791 | ||
792 | cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; | |
793 | cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; | |
794 | offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, | |
795 | GEM_T2CW1_OFFSET_VALUE_WIDTH); | |
796 | ||
797 | switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, | |
798 | GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { | |
799 | case 3: /* Skip UDP header */ | |
800 | qemu_log_mask(LOG_UNIMP, "TCP compare offsets" | |
801 | "unimplemented - assuming UDP\n"); | |
802 | offset += 8; | |
803 | /* Fallthrough */ | |
804 | case 2: /* skip the IP header */ | |
805 | offset += 20; | |
806 | /* Fallthrough */ | |
807 | case 1: /* Count from after the ethertype */ | |
808 | offset += 14; | |
809 | break; | |
810 | case 0: | |
811 | /* Offset from start of frame */ | |
812 | break; | |
813 | } | |
814 | ||
815 | rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; | |
816 | mask = extract32(cr0, 0, 16); | |
817 | ||
818 | if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { | |
819 | matched = true; | |
820 | } else { | |
821 | mismatched = true; | |
822 | } | |
823 | } | |
824 | ||
825 | if (matched && !mismatched) { | |
826 | return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); | |
827 | } | |
828 | } | |
829 | ||
830 | /* We made it here, assume it's queue 0 */ | |
831 | return 0; | |
832 | } | |
833 | ||
67101725 | 834 | static void gem_get_rx_desc(CadenceGEMState *s, int q) |
06c2fe95 | 835 | { |
67101725 | 836 | DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); |
06c2fe95 | 837 | /* read current descriptor */ |
75b77602 | 838 | cpu_physical_memory_read(s->rx_desc_addr[q], |
e48fdd9d EI |
839 | (uint8_t *)s->rx_desc[q], |
840 | sizeof(uint32_t) * gem_get_desc_len(s, true)); | |
06c2fe95 PC |
841 | |
842 | /* Descriptor owned by software ? */ | |
67101725 | 843 | if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { |
06c2fe95 | 844 | DB_PRINT("descriptor 0x%x owned by sw.\n", |
67101725 | 845 | (unsigned)s->rx_desc_addr[q]); |
06c2fe95 PC |
846 | s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; |
847 | s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); | |
848 | /* Handle interrupt consequences */ | |
849 | gem_update_int_status(s); | |
850 | } | |
851 | } | |
852 | ||
e9f186e5 PC |
853 | /* |
854 | * gem_receive: | |
855 | * Fit a packet handed to us by QEMU into the receive descriptor ring. | |
856 | */ | |
4e68f7a0 | 857 | static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) |
e9f186e5 | 858 | { |
448f19e2 | 859 | CadenceGEMState *s; |
e9f186e5 PC |
860 | unsigned rxbufsize, bytes_to_copy; |
861 | unsigned rxbuf_offset; | |
862 | uint8_t rxbuf[2048]; | |
863 | uint8_t *rxbuf_ptr; | |
3b2c97f9 | 864 | bool first_desc = true; |
63af1e0c | 865 | int maf; |
2bf57f73 | 866 | int q = 0; |
e9f186e5 | 867 | |
cc1f0f45 | 868 | s = qemu_get_nic_opaque(nc); |
e9f186e5 | 869 | |
e9f186e5 | 870 | /* Is this destination MAC address "for us" ? */ |
63af1e0c PC |
871 | maf = gem_mac_address_filter(s, buf); |
872 | if (maf == GEM_RX_REJECT) { | |
e9f186e5 PC |
873 | return -1; |
874 | } | |
875 | ||
876 | /* Discard packets with receive length error enabled ? */ | |
877 | if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { | |
878 | unsigned type_len; | |
879 | ||
880 | /* Fish the ethertype / length field out of the RX packet */ | |
881 | type_len = buf[12] << 8 | buf[13]; | |
882 | /* It is a length field, not an ethertype */ | |
883 | if (type_len < 0x600) { | |
884 | if (size < type_len) { | |
885 | /* discard */ | |
886 | return -1; | |
887 | } | |
888 | } | |
889 | } | |
890 | ||
891 | /* | |
892 | * Determine configured receive buffer offset (probably 0) | |
893 | */ | |
894 | rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> | |
895 | GEM_NWCFG_BUFF_OFST_S; | |
896 | ||
897 | /* The configure size of each receive buffer. Determines how many | |
898 | * buffers needed to hold this packet. | |
899 | */ | |
900 | rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> | |
901 | GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; | |
902 | bytes_to_copy = size; | |
903 | ||
f265ae8c AF |
904 | /* Hardware allows a zero value here but warns against it. To avoid QEMU |
905 | * indefinite loops we enforce a minimum value here | |
906 | */ | |
907 | if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { | |
908 | rxbufsize = GEM_DMACFG_RBUFSZ_MUL; | |
909 | } | |
910 | ||
191946c5 PC |
911 | /* Pad to minimum length. Assume FCS field is stripped, logic |
912 | * below will increment it to the real minimum of 64 when | |
913 | * not FCS stripping | |
914 | */ | |
915 | if (size < 60) { | |
916 | size = 60; | |
917 | } | |
918 | ||
e9f186e5 PC |
919 | /* Strip of FCS field ? (usually yes) */ |
920 | if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { | |
921 | rxbuf_ptr = (void *)buf; | |
922 | } else { | |
923 | unsigned crc_val; | |
e9f186e5 | 924 | |
244381ec PP |
925 | if (size > sizeof(rxbuf) - sizeof(crc_val)) { |
926 | size = sizeof(rxbuf) - sizeof(crc_val); | |
927 | } | |
928 | bytes_to_copy = size; | |
e9f186e5 | 929 | /* The application wants the FCS field, which QEMU does not provide. |
3048ed6a | 930 | * We must try and calculate one. |
e9f186e5 PC |
931 | */ |
932 | ||
933 | memcpy(rxbuf, buf, size); | |
5fbe02e8 | 934 | memset(rxbuf + size, 0, sizeof(rxbuf) - size); |
e9f186e5 PC |
935 | rxbuf_ptr = rxbuf; |
936 | crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); | |
c94239fe | 937 | memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); |
e9f186e5 PC |
938 | |
939 | bytes_to_copy += 4; | |
940 | size += 4; | |
941 | } | |
942 | ||
e9f186e5 PC |
943 | DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); |
944 | ||
b12227af | 945 | /* Find which queue we are targeting */ |
e8e49943 AF |
946 | q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); |
947 | ||
7cfd65e4 | 948 | while (bytes_to_copy) { |
06c2fe95 PC |
949 | /* Do nothing if receive is not enabled. */ |
950 | if (!gem_can_receive(nc)) { | |
951 | assert(!first_desc); | |
e9f186e5 PC |
952 | return -1; |
953 | } | |
954 | ||
955 | DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), | |
2bf57f73 | 956 | rx_desc_get_buffer(s->rx_desc[q])); |
e9f186e5 | 957 | |
e9f186e5 | 958 | /* Copy packet data to emulated DMA buffer */ |
e48fdd9d EI |
959 | cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + |
960 | rxbuf_offset, | |
961 | rxbuf_ptr, | |
962 | MIN(bytes_to_copy, rxbufsize)); | |
e9f186e5 | 963 | rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); |
30570698 | 964 | bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); |
3b2c97f9 EI |
965 | |
966 | /* Update the descriptor. */ | |
967 | if (first_desc) { | |
2bf57f73 | 968 | rx_desc_set_sof(s->rx_desc[q]); |
3b2c97f9 EI |
969 | first_desc = false; |
970 | } | |
971 | if (bytes_to_copy == 0) { | |
2bf57f73 AF |
972 | rx_desc_set_eof(s->rx_desc[q]); |
973 | rx_desc_set_length(s->rx_desc[q], size); | |
3b2c97f9 | 974 | } |
2bf57f73 | 975 | rx_desc_set_ownership(s->rx_desc[q]); |
63af1e0c PC |
976 | |
977 | switch (maf) { | |
978 | case GEM_RX_PROMISCUOUS_ACCEPT: | |
979 | break; | |
980 | case GEM_RX_BROADCAST_ACCEPT: | |
2bf57f73 | 981 | rx_desc_set_broadcast(s->rx_desc[q]); |
63af1e0c PC |
982 | break; |
983 | case GEM_RX_UNICAST_HASH_ACCEPT: | |
2bf57f73 | 984 | rx_desc_set_unicast_hash(s->rx_desc[q]); |
63af1e0c PC |
985 | break; |
986 | case GEM_RX_MULTICAST_HASH_ACCEPT: | |
2bf57f73 | 987 | rx_desc_set_multicast_hash(s->rx_desc[q]); |
63af1e0c PC |
988 | break; |
989 | case GEM_RX_REJECT: | |
990 | abort(); | |
991 | default: /* SAR */ | |
2bf57f73 | 992 | rx_desc_set_sar(s->rx_desc[q], maf); |
63af1e0c PC |
993 | } |
994 | ||
3b2c97f9 | 995 | /* Descriptor write-back. */ |
2bf57f73 AF |
996 | cpu_physical_memory_write(s->rx_desc_addr[q], |
997 | (uint8_t *)s->rx_desc[q], | |
e48fdd9d | 998 | sizeof(uint32_t) * gem_get_desc_len(s, true)); |
3b2c97f9 | 999 | |
e9f186e5 | 1000 | /* Next descriptor */ |
2bf57f73 | 1001 | if (rx_desc_get_wrap(s->rx_desc[q])) { |
7cfd65e4 | 1002 | DB_PRINT("wrapping RX descriptor list\n"); |
2bf57f73 | 1003 | s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; |
e9f186e5 | 1004 | } else { |
7cfd65e4 | 1005 | DB_PRINT("incrementing RX descriptor list\n"); |
e48fdd9d | 1006 | s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); |
e9f186e5 | 1007 | } |
67101725 AF |
1008 | |
1009 | gem_get_rx_desc(s, q); | |
e9f186e5 PC |
1010 | } |
1011 | ||
e9f186e5 PC |
1012 | /* Count it */ |
1013 | gem_receive_updatestats(s, buf, size); | |
1014 | ||
e9f186e5 | 1015 | s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; |
ae80a354 | 1016 | s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); |
e9f186e5 PC |
1017 | |
1018 | /* Handle interrupt consequences */ | |
1019 | gem_update_int_status(s); | |
1020 | ||
1021 | return size; | |
1022 | } | |
1023 | ||
1024 | /* | |
1025 | * gem_transmit_updatestats: | |
1026 | * Increment transmit statistics. | |
1027 | */ | |
448f19e2 | 1028 | static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, |
e9f186e5 PC |
1029 | unsigned bytes) |
1030 | { | |
1031 | uint64_t octets; | |
1032 | ||
1033 | /* Total octets (bytes) transmitted */ | |
1034 | octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | | |
1035 | s->regs[GEM_OCTTXHI]; | |
1036 | octets += bytes; | |
1037 | s->regs[GEM_OCTTXLO] = octets >> 32; | |
1038 | s->regs[GEM_OCTTXHI] = octets; | |
1039 | ||
1040 | /* Error-free Frames transmitted */ | |
1041 | s->regs[GEM_TXCNT]++; | |
1042 | ||
1043 | /* Error-free Broadcast Frames counter */ | |
1044 | if (!memcmp(packet, broadcast_addr, 6)) { | |
1045 | s->regs[GEM_TXBCNT]++; | |
1046 | } | |
1047 | ||
1048 | /* Error-free Multicast Frames counter */ | |
1049 | if (packet[0] == 0x01) { | |
1050 | s->regs[GEM_TXMCNT]++; | |
1051 | } | |
1052 | ||
1053 | if (bytes <= 64) { | |
1054 | s->regs[GEM_TX64CNT]++; | |
1055 | } else if (bytes <= 127) { | |
1056 | s->regs[GEM_TX65CNT]++; | |
1057 | } else if (bytes <= 255) { | |
1058 | s->regs[GEM_TX128CNT]++; | |
1059 | } else if (bytes <= 511) { | |
1060 | s->regs[GEM_TX256CNT]++; | |
1061 | } else if (bytes <= 1023) { | |
1062 | s->regs[GEM_TX512CNT]++; | |
1063 | } else if (bytes <= 1518) { | |
1064 | s->regs[GEM_TX1024CNT]++; | |
1065 | } else { | |
1066 | s->regs[GEM_TX1519CNT]++; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * gem_transmit: | |
1072 | * Fish packets out of the descriptor ring and feed them to QEMU | |
1073 | */ | |
448f19e2 | 1074 | static void gem_transmit(CadenceGEMState *s) |
e9f186e5 | 1075 | { |
8568313f | 1076 | uint32_t desc[DESC_MAX_NUM_WORDS]; |
a8170e5e | 1077 | hwaddr packet_desc_addr; |
e9f186e5 PC |
1078 | uint8_t tx_packet[2048]; |
1079 | uint8_t *p; | |
1080 | unsigned total_bytes; | |
2bf57f73 | 1081 | int q = 0; |
e9f186e5 PC |
1082 | |
1083 | /* Do nothing if transmit is not enabled. */ | |
1084 | if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { | |
1085 | return; | |
1086 | } | |
1087 | ||
1088 | DB_PRINT("\n"); | |
1089 | ||
3048ed6a | 1090 | /* The packet we will hand off to QEMU. |
e9f186e5 PC |
1091 | * Packets scattered across multiple descriptors are gathered to this |
1092 | * one contiguous buffer first. | |
1093 | */ | |
1094 | p = tx_packet; | |
1095 | total_bytes = 0; | |
1096 | ||
67101725 | 1097 | for (q = s->num_priority_queues - 1; q >= 0; q--) { |
77524d11 AF |
1098 | /* read current descriptor */ |
1099 | packet_desc_addr = s->tx_desc_addr[q]; | |
d7f05365 | 1100 | |
77524d11 AF |
1101 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); |
1102 | cpu_physical_memory_read(packet_desc_addr, | |
e48fdd9d EI |
1103 | (uint8_t *)desc, |
1104 | sizeof(uint32_t) * gem_get_desc_len(s, false)); | |
77524d11 AF |
1105 | /* Handle all descriptors owned by hardware */ |
1106 | while (tx_desc_get_used(desc) == 0) { | |
e9f186e5 | 1107 | |
77524d11 AF |
1108 | /* Do nothing if transmit is not enabled. */ |
1109 | if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { | |
1110 | return; | |
1111 | } | |
1112 | print_gem_tx_desc(desc, q); | |
6ab57a6b | 1113 | |
77524d11 AF |
1114 | /* The real hardware would eat this (and possibly crash). |
1115 | * For QEMU let's lend a helping hand. | |
e9f186e5 | 1116 | */ |
e48fdd9d | 1117 | if ((tx_desc_get_buffer(s, desc) == 0) || |
77524d11 AF |
1118 | (tx_desc_get_length(desc) == 0)) { |
1119 | DB_PRINT("Invalid TX descriptor @ 0x%x\n", | |
1120 | (unsigned)packet_desc_addr); | |
1121 | break; | |
e9f186e5 | 1122 | } |
e9f186e5 | 1123 | |
77524d11 AF |
1124 | if (tx_desc_get_length(desc) > sizeof(tx_packet) - |
1125 | (p - tx_packet)) { | |
1126 | DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \ | |
1127 | "0x%x\n", (unsigned)packet_desc_addr, | |
1128 | (unsigned)tx_desc_get_length(desc), | |
1129 | sizeof(tx_packet) - (p - tx_packet)); | |
1130 | break; | |
67101725 AF |
1131 | } |
1132 | ||
77524d11 AF |
1133 | /* Gather this fragment of the packet from "dma memory" to our |
1134 | * contig buffer. | |
1135 | */ | |
e48fdd9d | 1136 | cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, |
77524d11 AF |
1137 | tx_desc_get_length(desc)); |
1138 | p += tx_desc_get_length(desc); | |
1139 | total_bytes += tx_desc_get_length(desc); | |
1140 | ||
1141 | /* Last descriptor for this packet; hand the whole thing off */ | |
1142 | if (tx_desc_get_last(desc)) { | |
8568313f | 1143 | uint32_t desc_first[DESC_MAX_NUM_WORDS]; |
77524d11 AF |
1144 | |
1145 | /* Modify the 1st descriptor of this packet to be owned by | |
1146 | * the processor. | |
1147 | */ | |
1148 | cpu_physical_memory_read(s->tx_desc_addr[q], | |
1149 | (uint8_t *)desc_first, | |
1150 | sizeof(desc_first)); | |
1151 | tx_desc_set_used(desc_first); | |
1152 | cpu_physical_memory_write(s->tx_desc_addr[q], | |
1153 | (uint8_t *)desc_first, | |
1154 | sizeof(desc_first)); | |
1155 | /* Advance the hardware current descriptor past this packet */ | |
1156 | if (tx_desc_get_wrap(desc)) { | |
1157 | s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; | |
1158 | } else { | |
e48fdd9d EI |
1159 | s->tx_desc_addr[q] = packet_desc_addr + |
1160 | 4 * gem_get_desc_len(s, false); | |
77524d11 AF |
1161 | } |
1162 | DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); | |
1163 | ||
1164 | s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; | |
1165 | s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); | |
1166 | ||
1167 | /* Update queue interrupt status */ | |
1168 | if (s->num_priority_queues > 1) { | |
1169 | s->regs[GEM_INT_Q1_STATUS + q] |= | |
1170 | GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]); | |
1171 | } | |
1172 | ||
1173 | /* Handle interrupt consequences */ | |
1174 | gem_update_int_status(s); | |
1175 | ||
1176 | /* Is checksum offload enabled? */ | |
1177 | if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { | |
1178 | net_checksum_calculate(tx_packet, total_bytes); | |
1179 | } | |
1180 | ||
1181 | /* Update MAC statistics */ | |
1182 | gem_transmit_updatestats(s, tx_packet, total_bytes); | |
1183 | ||
1184 | /* Send the packet somewhere */ | |
1185 | if (s->phy_loop || (s->regs[GEM_NWCTRL] & | |
1186 | GEM_NWCTRL_LOCALLOOP)) { | |
1187 | gem_receive(qemu_get_queue(s->nic), tx_packet, | |
1188 | total_bytes); | |
1189 | } else { | |
1190 | qemu_send_packet(qemu_get_queue(s->nic), tx_packet, | |
1191 | total_bytes); | |
1192 | } | |
1193 | ||
1194 | /* Prepare for next packet */ | |
1195 | p = tx_packet; | |
1196 | total_bytes = 0; | |
e9f186e5 PC |
1197 | } |
1198 | ||
77524d11 AF |
1199 | /* read next descriptor */ |
1200 | if (tx_desc_get_wrap(desc)) { | |
1201 | tx_desc_set_last(desc); | |
1202 | packet_desc_addr = s->regs[GEM_TXQBASE]; | |
e9f186e5 | 1203 | } else { |
e48fdd9d | 1204 | packet_desc_addr += 4 * gem_get_desc_len(s, false); |
e9f186e5 | 1205 | } |
77524d11 | 1206 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); |
e48fdd9d EI |
1207 | cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, |
1208 | sizeof(uint32_t) * gem_get_desc_len(s, false)); | |
e9f186e5 PC |
1209 | } |
1210 | ||
77524d11 AF |
1211 | if (tx_desc_get_used(desc)) { |
1212 | s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; | |
1213 | s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); | |
1214 | gem_update_int_status(s); | |
e9f186e5 | 1215 | } |
67101725 | 1216 | } |
e9f186e5 PC |
1217 | } |
1218 | ||
448f19e2 | 1219 | static void gem_phy_reset(CadenceGEMState *s) |
e9f186e5 PC |
1220 | { |
1221 | memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); | |
1222 | s->phy_regs[PHY_REG_CONTROL] = 0x1140; | |
1223 | s->phy_regs[PHY_REG_STATUS] = 0x7969; | |
1224 | s->phy_regs[PHY_REG_PHYID1] = 0x0141; | |
1225 | s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; | |
1226 | s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; | |
1227 | s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; | |
1228 | s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; | |
1229 | s->phy_regs[PHY_REG_NEXTP] = 0x2001; | |
1230 | s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; | |
1231 | s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; | |
1232 | s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; | |
1233 | s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; | |
1234 | s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; | |
7777b7a0 | 1235 | s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; |
e9f186e5 PC |
1236 | s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; |
1237 | s->phy_regs[PHY_REG_LED] = 0x4100; | |
1238 | s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; | |
1239 | s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; | |
1240 | ||
1241 | phy_update_link(s); | |
1242 | } | |
1243 | ||
1244 | static void gem_reset(DeviceState *d) | |
1245 | { | |
64eb9301 | 1246 | int i; |
448f19e2 | 1247 | CadenceGEMState *s = CADENCE_GEM(d); |
afb4c51f | 1248 | const uint8_t *a; |
e9f186e5 PC |
1249 | |
1250 | DB_PRINT("\n"); | |
1251 | ||
1252 | /* Set post reset register values */ | |
1253 | memset(&s->regs[0], 0, sizeof(s->regs)); | |
1254 | s->regs[GEM_NWCFG] = 0x00080000; | |
1255 | s->regs[GEM_NWSTATUS] = 0x00000006; | |
1256 | s->regs[GEM_DMACFG] = 0x00020784; | |
1257 | s->regs[GEM_IMR] = 0x07ffffff; | |
1258 | s->regs[GEM_TXPAUSE] = 0x0000ffff; | |
1259 | s->regs[GEM_TXPARTIALSF] = 0x000003ff; | |
1260 | s->regs[GEM_RXPARTIALSF] = 0x000003ff; | |
a5517666 | 1261 | s->regs[GEM_MODID] = s->revision; |
e9f186e5 PC |
1262 | s->regs[GEM_DESCONF] = 0x02500111; |
1263 | s->regs[GEM_DESCONF2] = 0x2ab13fff; | |
b2d43091 | 1264 | s->regs[GEM_DESCONF5] = 0x002f2045; |
e9f186e5 PC |
1265 | s->regs[GEM_DESCONF6] = 0x00000200; |
1266 | ||
afb4c51f SH |
1267 | /* Set MAC address */ |
1268 | a = &s->conf.macaddr.a[0]; | |
1269 | s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); | |
1270 | s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); | |
1271 | ||
64eb9301 PC |
1272 | for (i = 0; i < 4; i++) { |
1273 | s->sar_active[i] = false; | |
1274 | } | |
1275 | ||
e9f186e5 PC |
1276 | gem_phy_reset(s); |
1277 | ||
1278 | gem_update_int_status(s); | |
1279 | } | |
1280 | ||
448f19e2 | 1281 | static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) |
e9f186e5 PC |
1282 | { |
1283 | DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); | |
1284 | return s->phy_regs[reg_num]; | |
1285 | } | |
1286 | ||
448f19e2 | 1287 | static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) |
e9f186e5 PC |
1288 | { |
1289 | DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); | |
1290 | ||
1291 | switch (reg_num) { | |
1292 | case PHY_REG_CONTROL: | |
1293 | if (val & PHY_REG_CONTROL_RST) { | |
1294 | /* Phy reset */ | |
1295 | gem_phy_reset(s); | |
1296 | val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); | |
1297 | s->phy_loop = 0; | |
1298 | } | |
1299 | if (val & PHY_REG_CONTROL_ANEG) { | |
1300 | /* Complete autonegotiation immediately */ | |
1301 | val &= ~PHY_REG_CONTROL_ANEG; | |
1302 | s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; | |
1303 | } | |
1304 | if (val & PHY_REG_CONTROL_LOOP) { | |
1305 | DB_PRINT("PHY placed in loopback\n"); | |
1306 | s->phy_loop = 1; | |
1307 | } else { | |
1308 | s->phy_loop = 0; | |
1309 | } | |
1310 | break; | |
1311 | } | |
1312 | s->phy_regs[reg_num] = val; | |
1313 | } | |
1314 | ||
1315 | /* | |
1316 | * gem_read32: | |
1317 | * Read a GEM register. | |
1318 | */ | |
a8170e5e | 1319 | static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) |
e9f186e5 | 1320 | { |
448f19e2 | 1321 | CadenceGEMState *s; |
e9f186e5 | 1322 | uint32_t retval; |
448f19e2 | 1323 | s = (CadenceGEMState *)opaque; |
e9f186e5 PC |
1324 | |
1325 | offset >>= 2; | |
1326 | retval = s->regs[offset]; | |
1327 | ||
080251a4 | 1328 | DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); |
e9f186e5 PC |
1329 | |
1330 | switch (offset) { | |
1331 | case GEM_ISR: | |
67101725 | 1332 | DB_PRINT("lowering irqs on ISR read\n"); |
596b6f51 | 1333 | /* The interrupts get updated at the end of the function. */ |
e9f186e5 PC |
1334 | break; |
1335 | case GEM_PHYMNTNC: | |
1336 | if (retval & GEM_PHYMNTNC_OP_R) { | |
1337 | uint32_t phy_addr, reg_num; | |
1338 | ||
1339 | phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; | |
55389373 | 1340 | if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { |
e9f186e5 PC |
1341 | reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; |
1342 | retval &= 0xFFFF0000; | |
1343 | retval |= gem_phy_read(s, reg_num); | |
1344 | } else { | |
1345 | retval |= 0xFFFF; /* No device at this address */ | |
1346 | } | |
1347 | } | |
1348 | break; | |
1349 | } | |
1350 | ||
1351 | /* Squash read to clear bits */ | |
1352 | s->regs[offset] &= ~(s->regs_rtc[offset]); | |
1353 | ||
1354 | /* Do not provide write only bits */ | |
1355 | retval &= ~(s->regs_wo[offset]); | |
1356 | ||
1357 | DB_PRINT("0x%08x\n", retval); | |
67101725 | 1358 | gem_update_int_status(s); |
e9f186e5 PC |
1359 | return retval; |
1360 | } | |
1361 | ||
1362 | /* | |
1363 | * gem_write32: | |
1364 | * Write a GEM register. | |
1365 | */ | |
a8170e5e | 1366 | static void gem_write(void *opaque, hwaddr offset, uint64_t val, |
e9f186e5 PC |
1367 | unsigned size) |
1368 | { | |
448f19e2 | 1369 | CadenceGEMState *s = (CadenceGEMState *)opaque; |
e9f186e5 | 1370 | uint32_t readonly; |
67101725 | 1371 | int i; |
e9f186e5 | 1372 | |
080251a4 | 1373 | DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); |
e9f186e5 PC |
1374 | offset >>= 2; |
1375 | ||
1376 | /* Squash bits which are read only in write value */ | |
1377 | val &= ~(s->regs_ro[offset]); | |
e2314fda PC |
1378 | /* Preserve (only) bits which are read only and wtc in register */ |
1379 | readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); | |
e9f186e5 PC |
1380 | |
1381 | /* Copy register write to backing store */ | |
e2314fda PC |
1382 | s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; |
1383 | ||
1384 | /* do w1c */ | |
1385 | s->regs[offset] &= ~(s->regs_w1c[offset] & val); | |
e9f186e5 PC |
1386 | |
1387 | /* Handle register write side effects */ | |
1388 | switch (offset) { | |
1389 | case GEM_NWCTRL: | |
06c2fe95 | 1390 | if (val & GEM_NWCTRL_RXENA) { |
67101725 AF |
1391 | for (i = 0; i < s->num_priority_queues; ++i) { |
1392 | gem_get_rx_desc(s, i); | |
1393 | } | |
06c2fe95 | 1394 | } |
e9f186e5 PC |
1395 | if (val & GEM_NWCTRL_TXSTART) { |
1396 | gem_transmit(s); | |
1397 | } | |
1398 | if (!(val & GEM_NWCTRL_TXENA)) { | |
1399 | /* Reset to start of Q when transmit disabled. */ | |
67101725 AF |
1400 | for (i = 0; i < s->num_priority_queues; i++) { |
1401 | s->tx_desc_addr[i] = s->regs[GEM_TXQBASE]; | |
1402 | } | |
e9f186e5 | 1403 | } |
8202aa53 | 1404 | if (gem_can_receive(qemu_get_queue(s->nic))) { |
e3f9d31c PC |
1405 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
1406 | } | |
e9f186e5 PC |
1407 | break; |
1408 | ||
1409 | case GEM_TXSTATUS: | |
1410 | gem_update_int_status(s); | |
1411 | break; | |
1412 | case GEM_RXQBASE: | |
2bf57f73 | 1413 | s->rx_desc_addr[0] = val; |
e9f186e5 | 1414 | break; |
79b2ac8f | 1415 | case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: |
67101725 AF |
1416 | s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; |
1417 | break; | |
e9f186e5 | 1418 | case GEM_TXQBASE: |
2bf57f73 | 1419 | s->tx_desc_addr[0] = val; |
e9f186e5 | 1420 | break; |
79b2ac8f | 1421 | case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: |
67101725 AF |
1422 | s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; |
1423 | break; | |
e9f186e5 PC |
1424 | case GEM_RXSTATUS: |
1425 | gem_update_int_status(s); | |
1426 | break; | |
1427 | case GEM_IER: | |
1428 | s->regs[GEM_IMR] &= ~val; | |
1429 | gem_update_int_status(s); | |
1430 | break; | |
67101725 AF |
1431 | case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: |
1432 | s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; | |
1433 | gem_update_int_status(s); | |
1434 | break; | |
e9f186e5 PC |
1435 | case GEM_IDR: |
1436 | s->regs[GEM_IMR] |= val; | |
1437 | gem_update_int_status(s); | |
1438 | break; | |
67101725 AF |
1439 | case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: |
1440 | s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; | |
1441 | gem_update_int_status(s); | |
1442 | break; | |
64eb9301 PC |
1443 | case GEM_SPADDR1LO: |
1444 | case GEM_SPADDR2LO: | |
1445 | case GEM_SPADDR3LO: | |
1446 | case GEM_SPADDR4LO: | |
1447 | s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; | |
1448 | break; | |
1449 | case GEM_SPADDR1HI: | |
1450 | case GEM_SPADDR2HI: | |
1451 | case GEM_SPADDR3HI: | |
1452 | case GEM_SPADDR4HI: | |
1453 | s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; | |
1454 | break; | |
e9f186e5 PC |
1455 | case GEM_PHYMNTNC: |
1456 | if (val & GEM_PHYMNTNC_OP_W) { | |
1457 | uint32_t phy_addr, reg_num; | |
1458 | ||
1459 | phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; | |
55389373 | 1460 | if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { |
e9f186e5 PC |
1461 | reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; |
1462 | gem_phy_write(s, reg_num, val); | |
1463 | } | |
1464 | } | |
1465 | break; | |
1466 | } | |
1467 | ||
1468 | DB_PRINT("newval: 0x%08x\n", s->regs[offset]); | |
1469 | } | |
1470 | ||
1471 | static const MemoryRegionOps gem_ops = { | |
1472 | .read = gem_read, | |
1473 | .write = gem_write, | |
1474 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1475 | }; | |
1476 | ||
4e68f7a0 | 1477 | static void gem_set_link(NetClientState *nc) |
e9f186e5 | 1478 | { |
67101725 AF |
1479 | CadenceGEMState *s = qemu_get_nic_opaque(nc); |
1480 | ||
e9f186e5 | 1481 | DB_PRINT("\n"); |
67101725 AF |
1482 | phy_update_link(s); |
1483 | gem_update_int_status(s); | |
e9f186e5 PC |
1484 | } |
1485 | ||
1486 | static NetClientInfo net_gem_info = { | |
f394b2e2 | 1487 | .type = NET_CLIENT_DRIVER_NIC, |
e9f186e5 PC |
1488 | .size = sizeof(NICState), |
1489 | .can_receive = gem_can_receive, | |
1490 | .receive = gem_receive, | |
e9f186e5 PC |
1491 | .link_status_changed = gem_set_link, |
1492 | }; | |
1493 | ||
bcb39a65 | 1494 | static void gem_realize(DeviceState *dev, Error **errp) |
e9f186e5 | 1495 | { |
448f19e2 | 1496 | CadenceGEMState *s = CADENCE_GEM(dev); |
67101725 | 1497 | int i; |
e9f186e5 | 1498 | |
2bf57f73 AF |
1499 | if (s->num_priority_queues == 0 || |
1500 | s->num_priority_queues > MAX_PRIORITY_QUEUES) { | |
1501 | error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, | |
1502 | s->num_priority_queues); | |
1503 | return; | |
e8e49943 AF |
1504 | } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { |
1505 | error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, | |
1506 | s->num_type1_screeners); | |
1507 | return; | |
1508 | } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { | |
1509 | error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, | |
1510 | s->num_type2_screeners); | |
1511 | return; | |
2bf57f73 AF |
1512 | } |
1513 | ||
67101725 AF |
1514 | for (i = 0; i < s->num_priority_queues; ++i) { |
1515 | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); | |
1516 | } | |
bcb39a65 AF |
1517 | |
1518 | qemu_macaddr_default_if_unset(&s->conf.macaddr); | |
1519 | ||
1520 | s->nic = qemu_new_nic(&net_gem_info, &s->conf, | |
1521 | object_get_typename(OBJECT(dev)), dev->id, s); | |
1522 | } | |
1523 | ||
1524 | static void gem_init(Object *obj) | |
1525 | { | |
1526 | CadenceGEMState *s = CADENCE_GEM(obj); | |
1527 | DeviceState *dev = DEVICE(obj); | |
1528 | ||
e9f186e5 PC |
1529 | DB_PRINT("\n"); |
1530 | ||
e9f186e5 | 1531 | gem_init_register_masks(s); |
eedfac6f PB |
1532 | memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, |
1533 | "enet", sizeof(s->regs)); | |
e9f186e5 | 1534 | |
bcb39a65 | 1535 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
e9f186e5 PC |
1536 | } |
1537 | ||
1538 | static const VMStateDescription vmstate_cadence_gem = { | |
1539 | .name = "cadence_gem", | |
e8e49943 AF |
1540 | .version_id = 4, |
1541 | .minimum_version_id = 4, | |
8f1e884b | 1542 | .fields = (VMStateField[]) { |
448f19e2 PC |
1543 | VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), |
1544 | VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), | |
1545 | VMSTATE_UINT8(phy_loop, CadenceGEMState), | |
2bf57f73 AF |
1546 | VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, |
1547 | MAX_PRIORITY_QUEUES), | |
1548 | VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, | |
1549 | MAX_PRIORITY_QUEUES), | |
448f19e2 | 1550 | VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), |
17cf2c76 | 1551 | VMSTATE_END_OF_LIST(), |
e9f186e5 PC |
1552 | } |
1553 | }; | |
1554 | ||
1555 | static Property gem_properties[] = { | |
448f19e2 | 1556 | DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), |
a5517666 AF |
1557 | DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, |
1558 | GEM_MODID_VALUE), | |
2bf57f73 AF |
1559 | DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, |
1560 | num_priority_queues, 1), | |
e8e49943 AF |
1561 | DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, |
1562 | num_type1_screeners, 4), | |
1563 | DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, | |
1564 | num_type2_screeners, 4), | |
e9f186e5 PC |
1565 | DEFINE_PROP_END_OF_LIST(), |
1566 | }; | |
1567 | ||
1568 | static void gem_class_init(ObjectClass *klass, void *data) | |
1569 | { | |
1570 | DeviceClass *dc = DEVICE_CLASS(klass); | |
e9f186e5 | 1571 | |
bcb39a65 | 1572 | dc->realize = gem_realize; |
e9f186e5 PC |
1573 | dc->props = gem_properties; |
1574 | dc->vmsd = &vmstate_cadence_gem; | |
1575 | dc->reset = gem_reset; | |
1576 | } | |
1577 | ||
8c43a6f0 | 1578 | static const TypeInfo gem_info = { |
318643be | 1579 | .name = TYPE_CADENCE_GEM, |
e9f186e5 | 1580 | .parent = TYPE_SYS_BUS_DEVICE, |
448f19e2 | 1581 | .instance_size = sizeof(CadenceGEMState), |
bcb39a65 | 1582 | .instance_init = gem_init, |
318643be | 1583 | .class_init = gem_class_init, |
e9f186e5 PC |
1584 | }; |
1585 | ||
1586 | static void gem_register_types(void) | |
1587 | { | |
1588 | type_register_static(&gem_info); | |
1589 | } | |
1590 | ||
1591 | type_init(gem_register_types) |