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Commit | Line | Data |
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7c23b892 AZ |
1 | /* |
2 | * QEMU e1000 emulation | |
3 | * | |
2758aa52 MT |
4 | * Software developer's manual: |
5 | * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf | |
6 | * | |
7c23b892 AZ |
7 | * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. |
8 | * Copyright (c) 2008 Qumranet | |
9 | * Based on work done by: | |
10 | * Copyright (c) 2007 Dan Aloni | |
11 | * Copyright (c) 2004 Antony T Curtis | |
12 | * | |
13 | * This library is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU Lesser General Public | |
15 | * License as published by the Free Software Foundation; either | |
16 | * version 2 of the License, or (at your option) any later version. | |
17 | * | |
18 | * This library is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
21 | * Lesser General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 24 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
7c23b892 AZ |
25 | */ |
26 | ||
27 | ||
83c9f4ca PB |
28 | #include "hw/hw.h" |
29 | #include "hw/pci/pci.h" | |
1422e32d | 30 | #include "net/net.h" |
7200ac3c | 31 | #include "net/checksum.h" |
83c9f4ca | 32 | #include "hw/loader.h" |
9c17d615 PB |
33 | #include "sysemu/sysemu.h" |
34 | #include "sysemu/dma.h" | |
97410dde | 35 | #include "qemu/iov.h" |
7c23b892 | 36 | |
47b43a1f | 37 | #include "e1000_regs.h" |
7c23b892 | 38 | |
27124888 | 39 | #define E1000_DEBUG |
7c23b892 | 40 | |
27124888 | 41 | #ifdef E1000_DEBUG |
7c23b892 AZ |
42 | enum { |
43 | DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT, | |
44 | DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM, | |
45 | DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR, | |
f9c1cdf4 | 46 | DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET, |
7c23b892 AZ |
47 | }; |
48 | #define DBGBIT(x) (1<<DEBUG_##x) | |
49 | static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL); | |
50 | ||
6c7f4b47 | 51 | #define DBGOUT(what, fmt, ...) do { \ |
7c23b892 | 52 | if (debugflags & DBGBIT(what)) \ |
6c7f4b47 | 53 | fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \ |
7c23b892 AZ |
54 | } while (0) |
55 | #else | |
6c7f4b47 | 56 | #define DBGOUT(what, fmt, ...) do {} while (0) |
7c23b892 AZ |
57 | #endif |
58 | ||
59 | #define IOPORT_SIZE 0x40 | |
e94bbefe | 60 | #define PNPMMIO_SIZE 0x20000 |
78aeb23e | 61 | #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */ |
7c23b892 | 62 | |
b0d9ffcd MC |
63 | /* this is the size past which hardware will drop packets when setting LPE=0 */ |
64 | #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 | |
2c0331f4 MC |
65 | /* this is the size past which hardware will drop packets when setting LPE=1 */ |
66 | #define MAXIMUM_ETHERNET_LPE_SIZE 16384 | |
b0d9ffcd | 67 | |
97410dde VM |
68 | #define MAXIMUM_ETHERNET_HDR_LEN (14+4) |
69 | ||
7c23b892 AZ |
70 | /* |
71 | * HW models: | |
8597f2e1 | 72 | * E1000_DEV_ID_82540EM works with Windows, Linux, and OS X <= 10.8 |
7c23b892 | 73 | * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested |
8597f2e1 | 74 | * E1000_DEV_ID_82545EM_COPPER works with Linux and OS X >= 10.6 |
7c23b892 AZ |
75 | * Others never tested |
76 | */ | |
7c23b892 AZ |
77 | |
78 | typedef struct E1000State_st { | |
b08340d5 AF |
79 | /*< private >*/ |
80 | PCIDevice parent_obj; | |
81 | /*< public >*/ | |
82 | ||
a03e2aec | 83 | NICState *nic; |
fbdaa002 | 84 | NICConf conf; |
ad00a9b9 AK |
85 | MemoryRegion mmio; |
86 | MemoryRegion io; | |
7c23b892 AZ |
87 | |
88 | uint32_t mac_reg[0x8000]; | |
89 | uint16_t phy_reg[0x20]; | |
90 | uint16_t eeprom_data[64]; | |
91 | ||
92 | uint32_t rxbuf_size; | |
93 | uint32_t rxbuf_min_shift; | |
7c23b892 AZ |
94 | struct e1000_tx { |
95 | unsigned char header[256]; | |
8f2e8d1f | 96 | unsigned char vlan_header[4]; |
b10fec9b | 97 | /* Fields vlan and data must not be reordered or separated. */ |
8f2e8d1f | 98 | unsigned char vlan[4]; |
7c23b892 AZ |
99 | unsigned char data[0x10000]; |
100 | uint16_t size; | |
101 | unsigned char sum_needed; | |
8f2e8d1f | 102 | unsigned char vlan_needed; |
7c23b892 AZ |
103 | uint8_t ipcss; |
104 | uint8_t ipcso; | |
105 | uint16_t ipcse; | |
106 | uint8_t tucss; | |
107 | uint8_t tucso; | |
108 | uint16_t tucse; | |
109 | uint8_t hdr_len; | |
110 | uint16_t mss; | |
111 | uint32_t paylen; | |
112 | uint16_t tso_frames; | |
113 | char tse; | |
b6c4f71f BS |
114 | int8_t ip; |
115 | int8_t tcp; | |
1b0009db | 116 | char cptse; // current packet tse bit |
7c23b892 AZ |
117 | } tx; |
118 | ||
119 | struct { | |
120 | uint32_t val_in; // shifted in from guest driver | |
121 | uint16_t bitnum_in; | |
122 | uint16_t bitnum_out; | |
123 | uint16_t reading; | |
124 | uint32_t old_eecd; | |
125 | } eecd_state; | |
b9d03e35 JW |
126 | |
127 | QEMUTimer *autoneg_timer; | |
2af234e6 | 128 | |
e9845f09 VM |
129 | QEMUTimer *mit_timer; /* Mitigation timer. */ |
130 | bool mit_timer_on; /* Mitigation timer is running. */ | |
131 | bool mit_irq_level; /* Tracks interrupt pin level. */ | |
132 | uint32_t mit_ide; /* Tracks E1000_TXD_CMD_IDE bit. */ | |
133 | ||
2af234e6 MT |
134 | /* Compatibility flags for migration to/from qemu 1.3.0 and older */ |
135 | #define E1000_FLAG_AUTONEG_BIT 0 | |
e9845f09 | 136 | #define E1000_FLAG_MIT_BIT 1 |
2af234e6 | 137 | #define E1000_FLAG_AUTONEG (1 << E1000_FLAG_AUTONEG_BIT) |
e9845f09 | 138 | #define E1000_FLAG_MIT (1 << E1000_FLAG_MIT_BIT) |
2af234e6 | 139 | uint32_t compat_flags; |
7c23b892 AZ |
140 | } E1000State; |
141 | ||
8597f2e1 GS |
142 | typedef struct E1000BaseClass { |
143 | PCIDeviceClass parent_class; | |
144 | uint16_t phy_id2; | |
8597f2e1 GS |
145 | } E1000BaseClass; |
146 | ||
147 | #define TYPE_E1000_BASE "e1000-base" | |
567a3c9e PC |
148 | |
149 | #define E1000(obj) \ | |
8597f2e1 GS |
150 | OBJECT_CHECK(E1000State, (obj), TYPE_E1000_BASE) |
151 | ||
152 | #define E1000_DEVICE_CLASS(klass) \ | |
153 | OBJECT_CLASS_CHECK(E1000BaseClass, (klass), TYPE_E1000_BASE) | |
154 | #define E1000_DEVICE_GET_CLASS(obj) \ | |
155 | OBJECT_GET_CLASS(E1000BaseClass, (obj), TYPE_E1000_BASE) | |
567a3c9e | 156 | |
7c23b892 AZ |
157 | #define defreg(x) x = (E1000_##x>>2) |
158 | enum { | |
159 | defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC), | |
160 | defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC), | |
161 | defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC), | |
162 | defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH), | |
163 | defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT), | |
164 | defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH), | |
165 | defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT), | |
166 | defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL), | |
167 | defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC), | |
8f2e8d1f | 168 | defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA), |
e9845f09 VM |
169 | defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV), |
170 | defreg(ITR), | |
7c23b892 AZ |
171 | }; |
172 | ||
71aadd3c JW |
173 | static void |
174 | e1000_link_down(E1000State *s) | |
175 | { | |
176 | s->mac_reg[STATUS] &= ~E1000_STATUS_LU; | |
177 | s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS; | |
6a2acedb | 178 | s->phy_reg[PHY_STATUS] &= ~MII_SR_AUTONEG_COMPLETE; |
6883b591 | 179 | s->phy_reg[PHY_LP_ABILITY] &= ~MII_LPAR_LPACK; |
71aadd3c JW |
180 | } |
181 | ||
182 | static void | |
183 | e1000_link_up(E1000State *s) | |
184 | { | |
185 | s->mac_reg[STATUS] |= E1000_STATUS_LU; | |
186 | s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS; | |
187 | } | |
188 | ||
1195fed9 GS |
189 | static bool |
190 | have_autoneg(E1000State *s) | |
191 | { | |
192 | return (s->compat_flags & E1000_FLAG_AUTONEG) && | |
193 | (s->phy_reg[PHY_CTRL] & MII_CR_AUTO_NEG_EN); | |
194 | } | |
195 | ||
b9d03e35 JW |
196 | static void |
197 | set_phy_ctrl(E1000State *s, int index, uint16_t val) | |
198 | { | |
1195fed9 GS |
199 | /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */ |
200 | s->phy_reg[PHY_CTRL] = val & ~(0x3f | | |
201 | MII_CR_RESET | | |
202 | MII_CR_RESTART_AUTO_NEG); | |
203 | ||
2af234e6 MT |
204 | /* |
205 | * QEMU 1.3 does not support link auto-negotiation emulation, so if we | |
206 | * migrate during auto negotiation, after migration the link will be | |
207 | * down. | |
208 | */ | |
1195fed9 | 209 | if (have_autoneg(s) && (val & MII_CR_RESTART_AUTO_NEG)) { |
b9d03e35 | 210 | e1000_link_down(s); |
b9d03e35 | 211 | DBGOUT(PHY, "Start link auto negotiation\n"); |
1195fed9 GS |
212 | timer_mod(s->autoneg_timer, |
213 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); | |
b9d03e35 JW |
214 | } |
215 | } | |
216 | ||
b9d03e35 JW |
217 | static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = { |
218 | [PHY_CTRL] = set_phy_ctrl, | |
219 | }; | |
220 | ||
221 | enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) }; | |
222 | ||
7c23b892 | 223 | enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W }; |
88b4e9db | 224 | static const char phy_regcap[0x20] = { |
7c23b892 AZ |
225 | [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW, |
226 | [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW, | |
227 | [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW, | |
228 | [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R, | |
229 | [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R, | |
6883b591 GS |
230 | [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R, |
231 | [PHY_AUTONEG_EXP] = PHY_R, | |
7c23b892 AZ |
232 | }; |
233 | ||
8597f2e1 | 234 | /* PHY_ID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */ |
814cd3ac | 235 | static const uint16_t phy_reg_init[] = { |
b9d03e35 JW |
236 | [PHY_CTRL] = 0x1140, |
237 | [PHY_STATUS] = 0x794d, /* link initially up with not completed autoneg */ | |
8597f2e1 | 238 | [PHY_ID1] = 0x141, /* [PHY_ID2] configured per DevId, from e1000_reset() */ |
814cd3ac MT |
239 | [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360, |
240 | [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1, | |
241 | [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00, | |
242 | [M88E1000_PHY_SPEC_STATUS] = 0xac00, | |
243 | }; | |
244 | ||
245 | static const uint32_t mac_reg_init[] = { | |
246 | [PBA] = 0x00100030, | |
247 | [LEDCTL] = 0x602, | |
248 | [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | | |
249 | E1000_CTRL_SPD_1000 | E1000_CTRL_SLU, | |
250 | [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE | | |
251 | E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK | | |
252 | E1000_STATUS_SPEED_1000 | E1000_STATUS_FD | | |
253 | E1000_STATUS_LU, | |
254 | [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN | | |
255 | E1000_MANC_ARP_EN | E1000_MANC_0298_EN | | |
256 | E1000_MANC_RMCP_EN, | |
257 | }; | |
258 | ||
e9845f09 VM |
259 | /* Helper function, *curr == 0 means the value is not set */ |
260 | static inline void | |
261 | mit_update_delay(uint32_t *curr, uint32_t value) | |
262 | { | |
263 | if (value && (*curr == 0 || value < *curr)) { | |
264 | *curr = value; | |
265 | } | |
266 | } | |
267 | ||
7c23b892 AZ |
268 | static void |
269 | set_interrupt_cause(E1000State *s, int index, uint32_t val) | |
270 | { | |
b08340d5 | 271 | PCIDevice *d = PCI_DEVICE(s); |
e9845f09 VM |
272 | uint32_t pending_ints; |
273 | uint32_t mit_delay; | |
b08340d5 | 274 | |
7c23b892 | 275 | s->mac_reg[ICR] = val; |
a52a8841 MT |
276 | |
277 | /* | |
278 | * Make sure ICR and ICS registers have the same value. | |
279 | * The spec says that the ICS register is write-only. However in practice, | |
280 | * on real hardware ICS is readable, and for reads it has the same value as | |
281 | * ICR (except that ICS does not have the clear on read behaviour of ICR). | |
282 | * | |
283 | * The VxWorks PRO/1000 driver uses this behaviour. | |
284 | */ | |
b1332393 | 285 | s->mac_reg[ICS] = val; |
a52a8841 | 286 | |
e9845f09 VM |
287 | pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]); |
288 | if (!s->mit_irq_level && pending_ints) { | |
289 | /* | |
290 | * Here we detect a potential raising edge. We postpone raising the | |
291 | * interrupt line if we are inside the mitigation delay window | |
292 | * (s->mit_timer_on == 1). | |
293 | * We provide a partial implementation of interrupt mitigation, | |
294 | * emulating only RADV, TADV and ITR (lower 16 bits, 1024ns units for | |
295 | * RADV and TADV, 256ns units for ITR). RDTR is only used to enable | |
296 | * RADV; relative timers based on TIDV and RDTR are not implemented. | |
297 | */ | |
298 | if (s->mit_timer_on) { | |
299 | return; | |
300 | } | |
301 | if (s->compat_flags & E1000_FLAG_MIT) { | |
302 | /* Compute the next mitigation delay according to pending | |
303 | * interrupts and the current values of RADV (provided | |
304 | * RDTR!=0), TADV and ITR. | |
305 | * Then rearm the timer. | |
306 | */ | |
307 | mit_delay = 0; | |
308 | if (s->mit_ide && | |
309 | (pending_ints & (E1000_ICR_TXQE | E1000_ICR_TXDW))) { | |
310 | mit_update_delay(&mit_delay, s->mac_reg[TADV] * 4); | |
311 | } | |
312 | if (s->mac_reg[RDTR] && (pending_ints & E1000_ICS_RXT0)) { | |
313 | mit_update_delay(&mit_delay, s->mac_reg[RADV] * 4); | |
314 | } | |
315 | mit_update_delay(&mit_delay, s->mac_reg[ITR]); | |
316 | ||
317 | if (mit_delay) { | |
318 | s->mit_timer_on = 1; | |
319 | timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
320 | mit_delay * 256); | |
321 | } | |
322 | s->mit_ide = 0; | |
323 | } | |
324 | } | |
325 | ||
326 | s->mit_irq_level = (pending_ints != 0); | |
9e64f8a3 | 327 | pci_set_irq(d, s->mit_irq_level); |
e9845f09 VM |
328 | } |
329 | ||
330 | static void | |
331 | e1000_mit_timer(void *opaque) | |
332 | { | |
333 | E1000State *s = opaque; | |
334 | ||
335 | s->mit_timer_on = 0; | |
336 | /* Call set_interrupt_cause to update the irq level (if necessary). */ | |
337 | set_interrupt_cause(s, 0, s->mac_reg[ICR]); | |
7c23b892 AZ |
338 | } |
339 | ||
340 | static void | |
341 | set_ics(E1000State *s, int index, uint32_t val) | |
342 | { | |
343 | DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], | |
344 | s->mac_reg[IMS]); | |
345 | set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); | |
346 | } | |
347 | ||
d52aec95 GS |
348 | static void |
349 | e1000_autoneg_timer(void *opaque) | |
350 | { | |
351 | E1000State *s = opaque; | |
352 | if (!qemu_get_queue(s->nic)->link_down) { | |
353 | e1000_link_up(s); | |
354 | s->phy_reg[PHY_LP_ABILITY] |= MII_LPAR_LPACK; | |
355 | s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE; | |
356 | DBGOUT(PHY, "Auto negotiation is completed\n"); | |
357 | set_ics(s, 0, E1000_ICS_LSC); /* signal link status change to guest */ | |
358 | } | |
359 | } | |
360 | ||
7c23b892 AZ |
361 | static int |
362 | rxbufsize(uint32_t v) | |
363 | { | |
364 | v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 | | |
365 | E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 | | |
366 | E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256; | |
367 | switch (v) { | |
368 | case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384: | |
369 | return 16384; | |
370 | case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192: | |
371 | return 8192; | |
372 | case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096: | |
373 | return 4096; | |
374 | case E1000_RCTL_SZ_1024: | |
375 | return 1024; | |
376 | case E1000_RCTL_SZ_512: | |
377 | return 512; | |
378 | case E1000_RCTL_SZ_256: | |
379 | return 256; | |
380 | } | |
381 | return 2048; | |
382 | } | |
383 | ||
814cd3ac MT |
384 | static void e1000_reset(void *opaque) |
385 | { | |
386 | E1000State *d = opaque; | |
8597f2e1 | 387 | E1000BaseClass *edc = E1000_DEVICE_GET_CLASS(d); |
372254c6 GS |
388 | uint8_t *macaddr = d->conf.macaddr.a; |
389 | int i; | |
814cd3ac | 390 | |
bc72ad67 | 391 | timer_del(d->autoneg_timer); |
e9845f09 VM |
392 | timer_del(d->mit_timer); |
393 | d->mit_timer_on = 0; | |
394 | d->mit_irq_level = 0; | |
395 | d->mit_ide = 0; | |
814cd3ac MT |
396 | memset(d->phy_reg, 0, sizeof d->phy_reg); |
397 | memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init); | |
8597f2e1 | 398 | d->phy_reg[PHY_ID2] = edc->phy_id2; |
814cd3ac MT |
399 | memset(d->mac_reg, 0, sizeof d->mac_reg); |
400 | memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init); | |
401 | d->rxbuf_min_shift = 1; | |
402 | memset(&d->tx, 0, sizeof d->tx); | |
403 | ||
b356f76d | 404 | if (qemu_get_queue(d->nic)->link_down) { |
71aadd3c | 405 | e1000_link_down(d); |
814cd3ac | 406 | } |
372254c6 GS |
407 | |
408 | /* Some guests expect pre-initialized RAH/RAL (AddrValid flag + MACaddr) */ | |
409 | d->mac_reg[RA] = 0; | |
410 | d->mac_reg[RA + 1] = E1000_RAH_AV; | |
411 | for (i = 0; i < 4; i++) { | |
412 | d->mac_reg[RA] |= macaddr[i] << (8 * i); | |
413 | d->mac_reg[RA + 1] |= (i < 2) ? macaddr[i + 4] << (8 * i) : 0; | |
414 | } | |
655d3b63 | 415 | qemu_format_nic_info_str(qemu_get_queue(d->nic), macaddr); |
814cd3ac MT |
416 | } |
417 | ||
cab3c825 KW |
418 | static void |
419 | set_ctrl(E1000State *s, int index, uint32_t val) | |
420 | { | |
421 | /* RST is self clearing */ | |
422 | s->mac_reg[CTRL] = val & ~E1000_CTRL_RST; | |
423 | } | |
424 | ||
7c23b892 AZ |
425 | static void |
426 | set_rx_control(E1000State *s, int index, uint32_t val) | |
427 | { | |
428 | s->mac_reg[RCTL] = val; | |
429 | s->rxbuf_size = rxbufsize(val); | |
430 | s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1; | |
431 | DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT], | |
432 | s->mac_reg[RCTL]); | |
b356f76d | 433 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
7c23b892 AZ |
434 | } |
435 | ||
436 | static void | |
437 | set_mdic(E1000State *s, int index, uint32_t val) | |
438 | { | |
439 | uint32_t data = val & E1000_MDIC_DATA_MASK; | |
440 | uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); | |
441 | ||
442 | if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy # | |
443 | val = s->mac_reg[MDIC] | E1000_MDIC_ERROR; | |
444 | else if (val & E1000_MDIC_OP_READ) { | |
445 | DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr); | |
446 | if (!(phy_regcap[addr] & PHY_R)) { | |
447 | DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr); | |
448 | val |= E1000_MDIC_ERROR; | |
449 | } else | |
450 | val = (val ^ data) | s->phy_reg[addr]; | |
451 | } else if (val & E1000_MDIC_OP_WRITE) { | |
452 | DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data); | |
453 | if (!(phy_regcap[addr] & PHY_W)) { | |
454 | DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr); | |
455 | val |= E1000_MDIC_ERROR; | |
b9d03e35 JW |
456 | } else { |
457 | if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) { | |
458 | phyreg_writeops[addr](s, index, data); | |
1195fed9 GS |
459 | } else { |
460 | s->phy_reg[addr] = data; | |
b9d03e35 | 461 | } |
b9d03e35 | 462 | } |
7c23b892 AZ |
463 | } |
464 | s->mac_reg[MDIC] = val | E1000_MDIC_READY; | |
17fbbb0b JW |
465 | |
466 | if (val & E1000_MDIC_INT_EN) { | |
467 | set_ics(s, 0, E1000_ICR_MDAC); | |
468 | } | |
7c23b892 AZ |
469 | } |
470 | ||
471 | static uint32_t | |
472 | get_eecd(E1000State *s, int index) | |
473 | { | |
474 | uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd; | |
475 | ||
476 | DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n", | |
477 | s->eecd_state.bitnum_out, s->eecd_state.reading); | |
478 | if (!s->eecd_state.reading || | |
479 | ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >> | |
480 | ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) | |
481 | ret |= E1000_EECD_DO; | |
482 | return ret; | |
483 | } | |
484 | ||
485 | static void | |
486 | set_eecd(E1000State *s, int index, uint32_t val) | |
487 | { | |
488 | uint32_t oldval = s->eecd_state.old_eecd; | |
489 | ||
490 | s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS | | |
491 | E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ); | |
9651ac55 IT |
492 | if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do |
493 | return; | |
494 | if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state | |
495 | s->eecd_state.val_in = 0; | |
496 | s->eecd_state.bitnum_in = 0; | |
497 | s->eecd_state.bitnum_out = 0; | |
498 | s->eecd_state.reading = 0; | |
499 | } | |
7c23b892 AZ |
500 | if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge |
501 | return; | |
502 | if (!(E1000_EECD_SK & val)) { // falling edge | |
503 | s->eecd_state.bitnum_out++; | |
504 | return; | |
505 | } | |
7c23b892 AZ |
506 | s->eecd_state.val_in <<= 1; |
507 | if (val & E1000_EECD_DI) | |
508 | s->eecd_state.val_in |= 1; | |
509 | if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) { | |
510 | s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1; | |
511 | s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) == | |
512 | EEPROM_READ_OPCODE_MICROWIRE); | |
513 | } | |
514 | DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n", | |
515 | s->eecd_state.bitnum_in, s->eecd_state.bitnum_out, | |
516 | s->eecd_state.reading); | |
517 | } | |
518 | ||
519 | static uint32_t | |
520 | flash_eerd_read(E1000State *s, int x) | |
521 | { | |
522 | unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START; | |
523 | ||
b1332393 BP |
524 | if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0) |
525 | return (s->mac_reg[EERD]); | |
526 | ||
7c23b892 | 527 | if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG) |
b1332393 BP |
528 | return (E1000_EEPROM_RW_REG_DONE | r); |
529 | ||
530 | return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) | | |
531 | E1000_EEPROM_RW_REG_DONE | r); | |
7c23b892 AZ |
532 | } |
533 | ||
7c23b892 AZ |
534 | static void |
535 | putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse) | |
536 | { | |
c6a6a5e3 AL |
537 | uint32_t sum; |
538 | ||
7c23b892 AZ |
539 | if (cse && cse < n) |
540 | n = cse + 1; | |
c6a6a5e3 AL |
541 | if (sloc < n-1) { |
542 | sum = net_checksum_add(n-css, data+css); | |
d8ee2591 | 543 | stw_be_p(data + sloc, net_checksum_finish(sum)); |
c6a6a5e3 | 544 | } |
7c23b892 AZ |
545 | } |
546 | ||
8f2e8d1f AL |
547 | static inline int |
548 | vlan_enabled(E1000State *s) | |
549 | { | |
550 | return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0); | |
551 | } | |
552 | ||
553 | static inline int | |
554 | vlan_rx_filter_enabled(E1000State *s) | |
555 | { | |
556 | return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0); | |
557 | } | |
558 | ||
559 | static inline int | |
560 | is_vlan_packet(E1000State *s, const uint8_t *buf) | |
561 | { | |
562 | return (be16_to_cpup((uint16_t *)(buf + 12)) == | |
563 | le16_to_cpup((uint16_t *)(s->mac_reg + VET))); | |
564 | } | |
565 | ||
566 | static inline int | |
567 | is_vlan_txd(uint32_t txd_lower) | |
568 | { | |
569 | return ((txd_lower & E1000_TXD_CMD_VLE) != 0); | |
570 | } | |
571 | ||
55e8d1ce MT |
572 | /* FCS aka Ethernet CRC-32. We don't get it from backends and can't |
573 | * fill it in, just pad descriptor length by 4 bytes unless guest | |
a05e8a6e | 574 | * told us to strip it off the packet. */ |
55e8d1ce MT |
575 | static inline int |
576 | fcs_len(E1000State *s) | |
577 | { | |
578 | return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4; | |
579 | } | |
580 | ||
93e37d76 JW |
581 | static void |
582 | e1000_send_packet(E1000State *s, const uint8_t *buf, int size) | |
583 | { | |
b356f76d | 584 | NetClientState *nc = qemu_get_queue(s->nic); |
93e37d76 | 585 | if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) { |
b356f76d | 586 | nc->info->receive(nc, buf, size); |
93e37d76 | 587 | } else { |
b356f76d | 588 | qemu_send_packet(nc, buf, size); |
93e37d76 JW |
589 | } |
590 | } | |
591 | ||
7c23b892 AZ |
592 | static void |
593 | xmit_seg(E1000State *s) | |
594 | { | |
595 | uint16_t len, *sp; | |
596 | unsigned int frames = s->tx.tso_frames, css, sofar, n; | |
597 | struct e1000_tx *tp = &s->tx; | |
598 | ||
1b0009db | 599 | if (tp->tse && tp->cptse) { |
7c23b892 AZ |
600 | css = tp->ipcss; |
601 | DBGOUT(TXSUM, "frames %d size %d ipcss %d\n", | |
602 | frames, tp->size, css); | |
603 | if (tp->ip) { // IPv4 | |
d8ee2591 PM |
604 | stw_be_p(tp->data+css+2, tp->size - css); |
605 | stw_be_p(tp->data+css+4, | |
7c23b892 AZ |
606 | be16_to_cpup((uint16_t *)(tp->data+css+4))+frames); |
607 | } else // IPv6 | |
d8ee2591 | 608 | stw_be_p(tp->data+css+4, tp->size - css); |
7c23b892 AZ |
609 | css = tp->tucss; |
610 | len = tp->size - css; | |
611 | DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len); | |
612 | if (tp->tcp) { | |
613 | sofar = frames * tp->mss; | |
6bd194ab | 614 | stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */ |
7c23b892 AZ |
615 | if (tp->paylen - sofar > tp->mss) |
616 | tp->data[css + 13] &= ~9; // PSH, FIN | |
617 | } else // UDP | |
d8ee2591 | 618 | stw_be_p(tp->data+css+4, len); |
7c23b892 | 619 | if (tp->sum_needed & E1000_TXD_POPTS_TXSM) { |
e685b4eb | 620 | unsigned int phsum; |
7c23b892 AZ |
621 | // add pseudo-header length before checksum calculation |
622 | sp = (uint16_t *)(tp->data + tp->tucso); | |
e685b4eb AW |
623 | phsum = be16_to_cpup(sp) + len; |
624 | phsum = (phsum >> 16) + (phsum & 0xffff); | |
d8ee2591 | 625 | stw_be_p(sp, phsum); |
7c23b892 AZ |
626 | } |
627 | tp->tso_frames++; | |
628 | } | |
629 | ||
630 | if (tp->sum_needed & E1000_TXD_POPTS_TXSM) | |
631 | putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse); | |
632 | if (tp->sum_needed & E1000_TXD_POPTS_IXSM) | |
633 | putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse); | |
8f2e8d1f | 634 | if (tp->vlan_needed) { |
b10fec9b SW |
635 | memmove(tp->vlan, tp->data, 4); |
636 | memmove(tp->data, tp->data + 4, 8); | |
8f2e8d1f | 637 | memcpy(tp->data + 8, tp->vlan_header, 4); |
93e37d76 | 638 | e1000_send_packet(s, tp->vlan, tp->size + 4); |
8f2e8d1f | 639 | } else |
93e37d76 | 640 | e1000_send_packet(s, tp->data, tp->size); |
7c23b892 AZ |
641 | s->mac_reg[TPT]++; |
642 | s->mac_reg[GPTC]++; | |
643 | n = s->mac_reg[TOTL]; | |
644 | if ((s->mac_reg[TOTL] += s->tx.size) < n) | |
645 | s->mac_reg[TOTH]++; | |
646 | } | |
647 | ||
648 | static void | |
649 | process_tx_desc(E1000State *s, struct e1000_tx_desc *dp) | |
650 | { | |
b08340d5 | 651 | PCIDevice *d = PCI_DEVICE(s); |
7c23b892 AZ |
652 | uint32_t txd_lower = le32_to_cpu(dp->lower.data); |
653 | uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); | |
654 | unsigned int split_size = txd_lower & 0xffff, bytes, sz, op; | |
a0ae17a6 | 655 | unsigned int msh = 0xfffff; |
7c23b892 AZ |
656 | uint64_t addr; |
657 | struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; | |
658 | struct e1000_tx *tp = &s->tx; | |
659 | ||
e9845f09 | 660 | s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE); |
7c23b892 AZ |
661 | if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor |
662 | op = le32_to_cpu(xp->cmd_and_length); | |
663 | tp->ipcss = xp->lower_setup.ip_fields.ipcss; | |
664 | tp->ipcso = xp->lower_setup.ip_fields.ipcso; | |
665 | tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse); | |
666 | tp->tucss = xp->upper_setup.tcp_fields.tucss; | |
667 | tp->tucso = xp->upper_setup.tcp_fields.tucso; | |
668 | tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse); | |
669 | tp->paylen = op & 0xfffff; | |
670 | tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len; | |
671 | tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss); | |
672 | tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0; | |
673 | tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0; | |
674 | tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0; | |
675 | tp->tso_frames = 0; | |
676 | if (tp->tucso == 0) { // this is probably wrong | |
677 | DBGOUT(TXSUM, "TCP/UDP: cso 0!\n"); | |
678 | tp->tucso = tp->tucss + (tp->tcp ? 16 : 6); | |
679 | } | |
680 | return; | |
1b0009db AZ |
681 | } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { |
682 | // data descriptor | |
735e77ec SH |
683 | if (tp->size == 0) { |
684 | tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8; | |
685 | } | |
1b0009db | 686 | tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0; |
43ad7e3e | 687 | } else { |
1b0009db AZ |
688 | // legacy descriptor |
689 | tp->cptse = 0; | |
43ad7e3e | 690 | } |
7c23b892 | 691 | |
8f2e8d1f AL |
692 | if (vlan_enabled(s) && is_vlan_txd(txd_lower) && |
693 | (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) { | |
694 | tp->vlan_needed = 1; | |
d8ee2591 | 695 | stw_be_p(tp->vlan_header, |
8f2e8d1f | 696 | le16_to_cpup((uint16_t *)(s->mac_reg + VET))); |
d8ee2591 | 697 | stw_be_p(tp->vlan_header + 2, |
8f2e8d1f AL |
698 | le16_to_cpu(dp->upper.fields.special)); |
699 | } | |
700 | ||
7c23b892 | 701 | addr = le64_to_cpu(dp->buffer_addr); |
1b0009db | 702 | if (tp->tse && tp->cptse) { |
a0ae17a6 | 703 | msh = tp->hdr_len + tp->mss; |
1b0009db AZ |
704 | do { |
705 | bytes = split_size; | |
706 | if (tp->size + bytes > msh) | |
707 | bytes = msh - tp->size; | |
65f82df0 AL |
708 | |
709 | bytes = MIN(sizeof(tp->data) - tp->size, bytes); | |
b08340d5 | 710 | pci_dma_read(d, addr, tp->data + tp->size, bytes); |
a0ae17a6 AJ |
711 | sz = tp->size + bytes; |
712 | if (sz >= tp->hdr_len && tp->size < tp->hdr_len) { | |
713 | memmove(tp->header, tp->data, tp->hdr_len); | |
714 | } | |
1b0009db AZ |
715 | tp->size = sz; |
716 | addr += bytes; | |
717 | if (sz == msh) { | |
718 | xmit_seg(s); | |
a0ae17a6 AJ |
719 | memmove(tp->data, tp->header, tp->hdr_len); |
720 | tp->size = tp->hdr_len; | |
1b0009db AZ |
721 | } |
722 | } while (split_size -= bytes); | |
723 | } else if (!tp->tse && tp->cptse) { | |
724 | // context descriptor TSE is not set, while data descriptor TSE is set | |
362f5fb5 | 725 | DBGOUT(TXERR, "TCP segmentation error\n"); |
1b0009db | 726 | } else { |
65f82df0 | 727 | split_size = MIN(sizeof(tp->data) - tp->size, split_size); |
b08340d5 | 728 | pci_dma_read(d, addr, tp->data + tp->size, split_size); |
1b0009db | 729 | tp->size += split_size; |
7c23b892 | 730 | } |
7c23b892 AZ |
731 | |
732 | if (!(txd_lower & E1000_TXD_CMD_EOP)) | |
733 | return; | |
a0ae17a6 | 734 | if (!(tp->tse && tp->cptse && tp->size < tp->hdr_len)) { |
7c23b892 | 735 | xmit_seg(s); |
a0ae17a6 | 736 | } |
7c23b892 AZ |
737 | tp->tso_frames = 0; |
738 | tp->sum_needed = 0; | |
8f2e8d1f | 739 | tp->vlan_needed = 0; |
7c23b892 | 740 | tp->size = 0; |
1b0009db | 741 | tp->cptse = 0; |
7c23b892 AZ |
742 | } |
743 | ||
744 | static uint32_t | |
62ecbd35 | 745 | txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp) |
7c23b892 | 746 | { |
b08340d5 | 747 | PCIDevice *d = PCI_DEVICE(s); |
7c23b892 AZ |
748 | uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); |
749 | ||
750 | if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS))) | |
751 | return 0; | |
752 | txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) & | |
753 | ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU); | |
754 | dp->upper.data = cpu_to_le32(txd_upper); | |
b08340d5 | 755 | pci_dma_write(d, base + ((char *)&dp->upper - (char *)dp), |
00c3a05b | 756 | &dp->upper, sizeof(dp->upper)); |
7c23b892 AZ |
757 | return E1000_ICR_TXDW; |
758 | } | |
759 | ||
d17161f6 KW |
760 | static uint64_t tx_desc_base(E1000State *s) |
761 | { | |
762 | uint64_t bah = s->mac_reg[TDBAH]; | |
763 | uint64_t bal = s->mac_reg[TDBAL] & ~0xf; | |
764 | ||
765 | return (bah << 32) + bal; | |
766 | } | |
767 | ||
7c23b892 AZ |
768 | static void |
769 | start_xmit(E1000State *s) | |
770 | { | |
b08340d5 | 771 | PCIDevice *d = PCI_DEVICE(s); |
62ecbd35 | 772 | dma_addr_t base; |
7c23b892 AZ |
773 | struct e1000_tx_desc desc; |
774 | uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; | |
775 | ||
776 | if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) { | |
777 | DBGOUT(TX, "tx disabled\n"); | |
778 | return; | |
779 | } | |
780 | ||
781 | while (s->mac_reg[TDH] != s->mac_reg[TDT]) { | |
d17161f6 | 782 | base = tx_desc_base(s) + |
7c23b892 | 783 | sizeof(struct e1000_tx_desc) * s->mac_reg[TDH]; |
b08340d5 | 784 | pci_dma_read(d, base, &desc, sizeof(desc)); |
7c23b892 AZ |
785 | |
786 | DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH], | |
6106075b | 787 | (void *)(intptr_t)desc.buffer_addr, desc.lower.data, |
7c23b892 AZ |
788 | desc.upper.data); |
789 | ||
790 | process_tx_desc(s, &desc); | |
62ecbd35 | 791 | cause |= txdesc_writeback(s, base, &desc); |
7c23b892 AZ |
792 | |
793 | if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN]) | |
794 | s->mac_reg[TDH] = 0; | |
795 | /* | |
796 | * the following could happen only if guest sw assigns | |
797 | * bogus values to TDT/TDLEN. | |
798 | * there's nothing too intelligent we could do about this. | |
799 | */ | |
800 | if (s->mac_reg[TDH] == tdh_start) { | |
801 | DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n", | |
802 | tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]); | |
803 | break; | |
804 | } | |
805 | } | |
806 | set_ics(s, 0, cause); | |
807 | } | |
808 | ||
809 | static int | |
810 | receive_filter(E1000State *s, const uint8_t *buf, int size) | |
811 | { | |
af2960f9 BS |
812 | static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; |
813 | static const int mta_shift[] = {4, 3, 2, 0}; | |
7c23b892 AZ |
814 | uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp; |
815 | ||
8f2e8d1f AL |
816 | if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) { |
817 | uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14)); | |
818 | uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) + | |
819 | ((vid >> 5) & 0x7f)); | |
820 | if ((vfta & (1 << (vid & 0x1f))) == 0) | |
821 | return 0; | |
822 | } | |
823 | ||
7c23b892 AZ |
824 | if (rctl & E1000_RCTL_UPE) // promiscuous |
825 | return 1; | |
826 | ||
827 | if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast | |
828 | return 1; | |
829 | ||
830 | if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast)) | |
831 | return 1; | |
832 | ||
833 | for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) { | |
834 | if (!(rp[1] & E1000_RAH_AV)) | |
835 | continue; | |
836 | ra[0] = cpu_to_le32(rp[0]); | |
837 | ra[1] = cpu_to_le32(rp[1]); | |
838 | if (!memcmp(buf, (uint8_t *)ra, 6)) { | |
839 | DBGOUT(RXFILTER, | |
840 | "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n", | |
841 | (int)(rp - s->mac_reg - RA)/2, | |
842 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); | |
843 | return 1; | |
844 | } | |
845 | } | |
846 | DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n", | |
847 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); | |
848 | ||
849 | f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; | |
850 | f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff; | |
851 | if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f))) | |
852 | return 1; | |
853 | DBGOUT(RXFILTER, | |
854 | "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n", | |
855 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], | |
856 | (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5, | |
857 | s->mac_reg[MTA + (f >> 5)]); | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
99ed7e30 | 862 | static void |
4e68f7a0 | 863 | e1000_set_link_status(NetClientState *nc) |
99ed7e30 | 864 | { |
cc1f0f45 | 865 | E1000State *s = qemu_get_nic_opaque(nc); |
99ed7e30 AL |
866 | uint32_t old_status = s->mac_reg[STATUS]; |
867 | ||
d4044c2a | 868 | if (nc->link_down) { |
71aadd3c | 869 | e1000_link_down(s); |
d4044c2a | 870 | } else { |
d7a41552 | 871 | if (have_autoneg(s) && |
6a2acedb GS |
872 | !(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { |
873 | /* emulate auto-negotiation if supported */ | |
874 | timer_mod(s->autoneg_timer, | |
875 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); | |
876 | } else { | |
877 | e1000_link_up(s); | |
878 | } | |
d4044c2a | 879 | } |
99ed7e30 AL |
880 | |
881 | if (s->mac_reg[STATUS] != old_status) | |
882 | set_ics(s, 0, E1000_ICR_LSC); | |
883 | } | |
884 | ||
322fd48a MT |
885 | static bool e1000_has_rxbufs(E1000State *s, size_t total_size) |
886 | { | |
887 | int bufs; | |
888 | /* Fast-path short packets */ | |
889 | if (total_size <= s->rxbuf_size) { | |
e5b8b0d4 | 890 | return s->mac_reg[RDH] != s->mac_reg[RDT]; |
322fd48a MT |
891 | } |
892 | if (s->mac_reg[RDH] < s->mac_reg[RDT]) { | |
893 | bufs = s->mac_reg[RDT] - s->mac_reg[RDH]; | |
e5b8b0d4 | 894 | } else if (s->mac_reg[RDH] > s->mac_reg[RDT]) { |
322fd48a MT |
895 | bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) + |
896 | s->mac_reg[RDT] - s->mac_reg[RDH]; | |
897 | } else { | |
898 | return false; | |
899 | } | |
900 | return total_size <= bufs * s->rxbuf_size; | |
901 | } | |
902 | ||
6cdfab28 | 903 | static int |
4e68f7a0 | 904 | e1000_can_receive(NetClientState *nc) |
6cdfab28 | 905 | { |
cc1f0f45 | 906 | E1000State *s = qemu_get_nic_opaque(nc); |
6cdfab28 | 907 | |
ddcb73b7 MT |
908 | return (s->mac_reg[STATUS] & E1000_STATUS_LU) && |
909 | (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1); | |
6cdfab28 MT |
910 | } |
911 | ||
d17161f6 KW |
912 | static uint64_t rx_desc_base(E1000State *s) |
913 | { | |
914 | uint64_t bah = s->mac_reg[RDBAH]; | |
915 | uint64_t bal = s->mac_reg[RDBAL] & ~0xf; | |
916 | ||
917 | return (bah << 32) + bal; | |
918 | } | |
919 | ||
4f1c942b | 920 | static ssize_t |
97410dde | 921 | e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt) |
7c23b892 | 922 | { |
cc1f0f45 | 923 | E1000State *s = qemu_get_nic_opaque(nc); |
b08340d5 | 924 | PCIDevice *d = PCI_DEVICE(s); |
7c23b892 | 925 | struct e1000_rx_desc desc; |
62ecbd35 | 926 | dma_addr_t base; |
7c23b892 AZ |
927 | unsigned int n, rdt; |
928 | uint32_t rdh_start; | |
8f2e8d1f | 929 | uint16_t vlan_special = 0; |
97410dde | 930 | uint8_t vlan_status = 0; |
78aeb23e | 931 | uint8_t min_buf[MIN_BUF_SIZE]; |
97410dde VM |
932 | struct iovec min_iov; |
933 | uint8_t *filter_buf = iov->iov_base; | |
934 | size_t size = iov_size(iov, iovcnt); | |
935 | size_t iov_ofs = 0; | |
b19487e2 MT |
936 | size_t desc_offset; |
937 | size_t desc_size; | |
938 | size_t total_size; | |
7c23b892 | 939 | |
ddcb73b7 MT |
940 | if (!(s->mac_reg[STATUS] & E1000_STATUS_LU)) { |
941 | return -1; | |
942 | } | |
943 | ||
944 | if (!(s->mac_reg[RCTL] & E1000_RCTL_EN)) { | |
4f1c942b | 945 | return -1; |
ddcb73b7 | 946 | } |
7c23b892 | 947 | |
78aeb23e SH |
948 | /* Pad to minimum Ethernet frame length */ |
949 | if (size < sizeof(min_buf)) { | |
97410dde | 950 | iov_to_buf(iov, iovcnt, 0, min_buf, size); |
78aeb23e | 951 | memset(&min_buf[size], 0, sizeof(min_buf) - size); |
97410dde VM |
952 | min_iov.iov_base = filter_buf = min_buf; |
953 | min_iov.iov_len = size = sizeof(min_buf); | |
954 | iovcnt = 1; | |
955 | iov = &min_iov; | |
956 | } else if (iov->iov_len < MAXIMUM_ETHERNET_HDR_LEN) { | |
957 | /* This is very unlikely, but may happen. */ | |
958 | iov_to_buf(iov, iovcnt, 0, min_buf, MAXIMUM_ETHERNET_HDR_LEN); | |
959 | filter_buf = min_buf; | |
78aeb23e SH |
960 | } |
961 | ||
b0d9ffcd | 962 | /* Discard oversized packets if !LPE and !SBP. */ |
2c0331f4 MC |
963 | if ((size > MAXIMUM_ETHERNET_LPE_SIZE || |
964 | (size > MAXIMUM_ETHERNET_VLAN_SIZE | |
965 | && !(s->mac_reg[RCTL] & E1000_RCTL_LPE))) | |
b0d9ffcd MC |
966 | && !(s->mac_reg[RCTL] & E1000_RCTL_SBP)) { |
967 | return size; | |
968 | } | |
969 | ||
97410dde | 970 | if (!receive_filter(s, filter_buf, size)) { |
4f1c942b | 971 | return size; |
97410dde | 972 | } |
7c23b892 | 973 | |
97410dde VM |
974 | if (vlan_enabled(s) && is_vlan_packet(s, filter_buf)) { |
975 | vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(filter_buf | |
976 | + 14))); | |
977 | iov_ofs = 4; | |
978 | if (filter_buf == iov->iov_base) { | |
979 | memmove(filter_buf + 4, filter_buf, 12); | |
980 | } else { | |
981 | iov_from_buf(iov, iovcnt, 4, filter_buf, 12); | |
982 | while (iov->iov_len <= iov_ofs) { | |
983 | iov_ofs -= iov->iov_len; | |
984 | iov++; | |
985 | } | |
986 | } | |
8f2e8d1f | 987 | vlan_status = E1000_RXD_STAT_VP; |
8f2e8d1f AL |
988 | size -= 4; |
989 | } | |
990 | ||
7c23b892 | 991 | rdh_start = s->mac_reg[RDH]; |
b19487e2 MT |
992 | desc_offset = 0; |
993 | total_size = size + fcs_len(s); | |
322fd48a MT |
994 | if (!e1000_has_rxbufs(s, total_size)) { |
995 | set_ics(s, 0, E1000_ICS_RXO); | |
996 | return -1; | |
997 | } | |
7c23b892 | 998 | do { |
b19487e2 MT |
999 | desc_size = total_size - desc_offset; |
1000 | if (desc_size > s->rxbuf_size) { | |
1001 | desc_size = s->rxbuf_size; | |
1002 | } | |
d17161f6 | 1003 | base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH]; |
b08340d5 | 1004 | pci_dma_read(d, base, &desc, sizeof(desc)); |
8f2e8d1f AL |
1005 | desc.special = vlan_special; |
1006 | desc.status |= (vlan_status | E1000_RXD_STAT_DD); | |
7c23b892 | 1007 | if (desc.buffer_addr) { |
b19487e2 | 1008 | if (desc_offset < size) { |
97410dde VM |
1009 | size_t iov_copy; |
1010 | hwaddr ba = le64_to_cpu(desc.buffer_addr); | |
b19487e2 MT |
1011 | size_t copy_size = size - desc_offset; |
1012 | if (copy_size > s->rxbuf_size) { | |
1013 | copy_size = s->rxbuf_size; | |
1014 | } | |
97410dde VM |
1015 | do { |
1016 | iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); | |
1017 | pci_dma_write(d, ba, iov->iov_base + iov_ofs, iov_copy); | |
1018 | copy_size -= iov_copy; | |
1019 | ba += iov_copy; | |
1020 | iov_ofs += iov_copy; | |
1021 | if (iov_ofs == iov->iov_len) { | |
1022 | iov++; | |
1023 | iov_ofs = 0; | |
1024 | } | |
1025 | } while (copy_size); | |
b19487e2 MT |
1026 | } |
1027 | desc_offset += desc_size; | |
ee912ccf | 1028 | desc.length = cpu_to_le16(desc_size); |
b19487e2 | 1029 | if (desc_offset >= total_size) { |
b19487e2 MT |
1030 | desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM; |
1031 | } else { | |
ee912ccf MT |
1032 | /* Guest zeroing out status is not a hardware requirement. |
1033 | Clear EOP in case guest didn't do it. */ | |
1034 | desc.status &= ~E1000_RXD_STAT_EOP; | |
b19487e2 | 1035 | } |
43ad7e3e | 1036 | } else { // as per intel docs; skip descriptors with null buf addr |
7c23b892 | 1037 | DBGOUT(RX, "Null RX descriptor!!\n"); |
43ad7e3e | 1038 | } |
b08340d5 | 1039 | pci_dma_write(d, base, &desc, sizeof(desc)); |
7c23b892 AZ |
1040 | |
1041 | if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) | |
1042 | s->mac_reg[RDH] = 0; | |
7c23b892 AZ |
1043 | /* see comment in start_xmit; same here */ |
1044 | if (s->mac_reg[RDH] == rdh_start) { | |
1045 | DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n", | |
1046 | rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); | |
1047 | set_ics(s, 0, E1000_ICS_RXO); | |
4f1c942b | 1048 | return -1; |
7c23b892 | 1049 | } |
b19487e2 | 1050 | } while (desc_offset < total_size); |
7c23b892 AZ |
1051 | |
1052 | s->mac_reg[GPRC]++; | |
1053 | s->mac_reg[TPR]++; | |
a05e8a6e MT |
1054 | /* TOR - Total Octets Received: |
1055 | * This register includes bytes received in a packet from the <Destination | |
1056 | * Address> field through the <CRC> field, inclusively. | |
1057 | */ | |
1058 | n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4; | |
1059 | if (n < s->mac_reg[TORL]) | |
7c23b892 | 1060 | s->mac_reg[TORH]++; |
a05e8a6e | 1061 | s->mac_reg[TORL] = n; |
7c23b892 AZ |
1062 | |
1063 | n = E1000_ICS_RXT0; | |
1064 | if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH]) | |
1065 | rdt += s->mac_reg[RDLEN] / sizeof(desc); | |
bf16cc8f AL |
1066 | if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >> |
1067 | s->rxbuf_min_shift) | |
7c23b892 AZ |
1068 | n |= E1000_ICS_RXDMT0; |
1069 | ||
1070 | set_ics(s, 0, n); | |
4f1c942b MM |
1071 | |
1072 | return size; | |
7c23b892 AZ |
1073 | } |
1074 | ||
97410dde VM |
1075 | static ssize_t |
1076 | e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size) | |
1077 | { | |
1078 | const struct iovec iov = { | |
1079 | .iov_base = (uint8_t *)buf, | |
1080 | .iov_len = size | |
1081 | }; | |
1082 | ||
1083 | return e1000_receive_iov(nc, &iov, 1); | |
1084 | } | |
1085 | ||
7c23b892 AZ |
1086 | static uint32_t |
1087 | mac_readreg(E1000State *s, int index) | |
1088 | { | |
1089 | return s->mac_reg[index]; | |
1090 | } | |
1091 | ||
1092 | static uint32_t | |
1093 | mac_icr_read(E1000State *s, int index) | |
1094 | { | |
1095 | uint32_t ret = s->mac_reg[ICR]; | |
1096 | ||
1097 | DBGOUT(INTERRUPT, "ICR read: %x\n", ret); | |
1098 | set_interrupt_cause(s, 0, 0); | |
1099 | return ret; | |
1100 | } | |
1101 | ||
1102 | static uint32_t | |
1103 | mac_read_clr4(E1000State *s, int index) | |
1104 | { | |
1105 | uint32_t ret = s->mac_reg[index]; | |
1106 | ||
1107 | s->mac_reg[index] = 0; | |
1108 | return ret; | |
1109 | } | |
1110 | ||
1111 | static uint32_t | |
1112 | mac_read_clr8(E1000State *s, int index) | |
1113 | { | |
1114 | uint32_t ret = s->mac_reg[index]; | |
1115 | ||
1116 | s->mac_reg[index] = 0; | |
1117 | s->mac_reg[index-1] = 0; | |
1118 | return ret; | |
1119 | } | |
1120 | ||
1121 | static void | |
1122 | mac_writereg(E1000State *s, int index, uint32_t val) | |
1123 | { | |
7c36507c AK |
1124 | uint32_t macaddr[2]; |
1125 | ||
7c23b892 | 1126 | s->mac_reg[index] = val; |
7c36507c | 1127 | |
90d131fb | 1128 | if (index == RA + 1) { |
7c36507c AK |
1129 | macaddr[0] = cpu_to_le32(s->mac_reg[RA]); |
1130 | macaddr[1] = cpu_to_le32(s->mac_reg[RA + 1]); | |
1131 | qemu_format_nic_info_str(qemu_get_queue(s->nic), (uint8_t *)macaddr); | |
1132 | } | |
7c23b892 AZ |
1133 | } |
1134 | ||
1135 | static void | |
1136 | set_rdt(E1000State *s, int index, uint32_t val) | |
1137 | { | |
7c23b892 | 1138 | s->mac_reg[index] = val & 0xffff; |
e8b4c680 | 1139 | if (e1000_has_rxbufs(s, 1)) { |
b356f76d | 1140 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
e8b4c680 | 1141 | } |
7c23b892 AZ |
1142 | } |
1143 | ||
1144 | static void | |
1145 | set_16bit(E1000State *s, int index, uint32_t val) | |
1146 | { | |
1147 | s->mac_reg[index] = val & 0xffff; | |
1148 | } | |
1149 | ||
1150 | static void | |
1151 | set_dlen(E1000State *s, int index, uint32_t val) | |
1152 | { | |
1153 | s->mac_reg[index] = val & 0xfff80; | |
1154 | } | |
1155 | ||
1156 | static void | |
1157 | set_tctl(E1000State *s, int index, uint32_t val) | |
1158 | { | |
1159 | s->mac_reg[index] = val; | |
1160 | s->mac_reg[TDT] &= 0xffff; | |
1161 | start_xmit(s); | |
1162 | } | |
1163 | ||
1164 | static void | |
1165 | set_icr(E1000State *s, int index, uint32_t val) | |
1166 | { | |
1167 | DBGOUT(INTERRUPT, "set_icr %x\n", val); | |
1168 | set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); | |
1169 | } | |
1170 | ||
1171 | static void | |
1172 | set_imc(E1000State *s, int index, uint32_t val) | |
1173 | { | |
1174 | s->mac_reg[IMS] &= ~val; | |
1175 | set_ics(s, 0, 0); | |
1176 | } | |
1177 | ||
1178 | static void | |
1179 | set_ims(E1000State *s, int index, uint32_t val) | |
1180 | { | |
1181 | s->mac_reg[IMS] |= val; | |
1182 | set_ics(s, 0, 0); | |
1183 | } | |
1184 | ||
1185 | #define getreg(x) [x] = mac_readreg | |
1186 | static uint32_t (*macreg_readops[])(E1000State *, int) = { | |
1187 | getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL), | |
1188 | getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL), | |
1189 | getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS), | |
1190 | getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL), | |
b1332393 | 1191 | getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS), |
a00b2335 | 1192 | getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL), |
e9845f09 VM |
1193 | getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV), |
1194 | getreg(TADV), getreg(ITR), | |
7c23b892 AZ |
1195 | |
1196 | [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4, | |
1197 | [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4, | |
1198 | [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read, | |
1199 | [CRCERRS ... MPC] = &mac_readreg, | |
1200 | [RA ... RA+31] = &mac_readreg, | |
1201 | [MTA ... MTA+127] = &mac_readreg, | |
8f2e8d1f | 1202 | [VFTA ... VFTA+127] = &mac_readreg, |
7c23b892 | 1203 | }; |
b1503cda | 1204 | enum { NREADOPS = ARRAY_SIZE(macreg_readops) }; |
7c23b892 AZ |
1205 | |
1206 | #define putreg(x) [x] = mac_writereg | |
1207 | static void (*macreg_writeops[])(E1000State *, int, uint32_t) = { | |
1208 | putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), | |
1209 | putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), | |
cab3c825 | 1210 | putreg(RDBAL), putreg(LEDCTL), putreg(VET), |
7c23b892 AZ |
1211 | [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl, |
1212 | [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics, | |
1213 | [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt, | |
1214 | [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr, | |
cab3c825 | 1215 | [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl, |
e9845f09 VM |
1216 | [RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit, |
1217 | [ITR] = set_16bit, | |
7c23b892 AZ |
1218 | [RA ... RA+31] = &mac_writereg, |
1219 | [MTA ... MTA+127] = &mac_writereg, | |
8f2e8d1f | 1220 | [VFTA ... VFTA+127] = &mac_writereg, |
7c23b892 | 1221 | }; |
b9d03e35 | 1222 | |
b1503cda | 1223 | enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) }; |
7c23b892 AZ |
1224 | |
1225 | static void | |
a8170e5e | 1226 | e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val, |
ad00a9b9 | 1227 | unsigned size) |
7c23b892 AZ |
1228 | { |
1229 | E1000State *s = opaque; | |
8da3ff18 | 1230 | unsigned int index = (addr & 0x1ffff) >> 2; |
7c23b892 | 1231 | |
43ad7e3e | 1232 | if (index < NWRITEOPS && macreg_writeops[index]) { |
6b59fc74 | 1233 | macreg_writeops[index](s, index, val); |
43ad7e3e | 1234 | } else if (index < NREADOPS && macreg_readops[index]) { |
ad00a9b9 | 1235 | DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val); |
43ad7e3e | 1236 | } else { |
ad00a9b9 | 1237 | DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n", |
7c23b892 | 1238 | index<<2, val); |
43ad7e3e | 1239 | } |
7c23b892 AZ |
1240 | } |
1241 | ||
ad00a9b9 | 1242 | static uint64_t |
a8170e5e | 1243 | e1000_mmio_read(void *opaque, hwaddr addr, unsigned size) |
7c23b892 AZ |
1244 | { |
1245 | E1000State *s = opaque; | |
8da3ff18 | 1246 | unsigned int index = (addr & 0x1ffff) >> 2; |
7c23b892 AZ |
1247 | |
1248 | if (index < NREADOPS && macreg_readops[index]) | |
6b59fc74 | 1249 | { |
32600a30 | 1250 | return macreg_readops[index](s, index); |
6b59fc74 | 1251 | } |
7c23b892 AZ |
1252 | DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); |
1253 | return 0; | |
1254 | } | |
1255 | ||
ad00a9b9 AK |
1256 | static const MemoryRegionOps e1000_mmio_ops = { |
1257 | .read = e1000_mmio_read, | |
1258 | .write = e1000_mmio_write, | |
1259 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1260 | .impl = { | |
1261 | .min_access_size = 4, | |
1262 | .max_access_size = 4, | |
1263 | }, | |
1264 | }; | |
1265 | ||
a8170e5e | 1266 | static uint64_t e1000_io_read(void *opaque, hwaddr addr, |
ad00a9b9 | 1267 | unsigned size) |
7c23b892 | 1268 | { |
ad00a9b9 AK |
1269 | E1000State *s = opaque; |
1270 | ||
1271 | (void)s; | |
1272 | return 0; | |
7c23b892 AZ |
1273 | } |
1274 | ||
a8170e5e | 1275 | static void e1000_io_write(void *opaque, hwaddr addr, |
ad00a9b9 | 1276 | uint64_t val, unsigned size) |
7c23b892 | 1277 | { |
ad00a9b9 AK |
1278 | E1000State *s = opaque; |
1279 | ||
1280 | (void)s; | |
7c23b892 AZ |
1281 | } |
1282 | ||
ad00a9b9 AK |
1283 | static const MemoryRegionOps e1000_io_ops = { |
1284 | .read = e1000_io_read, | |
1285 | .write = e1000_io_write, | |
1286 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1287 | }; | |
1288 | ||
e482dc3e | 1289 | static bool is_version_1(void *opaque, int version_id) |
7c23b892 | 1290 | { |
e482dc3e | 1291 | return version_id == 1; |
7c23b892 AZ |
1292 | } |
1293 | ||
ddcb73b7 MT |
1294 | static void e1000_pre_save(void *opaque) |
1295 | { | |
1296 | E1000State *s = opaque; | |
1297 | NetClientState *nc = qemu_get_queue(s->nic); | |
2af234e6 | 1298 | |
e9845f09 VM |
1299 | /* If the mitigation timer is active, emulate a timeout now. */ |
1300 | if (s->mit_timer_on) { | |
1301 | e1000_mit_timer(s); | |
1302 | } | |
1303 | ||
ddcb73b7 | 1304 | /* |
6a2acedb GS |
1305 | * If link is down and auto-negotiation is supported and ongoing, |
1306 | * complete auto-negotiation immediately. This allows us to look | |
1307 | * at MII_SR_AUTONEG_COMPLETE to infer link status on load. | |
ddcb73b7 | 1308 | */ |
d7a41552 GS |
1309 | if (nc->link_down && have_autoneg(s)) { |
1310 | s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE; | |
ddcb73b7 MT |
1311 | } |
1312 | } | |
1313 | ||
e4b82364 AK |
1314 | static int e1000_post_load(void *opaque, int version_id) |
1315 | { | |
1316 | E1000State *s = opaque; | |
b356f76d | 1317 | NetClientState *nc = qemu_get_queue(s->nic); |
e4b82364 | 1318 | |
e9845f09 VM |
1319 | if (!(s->compat_flags & E1000_FLAG_MIT)) { |
1320 | s->mac_reg[ITR] = s->mac_reg[RDTR] = s->mac_reg[RADV] = | |
1321 | s->mac_reg[TADV] = 0; | |
1322 | s->mit_irq_level = false; | |
1323 | } | |
1324 | s->mit_ide = 0; | |
1325 | s->mit_timer_on = false; | |
1326 | ||
e4b82364 | 1327 | /* nc.link_down can't be migrated, so infer link_down according |
ddcb73b7 MT |
1328 | * to link status bit in mac_reg[STATUS]. |
1329 | * Alternatively, restart link negotiation if it was in progress. */ | |
b356f76d | 1330 | nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0; |
2af234e6 | 1331 | |
d7a41552 | 1332 | if (have_autoneg(s) && |
ddcb73b7 MT |
1333 | !(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { |
1334 | nc->link_down = false; | |
d7a41552 GS |
1335 | timer_mod(s->autoneg_timer, |
1336 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); | |
ddcb73b7 | 1337 | } |
e4b82364 AK |
1338 | |
1339 | return 0; | |
1340 | } | |
1341 | ||
e9845f09 VM |
1342 | static bool e1000_mit_state_needed(void *opaque) |
1343 | { | |
1344 | E1000State *s = opaque; | |
1345 | ||
1346 | return s->compat_flags & E1000_FLAG_MIT; | |
1347 | } | |
1348 | ||
1349 | static const VMStateDescription vmstate_e1000_mit_state = { | |
1350 | .name = "e1000/mit_state", | |
1351 | .version_id = 1, | |
1352 | .minimum_version_id = 1, | |
d49805ae | 1353 | .fields = (VMStateField[]) { |
e9845f09 VM |
1354 | VMSTATE_UINT32(mac_reg[RDTR], E1000State), |
1355 | VMSTATE_UINT32(mac_reg[RADV], E1000State), | |
1356 | VMSTATE_UINT32(mac_reg[TADV], E1000State), | |
1357 | VMSTATE_UINT32(mac_reg[ITR], E1000State), | |
1358 | VMSTATE_BOOL(mit_irq_level, E1000State), | |
1359 | VMSTATE_END_OF_LIST() | |
1360 | } | |
1361 | }; | |
1362 | ||
e482dc3e JQ |
1363 | static const VMStateDescription vmstate_e1000 = { |
1364 | .name = "e1000", | |
1365 | .version_id = 2, | |
1366 | .minimum_version_id = 1, | |
ddcb73b7 | 1367 | .pre_save = e1000_pre_save, |
e4b82364 | 1368 | .post_load = e1000_post_load, |
d49805ae | 1369 | .fields = (VMStateField[]) { |
b08340d5 | 1370 | VMSTATE_PCI_DEVICE(parent_obj, E1000State), |
e482dc3e JQ |
1371 | VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */ |
1372 | VMSTATE_UNUSED(4), /* Was mmio_base. */ | |
1373 | VMSTATE_UINT32(rxbuf_size, E1000State), | |
1374 | VMSTATE_UINT32(rxbuf_min_shift, E1000State), | |
1375 | VMSTATE_UINT32(eecd_state.val_in, E1000State), | |
1376 | VMSTATE_UINT16(eecd_state.bitnum_in, E1000State), | |
1377 | VMSTATE_UINT16(eecd_state.bitnum_out, E1000State), | |
1378 | VMSTATE_UINT16(eecd_state.reading, E1000State), | |
1379 | VMSTATE_UINT32(eecd_state.old_eecd, E1000State), | |
1380 | VMSTATE_UINT8(tx.ipcss, E1000State), | |
1381 | VMSTATE_UINT8(tx.ipcso, E1000State), | |
1382 | VMSTATE_UINT16(tx.ipcse, E1000State), | |
1383 | VMSTATE_UINT8(tx.tucss, E1000State), | |
1384 | VMSTATE_UINT8(tx.tucso, E1000State), | |
1385 | VMSTATE_UINT16(tx.tucse, E1000State), | |
1386 | VMSTATE_UINT32(tx.paylen, E1000State), | |
1387 | VMSTATE_UINT8(tx.hdr_len, E1000State), | |
1388 | VMSTATE_UINT16(tx.mss, E1000State), | |
1389 | VMSTATE_UINT16(tx.size, E1000State), | |
1390 | VMSTATE_UINT16(tx.tso_frames, E1000State), | |
1391 | VMSTATE_UINT8(tx.sum_needed, E1000State), | |
1392 | VMSTATE_INT8(tx.ip, E1000State), | |
1393 | VMSTATE_INT8(tx.tcp, E1000State), | |
1394 | VMSTATE_BUFFER(tx.header, E1000State), | |
1395 | VMSTATE_BUFFER(tx.data, E1000State), | |
1396 | VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64), | |
1397 | VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20), | |
1398 | VMSTATE_UINT32(mac_reg[CTRL], E1000State), | |
1399 | VMSTATE_UINT32(mac_reg[EECD], E1000State), | |
1400 | VMSTATE_UINT32(mac_reg[EERD], E1000State), | |
1401 | VMSTATE_UINT32(mac_reg[GPRC], E1000State), | |
1402 | VMSTATE_UINT32(mac_reg[GPTC], E1000State), | |
1403 | VMSTATE_UINT32(mac_reg[ICR], E1000State), | |
1404 | VMSTATE_UINT32(mac_reg[ICS], E1000State), | |
1405 | VMSTATE_UINT32(mac_reg[IMC], E1000State), | |
1406 | VMSTATE_UINT32(mac_reg[IMS], E1000State), | |
1407 | VMSTATE_UINT32(mac_reg[LEDCTL], E1000State), | |
1408 | VMSTATE_UINT32(mac_reg[MANC], E1000State), | |
1409 | VMSTATE_UINT32(mac_reg[MDIC], E1000State), | |
1410 | VMSTATE_UINT32(mac_reg[MPC], E1000State), | |
1411 | VMSTATE_UINT32(mac_reg[PBA], E1000State), | |
1412 | VMSTATE_UINT32(mac_reg[RCTL], E1000State), | |
1413 | VMSTATE_UINT32(mac_reg[RDBAH], E1000State), | |
1414 | VMSTATE_UINT32(mac_reg[RDBAL], E1000State), | |
1415 | VMSTATE_UINT32(mac_reg[RDH], E1000State), | |
1416 | VMSTATE_UINT32(mac_reg[RDLEN], E1000State), | |
1417 | VMSTATE_UINT32(mac_reg[RDT], E1000State), | |
1418 | VMSTATE_UINT32(mac_reg[STATUS], E1000State), | |
1419 | VMSTATE_UINT32(mac_reg[SWSM], E1000State), | |
1420 | VMSTATE_UINT32(mac_reg[TCTL], E1000State), | |
1421 | VMSTATE_UINT32(mac_reg[TDBAH], E1000State), | |
1422 | VMSTATE_UINT32(mac_reg[TDBAL], E1000State), | |
1423 | VMSTATE_UINT32(mac_reg[TDH], E1000State), | |
1424 | VMSTATE_UINT32(mac_reg[TDLEN], E1000State), | |
1425 | VMSTATE_UINT32(mac_reg[TDT], E1000State), | |
1426 | VMSTATE_UINT32(mac_reg[TORH], E1000State), | |
1427 | VMSTATE_UINT32(mac_reg[TORL], E1000State), | |
1428 | VMSTATE_UINT32(mac_reg[TOTH], E1000State), | |
1429 | VMSTATE_UINT32(mac_reg[TOTL], E1000State), | |
1430 | VMSTATE_UINT32(mac_reg[TPR], E1000State), | |
1431 | VMSTATE_UINT32(mac_reg[TPT], E1000State), | |
1432 | VMSTATE_UINT32(mac_reg[TXDCTL], E1000State), | |
1433 | VMSTATE_UINT32(mac_reg[WUFC], E1000State), | |
1434 | VMSTATE_UINT32(mac_reg[VET], E1000State), | |
1435 | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32), | |
1436 | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128), | |
1437 | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128), | |
1438 | VMSTATE_END_OF_LIST() | |
e9845f09 VM |
1439 | }, |
1440 | .subsections = (VMStateSubsection[]) { | |
1441 | { | |
1442 | .vmsd = &vmstate_e1000_mit_state, | |
1443 | .needed = e1000_mit_state_needed, | |
1444 | }, { | |
1445 | /* empty */ | |
1446 | } | |
e482dc3e JQ |
1447 | } |
1448 | }; | |
7c23b892 | 1449 | |
8597f2e1 GS |
1450 | /* |
1451 | * EEPROM contents documented in Tables 5-2 and 5-3, pp. 98-102. | |
1452 | * Note: A valid DevId will be inserted during pci_e1000_init(). | |
1453 | */ | |
88b4e9db | 1454 | static const uint16_t e1000_eeprom_template[64] = { |
7c23b892 | 1455 | 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000, |
8597f2e1 | 1456 | 0x3000, 0x1000, 0x6403, 0 /*DevId*/, 0x8086, 0 /*DevId*/, 0x8086, 0x3040, |
7c23b892 AZ |
1457 | 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700, |
1458 | 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706, | |
1459 | 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff, | |
1460 | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
1461 | 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
1462 | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, | |
1463 | }; | |
1464 | ||
7c23b892 AZ |
1465 | /* PCI interface */ |
1466 | ||
7c23b892 | 1467 | static void |
ad00a9b9 | 1468 | e1000_mmio_setup(E1000State *d) |
7c23b892 | 1469 | { |
f65ed4c1 AL |
1470 | int i; |
1471 | const uint32_t excluded_regs[] = { | |
1472 | E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS, | |
1473 | E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE | |
1474 | }; | |
1475 | ||
eedfac6f PB |
1476 | memory_region_init_io(&d->mmio, OBJECT(d), &e1000_mmio_ops, d, |
1477 | "e1000-mmio", PNPMMIO_SIZE); | |
ad00a9b9 | 1478 | memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]); |
f65ed4c1 | 1479 | for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++) |
ad00a9b9 AK |
1480 | memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4, |
1481 | excluded_regs[i+1] - excluded_regs[i] - 4); | |
eedfac6f | 1482 | memory_region_init_io(&d->io, OBJECT(d), &e1000_io_ops, d, "e1000-io", IOPORT_SIZE); |
7c23b892 AZ |
1483 | } |
1484 | ||
b946a153 | 1485 | static void |
4e68f7a0 | 1486 | e1000_cleanup(NetClientState *nc) |
b946a153 | 1487 | { |
cc1f0f45 | 1488 | E1000State *s = qemu_get_nic_opaque(nc); |
b946a153 | 1489 | |
a03e2aec | 1490 | s->nic = NULL; |
b946a153 AL |
1491 | } |
1492 | ||
f90c2bcd | 1493 | static void |
4b09be85 AL |
1494 | pci_e1000_uninit(PCIDevice *dev) |
1495 | { | |
567a3c9e | 1496 | E1000State *d = E1000(dev); |
4b09be85 | 1497 | |
bc72ad67 AB |
1498 | timer_del(d->autoneg_timer); |
1499 | timer_free(d->autoneg_timer); | |
e9845f09 VM |
1500 | timer_del(d->mit_timer); |
1501 | timer_free(d->mit_timer); | |
ad00a9b9 AK |
1502 | memory_region_destroy(&d->mmio); |
1503 | memory_region_destroy(&d->io); | |
948ecf21 | 1504 | qemu_del_nic(d->nic); |
4b09be85 AL |
1505 | } |
1506 | ||
a03e2aec | 1507 | static NetClientInfo net_e1000_info = { |
2be64a68 | 1508 | .type = NET_CLIENT_OPTIONS_KIND_NIC, |
a03e2aec MM |
1509 | .size = sizeof(NICState), |
1510 | .can_receive = e1000_can_receive, | |
1511 | .receive = e1000_receive, | |
97410dde | 1512 | .receive_iov = e1000_receive_iov, |
a03e2aec MM |
1513 | .cleanup = e1000_cleanup, |
1514 | .link_status_changed = e1000_set_link_status, | |
1515 | }; | |
1516 | ||
81a322d4 | 1517 | static int pci_e1000_init(PCIDevice *pci_dev) |
7c23b892 | 1518 | { |
567a3c9e PC |
1519 | DeviceState *dev = DEVICE(pci_dev); |
1520 | E1000State *d = E1000(pci_dev); | |
8597f2e1 | 1521 | PCIDeviceClass *pdc = PCI_DEVICE_GET_CLASS(pci_dev); |
7c23b892 | 1522 | uint8_t *pci_conf; |
7c23b892 | 1523 | uint16_t checksum = 0; |
7c23b892 | 1524 | int i; |
fbdaa002 | 1525 | uint8_t *macaddr; |
aff427a1 | 1526 | |
b08340d5 | 1527 | pci_conf = pci_dev->config; |
7c23b892 | 1528 | |
a9cbacb0 MT |
1529 | /* TODO: RST# value should be 0, PCI spec 6.2.4 */ |
1530 | pci_conf[PCI_CACHE_LINE_SIZE] = 0x10; | |
7c23b892 | 1531 | |
817e0b6f | 1532 | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ |
7c23b892 | 1533 | |
ad00a9b9 | 1534 | e1000_mmio_setup(d); |
7c23b892 | 1535 | |
b08340d5 | 1536 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); |
7c23b892 | 1537 | |
b08340d5 | 1538 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io); |
7c23b892 | 1539 | |
7c23b892 AZ |
1540 | memmove(d->eeprom_data, e1000_eeprom_template, |
1541 | sizeof e1000_eeprom_template); | |
fbdaa002 GH |
1542 | qemu_macaddr_default_if_unset(&d->conf.macaddr); |
1543 | macaddr = d->conf.macaddr.a; | |
7c23b892 | 1544 | for (i = 0; i < 3; i++) |
9d07d757 | 1545 | d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i]; |
8597f2e1 | 1546 | d->eeprom_data[11] = d->eeprom_data[13] = pdc->device_id; |
7c23b892 AZ |
1547 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) |
1548 | checksum += d->eeprom_data[i]; | |
1549 | checksum = (uint16_t) EEPROM_SUM - checksum; | |
1550 | d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum; | |
1551 | ||
a03e2aec | 1552 | d->nic = qemu_new_nic(&net_e1000_info, &d->conf, |
567a3c9e | 1553 | object_get_typename(OBJECT(d)), dev->id, d); |
7c23b892 | 1554 | |
b356f76d | 1555 | qemu_format_nic_info_str(qemu_get_queue(d->nic), macaddr); |
1ca4d09a | 1556 | |
567a3c9e | 1557 | add_boot_device_path(d->conf.bootindex, dev, "/ethernet-phy@0"); |
1ca4d09a | 1558 | |
bc72ad67 | 1559 | d->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, e1000_autoneg_timer, d); |
e9845f09 | 1560 | d->mit_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000_mit_timer, d); |
b9d03e35 | 1561 | |
81a322d4 | 1562 | return 0; |
9d07d757 | 1563 | } |
72da4208 | 1564 | |
fbdaa002 GH |
1565 | static void qdev_e1000_reset(DeviceState *dev) |
1566 | { | |
567a3c9e | 1567 | E1000State *d = E1000(dev); |
fbdaa002 GH |
1568 | e1000_reset(d); |
1569 | } | |
1570 | ||
40021f08 AL |
1571 | static Property e1000_properties[] = { |
1572 | DEFINE_NIC_PROPERTIES(E1000State, conf), | |
2af234e6 MT |
1573 | DEFINE_PROP_BIT("autonegotiation", E1000State, |
1574 | compat_flags, E1000_FLAG_AUTONEG_BIT, true), | |
e9845f09 VM |
1575 | DEFINE_PROP_BIT("mitigation", E1000State, |
1576 | compat_flags, E1000_FLAG_MIT_BIT, true), | |
40021f08 AL |
1577 | DEFINE_PROP_END_OF_LIST(), |
1578 | }; | |
1579 | ||
8597f2e1 GS |
1580 | typedef struct E1000Info { |
1581 | const char *name; | |
1582 | uint16_t device_id; | |
1583 | uint8_t revision; | |
1584 | uint16_t phy_id2; | |
8597f2e1 GS |
1585 | } E1000Info; |
1586 | ||
40021f08 AL |
1587 | static void e1000_class_init(ObjectClass *klass, void *data) |
1588 | { | |
39bffca2 | 1589 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 1590 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
8597f2e1 GS |
1591 | E1000BaseClass *e = E1000_DEVICE_CLASS(klass); |
1592 | const E1000Info *info = data; | |
40021f08 AL |
1593 | |
1594 | k->init = pci_e1000_init; | |
1595 | k->exit = pci_e1000_uninit; | |
c45e5b5b | 1596 | k->romfile = "efi-e1000.rom"; |
40021f08 | 1597 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
8597f2e1 GS |
1598 | k->device_id = info->device_id; |
1599 | k->revision = info->revision; | |
1600 | e->phy_id2 = info->phy_id2; | |
40021f08 | 1601 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; |
125ee0ed | 1602 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
39bffca2 AL |
1603 | dc->desc = "Intel Gigabit Ethernet"; |
1604 | dc->reset = qdev_e1000_reset; | |
1605 | dc->vmsd = &vmstate_e1000; | |
1606 | dc->props = e1000_properties; | |
40021f08 AL |
1607 | } |
1608 | ||
8597f2e1 GS |
1609 | static const TypeInfo e1000_base_info = { |
1610 | .name = TYPE_E1000_BASE, | |
39bffca2 AL |
1611 | .parent = TYPE_PCI_DEVICE, |
1612 | .instance_size = sizeof(E1000State), | |
8597f2e1 GS |
1613 | .class_size = sizeof(E1000BaseClass), |
1614 | .abstract = true, | |
1615 | }; | |
1616 | ||
1617 | static const E1000Info e1000_devices[] = { | |
1618 | { | |
1619 | .name = "e1000-82540em", | |
1620 | .device_id = E1000_DEV_ID_82540EM, | |
1621 | .revision = 0x03, | |
1622 | .phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT, | |
1623 | }, | |
1624 | { | |
1625 | .name = "e1000-82544gc", | |
1626 | .device_id = E1000_DEV_ID_82544GC_COPPER, | |
1627 | .revision = 0x03, | |
1628 | .phy_id2 = E1000_PHY_ID2_82544x, | |
1629 | }, | |
1630 | { | |
1631 | .name = "e1000-82545em", | |
1632 | .device_id = E1000_DEV_ID_82545EM_COPPER, | |
1633 | .revision = 0x03, | |
1634 | .phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT, | |
1635 | }, | |
8597f2e1 GS |
1636 | }; |
1637 | ||
1638 | static const TypeInfo e1000_default_info = { | |
1639 | .name = "e1000", | |
1640 | .parent = "e1000-82540em", | |
0aab0d3a GH |
1641 | }; |
1642 | ||
83f7d43a | 1643 | static void e1000_register_types(void) |
9d07d757 | 1644 | { |
8597f2e1 GS |
1645 | int i; |
1646 | ||
1647 | type_register_static(&e1000_base_info); | |
1648 | for (i = 0; i < ARRAY_SIZE(e1000_devices); i++) { | |
1649 | const E1000Info *info = &e1000_devices[i]; | |
1650 | TypeInfo type_info = {}; | |
1651 | ||
1652 | type_info.name = info->name; | |
1653 | type_info.parent = TYPE_E1000_BASE; | |
1654 | type_info.class_data = (void *)info; | |
1655 | type_info.class_init = e1000_class_init; | |
1656 | ||
1657 | type_register(&type_info); | |
1658 | } | |
1659 | type_register_static(&e1000_default_info); | |
7c23b892 | 1660 | } |
9d07d757 | 1661 | |
83f7d43a | 1662 | type_init(e1000_register_types) |