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Commit | Line | Data |
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7c23b892 AZ |
1 | /* |
2 | * QEMU e1000 emulation | |
3 | * | |
2758aa52 MT |
4 | * Software developer's manual: |
5 | * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf | |
6 | * | |
7c23b892 AZ |
7 | * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. |
8 | * Copyright (c) 2008 Qumranet | |
9 | * Based on work done by: | |
10 | * Copyright (c) 2007 Dan Aloni | |
11 | * Copyright (c) 2004 Antony T Curtis | |
12 | * | |
13 | * This library is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU Lesser General Public | |
15 | * License as published by the Free Software Foundation; either | |
61f3c91a | 16 | * version 2.1 of the License, or (at your option) any later version. |
7c23b892 AZ |
17 | * |
18 | * This library is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
21 | * Lesser General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 24 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
7c23b892 AZ |
25 | */ |
26 | ||
27 | ||
e8d40465 | 28 | #include "qemu/osdep.h" |
b7728c9f | 29 | #include "hw/net/mii.h" |
edf5ca5d | 30 | #include "hw/pci/pci_device.h" |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
d6454270 | 32 | #include "migration/vmstate.h" |
a1d7e475 | 33 | #include "net/eth.h" |
1422e32d | 34 | #include "net/net.h" |
7200ac3c | 35 | #include "net/checksum.h" |
9c17d615 PB |
36 | #include "sysemu/sysemu.h" |
37 | #include "sysemu/dma.h" | |
97410dde | 38 | #include "qemu/iov.h" |
0b8fa32f | 39 | #include "qemu/module.h" |
20302e71 | 40 | #include "qemu/range.h" |
7c23b892 | 41 | |
c9653b77 | 42 | #include "e1000_common.h" |
093454e2 | 43 | #include "e1000x_common.h" |
1001cf45 | 44 | #include "trace.h" |
db1015e9 | 45 | #include "qom/object.h" |
7c23b892 | 46 | |
b4053c64 | 47 | /* #define E1000_DEBUG */ |
7c23b892 | 48 | |
27124888 | 49 | #ifdef E1000_DEBUG |
7c23b892 | 50 | enum { |
20f3e863 LB |
51 | DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT, |
52 | DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM, | |
53 | DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR, | |
f9c1cdf4 | 54 | DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET, |
7c23b892 | 55 | }; |
20f3e863 | 56 | #define DBGBIT(x) (1<<DEBUG_##x) |
7c23b892 AZ |
57 | static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL); |
58 | ||
20f3e863 | 59 | #define DBGOUT(what, fmt, ...) do { \ |
7c23b892 | 60 | if (debugflags & DBGBIT(what)) \ |
6c7f4b47 | 61 | fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \ |
7c23b892 AZ |
62 | } while (0) |
63 | #else | |
20f3e863 | 64 | #define DBGOUT(what, fmt, ...) do {} while (0) |
7c23b892 AZ |
65 | #endif |
66 | ||
67 | #define IOPORT_SIZE 0x40 | |
e94bbefe | 68 | #define PNPMMIO_SIZE 0x20000 |
7c23b892 | 69 | |
2fe63579 | 70 | #define MAXIMUM_ETHERNET_HDR_LEN (ETH_HLEN + 4) |
97410dde | 71 | |
7c23b892 AZ |
72 | /* |
73 | * HW models: | |
8597f2e1 | 74 | * E1000_DEV_ID_82540EM works with Windows, Linux, and OS X <= 10.8 |
7c23b892 | 75 | * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested |
8597f2e1 | 76 | * E1000_DEV_ID_82545EM_COPPER works with Linux and OS X >= 10.6 |
7c23b892 AZ |
77 | * Others never tested |
78 | */ | |
7c23b892 | 79 | |
db1015e9 | 80 | struct E1000State_st { |
b08340d5 AF |
81 | /*< private >*/ |
82 | PCIDevice parent_obj; | |
83 | /*< public >*/ | |
84 | ||
a03e2aec | 85 | NICState *nic; |
fbdaa002 | 86 | NICConf conf; |
ad00a9b9 AK |
87 | MemoryRegion mmio; |
88 | MemoryRegion io; | |
7c23b892 AZ |
89 | |
90 | uint32_t mac_reg[0x8000]; | |
91 | uint16_t phy_reg[0x20]; | |
92 | uint16_t eeprom_data[64]; | |
93 | ||
94 | uint32_t rxbuf_size; | |
95 | uint32_t rxbuf_min_shift; | |
7c23b892 AZ |
96 | struct e1000_tx { |
97 | unsigned char header[256]; | |
8f2e8d1f | 98 | unsigned char vlan_header[4]; |
b10fec9b | 99 | /* Fields vlan and data must not be reordered or separated. */ |
8f2e8d1f | 100 | unsigned char vlan[4]; |
7c23b892 AZ |
101 | unsigned char data[0x10000]; |
102 | uint16_t size; | |
8f2e8d1f | 103 | unsigned char vlan_needed; |
7d08c73e ES |
104 | unsigned char sum_needed; |
105 | bool cptse; | |
093454e2 | 106 | e1000x_txd_props props; |
d62644b4 | 107 | e1000x_txd_props tso_props; |
7c23b892 | 108 | uint16_t tso_frames; |
25ddb946 | 109 | bool busy; |
7c23b892 AZ |
110 | } tx; |
111 | ||
112 | struct { | |
20f3e863 | 113 | uint32_t val_in; /* shifted in from guest driver */ |
7c23b892 AZ |
114 | uint16_t bitnum_in; |
115 | uint16_t bitnum_out; | |
116 | uint16_t reading; | |
117 | uint32_t old_eecd; | |
118 | } eecd_state; | |
b9d03e35 JW |
119 | |
120 | QEMUTimer *autoneg_timer; | |
2af234e6 | 121 | |
e9845f09 VM |
122 | QEMUTimer *mit_timer; /* Mitigation timer. */ |
123 | bool mit_timer_on; /* Mitigation timer is running. */ | |
124 | bool mit_irq_level; /* Tracks interrupt pin level. */ | |
125 | uint32_t mit_ide; /* Tracks E1000_TXD_CMD_IDE bit. */ | |
126 | ||
157628d0 YCL |
127 | QEMUTimer *flush_queue_timer; |
128 | ||
2af234e6 | 129 | /* Compatibility flags for migration to/from qemu 1.3.0 and older */ |
9e117734 | 130 | #define E1000_FLAG_MAC_BIT 2 |
46f2a9ec | 131 | #define E1000_FLAG_TSO_BIT 3 |
a1d7e475 | 132 | #define E1000_FLAG_VET_BIT 4 |
9e117734 | 133 | #define E1000_FLAG_MAC (1 << E1000_FLAG_MAC_BIT) |
46f2a9ec | 134 | #define E1000_FLAG_TSO (1 << E1000_FLAG_TSO_BIT) |
a1d7e475 CW |
135 | #define E1000_FLAG_VET (1 << E1000_FLAG_VET_BIT) |
136 | ||
2af234e6 | 137 | uint32_t compat_flags; |
3c4053c5 | 138 | bool received_tx_tso; |
ff214d42 | 139 | bool use_tso_for_migration; |
59354484 | 140 | e1000x_txd_props mig_props; |
db1015e9 EH |
141 | }; |
142 | typedef struct E1000State_st E1000State; | |
7c23b892 | 143 | |
bc0f0674 LB |
144 | #define chkflag(x) (s->compat_flags & E1000_FLAG_##x) |
145 | ||
db1015e9 | 146 | struct E1000BaseClass { |
8597f2e1 GS |
147 | PCIDeviceClass parent_class; |
148 | uint16_t phy_id2; | |
db1015e9 EH |
149 | }; |
150 | typedef struct E1000BaseClass E1000BaseClass; | |
8597f2e1 GS |
151 | |
152 | #define TYPE_E1000_BASE "e1000-base" | |
567a3c9e | 153 | |
8110fa1d EH |
154 | DECLARE_OBJ_CHECKERS(E1000State, E1000BaseClass, |
155 | E1000, TYPE_E1000_BASE) | |
8597f2e1 | 156 | |
567a3c9e | 157 | |
71aadd3c | 158 | static void |
093454e2 | 159 | e1000_link_up(E1000State *s) |
71aadd3c | 160 | { |
093454e2 DF |
161 | e1000x_update_regs_on_link_up(s->mac_reg, s->phy_reg); |
162 | ||
163 | /* E1000_STATUS_LU is tested by e1000_can_receive() */ | |
164 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | |
71aadd3c JW |
165 | } |
166 | ||
167 | static void | |
093454e2 | 168 | e1000_autoneg_done(E1000State *s) |
71aadd3c | 169 | { |
093454e2 | 170 | e1000x_update_regs_on_autoneg_done(s->mac_reg, s->phy_reg); |
5df6a185 SH |
171 | |
172 | /* E1000_STATUS_LU is tested by e1000_can_receive() */ | |
173 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | |
71aadd3c JW |
174 | } |
175 | ||
1195fed9 GS |
176 | static bool |
177 | have_autoneg(E1000State *s) | |
178 | { | |
fa4ec9ff | 179 | return (s->phy_reg[MII_BMCR] & MII_BMCR_AUTOEN); |
1195fed9 GS |
180 | } |
181 | ||
b9d03e35 JW |
182 | static void |
183 | set_phy_ctrl(E1000State *s, int index, uint16_t val) | |
184 | { | |
b7728c9f AO |
185 | /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ |
186 | s->phy_reg[MII_BMCR] = val & ~(0x3f | | |
187 | MII_BMCR_RESET | | |
188 | MII_BMCR_ANRESTART); | |
1195fed9 | 189 | |
2af234e6 MT |
190 | /* |
191 | * QEMU 1.3 does not support link auto-negotiation emulation, so if we | |
192 | * migrate during auto negotiation, after migration the link will be | |
193 | * down. | |
194 | */ | |
b7728c9f | 195 | if (have_autoneg(s) && (val & MII_BMCR_ANRESTART)) { |
093454e2 | 196 | e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer); |
b9d03e35 JW |
197 | } |
198 | } | |
199 | ||
b9d03e35 | 200 | static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = { |
b7728c9f | 201 | [MII_BMCR] = set_phy_ctrl, |
b9d03e35 JW |
202 | }; |
203 | ||
204 | enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) }; | |
205 | ||
7c23b892 | 206 | enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W }; |
88b4e9db | 207 | static const char phy_regcap[0x20] = { |
b7728c9f AO |
208 | [MII_BMSR] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW, |
209 | [MII_PHYID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW, | |
210 | [MII_BMCR] = PHY_RW, [MII_CTRL1000] = PHY_RW, | |
211 | [MII_ANLPAR] = PHY_R, [MII_STAT1000] = PHY_R, | |
212 | [MII_ANAR] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R, | |
213 | [MII_PHYID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R, | |
214 | [MII_ANER] = PHY_R, | |
7c23b892 AZ |
215 | }; |
216 | ||
b7728c9f | 217 | /* MII_PHYID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */ |
814cd3ac | 218 | static const uint16_t phy_reg_init[] = { |
b7728c9f AO |
219 | [MII_BMCR] = MII_BMCR_SPEED1000 | |
220 | MII_BMCR_FD | | |
221 | MII_BMCR_AUTOEN, | |
222 | ||
223 | [MII_BMSR] = MII_BMSR_EXTCAP | | |
224 | MII_BMSR_LINK_ST | /* link initially up */ | |
225 | MII_BMSR_AUTONEG | | |
226 | /* MII_BMSR_AN_COMP: initially NOT completed */ | |
227 | MII_BMSR_MFPS | | |
228 | MII_BMSR_EXTSTAT | | |
229 | MII_BMSR_10T_HD | | |
230 | MII_BMSR_10T_FD | | |
231 | MII_BMSR_100TX_HD | | |
232 | MII_BMSR_100TX_FD, | |
233 | ||
234 | [MII_PHYID1] = 0x141, | |
235 | /* [MII_PHYID2] configured per DevId, from e1000_reset() */ | |
2fe63579 AO |
236 | [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | |
237 | MII_ANAR_10FD | MII_ANAR_TX | | |
238 | MII_ANAR_TXFD | MII_ANAR_PAUSE | | |
239 | MII_ANAR_PAUSE_ASYM, | |
240 | [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | | |
241 | MII_ANLPAR_TX | MII_ANLPAR_TXFD, | |
242 | [MII_CTRL1000] = MII_CTRL1000_FULL | MII_CTRL1000_PORT | | |
243 | MII_CTRL1000_MASTER, | |
244 | [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | | |
245 | MII_STAT1000_ROK | MII_STAT1000_LOK, | |
9616c290 | 246 | [M88E1000_PHY_SPEC_CTRL] = 0x360, |
814cd3ac | 247 | [M88E1000_PHY_SPEC_STATUS] = 0xac00, |
9616c290 | 248 | [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, |
814cd3ac MT |
249 | }; |
250 | ||
251 | static const uint32_t mac_reg_init[] = { | |
20f3e863 LB |
252 | [PBA] = 0x00100030, |
253 | [LEDCTL] = 0x602, | |
254 | [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | | |
814cd3ac | 255 | E1000_CTRL_SPD_1000 | E1000_CTRL_SLU, |
20f3e863 | 256 | [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE | |
814cd3ac MT |
257 | E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK | |
258 | E1000_STATUS_SPEED_1000 | E1000_STATUS_FD | | |
259 | E1000_STATUS_LU, | |
20f3e863 | 260 | [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN | |
814cd3ac MT |
261 | E1000_MANC_ARP_EN | E1000_MANC_0298_EN | |
262 | E1000_MANC_RMCP_EN, | |
263 | }; | |
264 | ||
e9845f09 VM |
265 | /* Helper function, *curr == 0 means the value is not set */ |
266 | static inline void | |
267 | mit_update_delay(uint32_t *curr, uint32_t value) | |
268 | { | |
269 | if (value && (*curr == 0 || value < *curr)) { | |
270 | *curr = value; | |
271 | } | |
272 | } | |
273 | ||
7c23b892 AZ |
274 | static void |
275 | set_interrupt_cause(E1000State *s, int index, uint32_t val) | |
276 | { | |
b08340d5 | 277 | PCIDevice *d = PCI_DEVICE(s); |
e9845f09 VM |
278 | uint32_t pending_ints; |
279 | uint32_t mit_delay; | |
b08340d5 | 280 | |
7c23b892 | 281 | s->mac_reg[ICR] = val; |
a52a8841 MT |
282 | |
283 | /* | |
284 | * Make sure ICR and ICS registers have the same value. | |
285 | * The spec says that the ICS register is write-only. However in practice, | |
286 | * on real hardware ICS is readable, and for reads it has the same value as | |
287 | * ICR (except that ICS does not have the clear on read behaviour of ICR). | |
288 | * | |
289 | * The VxWorks PRO/1000 driver uses this behaviour. | |
290 | */ | |
b1332393 | 291 | s->mac_reg[ICS] = val; |
a52a8841 | 292 | |
e9845f09 VM |
293 | pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]); |
294 | if (!s->mit_irq_level && pending_ints) { | |
295 | /* | |
296 | * Here we detect a potential raising edge. We postpone raising the | |
297 | * interrupt line if we are inside the mitigation delay window | |
298 | * (s->mit_timer_on == 1). | |
299 | * We provide a partial implementation of interrupt mitigation, | |
300 | * emulating only RADV, TADV and ITR (lower 16 bits, 1024ns units for | |
301 | * RADV and TADV, 256ns units for ITR). RDTR is only used to enable | |
302 | * RADV; relative timers based on TIDV and RDTR are not implemented. | |
303 | */ | |
304 | if (s->mit_timer_on) { | |
305 | return; | |
306 | } | |
fa4ec9ff PB |
307 | |
308 | /* Compute the next mitigation delay according to pending | |
309 | * interrupts and the current values of RADV (provided | |
310 | * RDTR!=0), TADV and ITR. | |
311 | * Then rearm the timer. | |
312 | */ | |
313 | mit_delay = 0; | |
314 | if (s->mit_ide && | |
315 | (pending_ints & (E1000_ICR_TXQE | E1000_ICR_TXDW))) { | |
316 | mit_update_delay(&mit_delay, s->mac_reg[TADV] * 4); | |
e9845f09 | 317 | } |
fa4ec9ff PB |
318 | if (s->mac_reg[RDTR] && (pending_ints & E1000_ICS_RXT0)) { |
319 | mit_update_delay(&mit_delay, s->mac_reg[RADV] * 4); | |
320 | } | |
321 | mit_update_delay(&mit_delay, s->mac_reg[ITR]); | |
322 | ||
323 | /* | |
324 | * According to e1000 SPEC, the Ethernet controller guarantees | |
325 | * a maximum observable interrupt rate of 7813 interrupts/sec. | |
326 | * Thus if mit_delay < 500 then the delay should be set to the | |
327 | * minimum delay possible which is 500. | |
328 | */ | |
329 | mit_delay = (mit_delay < 500) ? 500 : mit_delay; | |
330 | ||
331 | s->mit_timer_on = 1; | |
332 | timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
333 | mit_delay * 256); | |
334 | s->mit_ide = 0; | |
e9845f09 VM |
335 | } |
336 | ||
337 | s->mit_irq_level = (pending_ints != 0); | |
9e64f8a3 | 338 | pci_set_irq(d, s->mit_irq_level); |
e9845f09 VM |
339 | } |
340 | ||
341 | static void | |
342 | e1000_mit_timer(void *opaque) | |
343 | { | |
344 | E1000State *s = opaque; | |
345 | ||
346 | s->mit_timer_on = 0; | |
347 | /* Call set_interrupt_cause to update the irq level (if necessary). */ | |
348 | set_interrupt_cause(s, 0, s->mac_reg[ICR]); | |
7c23b892 AZ |
349 | } |
350 | ||
351 | static void | |
352 | set_ics(E1000State *s, int index, uint32_t val) | |
353 | { | |
354 | DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], | |
355 | s->mac_reg[IMS]); | |
356 | set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); | |
357 | } | |
358 | ||
d52aec95 GS |
359 | static void |
360 | e1000_autoneg_timer(void *opaque) | |
361 | { | |
362 | E1000State *s = opaque; | |
363 | if (!qemu_get_queue(s->nic)->link_down) { | |
093454e2 | 364 | e1000_autoneg_done(s); |
d52aec95 GS |
365 | set_ics(s, 0, E1000_ICS_LSC); /* signal link status change to guest */ |
366 | } | |
367 | } | |
368 | ||
a1d7e475 CW |
369 | static bool e1000_vet_init_need(void *opaque) |
370 | { | |
371 | E1000State *s = opaque; | |
372 | ||
373 | return chkflag(VET); | |
374 | } | |
375 | ||
9d465053 | 376 | static void e1000_reset_hold(Object *obj) |
814cd3ac | 377 | { |
9d465053 | 378 | E1000State *d = E1000(obj); |
c51325d8 | 379 | E1000BaseClass *edc = E1000_GET_CLASS(d); |
372254c6 | 380 | uint8_t *macaddr = d->conf.macaddr.a; |
814cd3ac | 381 | |
bc72ad67 | 382 | timer_del(d->autoneg_timer); |
e9845f09 | 383 | timer_del(d->mit_timer); |
157628d0 | 384 | timer_del(d->flush_queue_timer); |
e9845f09 VM |
385 | d->mit_timer_on = 0; |
386 | d->mit_irq_level = 0; | |
387 | d->mit_ide = 0; | |
814cd3ac | 388 | memset(d->phy_reg, 0, sizeof d->phy_reg); |
9eb525ee | 389 | memcpy(d->phy_reg, phy_reg_init, sizeof phy_reg_init); |
b7728c9f | 390 | d->phy_reg[MII_PHYID2] = edc->phy_id2; |
814cd3ac | 391 | memset(d->mac_reg, 0, sizeof d->mac_reg); |
9eb525ee | 392 | memcpy(d->mac_reg, mac_reg_init, sizeof mac_reg_init); |
814cd3ac MT |
393 | d->rxbuf_min_shift = 1; |
394 | memset(&d->tx, 0, sizeof d->tx); | |
395 | ||
b356f76d | 396 | if (qemu_get_queue(d->nic)->link_down) { |
093454e2 | 397 | e1000x_update_regs_on_link_down(d->mac_reg, d->phy_reg); |
814cd3ac | 398 | } |
372254c6 | 399 | |
093454e2 | 400 | e1000x_reset_mac_addr(d->nic, d->mac_reg, macaddr); |
a1d7e475 CW |
401 | |
402 | if (e1000_vet_init_need(d)) { | |
403 | d->mac_reg[VET] = ETH_P_VLAN; | |
404 | } | |
814cd3ac MT |
405 | } |
406 | ||
cab3c825 KW |
407 | static void |
408 | set_ctrl(E1000State *s, int index, uint32_t val) | |
409 | { | |
410 | /* RST is self clearing */ | |
411 | s->mac_reg[CTRL] = val & ~E1000_CTRL_RST; | |
412 | } | |
413 | ||
157628d0 YCL |
414 | static void |
415 | e1000_flush_queue_timer(void *opaque) | |
416 | { | |
417 | E1000State *s = opaque; | |
418 | ||
419 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | |
420 | } | |
421 | ||
7c23b892 AZ |
422 | static void |
423 | set_rx_control(E1000State *s, int index, uint32_t val) | |
424 | { | |
425 | s->mac_reg[RCTL] = val; | |
093454e2 | 426 | s->rxbuf_size = e1000x_rxbufsize(val); |
7c23b892 AZ |
427 | s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1; |
428 | DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT], | |
429 | s->mac_reg[RCTL]); | |
157628d0 YCL |
430 | timer_mod(s->flush_queue_timer, |
431 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000); | |
7c23b892 AZ |
432 | } |
433 | ||
434 | static void | |
435 | set_mdic(E1000State *s, int index, uint32_t val) | |
436 | { | |
437 | uint32_t data = val & E1000_MDIC_DATA_MASK; | |
438 | uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); | |
439 | ||
440 | if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy # | |
441 | val = s->mac_reg[MDIC] | E1000_MDIC_ERROR; | |
442 | else if (val & E1000_MDIC_OP_READ) { | |
443 | DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr); | |
444 | if (!(phy_regcap[addr] & PHY_R)) { | |
445 | DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr); | |
446 | val |= E1000_MDIC_ERROR; | |
447 | } else | |
448 | val = (val ^ data) | s->phy_reg[addr]; | |
449 | } else if (val & E1000_MDIC_OP_WRITE) { | |
450 | DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data); | |
451 | if (!(phy_regcap[addr] & PHY_W)) { | |
452 | DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr); | |
453 | val |= E1000_MDIC_ERROR; | |
b9d03e35 JW |
454 | } else { |
455 | if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) { | |
456 | phyreg_writeops[addr](s, index, data); | |
1195fed9 GS |
457 | } else { |
458 | s->phy_reg[addr] = data; | |
b9d03e35 | 459 | } |
b9d03e35 | 460 | } |
7c23b892 AZ |
461 | } |
462 | s->mac_reg[MDIC] = val | E1000_MDIC_READY; | |
17fbbb0b JW |
463 | |
464 | if (val & E1000_MDIC_INT_EN) { | |
465 | set_ics(s, 0, E1000_ICR_MDAC); | |
466 | } | |
7c23b892 AZ |
467 | } |
468 | ||
469 | static uint32_t | |
470 | get_eecd(E1000State *s, int index) | |
471 | { | |
472 | uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd; | |
473 | ||
474 | DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n", | |
475 | s->eecd_state.bitnum_out, s->eecd_state.reading); | |
476 | if (!s->eecd_state.reading || | |
477 | ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >> | |
478 | ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) | |
479 | ret |= E1000_EECD_DO; | |
480 | return ret; | |
481 | } | |
482 | ||
483 | static void | |
484 | set_eecd(E1000State *s, int index, uint32_t val) | |
485 | { | |
486 | uint32_t oldval = s->eecd_state.old_eecd; | |
487 | ||
488 | s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS | | |
489 | E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ); | |
20f3e863 LB |
490 | if (!(E1000_EECD_CS & val)) { /* CS inactive; nothing to do */ |
491 | return; | |
492 | } | |
493 | if (E1000_EECD_CS & (val ^ oldval)) { /* CS rise edge; reset state */ | |
494 | s->eecd_state.val_in = 0; | |
495 | s->eecd_state.bitnum_in = 0; | |
496 | s->eecd_state.bitnum_out = 0; | |
497 | s->eecd_state.reading = 0; | |
9651ac55 | 498 | } |
20f3e863 | 499 | if (!(E1000_EECD_SK & (val ^ oldval))) { /* no clock edge */ |
7c23b892 | 500 | return; |
20f3e863 LB |
501 | } |
502 | if (!(E1000_EECD_SK & val)) { /* falling edge */ | |
7c23b892 AZ |
503 | s->eecd_state.bitnum_out++; |
504 | return; | |
505 | } | |
7c23b892 AZ |
506 | s->eecd_state.val_in <<= 1; |
507 | if (val & E1000_EECD_DI) | |
508 | s->eecd_state.val_in |= 1; | |
509 | if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) { | |
510 | s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1; | |
511 | s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) == | |
512 | EEPROM_READ_OPCODE_MICROWIRE); | |
513 | } | |
514 | DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n", | |
515 | s->eecd_state.bitnum_in, s->eecd_state.bitnum_out, | |
516 | s->eecd_state.reading); | |
517 | } | |
518 | ||
519 | static uint32_t | |
520 | flash_eerd_read(E1000State *s, int x) | |
521 | { | |
522 | unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START; | |
523 | ||
b1332393 BP |
524 | if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0) |
525 | return (s->mac_reg[EERD]); | |
526 | ||
7c23b892 | 527 | if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG) |
b1332393 BP |
528 | return (E1000_EEPROM_RW_REG_DONE | r); |
529 | ||
530 | return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) | | |
531 | E1000_EEPROM_RW_REG_DONE | r); | |
7c23b892 AZ |
532 | } |
533 | ||
7c23b892 AZ |
534 | static void |
535 | putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse) | |
536 | { | |
c6a6a5e3 AL |
537 | uint32_t sum; |
538 | ||
7c23b892 AZ |
539 | if (cse && cse < n) |
540 | n = cse + 1; | |
c6a6a5e3 AL |
541 | if (sloc < n-1) { |
542 | sum = net_checksum_add(n-css, data+css); | |
0dacea92 | 543 | stw_be_p(data + sloc, net_checksum_finish_nozero(sum)); |
c6a6a5e3 | 544 | } |
7c23b892 AZ |
545 | } |
546 | ||
3b274301 LB |
547 | static inline void |
548 | inc_tx_bcast_or_mcast_count(E1000State *s, const unsigned char *arr) | |
549 | { | |
2fe63579 | 550 | if (is_broadcast_ether_addr(arr)) { |
093454e2 | 551 | e1000x_inc_reg_if_not_full(s->mac_reg, BPTC); |
2fe63579 | 552 | } else if (is_multicast_ether_addr(arr)) { |
093454e2 | 553 | e1000x_inc_reg_if_not_full(s->mac_reg, MPTC); |
3b274301 LB |
554 | } |
555 | } | |
556 | ||
93e37d76 JW |
557 | static void |
558 | e1000_send_packet(E1000State *s, const uint8_t *buf, int size) | |
559 | { | |
3b274301 LB |
560 | static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, |
561 | PTC1023, PTC1522 }; | |
562 | ||
b356f76d | 563 | NetClientState *nc = qemu_get_queue(s->nic); |
b7728c9f | 564 | if (s->phy_reg[MII_BMCR] & MII_BMCR_LOOPBACK) { |
1caff034 | 565 | qemu_receive_packet(nc, buf, size); |
93e37d76 | 566 | } else { |
b356f76d | 567 | qemu_send_packet(nc, buf, size); |
93e37d76 | 568 | } |
3b274301 | 569 | inc_tx_bcast_or_mcast_count(s, buf); |
c50b1524 | 570 | e1000x_increase_size_stats(s->mac_reg, PTCregs, size + 4); |
93e37d76 JW |
571 | } |
572 | ||
7c23b892 AZ |
573 | static void |
574 | xmit_seg(E1000State *s) | |
575 | { | |
14e60aae | 576 | uint16_t len; |
45e93764 | 577 | unsigned int frames = s->tx.tso_frames, css, sofar; |
7c23b892 | 578 | struct e1000_tx *tp = &s->tx; |
d62644b4 | 579 | struct e1000x_txd_props *props = tp->cptse ? &tp->tso_props : &tp->props; |
7c23b892 | 580 | |
d62644b4 ES |
581 | if (tp->cptse) { |
582 | css = props->ipcss; | |
7c23b892 AZ |
583 | DBGOUT(TXSUM, "frames %d size %d ipcss %d\n", |
584 | frames, tp->size, css); | |
d62644b4 | 585 | if (props->ip) { /* IPv4 */ |
d8ee2591 PM |
586 | stw_be_p(tp->data+css+2, tp->size - css); |
587 | stw_be_p(tp->data+css+4, | |
14e60aae | 588 | lduw_be_p(tp->data + css + 4) + frames); |
20f3e863 | 589 | } else { /* IPv6 */ |
d8ee2591 | 590 | stw_be_p(tp->data+css+4, tp->size - css); |
20f3e863 | 591 | } |
d62644b4 | 592 | css = props->tucss; |
7c23b892 | 593 | len = tp->size - css; |
d62644b4 ES |
594 | DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", props->tcp, css, len); |
595 | if (props->tcp) { | |
596 | sofar = frames * props->mss; | |
6bd194ab | 597 | stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */ |
d62644b4 | 598 | if (props->paylen - sofar > props->mss) { |
20f3e863 | 599 | tp->data[css + 13] &= ~9; /* PSH, FIN */ |
3b274301 | 600 | } else if (frames) { |
093454e2 | 601 | e1000x_inc_reg_if_not_full(s->mac_reg, TSCTC); |
3b274301 | 602 | } |
d62644b4 | 603 | } else { /* UDP */ |
d8ee2591 | 604 | stw_be_p(tp->data+css+4, len); |
d62644b4 | 605 | } |
7d08c73e | 606 | if (tp->sum_needed & E1000_TXD_POPTS_TXSM) { |
e685b4eb | 607 | unsigned int phsum; |
7c23b892 | 608 | // add pseudo-header length before checksum calculation |
d62644b4 | 609 | void *sp = tp->data + props->tucso; |
14e60aae PM |
610 | |
611 | phsum = lduw_be_p(sp) + len; | |
e685b4eb | 612 | phsum = (phsum >> 16) + (phsum & 0xffff); |
d8ee2591 | 613 | stw_be_p(sp, phsum); |
7c23b892 AZ |
614 | } |
615 | tp->tso_frames++; | |
616 | } | |
617 | ||
7d08c73e | 618 | if (tp->sum_needed & E1000_TXD_POPTS_TXSM) { |
d62644b4 | 619 | putsum(tp->data, tp->size, props->tucso, props->tucss, props->tucse); |
093454e2 | 620 | } |
7d08c73e | 621 | if (tp->sum_needed & E1000_TXD_POPTS_IXSM) { |
d62644b4 | 622 | putsum(tp->data, tp->size, props->ipcso, props->ipcss, props->ipcse); |
093454e2 | 623 | } |
8f2e8d1f | 624 | if (tp->vlan_needed) { |
b10fec9b SW |
625 | memmove(tp->vlan, tp->data, 4); |
626 | memmove(tp->data, tp->data + 4, 8); | |
8f2e8d1f | 627 | memcpy(tp->data + 8, tp->vlan_header, 4); |
93e37d76 | 628 | e1000_send_packet(s, tp->vlan, tp->size + 4); |
20f3e863 | 629 | } else { |
93e37d76 | 630 | e1000_send_packet(s, tp->data, tp->size); |
20f3e863 LB |
631 | } |
632 | ||
093454e2 | 633 | e1000x_inc_reg_if_not_full(s->mac_reg, TPT); |
c50b1524 | 634 | e1000x_grow_8reg_if_not_full(s->mac_reg, TOTL, s->tx.size + 4); |
8d689f6a TC |
635 | e1000x_inc_reg_if_not_full(s->mac_reg, GPTC); |
636 | e1000x_grow_8reg_if_not_full(s->mac_reg, GOTCL, s->tx.size + 4); | |
7c23b892 AZ |
637 | } |
638 | ||
639 | static void | |
640 | process_tx_desc(E1000State *s, struct e1000_tx_desc *dp) | |
641 | { | |
b08340d5 | 642 | PCIDevice *d = PCI_DEVICE(s); |
7c23b892 AZ |
643 | uint32_t txd_lower = le32_to_cpu(dp->lower.data); |
644 | uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); | |
093454e2 | 645 | unsigned int split_size = txd_lower & 0xffff, bytes, sz; |
a0ae17a6 | 646 | unsigned int msh = 0xfffff; |
7c23b892 AZ |
647 | uint64_t addr; |
648 | struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; | |
649 | struct e1000_tx *tp = &s->tx; | |
650 | ||
e9845f09 | 651 | s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE); |
20f3e863 | 652 | if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ |
d62644b4 ES |
653 | if (le32_to_cpu(xp->cmd_and_length) & E1000_TXD_CMD_TSE) { |
654 | e1000x_read_tx_ctx_descr(xp, &tp->tso_props); | |
ff214d42 | 655 | s->use_tso_for_migration = 1; |
d62644b4 ES |
656 | tp->tso_frames = 0; |
657 | } else { | |
658 | e1000x_read_tx_ctx_descr(xp, &tp->props); | |
ff214d42 | 659 | s->use_tso_for_migration = 0; |
7c23b892 AZ |
660 | } |
661 | return; | |
1b0009db AZ |
662 | } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { |
663 | // data descriptor | |
735e77ec | 664 | if (tp->size == 0) { |
7d08c73e | 665 | tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8; |
735e77ec | 666 | } |
7d08c73e | 667 | tp->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; |
43ad7e3e | 668 | } else { |
1b0009db | 669 | // legacy descriptor |
7d08c73e | 670 | tp->cptse = 0; |
43ad7e3e | 671 | } |
7c23b892 | 672 | |
093454e2 DF |
673 | if (e1000x_vlan_enabled(s->mac_reg) && |
674 | e1000x_is_vlan_txd(txd_lower) && | |
7d08c73e | 675 | (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) { |
8f2e8d1f | 676 | tp->vlan_needed = 1; |
d8ee2591 | 677 | stw_be_p(tp->vlan_header, |
4e60a250 | 678 | le16_to_cpu(s->mac_reg[VET])); |
d8ee2591 | 679 | stw_be_p(tp->vlan_header + 2, |
8f2e8d1f AL |
680 | le16_to_cpu(dp->upper.fields.special)); |
681 | } | |
20f3e863 | 682 | |
7c23b892 | 683 | addr = le64_to_cpu(dp->buffer_addr); |
d62644b4 ES |
684 | if (tp->cptse) { |
685 | msh = tp->tso_props.hdr_len + tp->tso_props.mss; | |
1b0009db AZ |
686 | do { |
687 | bytes = split_size; | |
3de46e6f JW |
688 | if (tp->size >= msh) { |
689 | goto eop; | |
690 | } | |
1b0009db AZ |
691 | if (tp->size + bytes > msh) |
692 | bytes = msh - tp->size; | |
65f82df0 AL |
693 | |
694 | bytes = MIN(sizeof(tp->data) - tp->size, bytes); | |
b08340d5 | 695 | pci_dma_read(d, addr, tp->data + tp->size, bytes); |
a0ae17a6 | 696 | sz = tp->size + bytes; |
d62644b4 ES |
697 | if (sz >= tp->tso_props.hdr_len |
698 | && tp->size < tp->tso_props.hdr_len) { | |
699 | memmove(tp->header, tp->data, tp->tso_props.hdr_len); | |
a0ae17a6 | 700 | } |
1b0009db AZ |
701 | tp->size = sz; |
702 | addr += bytes; | |
703 | if (sz == msh) { | |
704 | xmit_seg(s); | |
d62644b4 ES |
705 | memmove(tp->data, tp->header, tp->tso_props.hdr_len); |
706 | tp->size = tp->tso_props.hdr_len; | |
1b0009db | 707 | } |
b947ac2b PP |
708 | split_size -= bytes; |
709 | } while (bytes && split_size); | |
1b0009db | 710 | } else { |
65f82df0 | 711 | split_size = MIN(sizeof(tp->data) - tp->size, split_size); |
b08340d5 | 712 | pci_dma_read(d, addr, tp->data + tp->size, split_size); |
1b0009db | 713 | tp->size += split_size; |
7c23b892 | 714 | } |
7c23b892 | 715 | |
3de46e6f | 716 | eop: |
7c23b892 AZ |
717 | if (!(txd_lower & E1000_TXD_CMD_EOP)) |
718 | return; | |
d62644b4 | 719 | if (!(tp->cptse && tp->size < tp->tso_props.hdr_len)) { |
7c23b892 | 720 | xmit_seg(s); |
a0ae17a6 | 721 | } |
7c23b892 | 722 | tp->tso_frames = 0; |
7d08c73e | 723 | tp->sum_needed = 0; |
8f2e8d1f | 724 | tp->vlan_needed = 0; |
7c23b892 | 725 | tp->size = 0; |
7d08c73e | 726 | tp->cptse = 0; |
7c23b892 AZ |
727 | } |
728 | ||
729 | static uint32_t | |
62ecbd35 | 730 | txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp) |
7c23b892 | 731 | { |
b08340d5 | 732 | PCIDevice *d = PCI_DEVICE(s); |
7c23b892 AZ |
733 | uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); |
734 | ||
735 | if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS))) | |
736 | return 0; | |
737 | txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) & | |
738 | ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU); | |
739 | dp->upper.data = cpu_to_le32(txd_upper); | |
b08340d5 | 740 | pci_dma_write(d, base + ((char *)&dp->upper - (char *)dp), |
00c3a05b | 741 | &dp->upper, sizeof(dp->upper)); |
7c23b892 AZ |
742 | return E1000_ICR_TXDW; |
743 | } | |
744 | ||
d17161f6 KW |
745 | static uint64_t tx_desc_base(E1000State *s) |
746 | { | |
747 | uint64_t bah = s->mac_reg[TDBAH]; | |
748 | uint64_t bal = s->mac_reg[TDBAL] & ~0xf; | |
749 | ||
750 | return (bah << 32) + bal; | |
751 | } | |
752 | ||
7c23b892 AZ |
753 | static void |
754 | start_xmit(E1000State *s) | |
755 | { | |
b08340d5 | 756 | PCIDevice *d = PCI_DEVICE(s); |
62ecbd35 | 757 | dma_addr_t base; |
7c23b892 AZ |
758 | struct e1000_tx_desc desc; |
759 | uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; | |
760 | ||
761 | if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) { | |
762 | DBGOUT(TX, "tx disabled\n"); | |
763 | return; | |
764 | } | |
765 | ||
25ddb946 JM |
766 | if (s->tx.busy) { |
767 | return; | |
768 | } | |
769 | s->tx.busy = true; | |
770 | ||
7c23b892 | 771 | while (s->mac_reg[TDH] != s->mac_reg[TDT]) { |
d17161f6 | 772 | base = tx_desc_base(s) + |
7c23b892 | 773 | sizeof(struct e1000_tx_desc) * s->mac_reg[TDH]; |
b08340d5 | 774 | pci_dma_read(d, base, &desc, sizeof(desc)); |
7c23b892 AZ |
775 | |
776 | DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH], | |
6106075b | 777 | (void *)(intptr_t)desc.buffer_addr, desc.lower.data, |
7c23b892 AZ |
778 | desc.upper.data); |
779 | ||
780 | process_tx_desc(s, &desc); | |
62ecbd35 | 781 | cause |= txdesc_writeback(s, base, &desc); |
7c23b892 AZ |
782 | |
783 | if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN]) | |
784 | s->mac_reg[TDH] = 0; | |
785 | /* | |
786 | * the following could happen only if guest sw assigns | |
787 | * bogus values to TDT/TDLEN. | |
788 | * there's nothing too intelligent we could do about this. | |
789 | */ | |
dd793a74 LE |
790 | if (s->mac_reg[TDH] == tdh_start || |
791 | tdh_start >= s->mac_reg[TDLEN] / sizeof(desc)) { | |
7c23b892 AZ |
792 | DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n", |
793 | tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]); | |
794 | break; | |
795 | } | |
796 | } | |
25ddb946 | 797 | s->tx.busy = false; |
7c23b892 AZ |
798 | set_ics(s, 0, cause); |
799 | } | |
800 | ||
801 | static int | |
e9e5b930 AO |
802 | receive_filter(E1000State *s, const void *buf) |
803 | { | |
804 | return (!e1000x_is_vlan_packet(buf, s->mac_reg[VET]) || | |
805 | e1000x_rx_vlan_filter(s->mac_reg, PKT_GET_VLAN_HDR(buf))) && | |
806 | e1000x_rx_group_filter(s->mac_reg, buf); | |
7c23b892 AZ |
807 | } |
808 | ||
99ed7e30 | 809 | static void |
4e68f7a0 | 810 | e1000_set_link_status(NetClientState *nc) |
99ed7e30 | 811 | { |
cc1f0f45 | 812 | E1000State *s = qemu_get_nic_opaque(nc); |
99ed7e30 AL |
813 | uint32_t old_status = s->mac_reg[STATUS]; |
814 | ||
d4044c2a | 815 | if (nc->link_down) { |
093454e2 | 816 | e1000x_update_regs_on_link_down(s->mac_reg, s->phy_reg); |
d4044c2a | 817 | } else { |
d7a41552 | 818 | if (have_autoneg(s) && |
b7728c9f | 819 | !(s->phy_reg[MII_BMSR] & MII_BMSR_AN_COMP)) { |
093454e2 | 820 | e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer); |
6a2acedb GS |
821 | } else { |
822 | e1000_link_up(s); | |
823 | } | |
d4044c2a | 824 | } |
99ed7e30 AL |
825 | |
826 | if (s->mac_reg[STATUS] != old_status) | |
827 | set_ics(s, 0, E1000_ICR_LSC); | |
828 | } | |
829 | ||
322fd48a MT |
830 | static bool e1000_has_rxbufs(E1000State *s, size_t total_size) |
831 | { | |
832 | int bufs; | |
833 | /* Fast-path short packets */ | |
834 | if (total_size <= s->rxbuf_size) { | |
e5b8b0d4 | 835 | return s->mac_reg[RDH] != s->mac_reg[RDT]; |
322fd48a MT |
836 | } |
837 | if (s->mac_reg[RDH] < s->mac_reg[RDT]) { | |
838 | bufs = s->mac_reg[RDT] - s->mac_reg[RDH]; | |
e5b8b0d4 | 839 | } else if (s->mac_reg[RDH] > s->mac_reg[RDT]) { |
322fd48a MT |
840 | bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) + |
841 | s->mac_reg[RDT] - s->mac_reg[RDH]; | |
842 | } else { | |
843 | return false; | |
844 | } | |
845 | return total_size <= bufs * s->rxbuf_size; | |
846 | } | |
847 | ||
b8c4b67e | 848 | static bool |
4e68f7a0 | 849 | e1000_can_receive(NetClientState *nc) |
6cdfab28 | 850 | { |
cc1f0f45 | 851 | E1000State *s = qemu_get_nic_opaque(nc); |
6cdfab28 | 852 | |
093454e2 | 853 | return e1000x_rx_ready(&s->parent_obj, s->mac_reg) && |
157628d0 | 854 | e1000_has_rxbufs(s, 1) && !timer_pending(s->flush_queue_timer); |
6cdfab28 MT |
855 | } |
856 | ||
d17161f6 KW |
857 | static uint64_t rx_desc_base(E1000State *s) |
858 | { | |
859 | uint64_t bah = s->mac_reg[RDBAH]; | |
860 | uint64_t bal = s->mac_reg[RDBAL] & ~0xf; | |
861 | ||
862 | return (bah << 32) + bal; | |
863 | } | |
864 | ||
1001cf45 JW |
865 | static void |
866 | e1000_receiver_overrun(E1000State *s, size_t size) | |
867 | { | |
868 | trace_e1000_receiver_overrun(size, s->mac_reg[RDH], s->mac_reg[RDT]); | |
869 | e1000x_inc_reg_if_not_full(s->mac_reg, RNBC); | |
870 | e1000x_inc_reg_if_not_full(s->mac_reg, MPC); | |
871 | set_ics(s, 0, E1000_ICS_RXO); | |
872 | } | |
873 | ||
4f1c942b | 874 | static ssize_t |
97410dde | 875 | e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt) |
7c23b892 | 876 | { |
cc1f0f45 | 877 | E1000State *s = qemu_get_nic_opaque(nc); |
b08340d5 | 878 | PCIDevice *d = PCI_DEVICE(s); |
7c23b892 | 879 | struct e1000_rx_desc desc; |
62ecbd35 | 880 | dma_addr_t base; |
7c23b892 AZ |
881 | unsigned int n, rdt; |
882 | uint32_t rdh_start; | |
8f2e8d1f | 883 | uint16_t vlan_special = 0; |
97410dde | 884 | uint8_t vlan_status = 0; |
2fe63579 | 885 | uint8_t min_buf[ETH_ZLEN]; |
97410dde VM |
886 | uint8_t *filter_buf = iov->iov_base; |
887 | size_t size = iov_size(iov, iovcnt); | |
888 | size_t iov_ofs = 0; | |
b19487e2 MT |
889 | size_t desc_offset; |
890 | size_t desc_size; | |
891 | size_t total_size; | |
f3f9b726 | 892 | eth_pkt_types_e pkt_type; |
ddcb73b7 | 893 | |
093454e2 | 894 | if (!e1000x_hw_rx_enabled(s->mac_reg)) { |
4f1c942b | 895 | return -1; |
ddcb73b7 | 896 | } |
7c23b892 | 897 | |
157628d0 YCL |
898 | if (timer_pending(s->flush_queue_timer)) { |
899 | return 0; | |
900 | } | |
901 | ||
140eae9c | 902 | if (iov->iov_len < MAXIMUM_ETHERNET_HDR_LEN) { |
97410dde VM |
903 | /* This is very unlikely, but may happen. */ |
904 | iov_to_buf(iov, iovcnt, 0, min_buf, MAXIMUM_ETHERNET_HDR_LEN); | |
905 | filter_buf = min_buf; | |
78aeb23e SH |
906 | } |
907 | ||
b0d9ffcd | 908 | /* Discard oversized packets if !LPE and !SBP. */ |
093454e2 | 909 | if (e1000x_is_oversized(s->mac_reg, size)) { |
b0d9ffcd MC |
910 | return size; |
911 | } | |
912 | ||
e9e5b930 | 913 | if (!receive_filter(s, filter_buf)) { |
4f1c942b | 914 | return size; |
97410dde | 915 | } |
7c23b892 | 916 | |
093454e2 DF |
917 | if (e1000x_vlan_enabled(s->mac_reg) && |
918 | e1000x_is_vlan_packet(filter_buf, le16_to_cpu(s->mac_reg[VET]))) { | |
14e60aae | 919 | vlan_special = cpu_to_le16(lduw_be_p(filter_buf + 14)); |
97410dde VM |
920 | iov_ofs = 4; |
921 | if (filter_buf == iov->iov_base) { | |
922 | memmove(filter_buf + 4, filter_buf, 12); | |
923 | } else { | |
924 | iov_from_buf(iov, iovcnt, 4, filter_buf, 12); | |
925 | while (iov->iov_len <= iov_ofs) { | |
926 | iov_ofs -= iov->iov_len; | |
927 | iov++; | |
928 | } | |
929 | } | |
8f2e8d1f | 930 | vlan_status = E1000_RXD_STAT_VP; |
8f2e8d1f AL |
931 | size -= 4; |
932 | } | |
933 | ||
f3f9b726 | 934 | pkt_type = get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf)); |
7c23b892 | 935 | rdh_start = s->mac_reg[RDH]; |
b19487e2 | 936 | desc_offset = 0; |
093454e2 | 937 | total_size = size + e1000x_fcs_len(s->mac_reg); |
322fd48a | 938 | if (!e1000_has_rxbufs(s, total_size)) { |
1001cf45 JW |
939 | e1000_receiver_overrun(s, total_size); |
940 | return -1; | |
322fd48a | 941 | } |
7c23b892 | 942 | do { |
b19487e2 MT |
943 | desc_size = total_size - desc_offset; |
944 | if (desc_size > s->rxbuf_size) { | |
945 | desc_size = s->rxbuf_size; | |
946 | } | |
d17161f6 | 947 | base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH]; |
b08340d5 | 948 | pci_dma_read(d, base, &desc, sizeof(desc)); |
8f2e8d1f | 949 | desc.special = vlan_special; |
034d00d4 | 950 | desc.status &= ~E1000_RXD_STAT_DD; |
7c23b892 | 951 | if (desc.buffer_addr) { |
b19487e2 | 952 | if (desc_offset < size) { |
97410dde VM |
953 | size_t iov_copy; |
954 | hwaddr ba = le64_to_cpu(desc.buffer_addr); | |
b19487e2 MT |
955 | size_t copy_size = size - desc_offset; |
956 | if (copy_size > s->rxbuf_size) { | |
957 | copy_size = s->rxbuf_size; | |
958 | } | |
97410dde VM |
959 | do { |
960 | iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); | |
961 | pci_dma_write(d, ba, iov->iov_base + iov_ofs, iov_copy); | |
962 | copy_size -= iov_copy; | |
963 | ba += iov_copy; | |
964 | iov_ofs += iov_copy; | |
965 | if (iov_ofs == iov->iov_len) { | |
966 | iov++; | |
967 | iov_ofs = 0; | |
968 | } | |
969 | } while (copy_size); | |
b19487e2 MT |
970 | } |
971 | desc_offset += desc_size; | |
ee912ccf | 972 | desc.length = cpu_to_le16(desc_size); |
b19487e2 | 973 | if (desc_offset >= total_size) { |
b19487e2 MT |
974 | desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM; |
975 | } else { | |
ee912ccf MT |
976 | /* Guest zeroing out status is not a hardware requirement. |
977 | Clear EOP in case guest didn't do it. */ | |
978 | desc.status &= ~E1000_RXD_STAT_EOP; | |
b19487e2 | 979 | } |
43ad7e3e | 980 | } else { // as per intel docs; skip descriptors with null buf addr |
7c23b892 | 981 | DBGOUT(RX, "Null RX descriptor!!\n"); |
43ad7e3e | 982 | } |
b08340d5 | 983 | pci_dma_write(d, base, &desc, sizeof(desc)); |
034d00d4 DH |
984 | desc.status |= (vlan_status | E1000_RXD_STAT_DD); |
985 | pci_dma_write(d, base + offsetof(struct e1000_rx_desc, status), | |
986 | &desc.status, sizeof(desc.status)); | |
7c23b892 AZ |
987 | |
988 | if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) | |
989 | s->mac_reg[RDH] = 0; | |
7c23b892 | 990 | /* see comment in start_xmit; same here */ |
dd793a74 LE |
991 | if (s->mac_reg[RDH] == rdh_start || |
992 | rdh_start >= s->mac_reg[RDLEN] / sizeof(desc)) { | |
7c23b892 AZ |
993 | DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n", |
994 | rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); | |
1001cf45 | 995 | e1000_receiver_overrun(s, total_size); |
4f1c942b | 996 | return -1; |
7c23b892 | 997 | } |
b19487e2 | 998 | } while (desc_offset < total_size); |
7c23b892 | 999 | |
f3f9b726 | 1000 | e1000x_update_rx_total_stats(s->mac_reg, pkt_type, size, total_size); |
7c23b892 AZ |
1001 | |
1002 | n = E1000_ICS_RXT0; | |
1003 | if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH]) | |
1004 | rdt += s->mac_reg[RDLEN] / sizeof(desc); | |
bf16cc8f AL |
1005 | if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >> |
1006 | s->rxbuf_min_shift) | |
7c23b892 AZ |
1007 | n |= E1000_ICS_RXDMT0; |
1008 | ||
1009 | set_ics(s, 0, n); | |
4f1c942b MM |
1010 | |
1011 | return size; | |
7c23b892 AZ |
1012 | } |
1013 | ||
97410dde VM |
1014 | static ssize_t |
1015 | e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size) | |
1016 | { | |
1017 | const struct iovec iov = { | |
1018 | .iov_base = (uint8_t *)buf, | |
1019 | .iov_len = size | |
1020 | }; | |
1021 | ||
1022 | return e1000_receive_iov(nc, &iov, 1); | |
1023 | } | |
1024 | ||
7c23b892 AZ |
1025 | static uint32_t |
1026 | mac_readreg(E1000State *s, int index) | |
1027 | { | |
1028 | return s->mac_reg[index]; | |
1029 | } | |
1030 | ||
1031 | static uint32_t | |
1032 | mac_icr_read(E1000State *s, int index) | |
1033 | { | |
1034 | uint32_t ret = s->mac_reg[ICR]; | |
1035 | ||
1036 | DBGOUT(INTERRUPT, "ICR read: %x\n", ret); | |
1037 | set_interrupt_cause(s, 0, 0); | |
1038 | return ret; | |
1039 | } | |
1040 | ||
1041 | static uint32_t | |
1042 | mac_read_clr4(E1000State *s, int index) | |
1043 | { | |
1044 | uint32_t ret = s->mac_reg[index]; | |
1045 | ||
1046 | s->mac_reg[index] = 0; | |
1047 | return ret; | |
1048 | } | |
1049 | ||
1050 | static uint32_t | |
1051 | mac_read_clr8(E1000State *s, int index) | |
1052 | { | |
1053 | uint32_t ret = s->mac_reg[index]; | |
1054 | ||
1055 | s->mac_reg[index] = 0; | |
1056 | s->mac_reg[index-1] = 0; | |
1057 | return ret; | |
1058 | } | |
1059 | ||
1060 | static void | |
1061 | mac_writereg(E1000State *s, int index, uint32_t val) | |
1062 | { | |
7c36507c AK |
1063 | uint32_t macaddr[2]; |
1064 | ||
7c23b892 | 1065 | s->mac_reg[index] = val; |
7c36507c | 1066 | |
90d131fb | 1067 | if (index == RA + 1) { |
7c36507c AK |
1068 | macaddr[0] = cpu_to_le32(s->mac_reg[RA]); |
1069 | macaddr[1] = cpu_to_le32(s->mac_reg[RA + 1]); | |
1070 | qemu_format_nic_info_str(qemu_get_queue(s->nic), (uint8_t *)macaddr); | |
1071 | } | |
7c23b892 AZ |
1072 | } |
1073 | ||
1074 | static void | |
1075 | set_rdt(E1000State *s, int index, uint32_t val) | |
1076 | { | |
7c23b892 | 1077 | s->mac_reg[index] = val & 0xffff; |
e8b4c680 | 1078 | if (e1000_has_rxbufs(s, 1)) { |
b356f76d | 1079 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
e8b4c680 | 1080 | } |
7c23b892 AZ |
1081 | } |
1082 | ||
a9484b8a AO |
1083 | #define LOW_BITS_SET_FUNC(num) \ |
1084 | static void \ | |
1085 | set_##num##bit(E1000State *s, int index, uint32_t val) \ | |
1086 | { \ | |
1087 | s->mac_reg[index] = val & (BIT(num) - 1); \ | |
1088 | } | |
1089 | ||
1090 | LOW_BITS_SET_FUNC(4) | |
1091 | LOW_BITS_SET_FUNC(11) | |
1092 | LOW_BITS_SET_FUNC(13) | |
1093 | LOW_BITS_SET_FUNC(16) | |
7c23b892 AZ |
1094 | |
1095 | static void | |
1096 | set_dlen(E1000State *s, int index, uint32_t val) | |
1097 | { | |
1098 | s->mac_reg[index] = val & 0xfff80; | |
1099 | } | |
1100 | ||
1101 | static void | |
1102 | set_tctl(E1000State *s, int index, uint32_t val) | |
1103 | { | |
1104 | s->mac_reg[index] = val; | |
1105 | s->mac_reg[TDT] &= 0xffff; | |
1106 | start_xmit(s); | |
1107 | } | |
1108 | ||
1109 | static void | |
1110 | set_icr(E1000State *s, int index, uint32_t val) | |
1111 | { | |
1112 | DBGOUT(INTERRUPT, "set_icr %x\n", val); | |
1113 | set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); | |
1114 | } | |
1115 | ||
1116 | static void | |
1117 | set_imc(E1000State *s, int index, uint32_t val) | |
1118 | { | |
1119 | s->mac_reg[IMS] &= ~val; | |
1120 | set_ics(s, 0, 0); | |
1121 | } | |
1122 | ||
1123 | static void | |
1124 | set_ims(E1000State *s, int index, uint32_t val) | |
1125 | { | |
1126 | s->mac_reg[IMS] |= val; | |
1127 | set_ics(s, 0, 0); | |
1128 | } | |
1129 | ||
20f3e863 | 1130 | #define getreg(x) [x] = mac_readreg |
3b6b3a27 | 1131 | typedef uint32_t (*readops)(E1000State *, int); |
da5cf9a4 | 1132 | static const readops macreg_readops[] = { |
20f3e863 LB |
1133 | getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL), |
1134 | getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL), | |
1135 | getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS), | |
1136 | getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL), | |
1137 | getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS), | |
1138 | getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL), | |
1139 | getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV), | |
72ea771c LB |
1140 | getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV), |
1141 | getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL), | |
1142 | getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC), | |
757704f1 | 1143 | getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC), |
72ea771c LB |
1144 | getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC), |
1145 | getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC), | |
3b274301 | 1146 | getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), getreg(GORCL), |
a9484b8a AO |
1147 | getreg(GOTCL), getreg(RDFH), getreg(RDFT), getreg(RDFHS), |
1148 | getreg(RDFTS), getreg(RDFPC), getreg(TDFH), getreg(TDFT), | |
1149 | getreg(TDFHS), getreg(TDFTS), getreg(TDFPC), getreg(AIT), | |
20f3e863 LB |
1150 | |
1151 | [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, | |
3b274301 LB |
1152 | [GOTCH] = mac_read_clr8, [GORCH] = mac_read_clr8, |
1153 | [PRC64] = mac_read_clr4, [PRC127] = mac_read_clr4, | |
1154 | [PRC255] = mac_read_clr4, [PRC511] = mac_read_clr4, | |
1155 | [PRC1023] = mac_read_clr4, [PRC1522] = mac_read_clr4, | |
1156 | [PTC64] = mac_read_clr4, [PTC127] = mac_read_clr4, | |
1157 | [PTC255] = mac_read_clr4, [PTC511] = mac_read_clr4, | |
1158 | [PTC1023] = mac_read_clr4, [PTC1522] = mac_read_clr4, | |
20f3e863 LB |
1159 | [GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4, |
1160 | [TPT] = mac_read_clr4, [TPR] = mac_read_clr4, | |
3b274301 LB |
1161 | [RUC] = mac_read_clr4, [ROC] = mac_read_clr4, |
1162 | [BPRC] = mac_read_clr4, [MPRC] = mac_read_clr4, | |
1163 | [TSCTC] = mac_read_clr4, [BPTC] = mac_read_clr4, | |
1164 | [MPTC] = mac_read_clr4, | |
20f3e863 LB |
1165 | [ICR] = mac_icr_read, [EECD] = get_eecd, |
1166 | [EERD] = flash_eerd_read, | |
1167 | ||
0eadd56b AO |
1168 | [CRCERRS ... MPC] = &mac_readreg, |
1169 | [IP6AT ... IP6AT + 3] = &mac_readreg, [IP4AT ... IP4AT + 6] = &mac_readreg, | |
a9484b8a | 1170 | [FFLT ... FFLT + 6] = &mac_readreg, |
0eadd56b AO |
1171 | [RA ... RA + 31] = &mac_readreg, |
1172 | [WUPM ... WUPM + 31] = &mac_readreg, | |
2fe63579 AO |
1173 | [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = &mac_readreg, |
1174 | [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = &mac_readreg, | |
a9484b8a | 1175 | [FFMT ... FFMT + 254] = &mac_readreg, |
0eadd56b AO |
1176 | [FFVT ... FFVT + 254] = &mac_readreg, |
1177 | [PBM ... PBM + 16383] = &mac_readreg, | |
7c23b892 | 1178 | }; |
b1503cda | 1179 | enum { NREADOPS = ARRAY_SIZE(macreg_readops) }; |
7c23b892 | 1180 | |
20f3e863 | 1181 | #define putreg(x) [x] = mac_writereg |
3b6b3a27 | 1182 | typedef void (*writeops)(E1000State *, int, uint32_t); |
da5cf9a4 | 1183 | static const writeops macreg_writeops[] = { |
20f3e863 LB |
1184 | putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), |
1185 | putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), | |
72ea771c | 1186 | putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC), |
a9484b8a AO |
1187 | putreg(IPAV), putreg(WUC), |
1188 | putreg(WUS), | |
1189 | ||
1190 | [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl, | |
1191 | [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics, | |
1192 | [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt, | |
1193 | [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr, | |
1194 | [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl, | |
1195 | [RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit, | |
1196 | [ITR] = set_16bit, [TDFH] = set_11bit, [TDFT] = set_11bit, | |
1197 | [TDFHS] = set_13bit, [TDFTS] = set_13bit, [TDFPC] = set_13bit, | |
1198 | [RDFH] = set_13bit, [RDFT] = set_13bit, [RDFHS] = set_13bit, | |
1199 | [RDFTS] = set_13bit, [RDFPC] = set_13bit, [AIT] = set_16bit, | |
20f3e863 | 1200 | |
0eadd56b | 1201 | [IP6AT ... IP6AT + 3] = &mac_writereg, [IP4AT ... IP4AT + 6] = &mac_writereg, |
a9484b8a | 1202 | [FFLT ... FFLT + 6] = &set_11bit, |
0eadd56b AO |
1203 | [RA ... RA + 31] = &mac_writereg, |
1204 | [WUPM ... WUPM + 31] = &mac_writereg, | |
2fe63579 AO |
1205 | [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = &mac_writereg, |
1206 | [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = &mac_writereg, | |
a9484b8a | 1207 | [FFMT ... FFMT + 254] = &set_4bit, [FFVT ... FFVT + 254] = &mac_writereg, |
0eadd56b | 1208 | [PBM ... PBM + 16383] = &mac_writereg, |
7c23b892 | 1209 | }; |
b9d03e35 | 1210 | |
b1503cda | 1211 | enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) }; |
7c23b892 | 1212 | |
bc0f0674 LB |
1213 | enum { MAC_ACCESS_PARTIAL = 1, MAC_ACCESS_FLAG_NEEDED = 2 }; |
1214 | ||
1215 | #define markflag(x) ((E1000_FLAG_##x << 2) | MAC_ACCESS_FLAG_NEEDED) | |
1216 | /* In the array below the meaning of the bits is: [f|f|f|f|f|f|n|p] | |
1217 | * f - flag bits (up to 6 possible flags) | |
1218 | * n - flag needed | |
1219 | * p - partially implenented */ | |
1220 | static const uint8_t mac_reg_access[0x8000] = { | |
72ea771c LB |
1221 | [IPAV] = markflag(MAC), [WUC] = markflag(MAC), |
1222 | [IP6AT] = markflag(MAC), [IP4AT] = markflag(MAC), | |
1223 | [FFVT] = markflag(MAC), [WUPM] = markflag(MAC), | |
1224 | [ECOL] = markflag(MAC), [MCC] = markflag(MAC), | |
1225 | [DC] = markflag(MAC), [TNCRS] = markflag(MAC), | |
1226 | [RLEC] = markflag(MAC), [XONRXC] = markflag(MAC), | |
1227 | [XOFFTXC] = markflag(MAC), [RFC] = markflag(MAC), | |
1228 | [TSCTFC] = markflag(MAC), [MGTPRC] = markflag(MAC), | |
1229 | [WUS] = markflag(MAC), [AIT] = markflag(MAC), | |
1230 | [FFLT] = markflag(MAC), [FFMT] = markflag(MAC), | |
1231 | [SCC] = markflag(MAC), [FCRUC] = markflag(MAC), | |
1232 | [LATECOL] = markflag(MAC), [COLC] = markflag(MAC), | |
757704f1 | 1233 | [SEQEC] = markflag(MAC), [CEXTERR] = markflag(MAC), |
72ea771c LB |
1234 | [XONTXC] = markflag(MAC), [XOFFRXC] = markflag(MAC), |
1235 | [RJC] = markflag(MAC), [RNBC] = markflag(MAC), | |
1236 | [MGTPDC] = markflag(MAC), [MGTPTC] = markflag(MAC), | |
3b274301 LB |
1237 | [RUC] = markflag(MAC), [ROC] = markflag(MAC), |
1238 | [GORCL] = markflag(MAC), [GORCH] = markflag(MAC), | |
1239 | [GOTCL] = markflag(MAC), [GOTCH] = markflag(MAC), | |
1240 | [BPRC] = markflag(MAC), [MPRC] = markflag(MAC), | |
1241 | [TSCTC] = markflag(MAC), [PRC64] = markflag(MAC), | |
1242 | [PRC127] = markflag(MAC), [PRC255] = markflag(MAC), | |
1243 | [PRC511] = markflag(MAC), [PRC1023] = markflag(MAC), | |
1244 | [PRC1522] = markflag(MAC), [PTC64] = markflag(MAC), | |
1245 | [PTC127] = markflag(MAC), [PTC255] = markflag(MAC), | |
1246 | [PTC511] = markflag(MAC), [PTC1023] = markflag(MAC), | |
1247 | [PTC1522] = markflag(MAC), [MPTC] = markflag(MAC), | |
1248 | [BPTC] = markflag(MAC), | |
72ea771c LB |
1249 | |
1250 | [TDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1251 | [TDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1252 | [TDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1253 | [TDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1254 | [TDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1255 | [RDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1256 | [RDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1257 | [RDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1258 | [RDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1259 | [RDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
1260 | [PBM] = markflag(MAC) | MAC_ACCESS_PARTIAL, | |
bc0f0674 LB |
1261 | }; |
1262 | ||
7c23b892 | 1263 | static void |
a8170e5e | 1264 | e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val, |
ad00a9b9 | 1265 | unsigned size) |
7c23b892 AZ |
1266 | { |
1267 | E1000State *s = opaque; | |
8da3ff18 | 1268 | unsigned int index = (addr & 0x1ffff) >> 2; |
7c23b892 | 1269 | |
43ad7e3e | 1270 | if (index < NWRITEOPS && macreg_writeops[index]) { |
bc0f0674 LB |
1271 | if (!(mac_reg_access[index] & MAC_ACCESS_FLAG_NEEDED) |
1272 | || (s->compat_flags & (mac_reg_access[index] >> 2))) { | |
1273 | if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { | |
1274 | DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. " | |
1275 | "It is not fully implemented.\n", index<<2); | |
1276 | } | |
1277 | macreg_writeops[index](s, index, val); | |
1278 | } else { /* "flag needed" bit is set, but the flag is not active */ | |
1279 | DBGOUT(MMIO, "MMIO write attempt to disabled reg. addr=0x%08x\n", | |
1280 | index<<2); | |
1281 | } | |
43ad7e3e | 1282 | } else if (index < NREADOPS && macreg_readops[index]) { |
bc0f0674 LB |
1283 | DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", |
1284 | index<<2, val); | |
43ad7e3e | 1285 | } else { |
ad00a9b9 | 1286 | DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n", |
7c23b892 | 1287 | index<<2, val); |
43ad7e3e | 1288 | } |
7c23b892 AZ |
1289 | } |
1290 | ||
ad00a9b9 | 1291 | static uint64_t |
a8170e5e | 1292 | e1000_mmio_read(void *opaque, hwaddr addr, unsigned size) |
7c23b892 AZ |
1293 | { |
1294 | E1000State *s = opaque; | |
8da3ff18 | 1295 | unsigned int index = (addr & 0x1ffff) >> 2; |
7c23b892 | 1296 | |
bc0f0674 LB |
1297 | if (index < NREADOPS && macreg_readops[index]) { |
1298 | if (!(mac_reg_access[index] & MAC_ACCESS_FLAG_NEEDED) | |
1299 | || (s->compat_flags & (mac_reg_access[index] >> 2))) { | |
1300 | if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { | |
1301 | DBGOUT(GENERAL, "Reading register at offset: 0x%08x. " | |
1302 | "It is not fully implemented.\n", index<<2); | |
1303 | } | |
1304 | return macreg_readops[index](s, index); | |
1305 | } else { /* "flag needed" bit is set, but the flag is not active */ | |
1306 | DBGOUT(MMIO, "MMIO read attempt of disabled reg. addr=0x%08x\n", | |
1307 | index<<2); | |
1308 | } | |
1309 | } else { | |
1310 | DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); | |
6b59fc74 | 1311 | } |
7c23b892 AZ |
1312 | return 0; |
1313 | } | |
1314 | ||
ad00a9b9 AK |
1315 | static const MemoryRegionOps e1000_mmio_ops = { |
1316 | .read = e1000_mmio_read, | |
1317 | .write = e1000_mmio_write, | |
1318 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1319 | .impl = { | |
1320 | .min_access_size = 4, | |
1321 | .max_access_size = 4, | |
1322 | }, | |
1323 | }; | |
1324 | ||
a8170e5e | 1325 | static uint64_t e1000_io_read(void *opaque, hwaddr addr, |
ad00a9b9 | 1326 | unsigned size) |
7c23b892 | 1327 | { |
ad00a9b9 AK |
1328 | E1000State *s = opaque; |
1329 | ||
1330 | (void)s; | |
1331 | return 0; | |
7c23b892 AZ |
1332 | } |
1333 | ||
a8170e5e | 1334 | static void e1000_io_write(void *opaque, hwaddr addr, |
ad00a9b9 | 1335 | uint64_t val, unsigned size) |
7c23b892 | 1336 | { |
ad00a9b9 AK |
1337 | E1000State *s = opaque; |
1338 | ||
1339 | (void)s; | |
7c23b892 AZ |
1340 | } |
1341 | ||
ad00a9b9 AK |
1342 | static const MemoryRegionOps e1000_io_ops = { |
1343 | .read = e1000_io_read, | |
1344 | .write = e1000_io_write, | |
1345 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1346 | }; | |
1347 | ||
e482dc3e | 1348 | static bool is_version_1(void *opaque, int version_id) |
7c23b892 | 1349 | { |
e482dc3e | 1350 | return version_id == 1; |
7c23b892 AZ |
1351 | } |
1352 | ||
44b1ff31 | 1353 | static int e1000_pre_save(void *opaque) |
ddcb73b7 MT |
1354 | { |
1355 | E1000State *s = opaque; | |
1356 | NetClientState *nc = qemu_get_queue(s->nic); | |
2af234e6 | 1357 | |
ddcb73b7 | 1358 | /* |
6a2acedb GS |
1359 | * If link is down and auto-negotiation is supported and ongoing, |
1360 | * complete auto-negotiation immediately. This allows us to look | |
b7728c9f | 1361 | * at MII_BMSR_AN_COMP to infer link status on load. |
ddcb73b7 | 1362 | */ |
d7a41552 | 1363 | if (nc->link_down && have_autoneg(s)) { |
b7728c9f | 1364 | s->phy_reg[MII_BMSR] |= MII_BMSR_AN_COMP; |
ddcb73b7 | 1365 | } |
44b1ff31 | 1366 | |
ff214d42 DDAG |
1367 | /* Decide which set of props to migrate in the main structure */ |
1368 | if (chkflag(TSO) || !s->use_tso_for_migration) { | |
1369 | /* Either we're migrating with the extra subsection, in which | |
1370 | * case the mig_props is always 'props' OR | |
1371 | * we've not got the subsection, but 'props' was the last | |
1372 | * updated. | |
1373 | */ | |
1374 | s->mig_props = s->tx.props; | |
1375 | } else { | |
1376 | /* We're not using the subsection, and 'tso_props' was | |
1377 | * the last updated. | |
1378 | */ | |
1379 | s->mig_props = s->tx.tso_props; | |
1380 | } | |
44b1ff31 | 1381 | return 0; |
ddcb73b7 MT |
1382 | } |
1383 | ||
e4b82364 AK |
1384 | static int e1000_post_load(void *opaque, int version_id) |
1385 | { | |
1386 | E1000State *s = opaque; | |
b356f76d | 1387 | NetClientState *nc = qemu_get_queue(s->nic); |
e4b82364 | 1388 | |
e9845f09 | 1389 | s->mit_ide = 0; |
f46efa9b JW |
1390 | s->mit_timer_on = true; |
1391 | timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1); | |
e9845f09 | 1392 | |
e4b82364 | 1393 | /* nc.link_down can't be migrated, so infer link_down according |
ddcb73b7 MT |
1394 | * to link status bit in mac_reg[STATUS]. |
1395 | * Alternatively, restart link negotiation if it was in progress. */ | |
b356f76d | 1396 | nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0; |
2af234e6 | 1397 | |
b7728c9f | 1398 | if (have_autoneg(s) && !(s->phy_reg[MII_BMSR] & MII_BMSR_AN_COMP)) { |
ddcb73b7 | 1399 | nc->link_down = false; |
d7a41552 GS |
1400 | timer_mod(s->autoneg_timer, |
1401 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); | |
ddcb73b7 | 1402 | } |
e4b82364 | 1403 | |
59354484 | 1404 | s->tx.props = s->mig_props; |
3c4053c5 DDAG |
1405 | if (!s->received_tx_tso) { |
1406 | /* We received only one set of offload data (tx.props) | |
1407 | * and haven't got tx.tso_props. The best we can do | |
1408 | * is dupe the data. | |
1409 | */ | |
59354484 | 1410 | s->tx.tso_props = s->mig_props; |
3c4053c5 DDAG |
1411 | } |
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | static int e1000_tx_tso_post_load(void *opaque, int version_id) | |
1416 | { | |
1417 | E1000State *s = opaque; | |
1418 | s->received_tx_tso = true; | |
e4b82364 AK |
1419 | return 0; |
1420 | } | |
1421 | ||
9e117734 LB |
1422 | static bool e1000_full_mac_needed(void *opaque) |
1423 | { | |
1424 | E1000State *s = opaque; | |
1425 | ||
bc0f0674 | 1426 | return chkflag(MAC); |
9e117734 LB |
1427 | } |
1428 | ||
46f2a9ec DDAG |
1429 | static bool e1000_tso_state_needed(void *opaque) |
1430 | { | |
1431 | E1000State *s = opaque; | |
1432 | ||
1433 | return chkflag(TSO); | |
1434 | } | |
1435 | ||
e9845f09 VM |
1436 | static const VMStateDescription vmstate_e1000_mit_state = { |
1437 | .name = "e1000/mit_state", | |
1438 | .version_id = 1, | |
1439 | .minimum_version_id = 1, | |
1de81b42 | 1440 | .fields = (const VMStateField[]) { |
e9845f09 VM |
1441 | VMSTATE_UINT32(mac_reg[RDTR], E1000State), |
1442 | VMSTATE_UINT32(mac_reg[RADV], E1000State), | |
1443 | VMSTATE_UINT32(mac_reg[TADV], E1000State), | |
1444 | VMSTATE_UINT32(mac_reg[ITR], E1000State), | |
1445 | VMSTATE_BOOL(mit_irq_level, E1000State), | |
1446 | VMSTATE_END_OF_LIST() | |
1447 | } | |
1448 | }; | |
1449 | ||
9e117734 LB |
1450 | static const VMStateDescription vmstate_e1000_full_mac_state = { |
1451 | .name = "e1000/full_mac_state", | |
1452 | .version_id = 1, | |
1453 | .minimum_version_id = 1, | |
1454 | .needed = e1000_full_mac_needed, | |
1de81b42 | 1455 | .fields = (const VMStateField[]) { |
9e117734 LB |
1456 | VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000), |
1457 | VMSTATE_END_OF_LIST() | |
1458 | } | |
1459 | }; | |
1460 | ||
4ae4bf5b DDAG |
1461 | static const VMStateDescription vmstate_e1000_tx_tso_state = { |
1462 | .name = "e1000/tx_tso_state", | |
1463 | .version_id = 1, | |
1464 | .minimum_version_id = 1, | |
46f2a9ec | 1465 | .needed = e1000_tso_state_needed, |
3c4053c5 | 1466 | .post_load = e1000_tx_tso_post_load, |
1de81b42 | 1467 | .fields = (const VMStateField[]) { |
4ae4bf5b DDAG |
1468 | VMSTATE_UINT8(tx.tso_props.ipcss, E1000State), |
1469 | VMSTATE_UINT8(tx.tso_props.ipcso, E1000State), | |
1470 | VMSTATE_UINT16(tx.tso_props.ipcse, E1000State), | |
1471 | VMSTATE_UINT8(tx.tso_props.tucss, E1000State), | |
1472 | VMSTATE_UINT8(tx.tso_props.tucso, E1000State), | |
1473 | VMSTATE_UINT16(tx.tso_props.tucse, E1000State), | |
1474 | VMSTATE_UINT32(tx.tso_props.paylen, E1000State), | |
1475 | VMSTATE_UINT8(tx.tso_props.hdr_len, E1000State), | |
1476 | VMSTATE_UINT16(tx.tso_props.mss, E1000State), | |
1477 | VMSTATE_INT8(tx.tso_props.ip, E1000State), | |
1478 | VMSTATE_INT8(tx.tso_props.tcp, E1000State), | |
1479 | VMSTATE_END_OF_LIST() | |
1480 | } | |
1481 | }; | |
1482 | ||
e482dc3e JQ |
1483 | static const VMStateDescription vmstate_e1000 = { |
1484 | .name = "e1000", | |
4ae4bf5b | 1485 | .version_id = 2, |
e482dc3e | 1486 | .minimum_version_id = 1, |
ddcb73b7 | 1487 | .pre_save = e1000_pre_save, |
e4b82364 | 1488 | .post_load = e1000_post_load, |
1de81b42 | 1489 | .fields = (const VMStateField[]) { |
b08340d5 | 1490 | VMSTATE_PCI_DEVICE(parent_obj, E1000State), |
e482dc3e JQ |
1491 | VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */ |
1492 | VMSTATE_UNUSED(4), /* Was mmio_base. */ | |
1493 | VMSTATE_UINT32(rxbuf_size, E1000State), | |
1494 | VMSTATE_UINT32(rxbuf_min_shift, E1000State), | |
1495 | VMSTATE_UINT32(eecd_state.val_in, E1000State), | |
1496 | VMSTATE_UINT16(eecd_state.bitnum_in, E1000State), | |
1497 | VMSTATE_UINT16(eecd_state.bitnum_out, E1000State), | |
1498 | VMSTATE_UINT16(eecd_state.reading, E1000State), | |
1499 | VMSTATE_UINT32(eecd_state.old_eecd, E1000State), | |
59354484 DDAG |
1500 | VMSTATE_UINT8(mig_props.ipcss, E1000State), |
1501 | VMSTATE_UINT8(mig_props.ipcso, E1000State), | |
1502 | VMSTATE_UINT16(mig_props.ipcse, E1000State), | |
1503 | VMSTATE_UINT8(mig_props.tucss, E1000State), | |
1504 | VMSTATE_UINT8(mig_props.tucso, E1000State), | |
1505 | VMSTATE_UINT16(mig_props.tucse, E1000State), | |
1506 | VMSTATE_UINT32(mig_props.paylen, E1000State), | |
1507 | VMSTATE_UINT8(mig_props.hdr_len, E1000State), | |
1508 | VMSTATE_UINT16(mig_props.mss, E1000State), | |
e482dc3e JQ |
1509 | VMSTATE_UINT16(tx.size, E1000State), |
1510 | VMSTATE_UINT16(tx.tso_frames, E1000State), | |
7d08c73e | 1511 | VMSTATE_UINT8(tx.sum_needed, E1000State), |
59354484 DDAG |
1512 | VMSTATE_INT8(mig_props.ip, E1000State), |
1513 | VMSTATE_INT8(mig_props.tcp, E1000State), | |
e482dc3e JQ |
1514 | VMSTATE_BUFFER(tx.header, E1000State), |
1515 | VMSTATE_BUFFER(tx.data, E1000State), | |
1516 | VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64), | |
1517 | VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20), | |
1518 | VMSTATE_UINT32(mac_reg[CTRL], E1000State), | |
1519 | VMSTATE_UINT32(mac_reg[EECD], E1000State), | |
1520 | VMSTATE_UINT32(mac_reg[EERD], E1000State), | |
1521 | VMSTATE_UINT32(mac_reg[GPRC], E1000State), | |
1522 | VMSTATE_UINT32(mac_reg[GPTC], E1000State), | |
1523 | VMSTATE_UINT32(mac_reg[ICR], E1000State), | |
1524 | VMSTATE_UINT32(mac_reg[ICS], E1000State), | |
1525 | VMSTATE_UINT32(mac_reg[IMC], E1000State), | |
1526 | VMSTATE_UINT32(mac_reg[IMS], E1000State), | |
1527 | VMSTATE_UINT32(mac_reg[LEDCTL], E1000State), | |
1528 | VMSTATE_UINT32(mac_reg[MANC], E1000State), | |
1529 | VMSTATE_UINT32(mac_reg[MDIC], E1000State), | |
1530 | VMSTATE_UINT32(mac_reg[MPC], E1000State), | |
1531 | VMSTATE_UINT32(mac_reg[PBA], E1000State), | |
1532 | VMSTATE_UINT32(mac_reg[RCTL], E1000State), | |
1533 | VMSTATE_UINT32(mac_reg[RDBAH], E1000State), | |
1534 | VMSTATE_UINT32(mac_reg[RDBAL], E1000State), | |
1535 | VMSTATE_UINT32(mac_reg[RDH], E1000State), | |
1536 | VMSTATE_UINT32(mac_reg[RDLEN], E1000State), | |
1537 | VMSTATE_UINT32(mac_reg[RDT], E1000State), | |
1538 | VMSTATE_UINT32(mac_reg[STATUS], E1000State), | |
1539 | VMSTATE_UINT32(mac_reg[SWSM], E1000State), | |
1540 | VMSTATE_UINT32(mac_reg[TCTL], E1000State), | |
1541 | VMSTATE_UINT32(mac_reg[TDBAH], E1000State), | |
1542 | VMSTATE_UINT32(mac_reg[TDBAL], E1000State), | |
1543 | VMSTATE_UINT32(mac_reg[TDH], E1000State), | |
1544 | VMSTATE_UINT32(mac_reg[TDLEN], E1000State), | |
1545 | VMSTATE_UINT32(mac_reg[TDT], E1000State), | |
1546 | VMSTATE_UINT32(mac_reg[TORH], E1000State), | |
1547 | VMSTATE_UINT32(mac_reg[TORL], E1000State), | |
1548 | VMSTATE_UINT32(mac_reg[TOTH], E1000State), | |
1549 | VMSTATE_UINT32(mac_reg[TOTL], E1000State), | |
1550 | VMSTATE_UINT32(mac_reg[TPR], E1000State), | |
1551 | VMSTATE_UINT32(mac_reg[TPT], E1000State), | |
1552 | VMSTATE_UINT32(mac_reg[TXDCTL], E1000State), | |
1553 | VMSTATE_UINT32(mac_reg[WUFC], E1000State), | |
1554 | VMSTATE_UINT32(mac_reg[VET], E1000State), | |
1555 | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32), | |
2fe63579 AO |
1556 | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, E1000_MC_TBL_SIZE), |
1557 | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, | |
1558 | E1000_VLAN_FILTER_TBL_SIZE), | |
e482dc3e | 1559 | VMSTATE_END_OF_LIST() |
e9845f09 | 1560 | }, |
1de81b42 | 1561 | .subsections = (const VMStateDescription * const []) { |
5cd8cada | 1562 | &vmstate_e1000_mit_state, |
9e117734 | 1563 | &vmstate_e1000_full_mac_state, |
4ae4bf5b | 1564 | &vmstate_e1000_tx_tso_state, |
5cd8cada | 1565 | NULL |
e482dc3e JQ |
1566 | } |
1567 | }; | |
7c23b892 | 1568 | |
8597f2e1 GS |
1569 | /* |
1570 | * EEPROM contents documented in Tables 5-2 and 5-3, pp. 98-102. | |
80867bdb | 1571 | * Note: A valid DevId will be inserted during pci_e1000_realize(). |
8597f2e1 | 1572 | */ |
88b4e9db | 1573 | static const uint16_t e1000_eeprom_template[64] = { |
7c23b892 | 1574 | 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000, |
8597f2e1 | 1575 | 0x3000, 0x1000, 0x6403, 0 /*DevId*/, 0x8086, 0 /*DevId*/, 0x8086, 0x3040, |
7c23b892 AZ |
1576 | 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700, |
1577 | 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706, | |
1578 | 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff, | |
1579 | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
1580 | 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
1581 | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, | |
1582 | }; | |
1583 | ||
7c23b892 AZ |
1584 | /* PCI interface */ |
1585 | ||
7c23b892 | 1586 | static void |
ad00a9b9 | 1587 | e1000_mmio_setup(E1000State *d) |
7c23b892 | 1588 | { |
f65ed4c1 AL |
1589 | int i; |
1590 | const uint32_t excluded_regs[] = { | |
1591 | E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS, | |
1592 | E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE | |
1593 | }; | |
1594 | ||
eedfac6f PB |
1595 | memory_region_init_io(&d->mmio, OBJECT(d), &e1000_mmio_ops, d, |
1596 | "e1000-mmio", PNPMMIO_SIZE); | |
ad00a9b9 | 1597 | memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]); |
f65ed4c1 | 1598 | for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++) |
ad00a9b9 AK |
1599 | memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4, |
1600 | excluded_regs[i+1] - excluded_regs[i] - 4); | |
eedfac6f | 1601 | memory_region_init_io(&d->io, OBJECT(d), &e1000_io_ops, d, "e1000-io", IOPORT_SIZE); |
7c23b892 AZ |
1602 | } |
1603 | ||
f90c2bcd | 1604 | static void |
4b09be85 AL |
1605 | pci_e1000_uninit(PCIDevice *dev) |
1606 | { | |
567a3c9e | 1607 | E1000State *d = E1000(dev); |
4b09be85 | 1608 | |
bc72ad67 | 1609 | timer_free(d->autoneg_timer); |
e9845f09 | 1610 | timer_free(d->mit_timer); |
157628d0 | 1611 | timer_free(d->flush_queue_timer); |
948ecf21 | 1612 | qemu_del_nic(d->nic); |
4b09be85 AL |
1613 | } |
1614 | ||
a03e2aec | 1615 | static NetClientInfo net_e1000_info = { |
f394b2e2 | 1616 | .type = NET_CLIENT_DRIVER_NIC, |
a03e2aec MM |
1617 | .size = sizeof(NICState), |
1618 | .can_receive = e1000_can_receive, | |
1619 | .receive = e1000_receive, | |
97410dde | 1620 | .receive_iov = e1000_receive_iov, |
a03e2aec MM |
1621 | .link_status_changed = e1000_set_link_status, |
1622 | }; | |
1623 | ||
20302e71 MT |
1624 | static void e1000_write_config(PCIDevice *pci_dev, uint32_t address, |
1625 | uint32_t val, int len) | |
1626 | { | |
1627 | E1000State *s = E1000(pci_dev); | |
1628 | ||
1629 | pci_default_write_config(pci_dev, address, val, len); | |
1630 | ||
1631 | if (range_covers_byte(address, len, PCI_COMMAND) && | |
1632 | (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { | |
1633 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | |
1634 | } | |
1635 | } | |
1636 | ||
9af21dbe | 1637 | static void pci_e1000_realize(PCIDevice *pci_dev, Error **errp) |
7c23b892 | 1638 | { |
567a3c9e PC |
1639 | DeviceState *dev = DEVICE(pci_dev); |
1640 | E1000State *d = E1000(pci_dev); | |
7c23b892 | 1641 | uint8_t *pci_conf; |
fbdaa002 | 1642 | uint8_t *macaddr; |
aff427a1 | 1643 | |
20302e71 MT |
1644 | pci_dev->config_write = e1000_write_config; |
1645 | ||
b08340d5 | 1646 | pci_conf = pci_dev->config; |
7c23b892 | 1647 | |
a9cbacb0 MT |
1648 | /* TODO: RST# value should be 0, PCI spec 6.2.4 */ |
1649 | pci_conf[PCI_CACHE_LINE_SIZE] = 0x10; | |
7c23b892 | 1650 | |
817e0b6f | 1651 | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ |
7c23b892 | 1652 | |
ad00a9b9 | 1653 | e1000_mmio_setup(d); |
7c23b892 | 1654 | |
b08340d5 | 1655 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); |
7c23b892 | 1656 | |
b08340d5 | 1657 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io); |
7c23b892 | 1658 | |
fbdaa002 GH |
1659 | qemu_macaddr_default_if_unset(&d->conf.macaddr); |
1660 | macaddr = d->conf.macaddr.a; | |
093454e2 DF |
1661 | |
1662 | e1000x_core_prepare_eeprom(d->eeprom_data, | |
1663 | e1000_eeprom_template, | |
1664 | sizeof(e1000_eeprom_template), | |
1665 | PCI_DEVICE_GET_CLASS(pci_dev)->device_id, | |
1666 | macaddr); | |
7c23b892 | 1667 | |
a03e2aec | 1668 | d->nic = qemu_new_nic(&net_e1000_info, &d->conf, |
7d0fefdf AO |
1669 | object_get_typename(OBJECT(d)), dev->id, |
1670 | &dev->mem_reentrancy_guard, d); | |
7c23b892 | 1671 | |
b356f76d | 1672 | qemu_format_nic_info_str(qemu_get_queue(d->nic), macaddr); |
1ca4d09a | 1673 | |
bc72ad67 | 1674 | d->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, e1000_autoneg_timer, d); |
e9845f09 | 1675 | d->mit_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000_mit_timer, d); |
157628d0 YCL |
1676 | d->flush_queue_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, |
1677 | e1000_flush_queue_timer, d); | |
9d07d757 | 1678 | } |
72da4208 | 1679 | |
40021f08 AL |
1680 | static Property e1000_properties[] = { |
1681 | DEFINE_NIC_PROPERTIES(E1000State, conf), | |
ba63ec85 LB |
1682 | DEFINE_PROP_BIT("extra_mac_registers", E1000State, |
1683 | compat_flags, E1000_FLAG_MAC_BIT, true), | |
46f2a9ec DDAG |
1684 | DEFINE_PROP_BIT("migrate_tso_props", E1000State, |
1685 | compat_flags, E1000_FLAG_TSO_BIT, true), | |
a1d7e475 CW |
1686 | DEFINE_PROP_BIT("init-vet", E1000State, |
1687 | compat_flags, E1000_FLAG_VET_BIT, true), | |
40021f08 AL |
1688 | DEFINE_PROP_END_OF_LIST(), |
1689 | }; | |
1690 | ||
8597f2e1 GS |
1691 | typedef struct E1000Info { |
1692 | const char *name; | |
1693 | uint16_t device_id; | |
1694 | uint8_t revision; | |
1695 | uint16_t phy_id2; | |
8597f2e1 GS |
1696 | } E1000Info; |
1697 | ||
40021f08 AL |
1698 | static void e1000_class_init(ObjectClass *klass, void *data) |
1699 | { | |
39bffca2 | 1700 | DeviceClass *dc = DEVICE_CLASS(klass); |
9d465053 | 1701 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
40021f08 | 1702 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
c51325d8 | 1703 | E1000BaseClass *e = E1000_CLASS(klass); |
8597f2e1 | 1704 | const E1000Info *info = data; |
40021f08 | 1705 | |
9af21dbe | 1706 | k->realize = pci_e1000_realize; |
40021f08 | 1707 | k->exit = pci_e1000_uninit; |
c45e5b5b | 1708 | k->romfile = "efi-e1000.rom"; |
40021f08 | 1709 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
8597f2e1 GS |
1710 | k->device_id = info->device_id; |
1711 | k->revision = info->revision; | |
1712 | e->phy_id2 = info->phy_id2; | |
40021f08 | 1713 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; |
9d465053 | 1714 | rc->phases.hold = e1000_reset_hold; |
125ee0ed | 1715 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
39bffca2 | 1716 | dc->desc = "Intel Gigabit Ethernet"; |
39bffca2 | 1717 | dc->vmsd = &vmstate_e1000; |
4f67d30b | 1718 | device_class_set_props(dc, e1000_properties); |
40021f08 AL |
1719 | } |
1720 | ||
5df3bf62 GA |
1721 | static void e1000_instance_init(Object *obj) |
1722 | { | |
1723 | E1000State *n = E1000(obj); | |
1724 | device_add_bootindex_property(obj, &n->conf.bootindex, | |
1725 | "bootindex", "/ethernet-phy@0", | |
40c2281c | 1726 | DEVICE(n)); |
5df3bf62 GA |
1727 | } |
1728 | ||
8597f2e1 GS |
1729 | static const TypeInfo e1000_base_info = { |
1730 | .name = TYPE_E1000_BASE, | |
39bffca2 AL |
1731 | .parent = TYPE_PCI_DEVICE, |
1732 | .instance_size = sizeof(E1000State), | |
5df3bf62 | 1733 | .instance_init = e1000_instance_init, |
8597f2e1 GS |
1734 | .class_size = sizeof(E1000BaseClass), |
1735 | .abstract = true, | |
fd3b02c8 EH |
1736 | .interfaces = (InterfaceInfo[]) { |
1737 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1738 | { }, | |
1739 | }, | |
8597f2e1 GS |
1740 | }; |
1741 | ||
1742 | static const E1000Info e1000_devices[] = { | |
1743 | { | |
83044020 | 1744 | .name = "e1000", |
8597f2e1 GS |
1745 | .device_id = E1000_DEV_ID_82540EM, |
1746 | .revision = 0x03, | |
1747 | .phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT, | |
1748 | }, | |
1749 | { | |
1750 | .name = "e1000-82544gc", | |
1751 | .device_id = E1000_DEV_ID_82544GC_COPPER, | |
1752 | .revision = 0x03, | |
1753 | .phy_id2 = E1000_PHY_ID2_82544x, | |
1754 | }, | |
1755 | { | |
1756 | .name = "e1000-82545em", | |
1757 | .device_id = E1000_DEV_ID_82545EM_COPPER, | |
1758 | .revision = 0x03, | |
1759 | .phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT, | |
1760 | }, | |
8597f2e1 GS |
1761 | }; |
1762 | ||
83f7d43a | 1763 | static void e1000_register_types(void) |
9d07d757 | 1764 | { |
8597f2e1 GS |
1765 | int i; |
1766 | ||
1767 | type_register_static(&e1000_base_info); | |
1768 | for (i = 0; i < ARRAY_SIZE(e1000_devices); i++) { | |
1769 | const E1000Info *info = &e1000_devices[i]; | |
1770 | TypeInfo type_info = {}; | |
1771 | ||
1772 | type_info.name = info->name; | |
1773 | type_info.parent = TYPE_E1000_BASE; | |
1774 | type_info.class_data = (void *)info; | |
1775 | type_info.class_init = e1000_class_init; | |
1776 | ||
1777 | type_register(&type_info); | |
1778 | } | |
7c23b892 | 1779 | } |
9d07d757 | 1780 | |
83f7d43a | 1781 | type_init(e1000_register_types) |