[mirror_qemu.git] / hw / net / fsl_etsec / etsec.c

/*
 * QEMU Freescale eTSEC Emulator
 *
 * Copyright (c) 2011-2013 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/*
 * This implementation doesn't include ring priority, TCP/IP Off-Load, QoS.
 */

#include "qemu/osdep.h"
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
#include "hw/ptimer.h"
#include "etsec.h"
#include "registers.h"
#include "qemu/log.h"

/* #define HEX_DUMP */
/* #define DEBUG_REGISTER */

#ifdef DEBUG_REGISTER
static const int debug_etsec = 1;
#else
static const int debug_etsec;
#endif

#define DPRINTF(fmt, ...) do {                 \
    if (debug_etsec) {                         \
        qemu_log(fmt , ## __VA_ARGS__);        \
    }                                          \
    } while (0)

/* call after any change to IEVENT or IMASK */
void etsec_update_irq(eTSEC *etsec)
{
    uint32_t ievent = etsec->regs[IEVENT].value;
    uint32_t imask  = etsec->regs[IMASK].value;
    uint32_t active = ievent & imask;

    int tx  = !!(active & IEVENT_TX_MASK);
    int rx  = !!(active & IEVENT_RX_MASK);
    int err = !!(active & IEVENT_ERR_MASK);

    DPRINTF("%s IRQ ievent=%"PRIx32" imask=%"PRIx32" %c%c%c",
            __func__, ievent, imask,
            tx  ? 'T' : '_',
            rx  ? 'R' : '_',
            err ? 'E' : '_');

    qemu_set_irq(etsec->tx_irq, tx);
    qemu_set_irq(etsec->rx_irq, rx);
    qemu_set_irq(etsec->err_irq, err);
}

static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
{
    eTSEC          *etsec     = opaque;
    uint32_t        reg_index = addr / 4;
    eTSEC_Register *reg       = NULL;
    uint32_t        ret       = 0x0;

    assert(reg_index < ETSEC_REG_NUMBER);

    reg = &etsec->regs[reg_index];


    switch (reg->access) {
    case ACC_WO:
        ret = 0x00000000;
        break;

    case ACC_RW:
    case ACC_W1C:
    case ACC_RO:
    default:
        ret = reg->value;
        break;
    }

    DPRINTF("Read  0x%08x @ 0x" TARGET_FMT_plx
            "                            : %s (%s)\n",
            ret, addr, reg->name, reg->desc);

    return ret;
}

static void write_tstat(eTSEC          *etsec,
                        eTSEC_Register *reg,
                        uint32_t        reg_index,
                        uint32_t        value)
{
    int i = 0;

    for (i = 0; i < 8; i++) {
        /* Check THLTi flag in TSTAT */
        if (value & (1 << (31 - i))) {
            etsec_walk_tx_ring(etsec, i);
        }
    }

    /* Write 1 to clear */
    reg->value &= ~value;
}

static void write_rstat(eTSEC          *etsec,
                        eTSEC_Register *reg,
                        uint32_t        reg_index,
                        uint32_t        value)
{
    int i = 0;

    for (i = 0; i < 8; i++) {
        /* Check QHLTi flag in RSTAT */
        if (value & (1 << (23 - i)) && !(reg->value & (1 << (23 - i)))) {
            etsec_walk_rx_ring(etsec, i);
        }
    }

    /* Write 1 to clear */
    reg->value &= ~value;
}

static void write_tbasex(eTSEC          *etsec,
                         eTSEC_Register *reg,
                         uint32_t        reg_index,
                         uint32_t        value)
{
    reg->value = value & ~0x7;

    /* Copy this value in the ring's TxBD pointer */
    etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7;
}

static void write_rbasex(eTSEC          *etsec,
                         eTSEC_Register *reg,
                         uint32_t        reg_index,
                         uint32_t        value)
{
    reg->value = value & ~0x7;

    /* Copy this value in the ring's RxBD pointer */
    etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;
}

static void write_dmactrl(eTSEC          *etsec,
                          eTSEC_Register *reg,
                          uint32_t        reg_index,
                          uint32_t        value)
{
    reg->value = value;

    if (value & DMACTRL_GRS) {

        if (etsec->rx_buffer_len != 0) {
            /* Graceful receive stop delayed until end of frame */
        } else {
            /* Graceful receive stop now */
            etsec->regs[IEVENT].value |= IEVENT_GRSC;
            etsec_update_irq(etsec);
        }
    }

    if (value & DMACTRL_GTS) {

        if (etsec->tx_buffer_len != 0) {
            /* Graceful transmit stop delayed until end of frame */
        } else {
            /* Graceful transmit stop now */
            etsec->regs[IEVENT].value |= IEVENT_GTSC;
            etsec_update_irq(etsec);
        }
    }

    if (!(value & DMACTRL_WOP)) {
        /* Start polling */
        ptimer_stop(etsec->ptimer);
        ptimer_set_count(etsec->ptimer, 1);
        ptimer_run(etsec->ptimer, 1);
    }
}

static void etsec_write(void     *opaque,
                        hwaddr    addr,
                        uint64_t  value,
                        unsigned  size)
{
    eTSEC          *etsec     = opaque;
    uint32_t        reg_index = addr / 4;
    eTSEC_Register *reg       = NULL;
    uint32_t        before    = 0x0;

    assert(reg_index < ETSEC_REG_NUMBER);

    reg = &etsec->regs[reg_index];
    before = reg->value;

    switch (reg_index) {
    case IEVENT:
        /* Write 1 to clear */
        reg->value &= ~value;

        etsec_update_irq(etsec);
        break;

    case IMASK:
        reg->value = value;

        etsec_update_irq(etsec);
        break;

    case DMACTRL:
        write_dmactrl(etsec, reg, reg_index, value);
        break;

    case TSTAT:
        write_tstat(etsec, reg, reg_index, value);
        break;

    case RSTAT:
        write_rstat(etsec, reg, reg_index, value);
        break;

    case TBASE0 ... TBASE7:
        write_tbasex(etsec, reg, reg_index, value);
        break;

    case RBASE0 ... RBASE7:
        write_rbasex(etsec, reg, reg_index, value);
        break;

    case MIIMCFG ... MIIMIND:
        etsec_write_miim(etsec, reg, reg_index, value);
        break;

    default:
        /* Default handling */
        switch (reg->access) {

        case ACC_RW:
        case ACC_WO:
            reg->value = value;
            break;

        case ACC_W1C:
            reg->value &= ~value;
            break;

        case ACC_RO:
        default:
            /* Read Only or Unknown register */
            break;
        }
    }

    DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
            " val:0x%08x->0x%08x : %s (%s)\n",
            (unsigned int)value, addr, before, reg->value,
            reg->name, reg->desc);
}

static const MemoryRegionOps etsec_ops = {
    .read = etsec_read,
    .write = etsec_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void etsec_timer_hit(void *opaque)
{
    eTSEC *etsec = opaque;

    ptimer_stop(etsec->ptimer);

    if (!(etsec->regs[DMACTRL].value & DMACTRL_WOP)) {

        if (!(etsec->regs[DMACTRL].value & DMACTRL_GTS)) {
            etsec_walk_tx_ring(etsec, 0);
        }
        ptimer_set_count(etsec->ptimer, 1);
        ptimer_run(etsec->ptimer, 1);
    }
}

static void etsec_reset(DeviceState *d)
{
    eTSEC *etsec = ETSEC_COMMON(d);
    int i = 0;
    int reg_index = 0;

    /* Default value for all registers */
    for (i = 0; i < ETSEC_REG_NUMBER; i++) {
        etsec->regs[i].name   = "Reserved";
        etsec->regs[i].desc   = "";
        etsec->regs[i].access = ACC_UNKNOWN;
        etsec->regs[i].value  = 0x00000000;
    }

    /* Set-up known registers */
    for (i = 0; eTSEC_registers_def[i].name != NULL; i++) {

        reg_index = eTSEC_registers_def[i].offset / 4;

        etsec->regs[reg_index].name   = eTSEC_registers_def[i].name;
        etsec->regs[reg_index].desc   = eTSEC_registers_def[i].desc;
        etsec->regs[reg_index].access = eTSEC_registers_def[i].access;
        etsec->regs[reg_index].value  = eTSEC_registers_def[i].reset;
    }

    etsec->tx_buffer     = NULL;
    etsec->tx_buffer_len = 0;
    etsec->rx_buffer     = NULL;
    etsec->rx_buffer_len = 0;

    etsec->phy_status =
        MII_SR_EXTENDED_CAPS    | MII_SR_LINK_STATUS   | MII_SR_AUTONEG_CAPS  |
        MII_SR_AUTONEG_COMPLETE | MII_SR_PREAMBLE_SUPPRESS |
        MII_SR_EXTENDED_STATUS  | MII_SR_100T2_HD_CAPS | MII_SR_100T2_FD_CAPS |
        MII_SR_10T_HD_CAPS      | MII_SR_10T_FD_CAPS   | MII_SR_100X_HD_CAPS  |
        MII_SR_100X_FD_CAPS     | MII_SR_100T4_CAPS;

    etsec_update_irq(etsec);
}

static ssize_t etsec_receive(NetClientState *nc,
                             const uint8_t  *buf,
                             size_t          size)
{
    ssize_t ret;
    eTSEC *etsec = qemu_get_nic_opaque(nc);

#if defined(HEX_DUMP)
    fprintf(stderr, "%s receive size:%zd\n", nc->name, size);
    qemu_hexdump((void *)buf, stderr, "", size);
#endif
    /* Flush is unnecessary as are already in receiving path */
    etsec->need_flush = false;
    ret = etsec_rx_ring_write(etsec, buf, size);
    if (ret == 0) {
        /* The packet will be queued, let's flush it when buffer is available
         * again. */
        etsec->need_flush = true;
    }
    return ret;
}


static void etsec_set_link_status(NetClientState *nc)
{
    eTSEC *etsec = qemu_get_nic_opaque(nc);

    etsec_miim_link_status(etsec, nc);
}

static NetClientInfo net_etsec_info = {
    .type = NET_CLIENT_DRIVER_NIC,
    .size = sizeof(NICState),
    .receive = etsec_receive,
    .link_status_changed = etsec_set_link_status,
};

static void etsec_realize(DeviceState *dev, Error **errp)
{
    eTSEC        *etsec = ETSEC_COMMON(dev);

    etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
                              object_get_typename(OBJECT(dev)), dev->id, etsec);
    qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);


    etsec->bh     = qemu_bh_new(etsec_timer_hit, etsec);
    etsec->ptimer = ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT);
    ptimer_set_freq(etsec->ptimer, 100);
}

static void etsec_instance_init(Object *obj)
{
    eTSEC        *etsec = ETSEC_COMMON(obj);
    SysBusDevice *sbd   = SYS_BUS_DEVICE(obj);

    memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,
                          "eTSEC", 0x1000);
    sysbus_init_mmio(sbd, &etsec->io_area);

    sysbus_init_irq(sbd, &etsec->tx_irq);
    sysbus_init_irq(sbd, &etsec->rx_irq);
    sysbus_init_irq(sbd, &etsec->err_irq);
}

static Property etsec_properties[] = {
    DEFINE_NIC_PROPERTIES(eTSEC, conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void etsec_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = etsec_realize;
    dc->reset = etsec_reset;
    dc->props = etsec_properties;
    /* Supported by ppce500 machine */
    dc->user_creatable = true;
}

static TypeInfo etsec_info = {
    .name                  = "eTSEC",
    .parent                = TYPE_SYS_BUS_DEVICE,
    .instance_size         = sizeof(eTSEC),
    .class_init            = etsec_class_init,
    .instance_init         = etsec_instance_init,
};

static void etsec_register_types(void)
{
    type_register_static(&etsec_info);
}

type_init(etsec_register_types)

DeviceState *etsec_create(hwaddr         base,
                          MemoryRegion * mr,
                          NICInfo      * nd,
                          qemu_irq       tx_irq,
                          qemu_irq       rx_irq,
                          qemu_irq       err_irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "eTSEC");
    qdev_set_nic_properties(dev, nd);
    qdev_init_nofail(dev);

    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);

    memory_region_add_subregion(mr, base,
                                SYS_BUS_DEVICE(dev)->mmio[0].memory);

    return dev;
}
Commit	Line	Data
eb1e7c3e FC	1	/*
	2	* QEMU Freescale eTSEC Emulator
	3	*
	4	* Copyright (c) 2011-2013 AdaCore
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	/*
	26	* This implementation doesn't include ring priority, TCP/IP Off-Load, QoS.
	27	*/
	28
e8d40465	29	#include "qemu/osdep.h"
eb1e7c3e FC	30	#include "sysemu/sysemu.h"
eb1e7c3e FC	31	#include "hw/sysbus.h"
eb1e7c3e FC	32	#include "hw/ptimer.h"
	33	#include "etsec.h"
	34	#include "registers.h"
03dd024f	35	#include "qemu/log.h"
eb1e7c3e FC	36
	37	/* #define HEX_DUMP */
	38	/* #define DEBUG_REGISTER */
	39
	40	#ifdef DEBUG_REGISTER
	41	static const int debug_etsec = 1;
	42	#else
	43	static const int debug_etsec;
	44	#endif
	45
	46	#define DPRINTF(fmt, ...) do { \
	47	if (debug_etsec) { \
	48	qemu_log(fmt , ## __VA_ARGS__); \
	49	} \
	50	} while (0)
	51
fd8e3381 MD	52	/* call after any change to IEVENT or IMASK */
	53	void etsec_update_irq(eTSEC *etsec)
	54	{
	55	uint32_t ievent = etsec->regs[IEVENT].value;
	56	uint32_t imask = etsec->regs[IMASK].value;
	57	uint32_t active = ievent & imask;
	58
	59	int tx = !!(active & IEVENT_TX_MASK);
	60	int rx = !!(active & IEVENT_RX_MASK);
	61	int err = !!(active & IEVENT_ERR_MASK);
	62
	63	DPRINTF("%s IRQ ievent=%"PRIx32" imask=%"PRIx32" %c%c%c",
	64	__func__, ievent, imask,
	65	tx ? 'T' : '_',
	66	rx ? 'R' : '_',
	67	err ? 'E' : '_');
	68
	69	qemu_set_irq(etsec->tx_irq, tx);
	70	qemu_set_irq(etsec->rx_irq, rx);
	71	qemu_set_irq(etsec->err_irq, err);
	72	}
	73
eb1e7c3e FC	74	static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
	75	{
	76	eTSEC *etsec = opaque;
	77	uint32_t reg_index = addr / 4;
	78	eTSEC_Register *reg = NULL;
	79	uint32_t ret = 0x0;
	80
	81	assert(reg_index < ETSEC_REG_NUMBER);
	82
	83	reg = &etsec->regs[reg_index];
	84
	85
	86	switch (reg->access) {
	87	case ACC_WO:
	88	ret = 0x00000000;
	89	break;
	90
	91	case ACC_RW:
	92	case ACC_W1C:
	93	case ACC_RO:
	94	default:
	95	ret = reg->value;
	96	break;
	97	}
	98
	99	DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx
	100	" : %s (%s)\n",
	101	ret, addr, reg->name, reg->desc);
	102
	103	return ret;
	104	}
	105
	106	static void write_tstat(eTSEC *etsec,
	107	eTSEC_Register *reg,
	108	uint32_t reg_index,
	109	uint32_t value)
	110	{
	111	int i = 0;
	112
	113	for (i = 0; i < 8; i++) {
	114	/* Check THLTi flag in TSTAT */
	115	if (value & (1 << (31 - i))) {
	116	etsec_walk_tx_ring(etsec, i);
	117	}
	118	}
	119
	120	/* Write 1 to clear */
	121	reg->value &= ~value;
	122	}
	123
	124	static void write_rstat(eTSEC *etsec,
	125	eTSEC_Register *reg,
	126	uint32_t reg_index,
	127	uint32_t value)
	128	{
	129	int i = 0;
	130
	131	for (i = 0; i < 8; i++) {
	132	/* Check QHLTi flag in RSTAT */
	133	if (value & (1 << (23 - i)) && !(reg->value & (1 << (23 - i)))) {
	134	etsec_walk_rx_ring(etsec, i);
	135	}
	136	}
	137
138	/* Write 1 to clear */
139	reg->value &= ~value;
140	}
141
142	static void write_tbasex(eTSEC *etsec,
143	eTSEC_Register *reg,
144	uint32_t reg_index,
145	uint32_t value)
146	{
147	reg->value = value & ~0x7;
148
149	/* Copy this value in the ring's TxBD pointer */
150	etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7;
151	}
152
153	static void write_rbasex(eTSEC *etsec,
154	eTSEC_Register *reg,
155	uint32_t reg_index,
156	uint32_t value)
157	{
158	reg->value = value & ~0x7;
159
160	/* Copy this value in the ring's RxBD pointer */
161	etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;
162	}
163
eb1e7c3e FC	164	static void write_dmactrl(eTSEC *etsec,
	165	eTSEC_Register *reg,
	166	uint32_t reg_index,
	167	uint32_t value)
	168	{
	169	reg->value = value;
	170
	171	if (value & DMACTRL_GRS) {
	172
	173	if (etsec->rx_buffer_len != 0) {
	174	/* Graceful receive stop delayed until end of frame */
	175	} else {
	176	/* Graceful receive stop now */
	177	etsec->regs[IEVENT].value \|= IEVENT_GRSC;
fd8e3381	178	etsec_update_irq(etsec);
eb1e7c3e FC	179	}
	180	}
	181
	182	if (value & DMACTRL_GTS) {
	183
	184	if (etsec->tx_buffer_len != 0) {
	185	/* Graceful transmit stop delayed until end of frame */
	186	} else {
	187	/* Graceful transmit stop now */
	188	etsec->regs[IEVENT].value \|= IEVENT_GTSC;
fd8e3381	189	etsec_update_irq(etsec);
eb1e7c3e FC	190	}
	191	}
	192
	193	if (!(value & DMACTRL_WOP)) {
	194	/* Start polling */
	195	ptimer_stop(etsec->ptimer);
	196	ptimer_set_count(etsec->ptimer, 1);
	197	ptimer_run(etsec->ptimer, 1);
	198	}
	199	}
	200
	201	static void etsec_write(void *opaque,
	202	hwaddr addr,
	203	uint64_t value,
	204	unsigned size)
	205	{
	206	eTSEC *etsec = opaque;
	207	uint32_t reg_index = addr / 4;
	208	eTSEC_Register *reg = NULL;
	209	uint32_t before = 0x0;
	210
	211	assert(reg_index < ETSEC_REG_NUMBER);
	212
	213	reg = &etsec->regs[reg_index];
	214	before = reg->value;
	215
	216	switch (reg_index) {
	217	case IEVENT:
fd8e3381 MD	218	/* Write 1 to clear */
	219	reg->value &= ~value;
	220
	221	etsec_update_irq(etsec);
	222	break;
	223
	224	case IMASK:
	225	reg->value = value;
	226
	227	etsec_update_irq(etsec);
eb1e7c3e FC	228	break;
	229
	230	case DMACTRL:
	231	write_dmactrl(etsec, reg, reg_index, value);
	232	break;
	233
	234	case TSTAT:
	235	write_tstat(etsec, reg, reg_index, value);
	236	break;
	237
	238	case RSTAT:
	239	write_rstat(etsec, reg, reg_index, value);
	240	break;
	241
	242	case TBASE0 ... TBASE7:
	243	write_tbasex(etsec, reg, reg_index, value);
	244	break;
	245
	246	case RBASE0 ... RBASE7:
	247	write_rbasex(etsec, reg, reg_index, value);
	248	break;
	249
	250	case MIIMCFG ... MIIMIND:
	251	etsec_write_miim(etsec, reg, reg_index, value);
	252	break;
	253
	254	default:
	255	/* Default handling */
	256	switch (reg->access) {
	257
	258	case ACC_RW:
	259	case ACC_WO:
	260	reg->value = value;
	261	break;
	262
	263	case ACC_W1C:
	264	reg->value &= ~value;
	265	break;
	266
	267	case ACC_RO:
	268	default:
	269	/* Read Only or Unknown register */
	270	break;
	271	}
	272	}
	273
	274	DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
	275	" val:0x%08x->0x%08x : %s (%s)\n",
	276	(unsigned int)value, addr, before, reg->value,
	277	reg->name, reg->desc);
	278	}
	279
	280	static const MemoryRegionOps etsec_ops = {
	281	.read = etsec_read,
	282	.write = etsec_write,
	283	.endianness = DEVICE_NATIVE_ENDIAN,
	284	.impl = {
	285	.min_access_size = 4,
	286	.max_access_size = 4,
	287	},
	288	};
	289
	290	static void etsec_timer_hit(void *opaque)
	291	{
292	eTSEC *etsec = opaque;
293
294	ptimer_stop(etsec->ptimer);
295
296	if (!(etsec->regs[DMACTRL].value & DMACTRL_WOP)) {
297
298	if (!(etsec->regs[DMACTRL].value & DMACTRL_GTS)) {
299	etsec_walk_tx_ring(etsec, 0);
300	}
301	ptimer_set_count(etsec->ptimer, 1);
302	ptimer_run(etsec->ptimer, 1);
303	}
304	}
305
306	static void etsec_reset(DeviceState *d)
307	{
308	eTSEC *etsec = ETSEC_COMMON(d);
309	int i = 0;
310	int reg_index = 0;
311
312	/* Default value for all registers */
313	for (i = 0; i < ETSEC_REG_NUMBER; i++) {
314	etsec->regs[i].name = "Reserved";
315	etsec->regs[i].desc = "";
316	etsec->regs[i].access = ACC_UNKNOWN;
317	etsec->regs[i].value = 0x00000000;
318	}
319
320	/* Set-up known registers */
321	for (i = 0; eTSEC_registers_def[i].name != NULL; i++) {
322
323	reg_index = eTSEC_registers_def[i].offset / 4;
324
325	etsec->regs[reg_index].name = eTSEC_registers_def[i].name;
326	etsec->regs[reg_index].desc = eTSEC_registers_def[i].desc;
327	etsec->regs[reg_index].access = eTSEC_registers_def[i].access;
328	etsec->regs[reg_index].value = eTSEC_registers_def[i].reset;
329	}
330
331	etsec->tx_buffer = NULL;
332	etsec->tx_buffer_len = 0;
333	etsec->rx_buffer = NULL;
334	etsec->rx_buffer_len = 0;
335
336	etsec->phy_status =
337	MII_SR_EXTENDED_CAPS \| MII_SR_LINK_STATUS \| MII_SR_AUTONEG_CAPS \|
338	MII_SR_AUTONEG_COMPLETE \| MII_SR_PREAMBLE_SUPPRESS \|
339	MII_SR_EXTENDED_STATUS \| MII_SR_100T2_HD_CAPS \| MII_SR_100T2_FD_CAPS \|
340	MII_SR_10T_HD_CAPS \| MII_SR_10T_FD_CAPS \| MII_SR_100X_HD_CAPS \|
341	MII_SR_100X_FD_CAPS \| MII_SR_100T4_CAPS;
fd8e3381 MD	342
fd8e3381 MD	343	etsec_update_irq(etsec);
eb1e7c3e FC	344	}
eb1e7c3e FC	345
eb1e7c3e FC	346	static ssize_t etsec_receive(NetClientState *nc,
	347	const uint8_t *buf,
	348	size_t size)
	349	{
575bafd1	350	ssize_t ret;
eb1e7c3e FC	351	eTSEC *etsec = qemu_get_nic_opaque(nc);
	352
	353	#if defined(HEX_DUMP)
9f5832d3 AS	354	fprintf(stderr, "%s receive size:%zd\n", nc->name, size);
9f5832d3 AS	355	qemu_hexdump((void *)buf, stderr, "", size);
eb1e7c3e	356	#endif
575bafd1 FZ	357	/* Flush is unnecessary as are already in receiving path */
	358	etsec->need_flush = false;
	359	ret = etsec_rx_ring_write(etsec, buf, size);
	360	if (ret == 0) {
67cc32eb	361	/* The packet will be queued, let's flush it when buffer is available
575bafd1 FZ	362	* again. */
	363	etsec->need_flush = true;
	364	}
	365	return ret;
eb1e7c3e FC	366	}
	367
	368
	369	static void etsec_set_link_status(NetClientState *nc)
	370	{
	371	eTSEC *etsec = qemu_get_nic_opaque(nc);
	372
	373	etsec_miim_link_status(etsec, nc);
	374	}
	375
	376	static NetClientInfo net_etsec_info = {
f394b2e2	377	.type = NET_CLIENT_DRIVER_NIC,
eb1e7c3e	378	.size = sizeof(NICState),
eb1e7c3e	379	.receive = etsec_receive,
eb1e7c3e FC	380	.link_status_changed = etsec_set_link_status,
	381	};
	382
	383	static void etsec_realize(DeviceState dev, Error *errp)
	384	{
	385	eTSEC *etsec = ETSEC_COMMON(dev);
	386
	387	etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
	388	object_get_typename(OBJECT(dev)), dev->id, etsec);
	389	qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);
	390
	391
	392	etsec->bh = qemu_bh_new(etsec_timer_hit, etsec);
e7ea81c3	393	etsec->ptimer = ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT);
eb1e7c3e FC	394	ptimer_set_freq(etsec->ptimer, 100);
	395	}
	396
	397	static void etsec_instance_init(Object *obj)
	398	{
	399	eTSEC *etsec = ETSEC_COMMON(obj);
	400	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	401
	402	memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,
	403	"eTSEC", 0x1000);
	404	sysbus_init_mmio(sbd, &etsec->io_area);
	405
	406	sysbus_init_irq(sbd, &etsec->tx_irq);
	407	sysbus_init_irq(sbd, &etsec->rx_irq);
	408	sysbus_init_irq(sbd, &etsec->err_irq);
	409	}
	410
	411	static Property etsec_properties[] = {
	412	DEFINE_NIC_PROPERTIES(eTSEC, conf),
	413	DEFINE_PROP_END_OF_LIST(),
	414	};
	415
	416	static void etsec_class_init(ObjectClass klass, void data)
	417	{
	418	DeviceClass *dc = DEVICE_CLASS(klass);
	419
	420	dc->realize = etsec_realize;
	421	dc->reset = etsec_reset;
	422	dc->props = etsec_properties;
e4f4fb1e EH	423	/* Supported by ppce500 machine */
e4f4fb1e EH	424	dc->user_creatable = true;
eb1e7c3e FC	425	}
	426
	427	static TypeInfo etsec_info = {
	428	.name = "eTSEC",
	429	.parent = TYPE_SYS_BUS_DEVICE,
	430	.instance_size = sizeof(eTSEC),
	431	.class_init = etsec_class_init,
	432	.instance_init = etsec_instance_init,
	433	};
	434
	435	static void etsec_register_types(void)
	436	{
	437	type_register_static(&etsec_info);
	438	}
	439
	440	type_init(etsec_register_types)
	441
	442	DeviceState *etsec_create(hwaddr base,
	443	MemoryRegion * mr,
	444	NICInfo * nd,
	445	qemu_irq tx_irq,
	446	qemu_irq rx_irq,
	447	qemu_irq err_irq)
	448	{
	449	DeviceState *dev;
	450
	451	dev = qdev_create(NULL, "eTSEC");
	452	qdev_set_nic_properties(dev, nd);
aef0d55a	453	qdev_init_nofail(dev);
eb1e7c3e FC	454
	455	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
	456	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
	457	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);
	458
	459	memory_region_add_subregion(mr, base,
	460	SYS_BUS_DEVICE(dev)->mmio[0].memory);
	461
	462	return dev;
	463	}