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07424544 | 1 | /* |
57aa265d | 2 | * QEMU model of the Milkymist minimac2 block. |
07424544 | 3 | * |
57aa265d | 4 | * Copyright (c) 2011 Michael Walle <michael@walle.cc> |
07424544 MW |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
57aa265d | 21 | * not available yet |
07424544 MW |
22 | * |
23 | */ | |
24 | ||
ea99dde1 | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 | 27 | #include "cpu.h" /* FIXME: why does this use TARGET_PAGE_ALIGN? */ |
64552b6b | 28 | #include "hw/irq.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
83c9f4ca | 30 | #include "hw/sysbus.h" |
d6454270 | 31 | #include "migration/vmstate.h" |
07424544 | 32 | #include "trace.h" |
1422e32d | 33 | #include "net/net.h" |
7b2b797c | 34 | #include "qemu/log.h" |
0b8fa32f | 35 | #include "qemu/module.h" |
1de7afc9 | 36 | #include "qemu/error-report.h" |
07424544 MW |
37 | |
38 | #include <zlib.h> | |
39 | ||
40 | enum { | |
41 | R_SETUP = 0, | |
42 | R_MDIO, | |
43 | R_STATE0, | |
07424544 MW |
44 | R_COUNT0, |
45 | R_STATE1, | |
07424544 | 46 | R_COUNT1, |
07424544 MW |
47 | R_TXCOUNT, |
48 | R_MAX | |
49 | }; | |
50 | ||
51 | enum { | |
57aa265d | 52 | SETUP_PHY_RST = (1<<0), |
07424544 MW |
53 | }; |
54 | ||
55 | enum { | |
56 | MDIO_DO = (1<<0), | |
57 | MDIO_DI = (1<<1), | |
58 | MDIO_OE = (1<<2), | |
59 | MDIO_CLK = (1<<3), | |
60 | }; | |
61 | ||
62 | enum { | |
63 | STATE_EMPTY = 0, | |
64 | STATE_LOADED = 1, | |
65 | STATE_PENDING = 2, | |
66 | }; | |
67 | ||
68 | enum { | |
69 | MDIO_OP_WRITE = 1, | |
70 | MDIO_OP_READ = 2, | |
71 | }; | |
72 | ||
73 | enum mdio_state { | |
74 | MDIO_STATE_IDLE, | |
75 | MDIO_STATE_READING, | |
76 | MDIO_STATE_WRITING, | |
77 | }; | |
78 | ||
79 | enum { | |
80 | R_PHY_ID1 = 2, | |
81 | R_PHY_ID2 = 3, | |
82 | R_PHY_MAX = 32 | |
83 | }; | |
84 | ||
57aa265d MW |
85 | #define MINIMAC2_MTU 1530 |
86 | #define MINIMAC2_BUFFER_SIZE 2048 | |
07424544 | 87 | |
57aa265d | 88 | struct MilkymistMinimac2MdioState { |
07424544 MW |
89 | int last_clk; |
90 | int count; | |
91 | uint32_t data; | |
92 | uint16_t data_out; | |
93 | int state; | |
94 | ||
95 | uint8_t phy_addr; | |
96 | uint8_t reg_addr; | |
97 | }; | |
57aa265d | 98 | typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState; |
07424544 | 99 | |
0e57587f AF |
100 | #define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2" |
101 | #define MILKYMIST_MINIMAC2(obj) \ | |
102 | OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2) | |
103 | ||
57aa265d | 104 | struct MilkymistMinimac2State { |
0e57587f AF |
105 | SysBusDevice parent_obj; |
106 | ||
07424544 MW |
107 | NICState *nic; |
108 | NICConf conf; | |
109 | char *phy_model; | |
8a53d56f AK |
110 | MemoryRegion buffers; |
111 | MemoryRegion regs_region; | |
07424544 MW |
112 | |
113 | qemu_irq rx_irq; | |
114 | qemu_irq tx_irq; | |
115 | ||
116 | uint32_t regs[R_MAX]; | |
117 | ||
57aa265d | 118 | MilkymistMinimac2MdioState mdio; |
07424544 MW |
119 | |
120 | uint16_t phy_regs[R_PHY_MAX]; | |
57aa265d MW |
121 | |
122 | uint8_t *rx0_buf; | |
123 | uint8_t *rx1_buf; | |
124 | uint8_t *tx_buf; | |
07424544 | 125 | }; |
57aa265d | 126 | typedef struct MilkymistMinimac2State MilkymistMinimac2State; |
07424544 MW |
127 | |
128 | static const uint8_t preamble_sfd[] = { | |
129 | 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5 | |
130 | }; | |
131 | ||
57aa265d | 132 | static void minimac2_mdio_write_reg(MilkymistMinimac2State *s, |
07424544 MW |
133 | uint8_t phy_addr, uint8_t reg_addr, uint16_t value) |
134 | { | |
57aa265d | 135 | trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value); |
07424544 MW |
136 | |
137 | /* nop */ | |
138 | } | |
139 | ||
57aa265d | 140 | static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s, |
07424544 MW |
141 | uint8_t phy_addr, uint8_t reg_addr) |
142 | { | |
143 | uint16_t r = s->phy_regs[reg_addr]; | |
144 | ||
57aa265d | 145 | trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r); |
07424544 MW |
146 | |
147 | return r; | |
148 | } | |
149 | ||
57aa265d | 150 | static void minimac2_update_mdio(MilkymistMinimac2State *s) |
07424544 | 151 | { |
57aa265d | 152 | MilkymistMinimac2MdioState *m = &s->mdio; |
07424544 MW |
153 | |
154 | /* detect rising clk edge */ | |
155 | if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) { | |
156 | /* shift data in */ | |
157 | int bit = ((s->regs[R_MDIO] & MDIO_DO) | |
158 | && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0; | |
159 | m->data = (m->data << 1) | bit; | |
160 | ||
161 | /* check for sync */ | |
162 | if (m->data == 0xffffffff) { | |
163 | m->count = 32; | |
164 | } | |
165 | ||
166 | if (m->count == 16) { | |
167 | uint8_t start = (m->data >> 14) & 0x3; | |
168 | uint8_t op = (m->data >> 12) & 0x3; | |
169 | uint8_t ta = (m->data) & 0x3; | |
170 | ||
171 | if (start == 1 && op == MDIO_OP_WRITE && ta == 2) { | |
172 | m->state = MDIO_STATE_WRITING; | |
173 | } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) { | |
174 | m->state = MDIO_STATE_READING; | |
175 | } else { | |
176 | m->state = MDIO_STATE_IDLE; | |
177 | } | |
178 | ||
179 | if (m->state != MDIO_STATE_IDLE) { | |
180 | m->phy_addr = (m->data >> 7) & 0x1f; | |
181 | m->reg_addr = (m->data >> 2) & 0x1f; | |
182 | } | |
183 | ||
184 | if (m->state == MDIO_STATE_READING) { | |
57aa265d | 185 | m->data_out = minimac2_mdio_read_reg(s, m->phy_addr, |
07424544 MW |
186 | m->reg_addr); |
187 | } | |
188 | } | |
189 | ||
190 | if (m->count < 16 && m->state == MDIO_STATE_READING) { | |
191 | int bit = (m->data_out & 0x8000) ? 1 : 0; | |
192 | m->data_out <<= 1; | |
193 | ||
194 | if (bit) { | |
195 | s->regs[R_MDIO] |= MDIO_DI; | |
196 | } else { | |
197 | s->regs[R_MDIO] &= ~MDIO_DI; | |
198 | } | |
199 | } | |
200 | ||
201 | if (m->count == 0 && m->state) { | |
202 | if (m->state == MDIO_STATE_WRITING) { | |
203 | uint16_t data = m->data & 0xffff; | |
57aa265d | 204 | minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data); |
07424544 MW |
205 | } |
206 | m->state = MDIO_STATE_IDLE; | |
207 | } | |
208 | m->count--; | |
209 | } | |
210 | ||
211 | m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0; | |
212 | } | |
213 | ||
214 | static size_t assemble_frame(uint8_t *buf, size_t size, | |
215 | const uint8_t *payload, size_t payload_size) | |
216 | { | |
217 | uint32_t crc; | |
218 | ||
219 | if (size < payload_size + 12) { | |
7b2b797c PMD |
220 | qemu_log_mask(LOG_GUEST_ERROR, "milkymist_minimac2: frame too big " |
221 | "(%zd bytes)\n", payload_size); | |
07424544 MW |
222 | return 0; |
223 | } | |
224 | ||
225 | /* prepend preamble and sfd */ | |
226 | memcpy(buf, preamble_sfd, 8); | |
227 | ||
228 | /* now copy the payload */ | |
229 | memcpy(buf + 8, payload, payload_size); | |
230 | ||
231 | /* pad frame if needed */ | |
232 | if (payload_size < 60) { | |
233 | memset(buf + payload_size + 8, 0, 60 - payload_size); | |
234 | payload_size = 60; | |
235 | } | |
236 | ||
237 | /* append fcs */ | |
238 | crc = cpu_to_le32(crc32(0, buf + 8, payload_size)); | |
239 | memcpy(buf + payload_size + 8, &crc, 4); | |
240 | ||
241 | return payload_size + 12; | |
242 | } | |
243 | ||
57aa265d | 244 | static void minimac2_tx(MilkymistMinimac2State *s) |
07424544 | 245 | { |
07424544 | 246 | uint32_t txcount = s->regs[R_TXCOUNT]; |
57aa265d | 247 | uint8_t *buf = s->tx_buf; |
07424544 MW |
248 | |
249 | if (txcount < 64) { | |
6daf194d | 250 | error_report("milkymist_minimac2: ethernet frame too small (%u < %u)", |
07424544 | 251 | txcount, 64); |
57aa265d | 252 | goto err; |
07424544 MW |
253 | } |
254 | ||
57aa265d | 255 | if (txcount > MINIMAC2_MTU) { |
6daf194d | 256 | error_report("milkymist_minimac2: MTU exceeded (%u > %u)", |
57aa265d MW |
257 | txcount, MINIMAC2_MTU); |
258 | goto err; | |
07424544 MW |
259 | } |
260 | ||
07424544 | 261 | if (memcmp(buf, preamble_sfd, 8) != 0) { |
57aa265d | 262 | error_report("milkymist_minimac2: frame doesn't contain the preamble " |
6daf194d | 263 | "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)", |
07424544 | 264 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); |
57aa265d | 265 | goto err; |
07424544 MW |
266 | } |
267 | ||
57aa265d | 268 | trace_milkymist_minimac2_tx_frame(txcount - 12); |
07424544 MW |
269 | |
270 | /* send packet, skipping preamble and sfd */ | |
b356f76d | 271 | qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12); |
07424544 MW |
272 | |
273 | s->regs[R_TXCOUNT] = 0; | |
274 | ||
57aa265d MW |
275 | err: |
276 | trace_milkymist_minimac2_pulse_irq_tx(); | |
07424544 MW |
277 | qemu_irq_pulse(s->tx_irq); |
278 | } | |
279 | ||
57aa265d MW |
280 | static void update_rx_interrupt(MilkymistMinimac2State *s) |
281 | { | |
282 | if (s->regs[R_STATE0] == STATE_PENDING | |
283 | || s->regs[R_STATE1] == STATE_PENDING) { | |
284 | trace_milkymist_minimac2_raise_irq_rx(); | |
285 | qemu_irq_raise(s->rx_irq); | |
286 | } else { | |
287 | trace_milkymist_minimac2_lower_irq_rx(); | |
288 | qemu_irq_lower(s->rx_irq); | |
289 | } | |
290 | } | |
291 | ||
4e68f7a0 | 292 | static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size) |
07424544 | 293 | { |
cc1f0f45 | 294 | MilkymistMinimac2State *s = qemu_get_nic_opaque(nc); |
07424544 | 295 | |
07424544 MW |
296 | uint32_t r_count; |
297 | uint32_t r_state; | |
57aa265d | 298 | uint8_t *rx_buf; |
07424544 | 299 | |
07424544 MW |
300 | size_t frame_size; |
301 | ||
57aa265d | 302 | trace_milkymist_minimac2_rx_frame(buf, size); |
07424544 MW |
303 | |
304 | /* choose appropriate slot */ | |
305 | if (s->regs[R_STATE0] == STATE_LOADED) { | |
07424544 MW |
306 | r_count = R_COUNT0; |
307 | r_state = R_STATE0; | |
57aa265d | 308 | rx_buf = s->rx0_buf; |
07424544 | 309 | } else if (s->regs[R_STATE1] == STATE_LOADED) { |
07424544 MW |
310 | r_count = R_COUNT1; |
311 | r_state = R_STATE1; | |
57aa265d | 312 | rx_buf = s->rx1_buf; |
07424544 | 313 | } else { |
3b7031e9 | 314 | return 0; |
07424544 MW |
315 | } |
316 | ||
317 | /* assemble frame */ | |
57aa265d | 318 | frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size); |
07424544 MW |
319 | |
320 | if (frame_size == 0) { | |
321 | return size; | |
322 | } | |
323 | ||
57aa265d | 324 | trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size); |
07424544 MW |
325 | |
326 | /* update slot */ | |
327 | s->regs[r_count] = frame_size; | |
328 | s->regs[r_state] = STATE_PENDING; | |
329 | ||
57aa265d | 330 | update_rx_interrupt(s); |
07424544 MW |
331 | |
332 | return size; | |
333 | } | |
334 | ||
8a53d56f | 335 | static uint64_t |
a8170e5e | 336 | minimac2_read(void *opaque, hwaddr addr, unsigned size) |
07424544 | 337 | { |
57aa265d | 338 | MilkymistMinimac2State *s = opaque; |
07424544 MW |
339 | uint32_t r = 0; |
340 | ||
341 | addr >>= 2; | |
342 | switch (addr) { | |
343 | case R_SETUP: | |
344 | case R_MDIO: | |
345 | case R_STATE0: | |
07424544 MW |
346 | case R_COUNT0: |
347 | case R_STATE1: | |
07424544 | 348 | case R_COUNT1: |
07424544 MW |
349 | case R_TXCOUNT: |
350 | r = s->regs[addr]; | |
351 | break; | |
352 | ||
353 | default: | |
7b2b797c PMD |
354 | qemu_log_mask(LOG_GUEST_ERROR, |
355 | "milkymist_minimac2_rd%d: 0x%" HWADDR_PRIx "\n", | |
356 | size, addr << 2); | |
07424544 MW |
357 | break; |
358 | } | |
359 | ||
57aa265d | 360 | trace_milkymist_minimac2_memory_read(addr << 2, r); |
07424544 MW |
361 | |
362 | return r; | |
363 | } | |
364 | ||
3b7031e9 FZ |
365 | static int minimac2_can_rx(MilkymistMinimac2State *s) |
366 | { | |
367 | if (s->regs[R_STATE0] == STATE_LOADED) { | |
368 | return 1; | |
369 | } | |
370 | if (s->regs[R_STATE1] == STATE_LOADED) { | |
371 | return 1; | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
07424544 | 377 | static void |
a8170e5e | 378 | minimac2_write(void *opaque, hwaddr addr, uint64_t value, |
8a53d56f | 379 | unsigned size) |
07424544 | 380 | { |
57aa265d | 381 | MilkymistMinimac2State *s = opaque; |
07424544 | 382 | |
0ece9671 | 383 | trace_milkymist_minimac2_memory_write(addr, value); |
07424544 MW |
384 | |
385 | addr >>= 2; | |
386 | switch (addr) { | |
387 | case R_MDIO: | |
388 | { | |
389 | /* MDIO_DI is read only */ | |
390 | int mdio_di = (s->regs[R_MDIO] & MDIO_DI); | |
391 | s->regs[R_MDIO] = value; | |
392 | if (mdio_di) { | |
393 | s->regs[R_MDIO] |= mdio_di; | |
394 | } else { | |
395 | s->regs[R_MDIO] &= ~mdio_di; | |
396 | } | |
397 | ||
57aa265d | 398 | minimac2_update_mdio(s); |
07424544 MW |
399 | } break; |
400 | case R_TXCOUNT: | |
401 | s->regs[addr] = value; | |
402 | if (value > 0) { | |
57aa265d | 403 | minimac2_tx(s); |
07424544 MW |
404 | } |
405 | break; | |
07424544 | 406 | case R_STATE0: |
07424544 | 407 | case R_STATE1: |
57aa265d MW |
408 | s->regs[addr] = value; |
409 | update_rx_interrupt(s); | |
3b7031e9 FZ |
410 | if (minimac2_can_rx(s)) { |
411 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | |
412 | } | |
57aa265d MW |
413 | break; |
414 | case R_SETUP: | |
415 | case R_COUNT0: | |
07424544 | 416 | case R_COUNT1: |
07424544 MW |
417 | s->regs[addr] = value; |
418 | break; | |
419 | ||
420 | default: | |
7b2b797c PMD |
421 | qemu_log_mask(LOG_GUEST_ERROR, |
422 | "milkymist_minimac2_wr%d: 0x%" HWADDR_PRIx | |
423 | " = 0x%" PRIx64 "\n", | |
424 | size, addr << 2, value); | |
07424544 MW |
425 | break; |
426 | } | |
427 | } | |
428 | ||
8a53d56f AK |
429 | static const MemoryRegionOps minimac2_ops = { |
430 | .read = minimac2_read, | |
431 | .write = minimac2_write, | |
432 | .valid = { | |
433 | .min_access_size = 4, | |
434 | .max_access_size = 4, | |
435 | }, | |
436 | .endianness = DEVICE_NATIVE_ENDIAN, | |
07424544 MW |
437 | }; |
438 | ||
57aa265d | 439 | static void milkymist_minimac2_reset(DeviceState *d) |
07424544 | 440 | { |
0e57587f | 441 | MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d); |
07424544 MW |
442 | int i; |
443 | ||
444 | for (i = 0; i < R_MAX; i++) { | |
445 | s->regs[i] = 0; | |
446 | } | |
447 | for (i = 0; i < R_PHY_MAX; i++) { | |
448 | s->phy_regs[i] = 0; | |
449 | } | |
450 | ||
451 | /* defaults */ | |
452 | s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */ | |
453 | s->phy_regs[R_PHY_ID2] = 0x161a; | |
454 | } | |
455 | ||
57aa265d | 456 | static NetClientInfo net_milkymist_minimac2_info = { |
f394b2e2 | 457 | .type = NET_CLIENT_DRIVER_NIC, |
07424544 | 458 | .size = sizeof(NICState), |
57aa265d | 459 | .receive = minimac2_rx, |
07424544 MW |
460 | }; |
461 | ||
d85d0160 | 462 | static void milkymist_minimac2_realize(DeviceState *dev, Error **errp) |
07424544 | 463 | { |
d85d0160 | 464 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
0e57587f | 465 | MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev); |
57aa265d | 466 | size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE); |
07424544 | 467 | |
0e57587f AF |
468 | sysbus_init_irq(sbd, &s->rx_irq); |
469 | sysbus_init_irq(sbd, &s->tx_irq); | |
07424544 | 470 | |
eedfac6f | 471 | memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s, |
306f66b4 | 472 | "milkymist-minimac2", R_MAX * 4); |
0e57587f | 473 | sysbus_init_mmio(sbd, &s->regs_region); |
07424544 | 474 | |
57aa265d | 475 | /* register buffers memory */ |
1cfe48c1 | 476 | memory_region_init_ram_nomigrate(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers", |
f8ed85ac | 477 | buffers_size, &error_fatal); |
c5705a77 | 478 | vmstate_register_ram_global(&s->buffers); |
8a53d56f | 479 | s->rx0_buf = memory_region_get_ram_ptr(&s->buffers); |
57aa265d MW |
480 | s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE; |
481 | s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE; | |
482 | ||
0e57587f | 483 | sysbus_init_mmio(sbd, &s->buffers); |
57aa265d | 484 | |
07424544 | 485 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
57aa265d | 486 | s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf, |
0e57587f | 487 | object_get_typename(OBJECT(dev)), dev->id, s); |
b356f76d | 488 | qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
07424544 MW |
489 | } |
490 | ||
57aa265d MW |
491 | static const VMStateDescription vmstate_milkymist_minimac2_mdio = { |
492 | .name = "milkymist-minimac2-mdio", | |
07424544 MW |
493 | .version_id = 1, |
494 | .minimum_version_id = 1, | |
35d08458 | 495 | .fields = (VMStateField[]) { |
57aa265d MW |
496 | VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState), |
497 | VMSTATE_INT32(count, MilkymistMinimac2MdioState), | |
498 | VMSTATE_UINT32(data, MilkymistMinimac2MdioState), | |
499 | VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState), | |
500 | VMSTATE_INT32(state, MilkymistMinimac2MdioState), | |
501 | VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState), | |
502 | VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState), | |
07424544 MW |
503 | VMSTATE_END_OF_LIST() |
504 | } | |
505 | }; | |
506 | ||
57aa265d MW |
507 | static const VMStateDescription vmstate_milkymist_minimac2 = { |
508 | .name = "milkymist-minimac2", | |
07424544 MW |
509 | .version_id = 1, |
510 | .minimum_version_id = 1, | |
35d08458 | 511 | .fields = (VMStateField[]) { |
57aa265d MW |
512 | VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX), |
513 | VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX), | |
514 | VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0, | |
515 | vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState), | |
07424544 MW |
516 | VMSTATE_END_OF_LIST() |
517 | } | |
518 | }; | |
519 | ||
999e12bb | 520 | static Property milkymist_minimac2_properties[] = { |
999e12bb AL |
521 | DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf), |
522 | DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model), | |
523 | DEFINE_PROP_END_OF_LIST(), | |
524 | }; | |
525 | ||
526 | static void milkymist_minimac2_class_init(ObjectClass *klass, void *data) | |
527 | { | |
39bffca2 | 528 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 529 | |
d85d0160 | 530 | dc->realize = milkymist_minimac2_realize; |
39bffca2 AL |
531 | dc->reset = milkymist_minimac2_reset; |
532 | dc->vmsd = &vmstate_milkymist_minimac2; | |
4f67d30b | 533 | device_class_set_props(dc, milkymist_minimac2_properties); |
999e12bb AL |
534 | } |
535 | ||
8c43a6f0 | 536 | static const TypeInfo milkymist_minimac2_info = { |
0e57587f | 537 | .name = TYPE_MILKYMIST_MINIMAC2, |
39bffca2 AL |
538 | .parent = TYPE_SYS_BUS_DEVICE, |
539 | .instance_size = sizeof(MilkymistMinimac2State), | |
540 | .class_init = milkymist_minimac2_class_init, | |
07424544 MW |
541 | }; |
542 | ||
83f7d43a | 543 | static void milkymist_minimac2_register_types(void) |
07424544 | 544 | { |
39bffca2 | 545 | type_register_static(&milkymist_minimac2_info); |
07424544 MW |
546 | } |
547 | ||
83f7d43a | 548 | type_init(milkymist_minimac2_register_types) |