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07424544 | 1 | /* |
57aa265d | 2 | * QEMU model of the Milkymist minimac2 block. |
07424544 | 3 | * |
57aa265d | 4 | * Copyright (c) 2011 Michael Walle <michael@walle.cc> |
07424544 MW |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
57aa265d | 21 | * not available yet |
07424544 MW |
22 | * |
23 | */ | |
24 | ||
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/sysbus.h" | |
07424544 | 27 | #include "trace.h" |
1422e32d | 28 | #include "net/net.h" |
1de7afc9 | 29 | #include "qemu/error-report.h" |
07424544 MW |
30 | |
31 | #include <zlib.h> | |
32 | ||
33 | enum { | |
34 | R_SETUP = 0, | |
35 | R_MDIO, | |
36 | R_STATE0, | |
07424544 MW |
37 | R_COUNT0, |
38 | R_STATE1, | |
07424544 | 39 | R_COUNT1, |
07424544 MW |
40 | R_TXCOUNT, |
41 | R_MAX | |
42 | }; | |
43 | ||
44 | enum { | |
57aa265d | 45 | SETUP_PHY_RST = (1<<0), |
07424544 MW |
46 | }; |
47 | ||
48 | enum { | |
49 | MDIO_DO = (1<<0), | |
50 | MDIO_DI = (1<<1), | |
51 | MDIO_OE = (1<<2), | |
52 | MDIO_CLK = (1<<3), | |
53 | }; | |
54 | ||
55 | enum { | |
56 | STATE_EMPTY = 0, | |
57 | STATE_LOADED = 1, | |
58 | STATE_PENDING = 2, | |
59 | }; | |
60 | ||
61 | enum { | |
62 | MDIO_OP_WRITE = 1, | |
63 | MDIO_OP_READ = 2, | |
64 | }; | |
65 | ||
66 | enum mdio_state { | |
67 | MDIO_STATE_IDLE, | |
68 | MDIO_STATE_READING, | |
69 | MDIO_STATE_WRITING, | |
70 | }; | |
71 | ||
72 | enum { | |
73 | R_PHY_ID1 = 2, | |
74 | R_PHY_ID2 = 3, | |
75 | R_PHY_MAX = 32 | |
76 | }; | |
77 | ||
57aa265d MW |
78 | #define MINIMAC2_MTU 1530 |
79 | #define MINIMAC2_BUFFER_SIZE 2048 | |
07424544 | 80 | |
57aa265d | 81 | struct MilkymistMinimac2MdioState { |
07424544 MW |
82 | int last_clk; |
83 | int count; | |
84 | uint32_t data; | |
85 | uint16_t data_out; | |
86 | int state; | |
87 | ||
88 | uint8_t phy_addr; | |
89 | uint8_t reg_addr; | |
90 | }; | |
57aa265d | 91 | typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState; |
07424544 | 92 | |
57aa265d | 93 | struct MilkymistMinimac2State { |
07424544 MW |
94 | SysBusDevice busdev; |
95 | NICState *nic; | |
96 | NICConf conf; | |
97 | char *phy_model; | |
8a53d56f AK |
98 | MemoryRegion buffers; |
99 | MemoryRegion regs_region; | |
07424544 MW |
100 | |
101 | qemu_irq rx_irq; | |
102 | qemu_irq tx_irq; | |
103 | ||
104 | uint32_t regs[R_MAX]; | |
105 | ||
57aa265d | 106 | MilkymistMinimac2MdioState mdio; |
07424544 MW |
107 | |
108 | uint16_t phy_regs[R_PHY_MAX]; | |
57aa265d MW |
109 | |
110 | uint8_t *rx0_buf; | |
111 | uint8_t *rx1_buf; | |
112 | uint8_t *tx_buf; | |
07424544 | 113 | }; |
57aa265d | 114 | typedef struct MilkymistMinimac2State MilkymistMinimac2State; |
07424544 MW |
115 | |
116 | static const uint8_t preamble_sfd[] = { | |
117 | 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5 | |
118 | }; | |
119 | ||
57aa265d | 120 | static void minimac2_mdio_write_reg(MilkymistMinimac2State *s, |
07424544 MW |
121 | uint8_t phy_addr, uint8_t reg_addr, uint16_t value) |
122 | { | |
57aa265d | 123 | trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value); |
07424544 MW |
124 | |
125 | /* nop */ | |
126 | } | |
127 | ||
57aa265d | 128 | static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s, |
07424544 MW |
129 | uint8_t phy_addr, uint8_t reg_addr) |
130 | { | |
131 | uint16_t r = s->phy_regs[reg_addr]; | |
132 | ||
57aa265d | 133 | trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r); |
07424544 MW |
134 | |
135 | return r; | |
136 | } | |
137 | ||
57aa265d | 138 | static void minimac2_update_mdio(MilkymistMinimac2State *s) |
07424544 | 139 | { |
57aa265d | 140 | MilkymistMinimac2MdioState *m = &s->mdio; |
07424544 MW |
141 | |
142 | /* detect rising clk edge */ | |
143 | if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) { | |
144 | /* shift data in */ | |
145 | int bit = ((s->regs[R_MDIO] & MDIO_DO) | |
146 | && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0; | |
147 | m->data = (m->data << 1) | bit; | |
148 | ||
149 | /* check for sync */ | |
150 | if (m->data == 0xffffffff) { | |
151 | m->count = 32; | |
152 | } | |
153 | ||
154 | if (m->count == 16) { | |
155 | uint8_t start = (m->data >> 14) & 0x3; | |
156 | uint8_t op = (m->data >> 12) & 0x3; | |
157 | uint8_t ta = (m->data) & 0x3; | |
158 | ||
159 | if (start == 1 && op == MDIO_OP_WRITE && ta == 2) { | |
160 | m->state = MDIO_STATE_WRITING; | |
161 | } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) { | |
162 | m->state = MDIO_STATE_READING; | |
163 | } else { | |
164 | m->state = MDIO_STATE_IDLE; | |
165 | } | |
166 | ||
167 | if (m->state != MDIO_STATE_IDLE) { | |
168 | m->phy_addr = (m->data >> 7) & 0x1f; | |
169 | m->reg_addr = (m->data >> 2) & 0x1f; | |
170 | } | |
171 | ||
172 | if (m->state == MDIO_STATE_READING) { | |
57aa265d | 173 | m->data_out = minimac2_mdio_read_reg(s, m->phy_addr, |
07424544 MW |
174 | m->reg_addr); |
175 | } | |
176 | } | |
177 | ||
178 | if (m->count < 16 && m->state == MDIO_STATE_READING) { | |
179 | int bit = (m->data_out & 0x8000) ? 1 : 0; | |
180 | m->data_out <<= 1; | |
181 | ||
182 | if (bit) { | |
183 | s->regs[R_MDIO] |= MDIO_DI; | |
184 | } else { | |
185 | s->regs[R_MDIO] &= ~MDIO_DI; | |
186 | } | |
187 | } | |
188 | ||
189 | if (m->count == 0 && m->state) { | |
190 | if (m->state == MDIO_STATE_WRITING) { | |
191 | uint16_t data = m->data & 0xffff; | |
57aa265d | 192 | minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data); |
07424544 MW |
193 | } |
194 | m->state = MDIO_STATE_IDLE; | |
195 | } | |
196 | m->count--; | |
197 | } | |
198 | ||
199 | m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0; | |
200 | } | |
201 | ||
202 | static size_t assemble_frame(uint8_t *buf, size_t size, | |
203 | const uint8_t *payload, size_t payload_size) | |
204 | { | |
205 | uint32_t crc; | |
206 | ||
207 | if (size < payload_size + 12) { | |
57aa265d | 208 | error_report("milkymist_minimac2: received too big ethernet frame"); |
07424544 MW |
209 | return 0; |
210 | } | |
211 | ||
212 | /* prepend preamble and sfd */ | |
213 | memcpy(buf, preamble_sfd, 8); | |
214 | ||
215 | /* now copy the payload */ | |
216 | memcpy(buf + 8, payload, payload_size); | |
217 | ||
218 | /* pad frame if needed */ | |
219 | if (payload_size < 60) { | |
220 | memset(buf + payload_size + 8, 0, 60 - payload_size); | |
221 | payload_size = 60; | |
222 | } | |
223 | ||
224 | /* append fcs */ | |
225 | crc = cpu_to_le32(crc32(0, buf + 8, payload_size)); | |
226 | memcpy(buf + payload_size + 8, &crc, 4); | |
227 | ||
228 | return payload_size + 12; | |
229 | } | |
230 | ||
57aa265d | 231 | static void minimac2_tx(MilkymistMinimac2State *s) |
07424544 | 232 | { |
07424544 | 233 | uint32_t txcount = s->regs[R_TXCOUNT]; |
57aa265d | 234 | uint8_t *buf = s->tx_buf; |
07424544 MW |
235 | |
236 | if (txcount < 64) { | |
6daf194d | 237 | error_report("milkymist_minimac2: ethernet frame too small (%u < %u)", |
07424544 | 238 | txcount, 64); |
57aa265d | 239 | goto err; |
07424544 MW |
240 | } |
241 | ||
57aa265d | 242 | if (txcount > MINIMAC2_MTU) { |
6daf194d | 243 | error_report("milkymist_minimac2: MTU exceeded (%u > %u)", |
57aa265d MW |
244 | txcount, MINIMAC2_MTU); |
245 | goto err; | |
07424544 MW |
246 | } |
247 | ||
07424544 | 248 | if (memcmp(buf, preamble_sfd, 8) != 0) { |
57aa265d | 249 | error_report("milkymist_minimac2: frame doesn't contain the preamble " |
6daf194d | 250 | "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)", |
07424544 | 251 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); |
57aa265d | 252 | goto err; |
07424544 MW |
253 | } |
254 | ||
57aa265d | 255 | trace_milkymist_minimac2_tx_frame(txcount - 12); |
07424544 MW |
256 | |
257 | /* send packet, skipping preamble and sfd */ | |
b356f76d | 258 | qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12); |
07424544 MW |
259 | |
260 | s->regs[R_TXCOUNT] = 0; | |
261 | ||
57aa265d MW |
262 | err: |
263 | trace_milkymist_minimac2_pulse_irq_tx(); | |
07424544 MW |
264 | qemu_irq_pulse(s->tx_irq); |
265 | } | |
266 | ||
57aa265d MW |
267 | static void update_rx_interrupt(MilkymistMinimac2State *s) |
268 | { | |
269 | if (s->regs[R_STATE0] == STATE_PENDING | |
270 | || s->regs[R_STATE1] == STATE_PENDING) { | |
271 | trace_milkymist_minimac2_raise_irq_rx(); | |
272 | qemu_irq_raise(s->rx_irq); | |
273 | } else { | |
274 | trace_milkymist_minimac2_lower_irq_rx(); | |
275 | qemu_irq_lower(s->rx_irq); | |
276 | } | |
277 | } | |
278 | ||
4e68f7a0 | 279 | static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size) |
07424544 | 280 | { |
cc1f0f45 | 281 | MilkymistMinimac2State *s = qemu_get_nic_opaque(nc); |
07424544 | 282 | |
07424544 MW |
283 | uint32_t r_count; |
284 | uint32_t r_state; | |
57aa265d | 285 | uint8_t *rx_buf; |
07424544 | 286 | |
07424544 MW |
287 | size_t frame_size; |
288 | ||
57aa265d | 289 | trace_milkymist_minimac2_rx_frame(buf, size); |
07424544 MW |
290 | |
291 | /* choose appropriate slot */ | |
292 | if (s->regs[R_STATE0] == STATE_LOADED) { | |
07424544 MW |
293 | r_count = R_COUNT0; |
294 | r_state = R_STATE0; | |
57aa265d | 295 | rx_buf = s->rx0_buf; |
07424544 | 296 | } else if (s->regs[R_STATE1] == STATE_LOADED) { |
07424544 MW |
297 | r_count = R_COUNT1; |
298 | r_state = R_STATE1; | |
57aa265d | 299 | rx_buf = s->rx1_buf; |
07424544 | 300 | } else { |
57aa265d | 301 | trace_milkymist_minimac2_drop_rx_frame(buf); |
07424544 MW |
302 | return size; |
303 | } | |
304 | ||
305 | /* assemble frame */ | |
57aa265d | 306 | frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size); |
07424544 MW |
307 | |
308 | if (frame_size == 0) { | |
309 | return size; | |
310 | } | |
311 | ||
57aa265d | 312 | trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size); |
07424544 MW |
313 | |
314 | /* update slot */ | |
315 | s->regs[r_count] = frame_size; | |
316 | s->regs[r_state] = STATE_PENDING; | |
317 | ||
57aa265d | 318 | update_rx_interrupt(s); |
07424544 MW |
319 | |
320 | return size; | |
321 | } | |
322 | ||
8a53d56f | 323 | static uint64_t |
a8170e5e | 324 | minimac2_read(void *opaque, hwaddr addr, unsigned size) |
07424544 | 325 | { |
57aa265d | 326 | MilkymistMinimac2State *s = opaque; |
07424544 MW |
327 | uint32_t r = 0; |
328 | ||
329 | addr >>= 2; | |
330 | switch (addr) { | |
331 | case R_SETUP: | |
332 | case R_MDIO: | |
333 | case R_STATE0: | |
07424544 MW |
334 | case R_COUNT0: |
335 | case R_STATE1: | |
07424544 | 336 | case R_COUNT1: |
07424544 MW |
337 | case R_TXCOUNT: |
338 | r = s->regs[addr]; | |
339 | break; | |
340 | ||
341 | default: | |
57aa265d | 342 | error_report("milkymist_minimac2: read access to unknown register 0x" |
07424544 MW |
343 | TARGET_FMT_plx, addr << 2); |
344 | break; | |
345 | } | |
346 | ||
57aa265d | 347 | trace_milkymist_minimac2_memory_read(addr << 2, r); |
07424544 MW |
348 | |
349 | return r; | |
350 | } | |
351 | ||
352 | static void | |
a8170e5e | 353 | minimac2_write(void *opaque, hwaddr addr, uint64_t value, |
8a53d56f | 354 | unsigned size) |
07424544 | 355 | { |
57aa265d | 356 | MilkymistMinimac2State *s = opaque; |
07424544 | 357 | |
57aa265d | 358 | trace_milkymist_minimac2_memory_read(addr, value); |
07424544 MW |
359 | |
360 | addr >>= 2; | |
361 | switch (addr) { | |
362 | case R_MDIO: | |
363 | { | |
364 | /* MDIO_DI is read only */ | |
365 | int mdio_di = (s->regs[R_MDIO] & MDIO_DI); | |
366 | s->regs[R_MDIO] = value; | |
367 | if (mdio_di) { | |
368 | s->regs[R_MDIO] |= mdio_di; | |
369 | } else { | |
370 | s->regs[R_MDIO] &= ~mdio_di; | |
371 | } | |
372 | ||
57aa265d | 373 | minimac2_update_mdio(s); |
07424544 MW |
374 | } break; |
375 | case R_TXCOUNT: | |
376 | s->regs[addr] = value; | |
377 | if (value > 0) { | |
57aa265d | 378 | minimac2_tx(s); |
07424544 MW |
379 | } |
380 | break; | |
07424544 | 381 | case R_STATE0: |
07424544 | 382 | case R_STATE1: |
57aa265d MW |
383 | s->regs[addr] = value; |
384 | update_rx_interrupt(s); | |
385 | break; | |
386 | case R_SETUP: | |
387 | case R_COUNT0: | |
07424544 | 388 | case R_COUNT1: |
07424544 MW |
389 | s->regs[addr] = value; |
390 | break; | |
391 | ||
392 | default: | |
57aa265d | 393 | error_report("milkymist_minimac2: write access to unknown register 0x" |
07424544 MW |
394 | TARGET_FMT_plx, addr << 2); |
395 | break; | |
396 | } | |
397 | } | |
398 | ||
8a53d56f AK |
399 | static const MemoryRegionOps minimac2_ops = { |
400 | .read = minimac2_read, | |
401 | .write = minimac2_write, | |
402 | .valid = { | |
403 | .min_access_size = 4, | |
404 | .max_access_size = 4, | |
405 | }, | |
406 | .endianness = DEVICE_NATIVE_ENDIAN, | |
07424544 MW |
407 | }; |
408 | ||
4e68f7a0 | 409 | static int minimac2_can_rx(NetClientState *nc) |
07424544 | 410 | { |
cc1f0f45 | 411 | MilkymistMinimac2State *s = qemu_get_nic_opaque(nc); |
07424544 MW |
412 | |
413 | if (s->regs[R_STATE0] == STATE_LOADED) { | |
414 | return 1; | |
415 | } | |
416 | if (s->regs[R_STATE1] == STATE_LOADED) { | |
417 | return 1; | |
418 | } | |
07424544 MW |
419 | |
420 | return 0; | |
421 | } | |
422 | ||
4e68f7a0 | 423 | static void minimac2_cleanup(NetClientState *nc) |
07424544 | 424 | { |
cc1f0f45 | 425 | MilkymistMinimac2State *s = qemu_get_nic_opaque(nc); |
07424544 MW |
426 | |
427 | s->nic = NULL; | |
428 | } | |
429 | ||
57aa265d | 430 | static void milkymist_minimac2_reset(DeviceState *d) |
07424544 | 431 | { |
57aa265d MW |
432 | MilkymistMinimac2State *s = |
433 | container_of(d, MilkymistMinimac2State, busdev.qdev); | |
07424544 MW |
434 | int i; |
435 | ||
436 | for (i = 0; i < R_MAX; i++) { | |
437 | s->regs[i] = 0; | |
438 | } | |
439 | for (i = 0; i < R_PHY_MAX; i++) { | |
440 | s->phy_regs[i] = 0; | |
441 | } | |
442 | ||
443 | /* defaults */ | |
444 | s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */ | |
445 | s->phy_regs[R_PHY_ID2] = 0x161a; | |
446 | } | |
447 | ||
57aa265d | 448 | static NetClientInfo net_milkymist_minimac2_info = { |
2be64a68 | 449 | .type = NET_CLIENT_OPTIONS_KIND_NIC, |
07424544 | 450 | .size = sizeof(NICState), |
57aa265d MW |
451 | .can_receive = minimac2_can_rx, |
452 | .receive = minimac2_rx, | |
453 | .cleanup = minimac2_cleanup, | |
07424544 MW |
454 | }; |
455 | ||
57aa265d | 456 | static int milkymist_minimac2_init(SysBusDevice *dev) |
07424544 | 457 | { |
57aa265d | 458 | MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev); |
57aa265d | 459 | size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE); |
07424544 MW |
460 | |
461 | sysbus_init_irq(dev, &s->rx_irq); | |
462 | sysbus_init_irq(dev, &s->tx_irq); | |
463 | ||
2c9b15ca | 464 | memory_region_init_io(&s->regs_region, NULL, &minimac2_ops, s, |
306f66b4 | 465 | "milkymist-minimac2", R_MAX * 4); |
750ecd44 | 466 | sysbus_init_mmio(dev, &s->regs_region); |
07424544 | 467 | |
57aa265d | 468 | /* register buffers memory */ |
2c9b15ca | 469 | memory_region_init_ram(&s->buffers, NULL, "milkymist-minimac2.buffers", |
8a53d56f | 470 | buffers_size); |
c5705a77 | 471 | vmstate_register_ram_global(&s->buffers); |
8a53d56f | 472 | s->rx0_buf = memory_region_get_ram_ptr(&s->buffers); |
57aa265d MW |
473 | s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE; |
474 | s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE; | |
475 | ||
20cf850c | 476 | sysbus_init_mmio(dev, &s->buffers); |
57aa265d | 477 | |
07424544 | 478 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
57aa265d | 479 | s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf, |
f79f2bfc | 480 | object_get_typename(OBJECT(dev)), dev->qdev.id, s); |
b356f76d | 481 | qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
07424544 MW |
482 | |
483 | return 0; | |
484 | } | |
485 | ||
57aa265d MW |
486 | static const VMStateDescription vmstate_milkymist_minimac2_mdio = { |
487 | .name = "milkymist-minimac2-mdio", | |
07424544 MW |
488 | .version_id = 1, |
489 | .minimum_version_id = 1, | |
490 | .minimum_version_id_old = 1, | |
491 | .fields = (VMStateField[]) { | |
57aa265d MW |
492 | VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState), |
493 | VMSTATE_INT32(count, MilkymistMinimac2MdioState), | |
494 | VMSTATE_UINT32(data, MilkymistMinimac2MdioState), | |
495 | VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState), | |
496 | VMSTATE_INT32(state, MilkymistMinimac2MdioState), | |
497 | VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState), | |
498 | VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState), | |
07424544 MW |
499 | VMSTATE_END_OF_LIST() |
500 | } | |
501 | }; | |
502 | ||
57aa265d MW |
503 | static const VMStateDescription vmstate_milkymist_minimac2 = { |
504 | .name = "milkymist-minimac2", | |
07424544 MW |
505 | .version_id = 1, |
506 | .minimum_version_id = 1, | |
507 | .minimum_version_id_old = 1, | |
508 | .fields = (VMStateField[]) { | |
57aa265d MW |
509 | VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX), |
510 | VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX), | |
511 | VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0, | |
512 | vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState), | |
07424544 MW |
513 | VMSTATE_END_OF_LIST() |
514 | } | |
515 | }; | |
516 | ||
999e12bb | 517 | static Property milkymist_minimac2_properties[] = { |
999e12bb AL |
518 | DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf), |
519 | DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model), | |
520 | DEFINE_PROP_END_OF_LIST(), | |
521 | }; | |
522 | ||
523 | static void milkymist_minimac2_class_init(ObjectClass *klass, void *data) | |
524 | { | |
39bffca2 | 525 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
526 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
527 | ||
528 | k->init = milkymist_minimac2_init; | |
39bffca2 AL |
529 | dc->reset = milkymist_minimac2_reset; |
530 | dc->vmsd = &vmstate_milkymist_minimac2; | |
531 | dc->props = milkymist_minimac2_properties; | |
999e12bb AL |
532 | } |
533 | ||
8c43a6f0 | 534 | static const TypeInfo milkymist_minimac2_info = { |
39bffca2 AL |
535 | .name = "milkymist-minimac2", |
536 | .parent = TYPE_SYS_BUS_DEVICE, | |
537 | .instance_size = sizeof(MilkymistMinimac2State), | |
538 | .class_init = milkymist_minimac2_class_init, | |
07424544 MW |
539 | }; |
540 | ||
83f7d43a | 541 | static void milkymist_minimac2_register_types(void) |
07424544 | 542 | { |
39bffca2 | 543 | type_register_static(&milkymist_minimac2_info); |
07424544 MW |
544 | } |
545 | ||
83f7d43a | 546 | type_init(milkymist_minimac2_register_types) |