[mirror_qemu.git] / hw / net / mipsnet.c

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "net/net.h"
#include "trace.h"
#include "hw/sysbus.h"

/* MIPSnet register offsets */

#define MIPSNET_DEV_ID		0x00
#define MIPSNET_BUSY		0x08
#define MIPSNET_RX_DATA_COUNT	0x0c
#define MIPSNET_TX_DATA_COUNT	0x10
#define MIPSNET_INT_CTL		0x14
# define MIPSNET_INTCTL_TXDONE		0x00000001
# define MIPSNET_INTCTL_RXDONE		0x00000002
# define MIPSNET_INTCTL_TESTBIT		0x80000000
#define MIPSNET_INTERRUPT_INFO	0x18
#define MIPSNET_RX_DATA_BUFFER	0x1c
#define MIPSNET_TX_DATA_BUFFER	0x20

#define MAX_ETH_FRAME_SIZE	1514

#define TYPE_MIPS_NET "mipsnet"
#define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)

typedef struct MIPSnetState {
    SysBusDevice parent_obj;

    uint32_t busy;
    uint32_t rx_count;
    uint32_t rx_read;
    uint32_t tx_count;
    uint32_t tx_written;
    uint32_t intctl;
    uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
    uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
    MemoryRegion io;
    qemu_irq irq;
    NICState *nic;
    NICConf conf;
} MIPSnetState;

static void mipsnet_reset(MIPSnetState *s)
{
    s->busy = 1;
    s->rx_count = 0;
    s->rx_read = 0;
    s->tx_count = 0;
    s->tx_written = 0;
    s->intctl = 0;
    memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
    memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
}

static void mipsnet_update_irq(MIPSnetState *s)
{
    int isr = !!s->intctl;
    trace_mipsnet_irq(isr, s->intctl);
    qemu_set_irq(s->irq, isr);
}

static int mipsnet_buffer_full(MIPSnetState *s)
{
    if (s->rx_count >= MAX_ETH_FRAME_SIZE)
        return 1;
    return 0;
}

static int mipsnet_can_receive(NetClientState *nc)
{
    MIPSnetState *s = qemu_get_nic_opaque(nc);

    if (s->busy)
        return 0;
    return !mipsnet_buffer_full(s);
}

static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
    MIPSnetState *s = qemu_get_nic_opaque(nc);

    trace_mipsnet_receive(size);
    if (!mipsnet_can_receive(nc))
        return 0;

    if (size >= sizeof(s->rx_buffer)) {
        return 0;
    }
    s->busy = 1;

    /* Just accept everything. */

    /* Write packet data. */
    memcpy(s->rx_buffer, buf, size);

    s->rx_count = size;
    s->rx_read = 0;

    /* Now we can signal we have received something. */
    s->intctl |= MIPSNET_INTCTL_RXDONE;
    mipsnet_update_irq(s);

    return size;
}

static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
                                    unsigned int size)
{
    MIPSnetState *s = opaque;
    int ret = 0;

    addr &= 0x3f;
    switch (addr) {
    case MIPSNET_DEV_ID:
	ret = be32_to_cpu(0x4d495053);		/* MIPS */
        break;
    case MIPSNET_DEV_ID + 4:
	ret = be32_to_cpu(0x4e455430);		/* NET0 */
        break;
    case MIPSNET_BUSY:
	ret = s->busy;
        break;
    case MIPSNET_RX_DATA_COUNT:
	ret = s->rx_count;
        break;
    case MIPSNET_TX_DATA_COUNT:
	ret = s->tx_count;
        break;
    case MIPSNET_INT_CTL:
	ret = s->intctl;
        s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
        break;
    case MIPSNET_INTERRUPT_INFO:
        /* XXX: This seems to be a per-VPE interrupt number. */
	ret = 0;
        break;
    case MIPSNET_RX_DATA_BUFFER:
        if (s->rx_count) {
            s->rx_count--;
            ret = s->rx_buffer[s->rx_read++];
            if (mipsnet_can_receive(s->nic->ncs)) {
                qemu_flush_queued_packets(qemu_get_queue(s->nic));
            }
        }
        break;
    /* Reads as zero. */
    case MIPSNET_TX_DATA_BUFFER:
    default:
        break;
    }
    trace_mipsnet_read(addr, ret);
    return ret;
}

static void mipsnet_ioport_write(void *opaque, hwaddr addr,
                                 uint64_t val, unsigned int size)
{
    MIPSnetState *s = opaque;

    addr &= 0x3f;
    trace_mipsnet_write(addr, val);
    switch (addr) {
    case MIPSNET_TX_DATA_COUNT:
	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
        s->tx_written = 0;
        break;
    case MIPSNET_INT_CTL:
        if (val & MIPSNET_INTCTL_TXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_TXDONE;
        } else if (val & MIPSNET_INTCTL_RXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_RXDONE;
        } else if (val & MIPSNET_INTCTL_TESTBIT) {
            mipsnet_reset(s);
            s->intctl |= MIPSNET_INTCTL_TESTBIT;
        } else if (!val) {
            /* ACK testbit interrupt, flag was cleared on read. */
        }
        s->busy = !!s->intctl;
        mipsnet_update_irq(s);
        if (mipsnet_can_receive(s->nic->ncs)) {
            qemu_flush_queued_packets(qemu_get_queue(s->nic));
        }
        break;
    case MIPSNET_TX_DATA_BUFFER:
        s->tx_buffer[s->tx_written++] = val;
        if ((s->tx_written >= MAX_ETH_FRAME_SIZE)
            || (s->tx_written == s->tx_count)) {
            /* Send buffer. */
            trace_mipsnet_send(s->tx_written);
            qemu_send_packet(qemu_get_queue(s->nic),
                                s->tx_buffer, s->tx_written);
            s->tx_count = s->tx_written = 0;
            s->intctl |= MIPSNET_INTCTL_TXDONE;
            s->busy = 1;
            mipsnet_update_irq(s);
        }
        break;
    /* Read-only registers */
    case MIPSNET_DEV_ID:
    case MIPSNET_BUSY:
    case MIPSNET_RX_DATA_COUNT:
    case MIPSNET_INTERRUPT_INFO:
    case MIPSNET_RX_DATA_BUFFER:
    default:
        break;
    }
}

static const VMStateDescription vmstate_mipsnet = {
    .name = "mipsnet",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(busy, MIPSnetState),
        VMSTATE_UINT32(rx_count, MIPSnetState),
        VMSTATE_UINT32(rx_read, MIPSnetState),
        VMSTATE_UINT32(tx_count, MIPSnetState),
        VMSTATE_UINT32(tx_written, MIPSnetState),
        VMSTATE_UINT32(intctl, MIPSnetState),
        VMSTATE_BUFFER(rx_buffer, MIPSnetState),
        VMSTATE_BUFFER(tx_buffer, MIPSnetState),
        VMSTATE_END_OF_LIST()
    }
};

static NetClientInfo net_mipsnet_info = {
    .type = NET_CLIENT_DRIVER_NIC,
    .size = sizeof(NICState),
    .receive = mipsnet_receive,
};

static const MemoryRegionOps mipsnet_ioport_ops = {
    .read = mipsnet_ioport_read,
    .write = mipsnet_ioport_write,
    .impl.min_access_size = 1,
    .impl.max_access_size = 4,
};

static int mipsnet_sysbus_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    MIPSnetState *s = MIPS_NET(dev);

    memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
                          "mipsnet-io", 36);
    sysbus_init_mmio(sbd, &s->io);
    sysbus_init_irq(sbd, &s->irq);

    s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
                          object_get_typename(OBJECT(dev)), dev->id, s);
    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);

    return 0;
}

static void mipsnet_sysbus_reset(DeviceState *dev)
{
    MIPSnetState *s = MIPS_NET(dev);
    mipsnet_reset(s);
}

static Property mipsnet_properties[] = {
    DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void mipsnet_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = mipsnet_sysbus_init;
    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
    dc->desc = "MIPS Simulator network device";
    dc->reset = mipsnet_sysbus_reset;
    dc->vmsd = &vmstate_mipsnet;
    dc->props = mipsnet_properties;
}

static const TypeInfo mipsnet_info = {
    .name          = TYPE_MIPS_NET,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MIPSnetState),
    .class_init    = mipsnet_class_init,
};

static void mipsnet_register_types(void)
{
    type_register_static(&mipsnet_info);
}

type_init(mipsnet_register_types)
Commit	Line	Data
e8d40465	1	#include "qemu/osdep.h"
83c9f4ca	2	#include "hw/hw.h"
1422e32d	3	#include "net/net.h"
83818f7c	4	#include "trace.h"
83c9f4ca	5	#include "hw/sysbus.h"
f0fc6f8f	6
f0fc6f8f TS	7	/* MIPSnet register offsets */
	8
	9	#define MIPSNET_DEV_ID 0x00
f0fc6f8f TS	10	#define MIPSNET_BUSY 0x08
	11	#define MIPSNET_RX_DATA_COUNT 0x0c
	12	#define MIPSNET_TX_DATA_COUNT 0x10
	13	#define MIPSNET_INT_CTL 0x14
	14	# define MIPSNET_INTCTL_TXDONE 0x00000001
	15	# define MIPSNET_INTCTL_RXDONE 0x00000002
	16	# define MIPSNET_INTCTL_TESTBIT 0x80000000
	17	#define MIPSNET_INTERRUPT_INFO 0x18
	18	#define MIPSNET_RX_DATA_BUFFER 0x1c
	19	#define MIPSNET_TX_DATA_BUFFER 0x20
	20
	21	#define MAX_ETH_FRAME_SIZE 1514
	22
a4dbb8bd AF	23	#define TYPE_MIPS_NET "mipsnet"
	24	#define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)
	25
f0fc6f8f	26	typedef struct MIPSnetState {
a4dbb8bd	27	SysBusDevice parent_obj;
d118d64a	28
f0fc6f8f TS	29	uint32_t busy;
	30	uint32_t rx_count;
	31	uint32_t rx_read;
	32	uint32_t tx_count;
	33	uint32_t tx_written;
	34	uint32_t intctl;
	35	uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
	36	uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
d118d64a	37	MemoryRegion io;
f0fc6f8f	38	qemu_irq irq;
1f30d10a MM	39	NICState *nic;
1f30d10a MM	40	NICConf conf;
f0fc6f8f TS	41	} MIPSnetState;
	42
	43	static void mipsnet_reset(MIPSnetState *s)
	44	{
	45	s->busy = 1;
	46	s->rx_count = 0;
	47	s->rx_read = 0;
	48	s->tx_count = 0;
	49	s->tx_written = 0;
	50	s->intctl = 0;
	51	memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
	52	memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
	53	}
	54
	55	static void mipsnet_update_irq(MIPSnetState *s)
	56	{
	57	int isr = !!s->intctl;
83818f7c	58	trace_mipsnet_irq(isr, s->intctl);
f0fc6f8f TS	59	qemu_set_irq(s->irq, isr);
	60	}
	61
	62	static int mipsnet_buffer_full(MIPSnetState *s)
	63	{
	64	if (s->rx_count >= MAX_ETH_FRAME_SIZE)
	65	return 1;
	66	return 0;
	67	}
	68
4e68f7a0	69	static int mipsnet_can_receive(NetClientState *nc)
f0fc6f8f	70	{
cc1f0f45	71	MIPSnetState *s = qemu_get_nic_opaque(nc);
f0fc6f8f TS	72
	73	if (s->busy)
	74	return 0;
	75	return !mipsnet_buffer_full(s);
	76	}
	77
4e68f7a0	78	static ssize_t mipsnet_receive(NetClientState nc, const uint8_t buf, size_t size)
f0fc6f8f	79	{
cc1f0f45	80	MIPSnetState *s = qemu_get_nic_opaque(nc);
f0fc6f8f	81
83818f7c	82	trace_mipsnet_receive(size);
1f30d10a	83	if (!mipsnet_can_receive(nc))
1dd58ae0	84	return 0;
f0fc6f8f	85
3af9187f PP	86	if (size >= sizeof(s->rx_buffer)) {
	87	return 0;
	88	}
f0fc6f8f TS	89	s->busy = 1;
	90
	91	/* Just accept everything. */
	92
	93	/* Write packet data. */
	94	memcpy(s->rx_buffer, buf, size);
	95
	96	s->rx_count = size;
	97	s->rx_read = 0;
	98
	99	/* Now we can signal we have received something. */
	100	s->intctl \|= MIPSNET_INTCTL_RXDONE;
	101	mipsnet_update_irq(s);
4f1c942b MM	102
4f1c942b MM	103	return size;
f0fc6f8f TS	104	}
f0fc6f8f TS	105
a8170e5e	106	static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
d118d64a	107	unsigned int size)
f0fc6f8f TS	108	{
	109	MIPSnetState *s = opaque;
	110	int ret = 0;
f0fc6f8f TS	111
	112	addr &= 0x3f;
	113	switch (addr) {
	114	case MIPSNET_DEV_ID:
9b595395	115	ret = be32_to_cpu(0x4d495053); /* MIPS */
f0fc6f8f TS	116	break;
f0fc6f8f TS	117	case MIPSNET_DEV_ID + 4:
9b595395	118	ret = be32_to_cpu(0x4e455430); /* NET0 */
f0fc6f8f TS	119	break;
	120	case MIPSNET_BUSY:
	121	ret = s->busy;
	122	break;
	123	case MIPSNET_RX_DATA_COUNT:
	124	ret = s->rx_count;
	125	break;
	126	case MIPSNET_TX_DATA_COUNT:
	127	ret = s->tx_count;
	128	break;
	129	case MIPSNET_INT_CTL:
	130	ret = s->intctl;
	131	s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
	132	break;
	133	case MIPSNET_INTERRUPT_INFO:
	134	/* XXX: This seems to be a per-VPE interrupt number. */
	135	ret = 0;
	136	break;
	137	case MIPSNET_RX_DATA_BUFFER:
	138	if (s->rx_count) {
	139	s->rx_count--;
	140	ret = s->rx_buffer[s->rx_read++];
1dd58ae0 FZ	141	if (mipsnet_can_receive(s->nic->ncs)) {
	142	qemu_flush_queued_packets(qemu_get_queue(s->nic));
	143	}
f0fc6f8f TS	144	}
	145	break;
	146	/* Reads as zero. */
	147	case MIPSNET_TX_DATA_BUFFER:
	148	default:
	149	break;
	150	}
83818f7c	151	trace_mipsnet_read(addr, ret);
f0fc6f8f TS	152	return ret;
	153	}
	154
a8170e5e	155	static void mipsnet_ioport_write(void *opaque, hwaddr addr,
d118d64a	156	uint64_t val, unsigned int size)
f0fc6f8f TS	157	{
	158	MIPSnetState *s = opaque;
	159
	160	addr &= 0x3f;
83818f7c	161	trace_mipsnet_write(addr, val);
f0fc6f8f TS	162	switch (addr) {
	163	case MIPSNET_TX_DATA_COUNT:
	164	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
	165	s->tx_written = 0;
	166	break;
	167	case MIPSNET_INT_CTL:
	168	if (val & MIPSNET_INTCTL_TXDONE) {
	169	s->intctl &= ~MIPSNET_INTCTL_TXDONE;
	170	} else if (val & MIPSNET_INTCTL_RXDONE) {
	171	s->intctl &= ~MIPSNET_INTCTL_RXDONE;
	172	} else if (val & MIPSNET_INTCTL_TESTBIT) {
	173	mipsnet_reset(s);
	174	s->intctl \|= MIPSNET_INTCTL_TESTBIT;
	175	} else if (!val) {
	176	/* ACK testbit interrupt, flag was cleared on read. */
	177	}
	178	s->busy = !!s->intctl;
	179	mipsnet_update_irq(s);
1dd58ae0 FZ	180	if (mipsnet_can_receive(s->nic->ncs)) {
	181	qemu_flush_queued_packets(qemu_get_queue(s->nic));
	182	}
f0fc6f8f TS	183	break;
	184	case MIPSNET_TX_DATA_BUFFER:
	185	s->tx_buffer[s->tx_written++] = val;
d88d3a09 PP	186	if ((s->tx_written >= MAX_ETH_FRAME_SIZE)
d88d3a09 PP	187	\|\| (s->tx_written == s->tx_count)) {
f0fc6f8f	188	/* Send buffer. */
d88d3a09 PP	189	trace_mipsnet_send(s->tx_written);
	190	qemu_send_packet(qemu_get_queue(s->nic),
	191	s->tx_buffer, s->tx_written);
f0fc6f8f TS	192	s->tx_count = s->tx_written = 0;
	193	s->intctl \|= MIPSNET_INTCTL_TXDONE;
	194	s->busy = 1;
	195	mipsnet_update_irq(s);
	196	}
	197	break;
	198	/* Read-only registers */
	199	case MIPSNET_DEV_ID:
	200	case MIPSNET_BUSY:
	201	case MIPSNET_RX_DATA_COUNT:
	202	case MIPSNET_INTERRUPT_INFO:
	203	case MIPSNET_RX_DATA_BUFFER:
	204	default:
	205	break;
	206	}
	207	}
	208
c7298ab2 JQ	209	static const VMStateDescription vmstate_mipsnet = {
	210	.name = "mipsnet",
	211	.version_id = 0,
	212	.minimum_version_id = 0,
35d08458	213	.fields = (VMStateField[]) {
c7298ab2 JQ	214	VMSTATE_UINT32(busy, MIPSnetState),
	215	VMSTATE_UINT32(rx_count, MIPSnetState),
	216	VMSTATE_UINT32(rx_read, MIPSnetState),
	217	VMSTATE_UINT32(tx_count, MIPSnetState),
	218	VMSTATE_UINT32(tx_written, MIPSnetState),
	219	VMSTATE_UINT32(intctl, MIPSnetState),
	220	VMSTATE_BUFFER(rx_buffer, MIPSnetState),
	221	VMSTATE_BUFFER(tx_buffer, MIPSnetState),
	222	VMSTATE_END_OF_LIST()
	223	}
	224	};
f0fc6f8f	225
1f30d10a	226	static NetClientInfo net_mipsnet_info = {
f394b2e2	227	.type = NET_CLIENT_DRIVER_NIC,
1f30d10a	228	.size = sizeof(NICState),
1f30d10a	229	.receive = mipsnet_receive,
1f30d10a MM	230	};
1f30d10a MM	231
a348f108	232	static const MemoryRegionOps mipsnet_ioport_ops = {
d118d64a HP	233	.read = mipsnet_ioport_read,
	234	.write = mipsnet_ioport_write,
	235	.impl.min_access_size = 1,
	236	.impl.max_access_size = 4,
	237	};
0ae18cee	238
a4dbb8bd	239	static int mipsnet_sysbus_init(SysBusDevice *sbd)
d118d64a	240	{
a4dbb8bd AF	241	DeviceState *dev = DEVICE(sbd);
a4dbb8bd AF	242	MIPSnetState *s = MIPS_NET(dev);
f0fc6f8f	243
eedfac6f PB	244	memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
eedfac6f PB	245	"mipsnet-io", 36);
a4dbb8bd AF	246	sysbus_init_mmio(sbd, &s->io);
a4dbb8bd AF	247	sysbus_init_irq(sbd, &s->irq);
f0fc6f8f	248
d118d64a	249	s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
a4dbb8bd	250	object_get_typename(OBJECT(dev)), dev->id, s);
b356f76d	251	qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1f30d10a	252
d118d64a HP	253	return 0;
d118d64a HP	254	}
f0fc6f8f	255
d118d64a HP	256	static void mipsnet_sysbus_reset(DeviceState *dev)
d118d64a HP	257	{
a4dbb8bd	258	MIPSnetState *s = MIPS_NET(dev);
d118d64a HP	259	mipsnet_reset(s);
d118d64a HP	260	}
1f30d10a	261
999e12bb AL	262	static Property mipsnet_properties[] = {
	263	DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
	264	DEFINE_PROP_END_OF_LIST(),
	265	};
	266
	267	static void mipsnet_class_init(ObjectClass klass, void data)
	268	{
39bffca2	269	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	270	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	271
	272	k->init = mipsnet_sysbus_init;
125ee0ed	273	set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
39bffca2 AL	274	dc->desc = "MIPS Simulator network device";
	275	dc->reset = mipsnet_sysbus_reset;
	276	dc->vmsd = &vmstate_mipsnet;
	277	dc->props = mipsnet_properties;
999e12bb AL	278	}
999e12bb AL	279
8c43a6f0	280	static const TypeInfo mipsnet_info = {
a4dbb8bd	281	.name = TYPE_MIPS_NET,
39bffca2 AL	282	.parent = TYPE_SYS_BUS_DEVICE,
	283	.instance_size = sizeof(MIPSnetState),
	284	.class_init = mipsnet_class_init,
d118d64a	285	};
f0fc6f8f	286
83f7d43a	287	static void mipsnet_register_types(void)
d118d64a	288	{
39bffca2	289	type_register_static(&mipsnet_info);
f0fc6f8f	290	}
d118d64a	291
83f7d43a	292	type_init(mipsnet_register_types)