]>
Commit | Line | Data |
---|---|---|
e8d40465 | 1 | #include "qemu/osdep.h" |
64552b6b | 2 | #include "hw/irq.h" |
a27bd6c7 | 3 | #include "hw/qdev-properties.h" |
1422e32d | 4 | #include "net/net.h" |
0b8fa32f | 5 | #include "qemu/module.h" |
83818f7c | 6 | #include "trace.h" |
83c9f4ca | 7 | #include "hw/sysbus.h" |
d6454270 | 8 | #include "migration/vmstate.h" |
db1015e9 | 9 | #include "qom/object.h" |
f0fc6f8f | 10 | |
f0fc6f8f TS |
11 | /* MIPSnet register offsets */ |
12 | ||
83aecbaa FB |
13 | #define MIPSNET_DEV_ID 0x00 |
14 | #define MIPSNET_BUSY 0x08 | |
15 | #define MIPSNET_RX_DATA_COUNT 0x0c | |
16 | #define MIPSNET_TX_DATA_COUNT 0x10 | |
17 | #define MIPSNET_INT_CTL 0x14 | |
18 | # define MIPSNET_INTCTL_TXDONE 0x00000001 | |
19 | # define MIPSNET_INTCTL_RXDONE 0x00000002 | |
20 | # define MIPSNET_INTCTL_TESTBIT 0x80000000 | |
21 | #define MIPSNET_INTERRUPT_INFO 0x18 | |
22 | #define MIPSNET_RX_DATA_BUFFER 0x1c | |
23 | #define MIPSNET_TX_DATA_BUFFER 0x20 | |
24 | ||
25 | #define MAX_ETH_FRAME_SIZE 1514 | |
f0fc6f8f | 26 | |
a4dbb8bd | 27 | #define TYPE_MIPS_NET "mipsnet" |
db1015e9 | 28 | typedef struct MIPSnetState MIPSnetState; |
a4dbb8bd AF |
29 | #define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET) |
30 | ||
db1015e9 | 31 | struct MIPSnetState { |
a4dbb8bd | 32 | SysBusDevice parent_obj; |
d118d64a | 33 | |
f0fc6f8f TS |
34 | uint32_t busy; |
35 | uint32_t rx_count; | |
36 | uint32_t rx_read; | |
37 | uint32_t tx_count; | |
38 | uint32_t tx_written; | |
39 | uint32_t intctl; | |
40 | uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; | |
41 | uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; | |
d118d64a | 42 | MemoryRegion io; |
f0fc6f8f | 43 | qemu_irq irq; |
1f30d10a MM |
44 | NICState *nic; |
45 | NICConf conf; | |
db1015e9 | 46 | }; |
f0fc6f8f TS |
47 | |
48 | static void mipsnet_reset(MIPSnetState *s) | |
49 | { | |
50 | s->busy = 1; | |
51 | s->rx_count = 0; | |
52 | s->rx_read = 0; | |
53 | s->tx_count = 0; | |
54 | s->tx_written = 0; | |
55 | s->intctl = 0; | |
56 | memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE); | |
57 | memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE); | |
58 | } | |
59 | ||
60 | static void mipsnet_update_irq(MIPSnetState *s) | |
61 | { | |
62 | int isr = !!s->intctl; | |
83818f7c | 63 | trace_mipsnet_irq(isr, s->intctl); |
f0fc6f8f TS |
64 | qemu_set_irq(s->irq, isr); |
65 | } | |
66 | ||
67 | static int mipsnet_buffer_full(MIPSnetState *s) | |
68 | { | |
83aecbaa | 69 | if (s->rx_count >= MAX_ETH_FRAME_SIZE) { |
f0fc6f8f | 70 | return 1; |
83aecbaa | 71 | } |
f0fc6f8f TS |
72 | return 0; |
73 | } | |
74 | ||
4e68f7a0 | 75 | static int mipsnet_can_receive(NetClientState *nc) |
f0fc6f8f | 76 | { |
cc1f0f45 | 77 | MIPSnetState *s = qemu_get_nic_opaque(nc); |
f0fc6f8f | 78 | |
83aecbaa | 79 | if (s->busy) { |
f0fc6f8f | 80 | return 0; |
83aecbaa | 81 | } |
f0fc6f8f TS |
82 | return !mipsnet_buffer_full(s); |
83 | } | |
84 | ||
83aecbaa FB |
85 | static ssize_t mipsnet_receive(NetClientState *nc, |
86 | const uint8_t *buf, size_t size) | |
f0fc6f8f | 87 | { |
cc1f0f45 | 88 | MIPSnetState *s = qemu_get_nic_opaque(nc); |
f0fc6f8f | 89 | |
83818f7c | 90 | trace_mipsnet_receive(size); |
83aecbaa | 91 | if (!mipsnet_can_receive(nc)) { |
1dd58ae0 | 92 | return 0; |
83aecbaa | 93 | } |
f0fc6f8f | 94 | |
3af9187f PP |
95 | if (size >= sizeof(s->rx_buffer)) { |
96 | return 0; | |
97 | } | |
f0fc6f8f TS |
98 | s->busy = 1; |
99 | ||
100 | /* Just accept everything. */ | |
101 | ||
102 | /* Write packet data. */ | |
103 | memcpy(s->rx_buffer, buf, size); | |
104 | ||
105 | s->rx_count = size; | |
106 | s->rx_read = 0; | |
107 | ||
108 | /* Now we can signal we have received something. */ | |
109 | s->intctl |= MIPSNET_INTCTL_RXDONE; | |
110 | mipsnet_update_irq(s); | |
4f1c942b MM |
111 | |
112 | return size; | |
f0fc6f8f TS |
113 | } |
114 | ||
a8170e5e | 115 | static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr, |
d118d64a | 116 | unsigned int size) |
f0fc6f8f TS |
117 | { |
118 | MIPSnetState *s = opaque; | |
119 | int ret = 0; | |
f0fc6f8f TS |
120 | |
121 | addr &= 0x3f; | |
122 | switch (addr) { | |
123 | case MIPSNET_DEV_ID: | |
83aecbaa | 124 | ret = be32_to_cpu(0x4d495053); /* MIPS */ |
f0fc6f8f TS |
125 | break; |
126 | case MIPSNET_DEV_ID + 4: | |
83aecbaa | 127 | ret = be32_to_cpu(0x4e455430); /* NET0 */ |
f0fc6f8f TS |
128 | break; |
129 | case MIPSNET_BUSY: | |
7d37435b | 130 | ret = s->busy; |
f0fc6f8f TS |
131 | break; |
132 | case MIPSNET_RX_DATA_COUNT: | |
7d37435b | 133 | ret = s->rx_count; |
f0fc6f8f TS |
134 | break; |
135 | case MIPSNET_TX_DATA_COUNT: | |
7d37435b | 136 | ret = s->tx_count; |
f0fc6f8f TS |
137 | break; |
138 | case MIPSNET_INT_CTL: | |
7d37435b | 139 | ret = s->intctl; |
f0fc6f8f TS |
140 | s->intctl &= ~MIPSNET_INTCTL_TESTBIT; |
141 | break; | |
142 | case MIPSNET_INTERRUPT_INFO: | |
143 | /* XXX: This seems to be a per-VPE interrupt number. */ | |
7d37435b | 144 | ret = 0; |
f0fc6f8f TS |
145 | break; |
146 | case MIPSNET_RX_DATA_BUFFER: | |
147 | if (s->rx_count) { | |
148 | s->rx_count--; | |
149 | ret = s->rx_buffer[s->rx_read++]; | |
1dd58ae0 FZ |
150 | if (mipsnet_can_receive(s->nic->ncs)) { |
151 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | |
152 | } | |
f0fc6f8f TS |
153 | } |
154 | break; | |
155 | /* Reads as zero. */ | |
156 | case MIPSNET_TX_DATA_BUFFER: | |
157 | default: | |
158 | break; | |
159 | } | |
83818f7c | 160 | trace_mipsnet_read(addr, ret); |
f0fc6f8f TS |
161 | return ret; |
162 | } | |
163 | ||
a8170e5e | 164 | static void mipsnet_ioport_write(void *opaque, hwaddr addr, |
d118d64a | 165 | uint64_t val, unsigned int size) |
f0fc6f8f TS |
166 | { |
167 | MIPSnetState *s = opaque; | |
168 | ||
169 | addr &= 0x3f; | |
83818f7c | 170 | trace_mipsnet_write(addr, val); |
f0fc6f8f TS |
171 | switch (addr) { |
172 | case MIPSNET_TX_DATA_COUNT: | |
7d37435b | 173 | s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; |
f0fc6f8f TS |
174 | s->tx_written = 0; |
175 | break; | |
176 | case MIPSNET_INT_CTL: | |
177 | if (val & MIPSNET_INTCTL_TXDONE) { | |
178 | s->intctl &= ~MIPSNET_INTCTL_TXDONE; | |
179 | } else if (val & MIPSNET_INTCTL_RXDONE) { | |
180 | s->intctl &= ~MIPSNET_INTCTL_RXDONE; | |
181 | } else if (val & MIPSNET_INTCTL_TESTBIT) { | |
182 | mipsnet_reset(s); | |
183 | s->intctl |= MIPSNET_INTCTL_TESTBIT; | |
184 | } else if (!val) { | |
185 | /* ACK testbit interrupt, flag was cleared on read. */ | |
186 | } | |
187 | s->busy = !!s->intctl; | |
188 | mipsnet_update_irq(s); | |
1dd58ae0 FZ |
189 | if (mipsnet_can_receive(s->nic->ncs)) { |
190 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | |
191 | } | |
f0fc6f8f TS |
192 | break; |
193 | case MIPSNET_TX_DATA_BUFFER: | |
194 | s->tx_buffer[s->tx_written++] = val; | |
d88d3a09 PP |
195 | if ((s->tx_written >= MAX_ETH_FRAME_SIZE) |
196 | || (s->tx_written == s->tx_count)) { | |
f0fc6f8f | 197 | /* Send buffer. */ |
d88d3a09 PP |
198 | trace_mipsnet_send(s->tx_written); |
199 | qemu_send_packet(qemu_get_queue(s->nic), | |
200 | s->tx_buffer, s->tx_written); | |
f0fc6f8f TS |
201 | s->tx_count = s->tx_written = 0; |
202 | s->intctl |= MIPSNET_INTCTL_TXDONE; | |
203 | s->busy = 1; | |
204 | mipsnet_update_irq(s); | |
205 | } | |
206 | break; | |
207 | /* Read-only registers */ | |
208 | case MIPSNET_DEV_ID: | |
209 | case MIPSNET_BUSY: | |
210 | case MIPSNET_RX_DATA_COUNT: | |
211 | case MIPSNET_INTERRUPT_INFO: | |
212 | case MIPSNET_RX_DATA_BUFFER: | |
213 | default: | |
214 | break; | |
215 | } | |
216 | } | |
217 | ||
c7298ab2 JQ |
218 | static const VMStateDescription vmstate_mipsnet = { |
219 | .name = "mipsnet", | |
220 | .version_id = 0, | |
221 | .minimum_version_id = 0, | |
35d08458 | 222 | .fields = (VMStateField[]) { |
c7298ab2 JQ |
223 | VMSTATE_UINT32(busy, MIPSnetState), |
224 | VMSTATE_UINT32(rx_count, MIPSnetState), | |
225 | VMSTATE_UINT32(rx_read, MIPSnetState), | |
226 | VMSTATE_UINT32(tx_count, MIPSnetState), | |
227 | VMSTATE_UINT32(tx_written, MIPSnetState), | |
228 | VMSTATE_UINT32(intctl, MIPSnetState), | |
229 | VMSTATE_BUFFER(rx_buffer, MIPSnetState), | |
230 | VMSTATE_BUFFER(tx_buffer, MIPSnetState), | |
231 | VMSTATE_END_OF_LIST() | |
232 | } | |
233 | }; | |
f0fc6f8f | 234 | |
1f30d10a | 235 | static NetClientInfo net_mipsnet_info = { |
f394b2e2 | 236 | .type = NET_CLIENT_DRIVER_NIC, |
1f30d10a | 237 | .size = sizeof(NICState), |
1f30d10a | 238 | .receive = mipsnet_receive, |
1f30d10a MM |
239 | }; |
240 | ||
a348f108 | 241 | static const MemoryRegionOps mipsnet_ioport_ops = { |
d118d64a HP |
242 | .read = mipsnet_ioport_read, |
243 | .write = mipsnet_ioport_write, | |
244 | .impl.min_access_size = 1, | |
245 | .impl.max_access_size = 4, | |
246 | }; | |
0ae18cee | 247 | |
04cb1572 | 248 | static void mipsnet_realize(DeviceState *dev, Error **errp) |
d118d64a | 249 | { |
04cb1572 | 250 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
a4dbb8bd | 251 | MIPSnetState *s = MIPS_NET(dev); |
f0fc6f8f | 252 | |
eedfac6f PB |
253 | memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s, |
254 | "mipsnet-io", 36); | |
a4dbb8bd AF |
255 | sysbus_init_mmio(sbd, &s->io); |
256 | sysbus_init_irq(sbd, &s->irq); | |
f0fc6f8f | 257 | |
d118d64a | 258 | s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf, |
a4dbb8bd | 259 | object_get_typename(OBJECT(dev)), dev->id, s); |
b356f76d | 260 | qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
d118d64a | 261 | } |
f0fc6f8f | 262 | |
d118d64a HP |
263 | static void mipsnet_sysbus_reset(DeviceState *dev) |
264 | { | |
a4dbb8bd | 265 | MIPSnetState *s = MIPS_NET(dev); |
d118d64a HP |
266 | mipsnet_reset(s); |
267 | } | |
1f30d10a | 268 | |
999e12bb AL |
269 | static Property mipsnet_properties[] = { |
270 | DEFINE_NIC_PROPERTIES(MIPSnetState, conf), | |
271 | DEFINE_PROP_END_OF_LIST(), | |
272 | }; | |
273 | ||
274 | static void mipsnet_class_init(ObjectClass *klass, void *data) | |
275 | { | |
39bffca2 | 276 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 277 | |
04cb1572 | 278 | dc->realize = mipsnet_realize; |
125ee0ed | 279 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
39bffca2 AL |
280 | dc->desc = "MIPS Simulator network device"; |
281 | dc->reset = mipsnet_sysbus_reset; | |
282 | dc->vmsd = &vmstate_mipsnet; | |
4f67d30b | 283 | device_class_set_props(dc, mipsnet_properties); |
999e12bb AL |
284 | } |
285 | ||
8c43a6f0 | 286 | static const TypeInfo mipsnet_info = { |
a4dbb8bd | 287 | .name = TYPE_MIPS_NET, |
39bffca2 AL |
288 | .parent = TYPE_SYS_BUS_DEVICE, |
289 | .instance_size = sizeof(MIPSnetState), | |
290 | .class_init = mipsnet_class_init, | |
d118d64a | 291 | }; |
f0fc6f8f | 292 | |
83f7d43a | 293 | static void mipsnet_register_types(void) |
d118d64a | 294 | { |
39bffca2 | 295 | type_register_static(&mipsnet_info); |
f0fc6f8f | 296 | } |
d118d64a | 297 | |
83f7d43a | 298 | type_init(mipsnet_register_types) |