[mirror_qemu.git] / hw / net / mipsnet.c

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "net/net.h"
#include "qemu/module.h"
#include "trace.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"

/* MIPSnet register offsets */

#define MIPSNET_DEV_ID		0x00
#define MIPSNET_BUSY		0x08
#define MIPSNET_RX_DATA_COUNT	0x0c
#define MIPSNET_TX_DATA_COUNT	0x10
#define MIPSNET_INT_CTL		0x14
# define MIPSNET_INTCTL_TXDONE		0x00000001
# define MIPSNET_INTCTL_RXDONE		0x00000002
# define MIPSNET_INTCTL_TESTBIT		0x80000000
#define MIPSNET_INTERRUPT_INFO	0x18
#define MIPSNET_RX_DATA_BUFFER	0x1c
#define MIPSNET_TX_DATA_BUFFER	0x20

#define MAX_ETH_FRAME_SIZE	1514

#define TYPE_MIPS_NET "mipsnet"
#define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)

typedef struct MIPSnetState {
    SysBusDevice parent_obj;

    uint32_t busy;
    uint32_t rx_count;
    uint32_t rx_read;
    uint32_t tx_count;
    uint32_t tx_written;
    uint32_t intctl;
    uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
    uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
    MemoryRegion io;
    qemu_irq irq;
    NICState *nic;
    NICConf conf;
} MIPSnetState;

static void mipsnet_reset(MIPSnetState *s)
{
    s->busy = 1;
    s->rx_count = 0;
    s->rx_read = 0;
    s->tx_count = 0;
    s->tx_written = 0;
    s->intctl = 0;
    memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
    memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
}

static void mipsnet_update_irq(MIPSnetState *s)
{
    int isr = !!s->intctl;
    trace_mipsnet_irq(isr, s->intctl);
    qemu_set_irq(s->irq, isr);
}

static int mipsnet_buffer_full(MIPSnetState *s)
{
    if (s->rx_count >= MAX_ETH_FRAME_SIZE)
        return 1;
    return 0;
}

static int mipsnet_can_receive(NetClientState *nc)
{
    MIPSnetState *s = qemu_get_nic_opaque(nc);

    if (s->busy)
        return 0;
    return !mipsnet_buffer_full(s);
}

static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
    MIPSnetState *s = qemu_get_nic_opaque(nc);

    trace_mipsnet_receive(size);
    if (!mipsnet_can_receive(nc))
        return 0;

    if (size >= sizeof(s->rx_buffer)) {
        return 0;
    }
    s->busy = 1;

    /* Just accept everything. */

    /* Write packet data. */
    memcpy(s->rx_buffer, buf, size);

    s->rx_count = size;
    s->rx_read = 0;

    /* Now we can signal we have received something. */
    s->intctl |= MIPSNET_INTCTL_RXDONE;
    mipsnet_update_irq(s);

    return size;
}

static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
                                    unsigned int size)
{
    MIPSnetState *s = opaque;
    int ret = 0;

    addr &= 0x3f;
    switch (addr) {
    case MIPSNET_DEV_ID:
        ret = be32_to_cpu(0x4d495053);		/* MIPS */
        break;
    case MIPSNET_DEV_ID + 4:
        ret = be32_to_cpu(0x4e455430);		/* NET0 */
        break;
    case MIPSNET_BUSY:
        ret = s->busy;
        break;
    case MIPSNET_RX_DATA_COUNT:
        ret = s->rx_count;
        break;
    case MIPSNET_TX_DATA_COUNT:
        ret = s->tx_count;
        break;
    case MIPSNET_INT_CTL:
        ret = s->intctl;
        s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
        break;
    case MIPSNET_INTERRUPT_INFO:
        /* XXX: This seems to be a per-VPE interrupt number. */
        ret = 0;
        break;
    case MIPSNET_RX_DATA_BUFFER:
        if (s->rx_count) {
            s->rx_count--;
            ret = s->rx_buffer[s->rx_read++];
            if (mipsnet_can_receive(s->nic->ncs)) {
                qemu_flush_queued_packets(qemu_get_queue(s->nic));
            }
        }
        break;
    /* Reads as zero. */
    case MIPSNET_TX_DATA_BUFFER:
    default:
        break;
    }
    trace_mipsnet_read(addr, ret);
    return ret;
}

static void mipsnet_ioport_write(void *opaque, hwaddr addr,
                                 uint64_t val, unsigned int size)
{
    MIPSnetState *s = opaque;

    addr &= 0x3f;
    trace_mipsnet_write(addr, val);
    switch (addr) {
    case MIPSNET_TX_DATA_COUNT:
        s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
        s->tx_written = 0;
        break;
    case MIPSNET_INT_CTL:
        if (val & MIPSNET_INTCTL_TXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_TXDONE;
        } else if (val & MIPSNET_INTCTL_RXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_RXDONE;
        } else if (val & MIPSNET_INTCTL_TESTBIT) {
            mipsnet_reset(s);
            s->intctl |= MIPSNET_INTCTL_TESTBIT;
        } else if (!val) {
            /* ACK testbit interrupt, flag was cleared on read. */
        }
        s->busy = !!s->intctl;
        mipsnet_update_irq(s);
        if (mipsnet_can_receive(s->nic->ncs)) {
            qemu_flush_queued_packets(qemu_get_queue(s->nic));
        }
        break;
    case MIPSNET_TX_DATA_BUFFER:
        s->tx_buffer[s->tx_written++] = val;
        if ((s->tx_written >= MAX_ETH_FRAME_SIZE)
            || (s->tx_written == s->tx_count)) {
            /* Send buffer. */
            trace_mipsnet_send(s->tx_written);
            qemu_send_packet(qemu_get_queue(s->nic),
                                s->tx_buffer, s->tx_written);
            s->tx_count = s->tx_written = 0;
            s->intctl |= MIPSNET_INTCTL_TXDONE;
            s->busy = 1;
            mipsnet_update_irq(s);
        }
        break;
    /* Read-only registers */
    case MIPSNET_DEV_ID:
    case MIPSNET_BUSY:
    case MIPSNET_RX_DATA_COUNT:
    case MIPSNET_INTERRUPT_INFO:
    case MIPSNET_RX_DATA_BUFFER:
    default:
        break;
    }
}

static const VMStateDescription vmstate_mipsnet = {
    .name = "mipsnet",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(busy, MIPSnetState),
        VMSTATE_UINT32(rx_count, MIPSnetState),
        VMSTATE_UINT32(rx_read, MIPSnetState),
        VMSTATE_UINT32(tx_count, MIPSnetState),
        VMSTATE_UINT32(tx_written, MIPSnetState),
        VMSTATE_UINT32(intctl, MIPSnetState),
        VMSTATE_BUFFER(rx_buffer, MIPSnetState),
        VMSTATE_BUFFER(tx_buffer, MIPSnetState),
        VMSTATE_END_OF_LIST()
    }
};

static NetClientInfo net_mipsnet_info = {
    .type = NET_CLIENT_DRIVER_NIC,
    .size = sizeof(NICState),
    .receive = mipsnet_receive,
};

static const MemoryRegionOps mipsnet_ioport_ops = {
    .read = mipsnet_ioport_read,
    .write = mipsnet_ioport_write,
    .impl.min_access_size = 1,
    .impl.max_access_size = 4,
};

static void mipsnet_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    MIPSnetState *s = MIPS_NET(dev);

    memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
                          "mipsnet-io", 36);
    sysbus_init_mmio(sbd, &s->io);
    sysbus_init_irq(sbd, &s->irq);

    s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
                          object_get_typename(OBJECT(dev)), dev->id, s);
    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
}

static void mipsnet_sysbus_reset(DeviceState *dev)
{
    MIPSnetState *s = MIPS_NET(dev);
    mipsnet_reset(s);
}

static Property mipsnet_properties[] = {
    DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void mipsnet_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = mipsnet_realize;
    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
    dc->desc = "MIPS Simulator network device";
    dc->reset = mipsnet_sysbus_reset;
    dc->vmsd = &vmstate_mipsnet;
    dc->props = mipsnet_properties;
}

static const TypeInfo mipsnet_info = {
    .name          = TYPE_MIPS_NET,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MIPSnetState),
    .class_init    = mipsnet_class_init,
};

static void mipsnet_register_types(void)
{
    type_register_static(&mipsnet_info);
}

type_init(mipsnet_register_types)
Commit	Line	Data
e8d40465	1	#include "qemu/osdep.h"
64552b6b	2	#include "hw/irq.h"
a27bd6c7	3	#include "hw/qdev-properties.h"
1422e32d	4	#include "net/net.h"
0b8fa32f	5	#include "qemu/module.h"
83818f7c	6	#include "trace.h"
83c9f4ca	7	#include "hw/sysbus.h"
d6454270	8	#include "migration/vmstate.h"
f0fc6f8f	9
f0fc6f8f TS	10	/* MIPSnet register offsets */
	11
	12	#define MIPSNET_DEV_ID 0x00
f0fc6f8f TS	13	#define MIPSNET_BUSY 0x08
	14	#define MIPSNET_RX_DATA_COUNT 0x0c
	15	#define MIPSNET_TX_DATA_COUNT 0x10
	16	#define MIPSNET_INT_CTL 0x14
	17	# define MIPSNET_INTCTL_TXDONE 0x00000001
	18	# define MIPSNET_INTCTL_RXDONE 0x00000002
	19	# define MIPSNET_INTCTL_TESTBIT 0x80000000
	20	#define MIPSNET_INTERRUPT_INFO 0x18
	21	#define MIPSNET_RX_DATA_BUFFER 0x1c
	22	#define MIPSNET_TX_DATA_BUFFER 0x20
	23
	24	#define MAX_ETH_FRAME_SIZE 1514
	25
a4dbb8bd AF	26	#define TYPE_MIPS_NET "mipsnet"
	27	#define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)
	28
f0fc6f8f	29	typedef struct MIPSnetState {
a4dbb8bd	30	SysBusDevice parent_obj;
d118d64a	31
f0fc6f8f TS	32	uint32_t busy;
	33	uint32_t rx_count;
	34	uint32_t rx_read;
	35	uint32_t tx_count;
	36	uint32_t tx_written;
	37	uint32_t intctl;
	38	uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
	39	uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
d118d64a	40	MemoryRegion io;
f0fc6f8f	41	qemu_irq irq;
1f30d10a MM	42	NICState *nic;
1f30d10a MM	43	NICConf conf;
f0fc6f8f TS	44	} MIPSnetState;
	45
	46	static void mipsnet_reset(MIPSnetState *s)
	47	{
	48	s->busy = 1;
	49	s->rx_count = 0;
	50	s->rx_read = 0;
	51	s->tx_count = 0;
	52	s->tx_written = 0;
	53	s->intctl = 0;
	54	memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
	55	memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
	56	}
	57
	58	static void mipsnet_update_irq(MIPSnetState *s)
	59	{
	60	int isr = !!s->intctl;
83818f7c	61	trace_mipsnet_irq(isr, s->intctl);
f0fc6f8f TS	62	qemu_set_irq(s->irq, isr);
	63	}
	64
	65	static int mipsnet_buffer_full(MIPSnetState *s)
	66	{
	67	if (s->rx_count >= MAX_ETH_FRAME_SIZE)
	68	return 1;
	69	return 0;
	70	}
	71
4e68f7a0	72	static int mipsnet_can_receive(NetClientState *nc)
f0fc6f8f	73	{
cc1f0f45	74	MIPSnetState *s = qemu_get_nic_opaque(nc);
f0fc6f8f TS	75
	76	if (s->busy)
	77	return 0;
	78	return !mipsnet_buffer_full(s);
	79	}
	80
4e68f7a0	81	static ssize_t mipsnet_receive(NetClientState nc, const uint8_t buf, size_t size)
f0fc6f8f	82	{
cc1f0f45	83	MIPSnetState *s = qemu_get_nic_opaque(nc);
f0fc6f8f	84
83818f7c	85	trace_mipsnet_receive(size);
1f30d10a	86	if (!mipsnet_can_receive(nc))
1dd58ae0	87	return 0;
f0fc6f8f	88
3af9187f PP	89	if (size >= sizeof(s->rx_buffer)) {
	90	return 0;
	91	}
f0fc6f8f TS	92	s->busy = 1;
	93
	94	/* Just accept everything. */
	95
	96	/* Write packet data. */
	97	memcpy(s->rx_buffer, buf, size);
	98
	99	s->rx_count = size;
	100	s->rx_read = 0;
	101
	102	/* Now we can signal we have received something. */
	103	s->intctl \|= MIPSNET_INTCTL_RXDONE;
	104	mipsnet_update_irq(s);
4f1c942b MM	105
4f1c942b MM	106	return size;
f0fc6f8f TS	107	}
f0fc6f8f TS	108
a8170e5e	109	static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
d118d64a	110	unsigned int size)
f0fc6f8f TS	111	{
	112	MIPSnetState *s = opaque;
	113	int ret = 0;
f0fc6f8f TS	114
	115	addr &= 0x3f;
	116	switch (addr) {
	117	case MIPSNET_DEV_ID:
7d37435b	118	ret = be32_to_cpu(0x4d495053); /* MIPS */
f0fc6f8f TS	119	break;
f0fc6f8f TS	120	case MIPSNET_DEV_ID + 4:
7d37435b	121	ret = be32_to_cpu(0x4e455430); /* NET0 */
f0fc6f8f TS	122	break;
f0fc6f8f TS	123	case MIPSNET_BUSY:
7d37435b	124	ret = s->busy;
f0fc6f8f TS	125	break;
f0fc6f8f TS	126	case MIPSNET_RX_DATA_COUNT:
7d37435b	127	ret = s->rx_count;
f0fc6f8f TS	128	break;
f0fc6f8f TS	129	case MIPSNET_TX_DATA_COUNT:
7d37435b	130	ret = s->tx_count;
f0fc6f8f TS	131	break;
f0fc6f8f TS	132	case MIPSNET_INT_CTL:
7d37435b	133	ret = s->intctl;
f0fc6f8f TS	134	s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
	135	break;
	136	case MIPSNET_INTERRUPT_INFO:
	137	/* XXX: This seems to be a per-VPE interrupt number. */
7d37435b	138	ret = 0;
f0fc6f8f TS	139	break;
	140	case MIPSNET_RX_DATA_BUFFER:
	141	if (s->rx_count) {
	142	s->rx_count--;
	143	ret = s->rx_buffer[s->rx_read++];
1dd58ae0 FZ	144	if (mipsnet_can_receive(s->nic->ncs)) {
	145	qemu_flush_queued_packets(qemu_get_queue(s->nic));
	146	}
f0fc6f8f TS	147	}
	148	break;
	149	/* Reads as zero. */
	150	case MIPSNET_TX_DATA_BUFFER:
	151	default:
	152	break;
	153	}
83818f7c	154	trace_mipsnet_read(addr, ret);
f0fc6f8f TS	155	return ret;
	156	}
	157
a8170e5e	158	static void mipsnet_ioport_write(void *opaque, hwaddr addr,
d118d64a	159	uint64_t val, unsigned int size)
f0fc6f8f TS	160	{
	161	MIPSnetState *s = opaque;
	162
	163	addr &= 0x3f;
83818f7c	164	trace_mipsnet_write(addr, val);
f0fc6f8f TS	165	switch (addr) {
f0fc6f8f TS	166	case MIPSNET_TX_DATA_COUNT:
7d37435b	167	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
f0fc6f8f TS	168	s->tx_written = 0;
	169	break;
	170	case MIPSNET_INT_CTL:
	171	if (val & MIPSNET_INTCTL_TXDONE) {
	172	s->intctl &= ~MIPSNET_INTCTL_TXDONE;
	173	} else if (val & MIPSNET_INTCTL_RXDONE) {
	174	s->intctl &= ~MIPSNET_INTCTL_RXDONE;
	175	} else if (val & MIPSNET_INTCTL_TESTBIT) {
	176	mipsnet_reset(s);
	177	s->intctl \|= MIPSNET_INTCTL_TESTBIT;
	178	} else if (!val) {
	179	/* ACK testbit interrupt, flag was cleared on read. */
	180	}
	181	s->busy = !!s->intctl;
	182	mipsnet_update_irq(s);
1dd58ae0 FZ	183	if (mipsnet_can_receive(s->nic->ncs)) {
	184	qemu_flush_queued_packets(qemu_get_queue(s->nic));
	185	}
f0fc6f8f TS	186	break;
	187	case MIPSNET_TX_DATA_BUFFER:
	188	s->tx_buffer[s->tx_written++] = val;
d88d3a09 PP	189	if ((s->tx_written >= MAX_ETH_FRAME_SIZE)
d88d3a09 PP	190	\|\| (s->tx_written == s->tx_count)) {
f0fc6f8f	191	/* Send buffer. */
d88d3a09 PP	192	trace_mipsnet_send(s->tx_written);
	193	qemu_send_packet(qemu_get_queue(s->nic),
	194	s->tx_buffer, s->tx_written);
f0fc6f8f TS	195	s->tx_count = s->tx_written = 0;
	196	s->intctl \|= MIPSNET_INTCTL_TXDONE;
	197	s->busy = 1;
	198	mipsnet_update_irq(s);
	199	}
	200	break;
	201	/* Read-only registers */
	202	case MIPSNET_DEV_ID:
	203	case MIPSNET_BUSY:
	204	case MIPSNET_RX_DATA_COUNT:
	205	case MIPSNET_INTERRUPT_INFO:
	206	case MIPSNET_RX_DATA_BUFFER:
	207	default:
	208	break;
	209	}
	210	}
	211
c7298ab2 JQ	212	static const VMStateDescription vmstate_mipsnet = {
	213	.name = "mipsnet",
	214	.version_id = 0,
	215	.minimum_version_id = 0,
35d08458	216	.fields = (VMStateField[]) {
c7298ab2 JQ	217	VMSTATE_UINT32(busy, MIPSnetState),
	218	VMSTATE_UINT32(rx_count, MIPSnetState),
	219	VMSTATE_UINT32(rx_read, MIPSnetState),
	220	VMSTATE_UINT32(tx_count, MIPSnetState),
	221	VMSTATE_UINT32(tx_written, MIPSnetState),
	222	VMSTATE_UINT32(intctl, MIPSnetState),
	223	VMSTATE_BUFFER(rx_buffer, MIPSnetState),
	224	VMSTATE_BUFFER(tx_buffer, MIPSnetState),
	225	VMSTATE_END_OF_LIST()
	226	}
	227	};
f0fc6f8f	228
1f30d10a	229	static NetClientInfo net_mipsnet_info = {
f394b2e2	230	.type = NET_CLIENT_DRIVER_NIC,
1f30d10a	231	.size = sizeof(NICState),
1f30d10a	232	.receive = mipsnet_receive,
1f30d10a MM	233	};
1f30d10a MM	234
a348f108	235	static const MemoryRegionOps mipsnet_ioport_ops = {
d118d64a HP	236	.read = mipsnet_ioport_read,
	237	.write = mipsnet_ioport_write,
	238	.impl.min_access_size = 1,
	239	.impl.max_access_size = 4,
	240	};
0ae18cee	241
04cb1572	242	static void mipsnet_realize(DeviceState dev, Error *errp)
d118d64a	243	{
04cb1572	244	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
a4dbb8bd	245	MIPSnetState *s = MIPS_NET(dev);
f0fc6f8f	246
eedfac6f PB	247	memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
eedfac6f PB	248	"mipsnet-io", 36);
a4dbb8bd AF	249	sysbus_init_mmio(sbd, &s->io);
a4dbb8bd AF	250	sysbus_init_irq(sbd, &s->irq);
f0fc6f8f	251
d118d64a	252	s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
a4dbb8bd	253	object_get_typename(OBJECT(dev)), dev->id, s);
b356f76d	254	qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
d118d64a	255	}
f0fc6f8f	256
d118d64a HP	257	static void mipsnet_sysbus_reset(DeviceState *dev)
d118d64a HP	258	{
a4dbb8bd	259	MIPSnetState *s = MIPS_NET(dev);
d118d64a HP	260	mipsnet_reset(s);
d118d64a HP	261	}
1f30d10a	262
999e12bb AL	263	static Property mipsnet_properties[] = {
	264	DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
	265	DEFINE_PROP_END_OF_LIST(),
	266	};
	267
	268	static void mipsnet_class_init(ObjectClass klass, void data)
	269	{
39bffca2	270	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	271
04cb1572	272	dc->realize = mipsnet_realize;
125ee0ed	273	set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
39bffca2 AL	274	dc->desc = "MIPS Simulator network device";
	275	dc->reset = mipsnet_sysbus_reset;
	276	dc->vmsd = &vmstate_mipsnet;
	277	dc->props = mipsnet_properties;
999e12bb AL	278	}
999e12bb AL	279
8c43a6f0	280	static const TypeInfo mipsnet_info = {
a4dbb8bd	281	.name = TYPE_MIPS_NET,
39bffca2 AL	282	.parent = TYPE_SYS_BUS_DEVICE,
	283	.instance_size = sizeof(MIPSnetState),
	284	.class_init = mipsnet_class_init,
d118d64a	285	};
f0fc6f8f	286
83f7d43a	287	static void mipsnet_register_types(void)
d118d64a	288	{
39bffca2	289	type_register_static(&mipsnet_info);
f0fc6f8f	290	}
d118d64a	291
83f7d43a	292	type_init(mipsnet_register_types)