[mirror_qemu.git] / hw / net / pcnet-pci.c

/*
 * QEMU AMD PC-Net II (Am79C970A) PCI emulation
 *
 * Copyright (c) 2004 Antony T Curtis
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* This software was written to be compatible with the specification:
 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
 * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
 */

#include "hw/pci/pci.h"
#include "net/net.h"
#include "hw/loader.h"
#include "qemu/timer.h"
#include "sysemu/dma.h"

#include "pcnet.h"

//#define PCNET_DEBUG
//#define PCNET_DEBUG_IO
//#define PCNET_DEBUG_BCR
//#define PCNET_DEBUG_CSR
//#define PCNET_DEBUG_RMD
//#define PCNET_DEBUG_TMD
//#define PCNET_DEBUG_MATCH

#define TYPE_PCI_PCNET "pcnet"

#define PCI_PCNET(obj) \
     OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)

typedef struct {
    /*< private >*/
    PCIDevice parent_obj;
    /*< public >*/

    PCNetState state;
    MemoryRegion io_bar;
} PCIPCNetState;

static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCNetState *s = opaque;
#ifdef PCNET_DEBUG
    printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
#endif
    if (BCR_APROMWE(s)) {
        s->prom[addr & 15] = val;
    }
}

static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
{
    PCNetState *s = opaque;
    uint32_t val = s->prom[addr & 15];
#ifdef PCNET_DEBUG
    printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
#endif
    return val;
}

static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
                                  unsigned size)
{
    PCNetState *d = opaque;

    if (addr < 0x10) {
        if (!BCR_DWIO(d) && size == 1) {
            return pcnet_aprom_readb(d, addr);
        } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
            return pcnet_aprom_readb(d, addr) |
                   (pcnet_aprom_readb(d, addr + 1) << 8);
        } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
            return pcnet_aprom_readb(d, addr) |
                   (pcnet_aprom_readb(d, addr + 1) << 8) |
                   (pcnet_aprom_readb(d, addr + 2) << 16) |
                   (pcnet_aprom_readb(d, addr + 3) << 24);
        }
    } else {
        if (size == 2) {
            return pcnet_ioport_readw(d, addr);
        } else if (size == 4) {
            return pcnet_ioport_readl(d, addr);
        }
    }
    return ((uint64_t)1 << (size * 8)) - 1;
}

static void pcnet_ioport_write(void *opaque, hwaddr addr,
                               uint64_t data, unsigned size)
{
    PCNetState *d = opaque;

    if (addr < 0x10) {
        if (!BCR_DWIO(d) && size == 1) {
            pcnet_aprom_writeb(d, addr, data);
        } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
            pcnet_aprom_writeb(d, addr, data & 0xff);
            pcnet_aprom_writeb(d, addr + 1, data >> 8);
        } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
            pcnet_aprom_writeb(d, addr, data & 0xff);
            pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
            pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
            pcnet_aprom_writeb(d, addr + 3, data >> 24);
        }
    } else {
        if (size == 2) {
            pcnet_ioport_writew(d, addr, data);
        } else if (size == 4) {
            pcnet_ioport_writel(d, addr, data);
        }
    }
}

static const MemoryRegionOps pcnet_io_ops = {
    .read = pcnet_ioport_read,
    .write = pcnet_ioport_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
           val);
#endif
    if (!(addr & 0x10))
        pcnet_aprom_writeb(d, addr & 0x0f, val);
}

static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;
    if (!(addr & 0x10))
        val = pcnet_aprom_readb(d, addr & 0x0f);
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
           val & 0xff);
#endif
    return val;
}

static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
           val);
#endif
    if (addr & 0x10)
        pcnet_ioport_writew(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
    }
}

static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;
    if (addr & 0x10)
        val = pcnet_ioport_readw(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
           val & 0xffff);
#endif
    return val;
}

static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
           val);
#endif
    if (addr & 0x10)
        pcnet_ioport_writel(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
        pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
        pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
    }
}

static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
{
    PCNetState *d = opaque;
    uint32_t val;
    if (addr & 0x10)
        val = pcnet_ioport_readl(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+3);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+2);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
           val);
#endif
    return val;
}

static const VMStateDescription vmstate_pci_pcnet = {
    .name = "pcnet",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
        VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
        VMSTATE_END_OF_LIST()
    }
};

/* PCI interface */

static const MemoryRegionOps pcnet_mmio_ops = {
    .old_mmio = {
        .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
        .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
                                      uint8_t *buf, int len, int do_bswap)
{
    pci_dma_write(dma_opaque, addr, buf, len);
}

static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
                                     uint8_t *buf, int len, int do_bswap)
{
    pci_dma_read(dma_opaque, addr, buf, len);
}

static void pci_pcnet_cleanup(NetClientState *nc)
{
    PCNetState *d = qemu_get_nic_opaque(nc);

    pcnet_common_cleanup(d);
}

static void pci_pcnet_uninit(PCIDevice *dev)
{
    PCIPCNetState *d = PCI_PCNET(dev);

    qemu_free_irq(d->state.irq);
    memory_region_destroy(&d->state.mmio);
    memory_region_destroy(&d->io_bar);
    timer_del(d->state.poll_timer);
    timer_free(d->state.poll_timer);
    qemu_del_nic(d->state.nic);
}

static NetClientInfo net_pci_pcnet_info = {
    .type = NET_CLIENT_OPTIONS_KIND_NIC,
    .size = sizeof(NICState),
    .can_receive = pcnet_can_receive,
    .receive = pcnet_receive,
    .link_status_changed = pcnet_set_link_status,
    .cleanup = pci_pcnet_cleanup,
};

static int pci_pcnet_init(PCIDevice *pci_dev)
{
    PCIPCNetState *d = PCI_PCNET(pci_dev);
    PCNetState *s = &d->state;
    uint8_t *pci_conf;

#if 0
    printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
        sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
#endif

    pci_conf = pci_dev->config;

    pci_set_word(pci_conf + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);

    pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
    pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);

    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
    pci_conf[PCI_MIN_GNT] = 0x06;
    pci_conf[PCI_MAX_LAT] = 0xff;

    /* Handler for memory-mapped I/O */
    memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
                          "pcnet-mmio", PCNET_PNPMMIO_SIZE);

    memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
                          PCNET_IOPORT_SIZE);
    pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);

    pci_register_bar(pci_dev, 1, 0, &s->mmio);

    s->irq = pci_allocate_irq(pci_dev);
    s->phys_mem_read = pci_physical_memory_read;
    s->phys_mem_write = pci_physical_memory_write;
    s->dma_opaque = pci_dev;

    return pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
}

static void pci_reset(DeviceState *dev)
{
    PCIPCNetState *d = PCI_PCNET(dev);

    pcnet_h_reset(&d->state);
}

static Property pcnet_properties[] = {
    DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void pcnet_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = pci_pcnet_init;
    k->exit = pci_pcnet_uninit;
    k->romfile = "efi-pcnet.rom",
    k->vendor_id = PCI_VENDOR_ID_AMD;
    k->device_id = PCI_DEVICE_ID_AMD_LANCE;
    k->revision = 0x10;
    k->class_id = PCI_CLASS_NETWORK_ETHERNET;
    dc->reset = pci_reset;
    dc->vmsd = &vmstate_pci_pcnet;
    dc->props = pcnet_properties;
    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}

static const TypeInfo pcnet_info = {
    .name          = TYPE_PCI_PCNET,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIPCNetState),
    .class_init    = pcnet_class_init,
};

static void pci_pcnet_register_types(void)
{
    type_register_static(&pcnet_info);
}

type_init(pci_pcnet_register_types)
Commit	Line	Data
661a1799 PB	1	/*
	2	* QEMU AMD PC-Net II (Am79C970A) PCI emulation
	3	*
	4	* Copyright (c) 2004 Antony T Curtis
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	/* This software was written to be compatible with the specification:
	26	* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
	27	* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
	28	*/
	29
83c9f4ca	30	#include "hw/pci/pci.h"
1422e32d	31	#include "net/net.h"
83c9f4ca	32	#include "hw/loader.h"
1de7afc9	33	#include "qemu/timer.h"
9c17d615	34	#include "sysemu/dma.h"
661a1799	35
47b43a1f	36	#include "pcnet.h"
661a1799 PB	37
	38	//#define PCNET_DEBUG
	39	//#define PCNET_DEBUG_IO
	40	//#define PCNET_DEBUG_BCR
	41	//#define PCNET_DEBUG_CSR
	42	//#define PCNET_DEBUG_RMD
	43	//#define PCNET_DEBUG_TMD
	44	//#define PCNET_DEBUG_MATCH
	45
1f8c7946 PC	46	#define TYPE_PCI_PCNET "pcnet"
	47
	48	#define PCI_PCNET(obj) \
	49	OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)
661a1799 PB	50
661a1799 PB	51	typedef struct {
1f8c7946 PC	52	/< private >/
	53	PCIDevice parent_obj;
	54	/< public >/
	55
661a1799	56	PCNetState state;
bd8d6f7c	57	MemoryRegion io_bar;
661a1799 PB	58	} PCIPCNetState;
	59
	60	static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
	61	{
	62	PCNetState *s = opaque;
	63	#ifdef PCNET_DEBUG
	64	printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
	65	#endif
488a1a5d	66	if (BCR_APROMWE(s)) {
661a1799	67	s->prom[addr & 15] = val;
488a1a5d	68	}
661a1799 PB	69	}
	70
	71	static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
	72	{
	73	PCNetState *s = opaque;
	74	uint32_t val = s->prom[addr & 15];
	75	#ifdef PCNET_DEBUG
	76	printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
	77	#endif
	78	return val;
	79	}
	80
a8170e5e	81	static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
bd8d6f7c	82	unsigned size)
661a1799	83	{
bd8d6f7c	84	PCNetState *d = opaque;
661a1799	85
7ba79741 JK	86	if (addr < 0x10) {
	87	if (!BCR_DWIO(d) && size == 1) {
	88	return pcnet_aprom_readb(d, addr);
	89	} else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
	90	return pcnet_aprom_readb(d, addr) \|
	91	(pcnet_aprom_readb(d, addr + 1) << 8);
	92	} else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
	93	return pcnet_aprom_readb(d, addr) \|
	94	(pcnet_aprom_readb(d, addr + 1) << 8) \|
	95	(pcnet_aprom_readb(d, addr + 2) << 16) \|
	96	(pcnet_aprom_readb(d, addr + 3) << 24);
	97	}
	98	} else {
	99	if (size == 2) {
	100	return pcnet_ioport_readw(d, addr);
	101	} else if (size == 4) {
	102	return pcnet_ioport_readl(d, addr);
	103	}
bd8d6f7c AK	104	}
	105	return ((uint64_t)1 << (size * 8)) - 1;
	106	}
661a1799	107
a8170e5e	108	static void pcnet_ioport_write(void *opaque, hwaddr addr,
bd8d6f7c AK	109	uint64_t data, unsigned size)
	110	{
	111	PCNetState *d = opaque;
661a1799	112
7ba79741 JK	113	if (addr < 0x10) {
	114	if (!BCR_DWIO(d) && size == 1) {
	115	pcnet_aprom_writeb(d, addr, data);
	116	} else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
	117	pcnet_aprom_writeb(d, addr, data & 0xff);
	118	pcnet_aprom_writeb(d, addr + 1, data >> 8);
	119	} else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
	120	pcnet_aprom_writeb(d, addr, data & 0xff);
	121	pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
	122	pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
	123	pcnet_aprom_writeb(d, addr + 3, data >> 24);
	124	}
	125	} else {
	126	if (size == 2) {
	127	pcnet_ioport_writew(d, addr, data);
	128	} else if (size == 4) {
	129	pcnet_ioport_writel(d, addr, data);
	130	}
bd8d6f7c	131	}
661a1799 PB	132	}
661a1799 PB	133
bd8d6f7c AK	134	static const MemoryRegionOps pcnet_io_ops = {
	135	.read = pcnet_ioport_read,
	136	.write = pcnet_ioport_write,
a26405b3	137	.endianness = DEVICE_LITTLE_ENDIAN,
bd8d6f7c AK	138	};
bd8d6f7c AK	139
a8170e5e	140	static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	141	{
	142	PCNetState *d = opaque;
	143	#ifdef PCNET_DEBUG_IO
	144	printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
	145	val);
	146	#endif
	147	if (!(addr & 0x10))
	148	pcnet_aprom_writeb(d, addr & 0x0f, val);
	149	}
	150
a8170e5e	151	static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
661a1799 PB	152	{
	153	PCNetState *d = opaque;
	154	uint32_t val = -1;
	155	if (!(addr & 0x10))
	156	val = pcnet_aprom_readb(d, addr & 0x0f);
	157	#ifdef PCNET_DEBUG_IO
	158	printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
	159	val & 0xff);
	160	#endif
	161	return val;
	162	}
	163
a8170e5e	164	static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	165	{
	166	PCNetState *d = opaque;
	167	#ifdef PCNET_DEBUG_IO
	168	printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
	169	val);
	170	#endif
	171	if (addr & 0x10)
	172	pcnet_ioport_writew(d, addr & 0x0f, val);
	173	else {
	174	addr &= 0x0f;
	175	pcnet_aprom_writeb(d, addr, val & 0xff);
	176	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
	177	}
	178	}
	179
a8170e5e	180	static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
661a1799 PB	181	{
	182	PCNetState *d = opaque;
	183	uint32_t val = -1;
	184	if (addr & 0x10)
	185	val = pcnet_ioport_readw(d, addr & 0x0f);
	186	else {
	187	addr &= 0x0f;
	188	val = pcnet_aprom_readb(d, addr+1);
	189	val <<= 8;
	190	val \|= pcnet_aprom_readb(d, addr);
	191	}
	192	#ifdef PCNET_DEBUG_IO
	193	printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
	194	val & 0xffff);
	195	#endif
	196	return val;
	197	}
	198
a8170e5e	199	static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
661a1799 PB	200	{
	201	PCNetState *d = opaque;
	202	#ifdef PCNET_DEBUG_IO
	203	printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
	204	val);
	205	#endif
	206	if (addr & 0x10)
	207	pcnet_ioport_writel(d, addr & 0x0f, val);
	208	else {
	209	addr &= 0x0f;
	210	pcnet_aprom_writeb(d, addr, val & 0xff);
	211	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
	212	pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
	213	pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
	214	}
	215	}
	216
a8170e5e	217	static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
661a1799 PB	218	{
	219	PCNetState *d = opaque;
	220	uint32_t val;
	221	if (addr & 0x10)
	222	val = pcnet_ioport_readl(d, addr & 0x0f);
	223	else {
	224	addr &= 0x0f;
	225	val = pcnet_aprom_readb(d, addr+3);
	226	val <<= 8;
	227	val \|= pcnet_aprom_readb(d, addr+2);
	228	val <<= 8;
	229	val \|= pcnet_aprom_readb(d, addr+1);
	230	val <<= 8;
	231	val \|= pcnet_aprom_readb(d, addr);
	232	}
	233	#ifdef PCNET_DEBUG_IO
	234	printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
	235	val);
	236	#endif
	237	return val;
	238	}
	239
	240	static const VMStateDescription vmstate_pci_pcnet = {
	241	.name = "pcnet",
	242	.version_id = 3,
	243	.minimum_version_id = 2,
	244	.minimum_version_id_old = 2,
	245	.fields = (VMStateField []) {
1f8c7946	246	VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
661a1799 PB	247	VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
	248	VMSTATE_END_OF_LIST()
	249	}
	250	};
	251
	252	/* PCI interface */
	253
bd8d6f7c AK	254	static const MemoryRegionOps pcnet_mmio_ops = {
	255	.old_mmio = {
	256	.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
	257	.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
	258	},
a26405b3	259	.endianness = DEVICE_LITTLE_ENDIAN,
661a1799 PB	260	};
661a1799 PB	261
a8170e5e	262	static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
661a1799 PB	263	uint8_t *buf, int len, int do_bswap)
661a1799 PB	264	{
14fecf26	265	pci_dma_write(dma_opaque, addr, buf, len);
661a1799 PB	266	}
661a1799 PB	267
a8170e5e	268	static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
661a1799 PB	269	uint8_t *buf, int len, int do_bswap)
661a1799 PB	270	{
14fecf26	271	pci_dma_read(dma_opaque, addr, buf, len);
661a1799 PB	272	}
661a1799 PB	273
4e68f7a0	274	static void pci_pcnet_cleanup(NetClientState *nc)
661a1799	275	{
cc1f0f45	276	PCNetState *d = qemu_get_nic_opaque(nc);
661a1799 PB	277
	278	pcnet_common_cleanup(d);
	279	}
	280
f90c2bcd	281	static void pci_pcnet_uninit(PCIDevice *dev)
661a1799	282	{
1f8c7946	283	PCIPCNetState *d = PCI_PCNET(dev);
661a1799	284
9e64f8a3	285	qemu_free_irq(d->state.irq);
bd8d6f7c AK	286	memory_region_destroy(&d->state.mmio);
bd8d6f7c AK	287	memory_region_destroy(&d->io_bar);
bc72ad67 AB	288	timer_del(d->state.poll_timer);
bc72ad67 AB	289	timer_free(d->state.poll_timer);
948ecf21	290	qemu_del_nic(d->state.nic);
661a1799 PB	291	}
	292
	293	static NetClientInfo net_pci_pcnet_info = {
2be64a68	294	.type = NET_CLIENT_OPTIONS_KIND_NIC,
661a1799 PB	295	.size = sizeof(NICState),
	296	.can_receive = pcnet_can_receive,
	297	.receive = pcnet_receive,
e1c2008a	298	.link_status_changed = pcnet_set_link_status,
661a1799 PB	299	.cleanup = pci_pcnet_cleanup,
	300	};
	301
	302	static int pci_pcnet_init(PCIDevice *pci_dev)
	303	{
1f8c7946	304	PCIPCNetState *d = PCI_PCNET(pci_dev);
661a1799 PB	305	PCNetState *s = &d->state;
	306	uint8_t *pci_conf;
	307
	308	#if 0
	309	printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
	310	sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
	311	#endif
	312
	313	pci_conf = pci_dev->config;
	314
661a1799 PB	315	pci_set_word(pci_conf + PCI_STATUS,
661a1799 PB	316	PCI_STATUS_FAST_BACK \| PCI_STATUS_DEVSEL_MEDIUM);
661a1799 PB	317
	318	pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
	319	pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
	320
817e0b6f	321	pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
661a1799 PB	322	pci_conf[PCI_MIN_GNT] = 0x06;
	323	pci_conf[PCI_MAX_LAT] = 0xff;
	324
	325	/* Handler for memory-mapped I/O */
eedfac6f PB	326	memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
eedfac6f PB	327	"pcnet-mmio", PCNET_PNPMMIO_SIZE);
661a1799	328
eedfac6f	329	memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
bd8d6f7c	330	PCNET_IOPORT_SIZE);
e824b2cc	331	pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
661a1799	332
e824b2cc	333	pci_register_bar(pci_dev, 1, 0, &s->mmio);
661a1799	334
9e64f8a3	335	s->irq = pci_allocate_irq(pci_dev);
661a1799 PB	336	s->phys_mem_read = pci_physical_memory_read;
661a1799 PB	337	s->phys_mem_write = pci_physical_memory_write;
14fecf26	338	s->dma_opaque = pci_dev;
661a1799	339
1f8c7946	340	return pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
661a1799 PB	341	}
	342
	343	static void pci_reset(DeviceState *dev)
	344	{
1f8c7946	345	PCIPCNetState *d = PCI_PCNET(dev);
661a1799 PB	346
	347	pcnet_h_reset(&d->state);
	348	}
	349
40021f08 AL	350	static Property pcnet_properties[] = {
	351	DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
	352	DEFINE_PROP_END_OF_LIST(),
	353	};
	354
	355	static void pcnet_class_init(ObjectClass klass, void data)
	356	{
39bffca2	357	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	358	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	359
	360	k->init = pci_pcnet_init;
	361	k->exit = pci_pcnet_uninit;
c45e5b5b	362	k->romfile = "efi-pcnet.rom",
40021f08 AL	363	k->vendor_id = PCI_VENDOR_ID_AMD;
	364	k->device_id = PCI_DEVICE_ID_AMD_LANCE;
	365	k->revision = 0x10;
	366	k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2 AL	367	dc->reset = pci_reset;
	368	dc->vmsd = &vmstate_pci_pcnet;
	369	dc->props = pcnet_properties;
125ee0ed	370	set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
40021f08 AL	371	}
40021f08 AL	372
8c43a6f0	373	static const TypeInfo pcnet_info = {
1f8c7946	374	.name = TYPE_PCI_PCNET,
39bffca2 AL	375	.parent = TYPE_PCI_DEVICE,
	376	.instance_size = sizeof(PCIPCNetState),
	377	.class_init = pcnet_class_init,
661a1799 PB	378	};
661a1799 PB	379
83f7d43a	380	static void pci_pcnet_register_types(void)
661a1799	381	{
39bffca2	382	type_register_static(&pcnet_info);
661a1799 PB	383	}
661a1799 PB	384
83f7d43a	385	type_init(pci_pcnet_register_types)