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[mirror_qemu.git] / hw / net / rtl8139.c
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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
83c9f4ca
PB		 54#include "hw/hw.h"
55#include "hw/pci/pci.h"
9c17d615 56#include "sysemu/dma.h"
1de7afc9 57#include "qemu/timer.h"
1422e32d 58#include "net/net.h"
83c9f4ca 59#include "hw/loader.h"
9c17d615 60#include "sysemu/sysemu.h"
1de7afc9 61#include "qemu/iov.h"
a41b2ff2 62
a41b2ff2
PB		 63/* debug RTL8139 card */
64//#define DEBUG_RTL8139 1
65
6cadb320
FB		 66#define PCI_FREQUENCY 33000000L
67
a41b2ff2
PB		 68#define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71/* arg % size for size which is a power of 2 */
72#define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
18dabfd1
BP		 75#define ETHER_ADDR_LEN 6
76#define ETHER_TYPE_LEN 2
77#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78#define ETH_P_IP 0x0800 /* Internet Protocol packet */
79#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80#define ETH_MTU 1500
81
82#define VLAN_TCI_LEN 2
83#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
6cadb320 85#if defined (DEBUG_RTL8139)
7cdeb319
BP		 86# define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 88#else
c6a0487b 89static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 90{
91 return 0;
92}
6cadb320
FB		 93#endif
94
39257515
PC		 95#define TYPE_RTL8139 "rtl8139"
96
97#define RTL8139(obj) \
98 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139)
99
a41b2ff2
PB		 100/* Symbolic offsets to registers. */
101enum RTL8139_registers {
102 MAC0 = 0, /* Ethernet hardware address. */
103 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 104 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
105 /* Dump Tally Conter control register(64bit). C+ mode only */
106 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 107 RxBuf = 0x30,
108 ChipCmd = 0x37,
109 RxBufPtr = 0x38,
110 RxBufAddr = 0x3A,
111 IntrMask = 0x3C,
112 IntrStatus = 0x3E,
113 TxConfig = 0x40,
114 RxConfig = 0x44,
115 Timer = 0x48, /* A general-purpose counter. */
116 RxMissed = 0x4C, /* 24 bits valid, write clears. */
117 Cfg9346 = 0x50,
118 Config0 = 0x51,
119 Config1 = 0x52,
120 FlashReg = 0x54,
121 MediaStatus = 0x58,
122 Config3 = 0x59,
123 Config4 = 0x5A, /* absent on RTL-8139A */
124 HltClk = 0x5B,
125 MultiIntr = 0x5C,
126 PCIRevisionID = 0x5E,
127 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
128 BasicModeCtrl = 0x62,
129 BasicModeStatus = 0x64,
130 NWayAdvert = 0x66,
131 NWayLPAR = 0x68,
132 NWayExpansion = 0x6A,
133 /* Undocumented registers, but required for proper operation. */
134 FIFOTMS = 0x70, /* FIFO Control and test. */
135 CSCR = 0x74, /* Chip Status and Configuration Register. */
136 PARA78 = 0x78,
137 PARA7c = 0x7c, /* Magic transceiver parameter register. */
138 Config5 = 0xD8, /* absent on RTL-8139A */
139 /* C+ mode */
140 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
141 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
142 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
143 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
144 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
145 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
146 TxThresh = 0xEC, /* Early Tx threshold */
147};
148
149enum ClearBitMasks {
150 MultiIntrClear = 0xF000,
151 ChipCmdClear = 0xE2,
152 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
153};
154
155enum ChipCmdBits {
156 CmdReset = 0x10,
157 CmdRxEnb = 0x08,
158 CmdTxEnb = 0x04,
159 RxBufEmpty = 0x01,
160};
161
162/* C+ mode */
163enum CplusCmdBits {
6cadb320
FB		 164 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
165 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
166 CPlusRxEnb = 0x0002,
167 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 168};
169
170/* Interrupt register bits, using my own meaningful names. */
171enum IntrStatusBits {
172 PCIErr = 0x8000,
173 PCSTimeout = 0x4000,
174 RxFIFOOver = 0x40,
9e12c5af 175 RxUnderrun = 0x20, /* Packet Underrun / Link Change */
a41b2ff2
PB		 176 RxOverflow = 0x10,
177 TxErr = 0x08,
178 TxOK = 0x04,
179 RxErr = 0x02,
180 RxOK = 0x01,
181
182 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
183};
184
185enum TxStatusBits {
186 TxHostOwns = 0x2000,
187 TxUnderrun = 0x4000,
188 TxStatOK = 0x8000,
189 TxOutOfWindow = 0x20000000,
190 TxAborted = 0x40000000,
191 TxCarrierLost = 0x80000000,
192};
193enum RxStatusBits {
194 RxMulticast = 0x8000,
195 RxPhysical = 0x4000,
196 RxBroadcast = 0x2000,
197 RxBadSymbol = 0x0020,
198 RxRunt = 0x0010,
199 RxTooLong = 0x0008,
200 RxCRCErr = 0x0004,
201 RxBadAlign = 0x0002,
202 RxStatusOK = 0x0001,
203};
204
205/* Bits in RxConfig. */
206enum rx_mode_bits {
207 AcceptErr = 0x20,
208 AcceptRunt = 0x10,
209 AcceptBroadcast = 0x08,
210 AcceptMulticast = 0x04,
211 AcceptMyPhys = 0x02,
212 AcceptAllPhys = 0x01,
213};
214
215/* Bits in TxConfig. */
216enum tx_config_bits {
217
218 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
219 TxIFGShift = 24,
220 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
221 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
222 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
223 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
224
225 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
226 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
227 TxClearAbt = (1 << 0), /* Clear abort (WO) */
228 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
229 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
230
231 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
232};
233
234
235/* Transmit Status of All Descriptors (TSAD) Register */
236enum TSAD_bits {
237 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
238 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
239 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
240 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
241 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
242 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
243 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
244 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
245 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
246 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
247 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
248 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
249 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
250 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
251 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
252 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
253};
254
255
256/* Bits in Config1 */
257enum Config1Bits {
258 Cfg1_PM_Enable = 0x01,
259 Cfg1_VPD_Enable = 0x02,
260 Cfg1_PIO = 0x04,
261 Cfg1_MMIO = 0x08,
262 LWAKE = 0x10, /* not on 8139, 8139A */
263 Cfg1_Driver_Load = 0x20,
264 Cfg1_LED0 = 0x40,
265 Cfg1_LED1 = 0x80,
266 SLEEP = (1 << 1), /* only on 8139, 8139A */
267 PWRDN = (1 << 0), /* only on 8139, 8139A */
268};
269
270/* Bits in Config3 */
271enum Config3Bits {
272 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
273 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
274 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
275 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
276 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
277 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
278 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
279 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
280};
281
282/* Bits in Config4 */
283enum Config4Bits {
284 LWPTN = (1 << 2), /* not on 8139, 8139A */
285};
286
287/* Bits in Config5 */
288enum Config5Bits {
289 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
290 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
291 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
292 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
293 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
294 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
295 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
296};
297
298enum RxConfigBits {
299 /* rx fifo threshold */
300 RxCfgFIFOShift = 13,
301 RxCfgFIFONone = (7 << RxCfgFIFOShift),
302
303 /* Max DMA burst */
304 RxCfgDMAShift = 8,
305 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
306
307 /* rx ring buffer length */
308 RxCfgRcv8K = 0,
309 RxCfgRcv16K = (1 << 11),
310 RxCfgRcv32K = (1 << 12),
311 RxCfgRcv64K = (1 << 11) | (1 << 12),
312
313 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
314 RxNoWrap = (1 << 7),
315};
316
317/* Twister tuning parameters from RealTek.
318 Completely undocumented, but required to tune bad links on some boards. */
319/*
320enum CSCRBits {
321 CSCR_LinkOKBit = 0x0400,
322 CSCR_LinkChangeBit = 0x0800,
323 CSCR_LinkStatusBits = 0x0f000,
324 CSCR_LinkDownOffCmd = 0x003c0,
325 CSCR_LinkDownCmd = 0x0f3c0,
326*/
327enum CSCRBits {
5fafdf24 328 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 329 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
330 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
331 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 332 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 333 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
334 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
335 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
336 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
337};
338
339enum Cfg9346Bits {
eb46c5ed
JW		 340 Cfg9346_Normal = 0x00,
341 Cfg9346_Autoload = 0x40,
342 Cfg9346_Programming = 0x80,
343 Cfg9346_ConfigWrite = 0xC0,
a41b2ff2
PB		 344};
345
346typedef enum {
347 CH_8139 = 0,
348 CH_8139_K,
349 CH_8139A,
350 CH_8139A_G,
351 CH_8139B,
352 CH_8130,
353 CH_8139C,
354 CH_8100,
355 CH_8100B_8139D,
356 CH_8101,
c227f099 357} chip_t;
a41b2ff2
PB		 358
359enum chip_flags {
360 HasHltClk = (1 << 0),
361 HasLWake = (1 << 1),
362};
363
364#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
365 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
366#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
367
6cadb320
FB		 368#define RTL8139_PCI_REVID_8139 0x10
369#define RTL8139_PCI_REVID_8139CPLUS 0x20
370
371#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
372
a41b2ff2
PB		 373/* Size is 64 * 16bit words */
374#define EEPROM_9346_ADDR_BITS 6
375#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
376#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
377
378enum Chip9346Operation
379{
380 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
381 Chip9346_op_read = 0x80, /* 10 AAAAAA */
382 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
383 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
384 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
385 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
386 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
387};
388
389enum Chip9346Mode
390{
391 Chip9346_none = 0,
392 Chip9346_enter_command_mode,
393 Chip9346_read_command,
394 Chip9346_data_read, /* from output register */
395 Chip9346_data_write, /* to input register, then to contents at specified address */
396 Chip9346_data_write_all, /* to input register, then filling contents */
397};
398
399typedef struct EEprom9346
400{
401 uint16_t contents[EEPROM_9346_SIZE];
402 int mode;
403 uint32_t tick;
404 uint8_t address;
405 uint16_t input;
406 uint16_t output;
407
408 uint8_t eecs;
409 uint8_t eesk;
410 uint8_t eedi;
411 uint8_t eedo;
412} EEprom9346;
413
6cadb320
FB		 414typedef struct RTL8139TallyCounters
415{
416 /* Tally counters */
417 uint64_t TxOk;
418 uint64_t RxOk;
419 uint64_t TxERR;
420 uint32_t RxERR;
421 uint16_t MissPkt;
422 uint16_t FAE;
423 uint32_t Tx1Col;
424 uint32_t TxMCol;
425 uint64_t RxOkPhy;
426 uint64_t RxOkBrd;
427 uint32_t RxOkMul;
428 uint16_t TxAbt;
429 uint16_t TxUndrn;
430} RTL8139TallyCounters;
431
432/* Clears all tally counters */
433static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
434
a41b2ff2 435typedef struct RTL8139State {
88a411a8
AF		 436 /*< private >*/
437 PCIDevice parent_obj;
438 /*< public >*/
439
a41b2ff2
PB		 440 uint8_t phys[8]; /* mac address */
441 uint8_t mult[8]; /* multicast mask array */
442
6cadb320 443 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 444 uint32_t TxAddr[4]; /* TxAddr0 */
445 uint32_t RxBuf; /* Receive buffer */
446 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
447 uint32_t RxBufPtr;
448 uint32_t RxBufAddr;
449
450 uint16_t IntrStatus;
451 uint16_t IntrMask;
452
453 uint32_t TxConfig;
454 uint32_t RxConfig;
455 uint32_t RxMissed;
456
457 uint16_t CSCR;
458
459 uint8_t Cfg9346;
460 uint8_t Config0;
461 uint8_t Config1;
462 uint8_t Config3;
463 uint8_t Config4;
464 uint8_t Config5;
465
466 uint8_t clock_enabled;
467 uint8_t bChipCmdState;
468
469 uint16_t MultiIntr;
470
471 uint16_t BasicModeCtrl;
472 uint16_t BasicModeStatus;
473 uint16_t NWayAdvert;
474 uint16_t NWayLPAR;
475 uint16_t NWayExpansion;
476
477 uint16_t CpCmd;
478 uint8_t TxThresh;
479
1673ad51 480 NICState *nic;
254111ec 481 NICConf conf;
a41b2ff2
PB		 482
483 /* C ring mode */
484 uint32_t currTxDesc;
485
486 /* C+ mode */
2c3891ab
AL		 487 uint32_t cplus_enabled;
488
a41b2ff2
PB		 489 uint32_t currCPlusRxDesc;
490 uint32_t currCPlusTxDesc;
491
492 uint32_t RxRingAddrLO;
493 uint32_t RxRingAddrHI;
494
495 EEprom9346 eeprom;
6cadb320
FB		 496
497 uint32_t TCTR;
498 uint32_t TimerInt;
499 int64_t TCTR_base;
500
501 /* Tally counters */
502 RTL8139TallyCounters tally_counters;
503
504 /* Non-persistent data */
505 uint8_t *cplus_txbuffer;
506 int cplus_txbuffer_len;
507 int cplus_txbuffer_offset;
508
509 /* PCI interrupt timer */
510 QEMUTimer *timer;
511
bd80f3fc
AK		 512 MemoryRegion bar_io;
513 MemoryRegion bar_mem;
514
c574ba5a
AW		 515 /* Support migration to/from old versions */
516 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 517} RTL8139State;
518
3ada003a
EGM		 519/* Writes tally counters to memory via DMA */
520static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
521
237c255c 522static void rtl8139_set_next_tctr_time(RTL8139State *s);
05447803 523
9596ebb7 524static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 525{
7cdeb319 526 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 527
528 switch (command & Chip9346_op_mask)
529 {
530 case Chip9346_op_read:
531 {
532 eeprom->address = command & EEPROM_9346_ADDR_MASK;
533 eeprom->output = eeprom->contents[eeprom->address];
534 eeprom->eedo = 0;
535 eeprom->tick = 0;
536 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 537 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
538 eeprom->address, eeprom->output);
a41b2ff2
PB		 539 }
540 break;
541
542 case Chip9346_op_write:
543 {
544 eeprom->address = command & EEPROM_9346_ADDR_MASK;
545 eeprom->input = 0;
546 eeprom->tick = 0;
547 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 548 DPRINTF("eeprom begin write to address 0x%02x\n",
549 eeprom->address);
a41b2ff2
PB		 550 }
551 break;
552 default:
553 eeprom->mode = Chip9346_none;
554 switch (command & Chip9346_op_ext_mask)
555 {
556 case Chip9346_op_write_enable:
7cdeb319 557 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 558 break;
559 case Chip9346_op_write_all:
7cdeb319 560 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 561 break;
562 case Chip9346_op_write_disable:
7cdeb319 563 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 564 break;
565 }
566 break;
567 }
568}
569
9596ebb7 570static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 571{
572 int bit = eeprom->eedi?1:0;
573
574 ++ eeprom->tick;
575
7cdeb319
BP		 576 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
577 eeprom->eedo);
a41b2ff2
PB		 578
579 switch (eeprom->mode)
580 {
581 case Chip9346_enter_command_mode:
582 if (bit)
583 {
584 eeprom->mode = Chip9346_read_command;
585 eeprom->tick = 0;
586 eeprom->input = 0;
7cdeb319 587 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 588 }
589 break;
590
591 case Chip9346_read_command:
592 eeprom->input = (eeprom->input << 1) | (bit & 1);
593 if (eeprom->tick == 8)
594 {
595 prom9346_decode_command(eeprom, eeprom->input & 0xff);
596 }
597 break;
598
599 case Chip9346_data_read:
600 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
601 eeprom->output <<= 1;
602 if (eeprom->tick == 16)
603 {
6cadb320
FB		 604#if 1
605 // the FreeBSD drivers (rl and re) don't explicitly toggle
606 // CS between reads (or does setting Cfg9346 to 0 count too?),
607 // so we need to enter wait-for-command state here
608 eeprom->mode = Chip9346_enter_command_mode;
609 eeprom->input = 0;
610 eeprom->tick = 0;
611
7cdeb319 612 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 613#else
614 // original behaviour
a41b2ff2
PB		 615 ++eeprom->address;
616 eeprom->address &= EEPROM_9346_ADDR_MASK;
617 eeprom->output = eeprom->contents[eeprom->address];
618 eeprom->tick = 0;
619
7cdeb319
BP		 620 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
621 eeprom->address, eeprom->output);
a41b2ff2
PB		 622#endif
623 }
624 break;
625
626 case Chip9346_data_write:
627 eeprom->input = (eeprom->input << 1) | (bit & 1);
628 if (eeprom->tick == 16)
629 {
7cdeb319
BP		 630 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
631 eeprom->address, eeprom->input);
6cadb320 632
a41b2ff2
PB		 633 eeprom->contents[eeprom->address] = eeprom->input;
634 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
635 eeprom->tick = 0;
636 eeprom->input = 0;
637 }
638 break;
639
640 case Chip9346_data_write_all:
641 eeprom->input = (eeprom->input << 1) | (bit & 1);
642 if (eeprom->tick == 16)
643 {
644 int i;
645 for (i = 0; i < EEPROM_9346_SIZE; i++)
646 {
647 eeprom->contents[i] = eeprom->input;
648 }
7cdeb319 649 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 650
a41b2ff2
PB		 651 eeprom->mode = Chip9346_enter_command_mode;
652 eeprom->tick = 0;
653 eeprom->input = 0;
654 }
655 break;
656
657 default:
658 break;
659 }
660}
661
9596ebb7 662static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 663{
664 EEprom9346 *eeprom = &s->eeprom;
665 if (!eeprom->eecs)
666 return 0;
667
668 return eeprom->eedo;
669}
670
9596ebb7
PB		 671/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
672static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 673{
674 EEprom9346 *eeprom = &s->eeprom;
675 uint8_t old_eecs = eeprom->eecs;
676 uint8_t old_eesk = eeprom->eesk;
677
678 eeprom->eecs = eecs;
679 eeprom->eesk = eesk;
680 eeprom->eedi = eedi;
681
7cdeb319
BP		 682 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
683 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 684
685 if (!old_eecs && eecs)
686 {
687 /* Synchronize start */
688 eeprom->tick = 0;
689 eeprom->input = 0;
690 eeprom->output = 0;
691 eeprom->mode = Chip9346_enter_command_mode;
692
7cdeb319 693 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 694 }
695
696 if (!eecs)
697 {
7cdeb319 698 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 699 return;
700 }
701
702 if (!old_eesk && eesk)
703 {
704 /* SK front rules */
705 prom9346_shift_clock(eeprom);
706 }
707}
708
709static void rtl8139_update_irq(RTL8139State *s)
710{
88a411a8 711 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 712 int isr;
713 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 714
7cdeb319
BP		 715 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
716 s->IntrMask);
6cadb320 717
9e64f8a3 718 pci_set_irq(d, (isr != 0));
a41b2ff2
PB		 719}
720
a41b2ff2
PB		 721static int rtl8139_RxWrap(RTL8139State *s)
722{
723 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
724 return (s->RxConfig & (1 << 7));
725}
726
727static int rtl8139_receiver_enabled(RTL8139State *s)
728{
729 return s->bChipCmdState & CmdRxEnb;
730}
731
732static int rtl8139_transmitter_enabled(RTL8139State *s)
733{
734 return s->bChipCmdState & CmdTxEnb;
735}
736
737static int rtl8139_cp_receiver_enabled(RTL8139State *s)
738{
739 return s->CpCmd & CPlusRxEnb;
740}
741
742static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
743{
744 return s->CpCmd & CPlusTxEnb;
745}
746
747static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
748{
88a411a8
AF		 749 PCIDevice *d = PCI_DEVICE(s);
750
a41b2ff2
PB		 751 if (s->RxBufAddr + size > s->RxBufferSize)
752 {
753 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
754
755 /* write packet data */
ccf1d14a 756 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 757 {
7cdeb319 758 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 759
760 if (size > wrapped)
761 {
88a411a8 762 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
3ada003a 763 buf, size-wrapped);
a41b2ff2
PB		 764 }
765
766 /* reset buffer pointer */
767 s->RxBufAddr = 0;
768
88a411a8 769 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
3ada003a 770 buf + (size-wrapped), wrapped);
a41b2ff2
PB		 771
772 s->RxBufAddr = wrapped;
773
774 return;
775 }
776 }
777
778 /* non-wrapping path or overwrapping enabled */
88a411a8 779 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
a41b2ff2
PB		 780
781 s->RxBufAddr += size;
782}
783
784#define MIN_BUF_SIZE 60
3ada003a 785static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2 786{
4be403c8 787 return low | ((uint64_t)high << 32);
a41b2ff2
PB		 788}
789
fcce6fd2
JW		 790/* Workaround for buggy guest driver such as linux who allocates rx
791 * rings after the receiver were enabled. */
792static bool rtl8139_cp_rx_valid(RTL8139State *s)
793{
794 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
795}
796
4e68f7a0 797static int rtl8139_can_receive(NetClientState *nc)
a41b2ff2 798{
cc1f0f45 799 RTL8139State *s = qemu_get_nic_opaque(nc);
a41b2ff2
PB		 800 int avail;
801
aa1f17c1 802 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 803 if (!s->clock_enabled)
804 return 1;
805 if (!rtl8139_receiver_enabled(s))
806 return 1;
807
fcce6fd2 808 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
a41b2ff2
PB		 809 /* ??? Flow control not implemented in c+ mode.
810 This is a hack to work around slirp deficiencies anyway. */
811 return 1;
812 } else {
813 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
814 s->RxBufferSize);
fee9d348 815 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow));
a41b2ff2
PB		 816 }
817}
818
4e68f7a0 819static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 820{
cc1f0f45 821 RTL8139State *s = qemu_get_nic_opaque(nc);
88a411a8 822 PCIDevice *d = PCI_DEVICE(s);
18dabfd1 823 /* size is the length of the buffer passed to the driver */
4f1c942b 824 int size = size_;
18dabfd1 825 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 826
827 uint32_t packet_header = 0;
828
18dabfd1 829 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 830 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 831 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
832
7cdeb319 833 DPRINTF(">>> received len=%d\n", size);
a41b2ff2
PB		 834
835 /* test if board clock is stopped */
836 if (!s->clock_enabled)
837 {
7cdeb319 838 DPRINTF("stopped ==========================\n");
4f1c942b 839 return -1;
a41b2ff2
PB		 840 }
841
842 /* first check if receiver is enabled */
843
844 if (!rtl8139_receiver_enabled(s))
845 {
7cdeb319 846 DPRINTF("receiver disabled ================\n");
4f1c942b 847 return -1;
a41b2ff2
PB		 848 }
849
850 /* XXX: check this */
851 if (s->RxConfig & AcceptAllPhys) {
852 /* promiscuous: receive all */
7cdeb319 853 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 854
855 } else {
856 if (!memcmp(buf, broadcast_macaddr, 6)) {
857 /* broadcast address */
858 if (!(s->RxConfig & AcceptBroadcast))
859 {
7cdeb319 860 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 861
862 /* update tally counter */
863 ++s->tally_counters.RxERR;
864
4f1c942b 865 return size;
a41b2ff2
PB		 866 }
867
868 packet_header |= RxBroadcast;
869
7cdeb319 870 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 871
872 /* update tally counter */
873 ++s->tally_counters.RxOkBrd;
874
a41b2ff2
PB		 875 } else if (buf[0] & 0x01) {
876 /* multicast */
877 if (!(s->RxConfig & AcceptMulticast))
878 {
7cdeb319 879 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 880
881 /* update tally counter */
882 ++s->tally_counters.RxERR;
883
4f1c942b 884 return size;
a41b2ff2
PB		 885 }
886
887 int mcast_idx = compute_mcast_idx(buf);
888
889 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
890 {
7cdeb319 891 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 892
893 /* update tally counter */
894 ++s->tally_counters.RxERR;
895
4f1c942b 896 return size;
a41b2ff2
PB		 897 }
898
899 packet_header |= RxMulticast;
900
7cdeb319 901 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 902
903 /* update tally counter */
904 ++s->tally_counters.RxOkMul;
905
a41b2ff2 906 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 907 s->phys[1] == buf[1] &&
908 s->phys[2] == buf[2] &&
909 s->phys[3] == buf[3] &&
910 s->phys[4] == buf[4] &&
a41b2ff2
PB		 911 s->phys[5] == buf[5]) {
912 /* match */
913 if (!(s->RxConfig & AcceptMyPhys))
914 {
7cdeb319 915 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 916
917 /* update tally counter */
918 ++s->tally_counters.RxERR;
919
4f1c942b 920 return size;
a41b2ff2
PB		 921 }
922
923 packet_header |= RxPhysical;
924
7cdeb319 925 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 926
927 /* update tally counter */
928 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 929
930 } else {
931
7cdeb319 932 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 933
934 /* update tally counter */
935 ++s->tally_counters.RxERR;
936
4f1c942b 937 return size;
a41b2ff2
PB		 938 }
939 }
940
18dabfd1
BP		 941 /* if too small buffer, then expand it
942 * Include some tailroom in case a vlan tag is later removed. */
943 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 944 memcpy(buf1, buf, size);
18dabfd1 945 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 946 buf = buf1;
18dabfd1
BP		 947 if (size < MIN_BUF_SIZE) {
948 size = MIN_BUF_SIZE;
949 }
a41b2ff2
PB		 950 }
951
952 if (rtl8139_cp_receiver_enabled(s))
953 {
fcce6fd2
JW		 954 if (!rtl8139_cp_rx_valid(s)) {
955 return size;
956 }
957
7cdeb319 958 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 959
960 /* begin C+ receiver mode */
961
962/* w0 ownership flag */
963#define CP_RX_OWN (1<<31)
964/* w0 end of ring flag */
965#define CP_RX_EOR (1<<30)
966/* w0 bits 0...12 : buffer size */
967#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
968/* w1 tag available flag */
969#define CP_RX_TAVA (1<<16)
970/* w1 bits 0...15 : VLAN tag */
971#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
972/* w2 low 32bit of Rx buffer ptr */
973/* w3 high 32bit of Rx buffer ptr */
974
975 int descriptor = s->currCPlusRxDesc;
3ada003a 976 dma_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 977
978 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
979 cplus_rx_ring_desc += 16 * descriptor;
980
7cdeb319 981 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
3ada003a 982 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
7cdeb319 983 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 984
985 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
986
88a411a8 987 pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
a41b2ff2 988 rxdw0 = le32_to_cpu(val);
88a411a8 989 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
a41b2ff2 990 rxdw1 = le32_to_cpu(val);
88a411a8 991 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
a41b2ff2 992 rxbufLO = le32_to_cpu(val);
88a411a8 993 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
a41b2ff2
PB		 994 rxbufHI = le32_to_cpu(val);
995
7cdeb319
BP		 996 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
997 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 998
999 if (!(rxdw0 & CP_RX_OWN))
1000 {
7cdeb319
BP		 1001 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1002 descriptor);
6cadb320 1003
a41b2ff2
PB		 1004 s->IntrStatus |= RxOverflow;
1005 ++s->RxMissed;
6cadb320
FB		 1006
1007 /* update tally counter */
1008 ++s->tally_counters.RxERR;
1009 ++s->tally_counters.MissPkt;
1010
a41b2ff2 1011 rtl8139_update_irq(s);
4f1c942b 1012 return size_;
a41b2ff2
PB		 1013 }
1014
1015 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1016
18dabfd1
BP		 1017 /* write VLAN info to descriptor variables. */
1018 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1019 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1020 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1021 size -= VLAN_HLEN;
1022 /* if too small buffer, use the tailroom added duing expansion */
1023 if (size < MIN_BUF_SIZE) {
1024 size = MIN_BUF_SIZE;
1025 }
1026
1027 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1028 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1029 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1030 &dot1q_buf[ETHER_TYPE_LEN]);
1031
7cdeb319
BP		 1032 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1033 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1034 } else {
1035 /* reset VLAN tag flag */
1036 rxdw1 &= ~CP_RX_TAVA;
1037 }
1038
6cadb320
FB		 1039 /* TODO: scatter the packet over available receive ring descriptors space */
1040
a41b2ff2
PB		 1041 if (size+4 > rx_space)
1042 {
7cdeb319
BP		 1043 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1044 descriptor, rx_space, size);
6cadb320 1045
a41b2ff2
PB		 1046 s->IntrStatus |= RxOverflow;
1047 ++s->RxMissed;
6cadb320
FB		 1048
1049 /* update tally counter */
1050 ++s->tally_counters.RxERR;
1051 ++s->tally_counters.MissPkt;
1052
a41b2ff2 1053 rtl8139_update_irq(s);
4f1c942b 1054 return size_;
a41b2ff2
PB		 1055 }
1056
3ada003a 1057 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1058
1059 /* receive/copy to target memory */
18dabfd1 1060 if (dot1q_buf) {
88a411a8
AF		 1061 pci_dma_write(d, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1062 pci_dma_write(d, rx_addr + 2 * ETHER_ADDR_LEN,
3ada003a
EGM		 1063 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1064 size - 2 * ETHER_ADDR_LEN);
18dabfd1 1065 } else {
88a411a8 1066 pci_dma_write(d, rx_addr, buf, size);
18dabfd1 1067 }
a41b2ff2 1068
6cadb320
FB		 1069 if (s->CpCmd & CPlusRxChkSum)
1070 {
1071 /* do some packet checksumming */
1072 }
1073
a41b2ff2 1074 /* write checksum */
18dabfd1 1075 val = cpu_to_le32(crc32(0, buf, size_));
88a411a8 1076 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
a41b2ff2
PB		 1077
1078/* first segment of received packet flag */
1079#define CP_RX_STATUS_FS (1<<29)
1080/* last segment of received packet flag */
1081#define CP_RX_STATUS_LS (1<<28)
1082/* multicast packet flag */
1083#define CP_RX_STATUS_MAR (1<<26)
1084/* physical-matching packet flag */
1085#define CP_RX_STATUS_PAM (1<<25)
1086/* broadcast packet flag */
1087#define CP_RX_STATUS_BAR (1<<24)
1088/* runt packet flag */
1089#define CP_RX_STATUS_RUNT (1<<19)
1090/* crc error flag */
1091#define CP_RX_STATUS_CRC (1<<18)
1092/* IP checksum error flag */
1093#define CP_RX_STATUS_IPF (1<<15)
1094/* UDP checksum error flag */
1095#define CP_RX_STATUS_UDPF (1<<14)
1096/* TCP checksum error flag */
1097#define CP_RX_STATUS_TCPF (1<<13)
1098
1099 /* transfer ownership to target */
1100 rxdw0 &= ~CP_RX_OWN;
1101
1102 /* set first segment bit */
1103 rxdw0 |= CP_RX_STATUS_FS;
1104
1105 /* set last segment bit */
1106 rxdw0 |= CP_RX_STATUS_LS;
1107
1108 /* set received packet type flags */
1109 if (packet_header & RxBroadcast)
1110 rxdw0 |= CP_RX_STATUS_BAR;
1111 if (packet_header & RxMulticast)
1112 rxdw0 |= CP_RX_STATUS_MAR;
1113 if (packet_header & RxPhysical)
1114 rxdw0 |= CP_RX_STATUS_PAM;
1115
1116 /* set received size */
1117 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1118 rxdw0 |= (size+4);
1119
a41b2ff2
PB		 1120 /* update ring data */
1121 val = cpu_to_le32(rxdw0);
88a411a8 1122 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1123 val = cpu_to_le32(rxdw1);
88a411a8 1124 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1125
6cadb320
FB		 1126 /* update tally counter */
1127 ++s->tally_counters.RxOk;
1128
a41b2ff2
PB		 1129 /* seek to next Rx descriptor */
1130 if (rxdw0 & CP_RX_EOR)
1131 {
1132 s->currCPlusRxDesc = 0;
1133 }
1134 else
1135 {
1136 ++s->currCPlusRxDesc;
1137 }
1138
7cdeb319 1139 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1140
1141 }
1142 else
1143 {
7cdeb319 1144 DPRINTF("in ring Rx mode ================\n");
6cadb320 1145
a41b2ff2
PB		 1146 /* begin ring receiver mode */
1147 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1148
1149 /* if receiver buffer is empty then avail == 0 */
1150
1151 if (avail != 0 && size + 8 >= avail)
1152 {
7cdeb319
BP		 1153 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1154 "read 0x%04x === available 0x%04x need 0x%04x\n",
1155 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1156
a41b2ff2
PB		 1157 s->IntrStatus |= RxOverflow;
1158 ++s->RxMissed;
1159 rtl8139_update_irq(s);
4f1c942b 1160 return size_;
a41b2ff2
PB		 1161 }
1162
1163 packet_header |= RxStatusOK;
1164
1165 packet_header |= (((size+4) << 16) & 0xffff0000);
1166
1167 /* write header */
1168 uint32_t val = cpu_to_le32(packet_header);
1169
1170 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1171
1172 rtl8139_write_buffer(s, buf, size);
1173
1174 /* write checksum */
ccf1d14a 1175 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1176 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1177
1178 /* correct buffer write pointer */
1179 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1180
1181 /* now we can signal we have received something */
1182
7cdeb319
BP		 1183 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1184 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1185 }
1186
1187 s->IntrStatus |= RxOK;
6cadb320
FB		 1188
1189 if (do_interrupt)
1190 {
1191 rtl8139_update_irq(s);
1192 }
4f1c942b
MM		 1193
1194 return size_;
6cadb320
FB		 1195}
1196
4e68f7a0 1197static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1198{
1673ad51 1199 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1200}
1201
1202static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1203{
1204 s->RxBufferSize = bufferSize;
1205 s->RxBufPtr = 0;
1206 s->RxBufAddr = 0;
1207}
1208
7f23f812 1209static void rtl8139_reset(DeviceState *d)
a41b2ff2 1210{
39257515 1211 RTL8139State *s = RTL8139(d);
a41b2ff2
PB		 1212 int i;
1213
1214 /* restore MAC address */
254111ec 1215 memcpy(s->phys, s->conf.macaddr.a, 6);
655d3b63 1216 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
a41b2ff2
PB		 1217
1218 /* reset interrupt mask */
1219 s->IntrStatus = 0;
1220 s->IntrMask = 0;
1221
1222 rtl8139_update_irq(s);
1223
a41b2ff2
PB		 1224 /* mark all status registers as owned by host */
1225 for (i = 0; i < 4; ++i)
1226 {
1227 s->TxStatus[i] = TxHostOwns;
1228 }
1229
1230 s->currTxDesc = 0;
1231 s->currCPlusRxDesc = 0;
1232 s->currCPlusTxDesc = 0;
1233
1234 s->RxRingAddrLO = 0;
1235 s->RxRingAddrHI = 0;
1236
1237 s->RxBuf = 0;
1238
1239 rtl8139_reset_rxring(s, 8192);
1240
1241 /* ACK the reset */
1242 s->TxConfig = 0;
1243
1244#if 0
1245// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1246 s->clock_enabled = 0;
1247#else
6cadb320 1248 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1249 s->clock_enabled = 1;
1250#endif
1251
1252 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1253
1254 /* set initial state data */
1255 s->Config0 = 0x0; /* No boot ROM */
1256 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1257 s->Config3 = 0x1; /* fast back-to-back compatible */
1258 s->Config5 = 0x0;
1259
5fafdf24 1260 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1261
1262 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1263 s->cplus_enabled = 0;
1264
a41b2ff2
PB		 1265
1266// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1267// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1268 s->BasicModeCtrl = 0x1000; // autonegotiation
1269
1270 s->BasicModeStatus = 0x7809;
1271 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1272 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
83f58e57 1273 /* preserve link state */
b356f76d 1274 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04;
a41b2ff2
PB		 1275
1276 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1277 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1278 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1279
1280 /* also reset timer and disable timer interrupt */
1281 s->TCTR = 0;
1282 s->TimerInt = 0;
1283 s->TCTR_base = 0;
237c255c 1284 rtl8139_set_next_tctr_time(s);
6cadb320
FB		 1285
1286 /* reset tally counters */
1287 RTL8139TallyCounters_clear(&s->tally_counters);
1288}
1289
b1d8e52e 1290static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1291{
1292 counters->TxOk = 0;
1293 counters->RxOk = 0;
1294 counters->TxERR = 0;
1295 counters->RxERR = 0;
1296 counters->MissPkt = 0;
1297 counters->FAE = 0;
1298 counters->Tx1Col = 0;
1299 counters->TxMCol = 0;
1300 counters->RxOkPhy = 0;
1301 counters->RxOkBrd = 0;
1302 counters->RxOkMul = 0;
1303 counters->TxAbt = 0;
1304 counters->TxUndrn = 0;
1305}
1306
3ada003a 1307static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
6cadb320 1308{
88a411a8 1309 PCIDevice *d = PCI_DEVICE(s);
3ada003a 1310 RTL8139TallyCounters *tally_counters = &s->tally_counters;
6cadb320
FB		 1311 uint16_t val16;
1312 uint32_t val32;
1313 uint64_t val64;
1314
1315 val64 = cpu_to_le64(tally_counters->TxOk);
88a411a8 1316 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
6cadb320
FB		 1317
1318 val64 = cpu_to_le64(tally_counters->RxOk);
88a411a8 1319 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
6cadb320
FB		 1320
1321 val64 = cpu_to_le64(tally_counters->TxERR);
88a411a8 1322 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
6cadb320
FB		 1323
1324 val32 = cpu_to_le32(tally_counters->RxERR);
88a411a8 1325 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
6cadb320
FB		 1326
1327 val16 = cpu_to_le16(tally_counters->MissPkt);
88a411a8 1328 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
6cadb320
FB		 1329
1330 val16 = cpu_to_le16(tally_counters->FAE);
88a411a8 1331 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
6cadb320
FB		 1332
1333 val32 = cpu_to_le32(tally_counters->Tx1Col);
88a411a8 1334 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
6cadb320
FB		 1335
1336 val32 = cpu_to_le32(tally_counters->TxMCol);
88a411a8 1337 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
6cadb320
FB		 1338
1339 val64 = cpu_to_le64(tally_counters->RxOkPhy);
88a411a8 1340 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
6cadb320
FB		 1341
1342 val64 = cpu_to_le64(tally_counters->RxOkBrd);
88a411a8 1343 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
6cadb320
FB		 1344
1345 val32 = cpu_to_le32(tally_counters->RxOkMul);
88a411a8 1346 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
6cadb320
FB		 1347
1348 val16 = cpu_to_le16(tally_counters->TxAbt);
88a411a8 1349 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
6cadb320
FB		 1350
1351 val16 = cpu_to_le16(tally_counters->TxUndrn);
88a411a8 1352 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
6cadb320
FB		 1353}
1354
1355/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1356
1357static const VMStateDescription vmstate_tally_counters = {
1358 .name = "tally_counters",
1359 .version_id = 1,
1360 .minimum_version_id = 1,
d49805ae 1361 .fields = (VMStateField[]) {
9d29cdea
JQ		 1362 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1363 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1364 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1365 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1366 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1367 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1368 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1369 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1370 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1371 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1372 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1373 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1374 VMSTATE_END_OF_LIST()
1375 }
1376};
a41b2ff2
PB		 1377
1378static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1379{
39257515
PC		 1380 DeviceState *d = DEVICE(s);
1381
a41b2ff2
PB		 1382 val &= 0xff;
1383
7cdeb319 1384 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1385
1386 if (val & CmdReset)
1387 {
7cdeb319 1388 DPRINTF("ChipCmd reset\n");
39257515 1389 rtl8139_reset(d);
a41b2ff2
PB		 1390 }
1391 if (val & CmdRxEnb)
1392 {
7cdeb319 1393 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1394
1395 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1396 }
1397 if (val & CmdTxEnb)
1398 {
7cdeb319 1399 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1400
1401 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1402 }
1403
ebabb67a 1404 /* mask unwritable bits */
a41b2ff2
PB		 1405 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1406
1407 /* Deassert reset pin before next read */
1408 val &= ~CmdReset;
1409
1410 s->bChipCmdState = val;
1411}
1412
1413static int rtl8139_RxBufferEmpty(RTL8139State *s)
1414{
1415 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1416
1417 if (unread != 0)
1418 {
7cdeb319 1419 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1420 return 0;
1421 }
1422
7cdeb319 1423 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1424
1425 return 1;
1426}
1427
1428static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1429{
1430 uint32_t ret = s->bChipCmdState;
1431
1432 if (rtl8139_RxBufferEmpty(s))
1433 ret |= RxBufEmpty;
1434
7cdeb319 1435 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1436
1437 return ret;
1438}
1439
1440static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1441{
1442 val &= 0xffff;
1443
7cdeb319 1444 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1445
2c3891ab
AL		 1446 s->cplus_enabled = 1;
1447
ebabb67a 1448 /* mask unwritable bits */
a41b2ff2
PB		 1449 val = SET_MASKED(val, 0xff84, s->CpCmd);
1450
1451 s->CpCmd = val;
1452}
1453
1454static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1455{
1456 uint32_t ret = s->CpCmd;
1457
7cdeb319 1458 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1459
1460 return ret;
1461}
1462
1463static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1464{
7cdeb319 1465 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1466}
1467
1468static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1469{
1470 uint32_t ret = 0;
1471
7cdeb319 1472 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1473
1474 return ret;
1475}
1476
ebabb67a 1477static int rtl8139_config_writable(RTL8139State *s)
a41b2ff2 1478{
eb46c5ed 1479 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
a41b2ff2
PB		 1480 {
1481 return 1;
1482 }
1483
7cdeb319 1484 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1485
1486 return 0;
1487}
1488
1489static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1490{
1491 val &= 0xffff;
1492
7cdeb319 1493 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2 1494
ebabb67a 1495 /* mask unwritable bits */
e3d7e843 1496 uint32_t mask = 0x4cff;
a41b2ff2 1497
ebabb67a 1498 if (1 || !rtl8139_config_writable(s))
a41b2ff2
PB		 1499 {
1500 /* Speed setting and autonegotiation enable bits are read-only */
1501 mask |= 0x3000;
1502 /* Duplex mode setting is read-only */
1503 mask |= 0x0100;
1504 }
1505
1506 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1507
1508 s->BasicModeCtrl = val;
1509}
1510
1511static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1512{
1513 uint32_t ret = s->BasicModeCtrl;
1514
7cdeb319 1515 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1516
1517 return ret;
1518}
1519
1520static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1521{
1522 val &= 0xffff;
1523
7cdeb319 1524 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2 1525
ebabb67a 1526 /* mask unwritable bits */
a41b2ff2
PB		 1527 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1528
1529 s->BasicModeStatus = val;
1530}
1531
1532static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1533{
1534 uint32_t ret = s->BasicModeStatus;
1535
7cdeb319 1536 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1537
1538 return ret;
1539}
1540
1541static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1542{
39257515
PC		 1543 DeviceState *d = DEVICE(s);
1544
a41b2ff2
PB		 1545 val &= 0xff;
1546
7cdeb319 1547 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2 1548
ebabb67a 1549 /* mask unwritable bits */
a41b2ff2
PB		 1550 val = SET_MASKED(val, 0x31, s->Cfg9346);
1551
1552 uint32_t opmode = val & 0xc0;
1553 uint32_t eeprom_val = val & 0xf;
1554
1555 if (opmode == 0x80) {
1556 /* eeprom access */
1557 int eecs = (eeprom_val & 0x08)?1:0;
1558 int eesk = (eeprom_val & 0x04)?1:0;
1559 int eedi = (eeprom_val & 0x02)?1:0;
1560 prom9346_set_wire(s, eecs, eesk, eedi);
1561 } else if (opmode == 0x40) {
1562 /* Reset. */
1563 val = 0;
39257515 1564 rtl8139_reset(d);
a41b2ff2
PB		 1565 }
1566
1567 s->Cfg9346 = val;
1568}
1569
1570static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1571{
1572 uint32_t ret = s->Cfg9346;
1573
1574 uint32_t opmode = ret & 0xc0;
1575
1576 if (opmode == 0x80)
1577 {
1578 /* eeprom access */
1579 int eedo = prom9346_get_wire(s);
1580 if (eedo)
1581 {
1582 ret |= 0x01;
1583 }
1584 else
1585 {
1586 ret &= ~0x01;
1587 }
1588 }
1589
7cdeb319 1590 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1591
1592 return ret;
1593}
1594
1595static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1596{
1597 val &= 0xff;
1598
7cdeb319 1599 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2 1600
ebabb67a 1601 if (!rtl8139_config_writable(s)) {
a41b2ff2 1602 return;
ebabb67a 1603 }
a41b2ff2 1604
ebabb67a 1605 /* mask unwritable bits */
a41b2ff2
PB		 1606 val = SET_MASKED(val, 0xf8, s->Config0);
1607
1608 s->Config0 = val;
1609}
1610
1611static uint32_t rtl8139_Config0_read(RTL8139State *s)
1612{
1613 uint32_t ret = s->Config0;
1614
7cdeb319 1615 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1616
1617 return ret;
1618}
1619
1620static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1621{
1622 val &= 0xff;
1623
7cdeb319 1624 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2 1625
ebabb67a 1626 if (!rtl8139_config_writable(s)) {
a41b2ff2 1627 return;
ebabb67a 1628 }
a41b2ff2 1629
ebabb67a 1630 /* mask unwritable bits */
a41b2ff2
PB		 1631 val = SET_MASKED(val, 0xC, s->Config1);
1632
1633 s->Config1 = val;
1634}
1635
1636static uint32_t rtl8139_Config1_read(RTL8139State *s)
1637{
1638 uint32_t ret = s->Config1;
1639
7cdeb319 1640 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1641
1642 return ret;
1643}
1644
1645static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1646{
1647 val &= 0xff;
1648
7cdeb319 1649 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2 1650
ebabb67a 1651 if (!rtl8139_config_writable(s)) {
a41b2ff2 1652 return;
ebabb67a 1653 }
a41b2ff2 1654
ebabb67a 1655 /* mask unwritable bits */
a41b2ff2
PB		 1656 val = SET_MASKED(val, 0x8F, s->Config3);
1657
1658 s->Config3 = val;
1659}
1660
1661static uint32_t rtl8139_Config3_read(RTL8139State *s)
1662{
1663 uint32_t ret = s->Config3;
1664
7cdeb319 1665 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1666
1667 return ret;
1668}
1669
1670static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1671{
1672 val &= 0xff;
1673
7cdeb319 1674 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2 1675
ebabb67a 1676 if (!rtl8139_config_writable(s)) {
a41b2ff2 1677 return;
ebabb67a 1678 }
a41b2ff2 1679
ebabb67a 1680 /* mask unwritable bits */
a41b2ff2
PB		 1681 val = SET_MASKED(val, 0x0a, s->Config4);
1682
1683 s->Config4 = val;
1684}
1685
1686static uint32_t rtl8139_Config4_read(RTL8139State *s)
1687{
1688 uint32_t ret = s->Config4;
1689
7cdeb319 1690 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1691
1692 return ret;
1693}
1694
1695static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1696{
1697 val &= 0xff;
1698
7cdeb319 1699 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2 1700
ebabb67a 1701 /* mask unwritable bits */
a41b2ff2
PB		 1702 val = SET_MASKED(val, 0x80, s->Config5);
1703
1704 s->Config5 = val;
1705}
1706
1707static uint32_t rtl8139_Config5_read(RTL8139State *s)
1708{
1709 uint32_t ret = s->Config5;
1710
7cdeb319 1711 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1712
1713 return ret;
1714}
1715
1716static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1717{
1718 if (!rtl8139_transmitter_enabled(s))
1719 {
7cdeb319 1720 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1721 return;
1722 }
1723
7cdeb319 1724 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1725
1726 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1727
1728 s->TxConfig = val;
1729}
1730
1731static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1732{
7cdeb319 1733 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1734
1735 uint32_t tc = s->TxConfig;
1736 tc &= 0xFFFFFF00;
1737 tc |= (val & 0x000000FF);
1738 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1739}
1740
1741static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1742{
1743 uint32_t ret = s->TxConfig;
1744
7cdeb319 1745 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1746
1747 return ret;
1748}
1749
1750static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1751{
7cdeb319 1752 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2 1753
ebabb67a 1754 /* mask unwritable bits */
a41b2ff2
PB		 1755 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1756
1757 s->RxConfig = val;
1758
1759 /* reset buffer size and read/write pointers */
1760 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1761
7cdeb319 1762 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1763}
1764
1765static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1766{
1767 uint32_t ret = s->RxConfig;
1768
7cdeb319 1769 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1770
1771 return ret;
1772}
1773
bf6b87a8
BP		 1774static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1775 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1776{
bf6b87a8 1777 struct iovec *iov = NULL;
b0af8440 1778 struct iovec vlan_iov[3];
bf6b87a8 1779
718da2b9
FB		 1780 if (!size)
1781 {
7cdeb319 1782 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1783 return;
1784 }
1785
bf6b87a8
BP		 1786 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1787 iov = (struct iovec[3]) {
1788 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1789 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1790 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1791 .iov_len = size - ETHER_ADDR_LEN * 2 },
1792 };
b0af8440
GA		 1793
1794 memcpy(vlan_iov, iov, sizeof(vlan_iov));
1795 iov = vlan_iov;
bf6b87a8
BP		 1796 }
1797
718da2b9
FB		 1798 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1799 {
bf6b87a8
BP		 1800 size_t buf2_size;
1801 uint8_t *buf2;
1802
1803 if (iov) {
1804 buf2_size = iov_size(iov, 3);
7267c094 1805 buf2 = g_malloc(buf2_size);
dcf6f5e1 1806 iov_to_buf(iov, 3, 0, buf2, buf2_size);
bf6b87a8
BP		 1807 buf = buf2;
1808 }
1809
7cdeb319 1810 DPRINTF("+++ transmit loopback mode\n");
b356f76d 1811 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt);
bf6b87a8
BP		 1812
1813 if (iov) {
7267c094 1814 g_free(buf2);
bf6b87a8 1815 }
718da2b9
FB		 1816 }
1817 else
1818 {
bf6b87a8 1819 if (iov) {
b356f76d 1820 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3);
bf6b87a8 1821 } else {
b356f76d 1822 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
bf6b87a8 1823 }
718da2b9
FB		 1824 }
1825}
1826
a41b2ff2
PB		 1827static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1828{
1829 if (!rtl8139_transmitter_enabled(s))
1830 {
7cdeb319
BP		 1831 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1832 "disabled\n", descriptor);
a41b2ff2
PB		 1833 return 0;
1834 }
1835
1836 if (s->TxStatus[descriptor] & TxHostOwns)
1837 {
7cdeb319
BP		 1838 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1839 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1840 return 0;
1841 }
1842
7cdeb319 1843 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2 1844
88a411a8 1845 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 1846 int txsize = s->TxStatus[descriptor] & 0x1fff;
1847 uint8_t txbuffer[0x2000];
1848
7cdeb319
BP		 1849 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1850 txsize, s->TxAddr[descriptor]);
a41b2ff2 1851
88a411a8 1852 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1853
1854 /* Mark descriptor as transferred */
1855 s->TxStatus[descriptor] |= TxHostOwns;
1856 s->TxStatus[descriptor] |= TxStatOK;
1857
bf6b87a8 1858 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1859
7cdeb319
BP		 1860 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1861 descriptor);
a41b2ff2
PB		 1862
1863 /* update interrupt */
1864 s->IntrStatus |= TxOK;
1865 rtl8139_update_irq(s);
1866
1867 return 1;
1868}
1869
718da2b9
FB		 1870/* structures and macros for task offloading */
1871typedef struct ip_header
1872{
1873 uint8_t ip_ver_len; /* version and header length */
1874 uint8_t ip_tos; /* type of service */
1875 uint16_t ip_len; /* total length */
1876 uint16_t ip_id; /* identification */
1877 uint16_t ip_off; /* fragment offset field */
1878 uint8_t ip_ttl; /* time to live */
1879 uint8_t ip_p; /* protocol */
1880 uint16_t ip_sum; /* checksum */
1881 uint32_t ip_src,ip_dst; /* source and dest address */
1882} ip_header;
1883
1884#define IP_HEADER_VERSION_4 4
1885#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1886#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1887
1888typedef struct tcp_header
1889{
1890 uint16_t th_sport; /* source port */
1891 uint16_t th_dport; /* destination port */
1892 uint32_t th_seq; /* sequence number */
1893 uint32_t th_ack; /* acknowledgement number */
1894 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1895 uint16_t th_win; /* window */
1896 uint16_t th_sum; /* checksum */
1897 uint16_t th_urp; /* urgent pointer */
1898} tcp_header;
1899
1900typedef struct udp_header
1901{
1902 uint16_t uh_sport; /* source port */
1903 uint16_t uh_dport; /* destination port */
1904 uint16_t uh_ulen; /* udp length */
1905 uint16_t uh_sum; /* udp checksum */
1906} udp_header;
1907
1908typedef struct ip_pseudo_header
1909{
1910 uint32_t ip_src;
1911 uint32_t ip_dst;
1912 uint8_t zeros;
1913 uint8_t ip_proto;
1914 uint16_t ip_payload;
1915} ip_pseudo_header;
1916
1917#define IP_PROTO_TCP 6
1918#define IP_PROTO_UDP 17
1919
1920#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1921#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1922#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1923
1924#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1925
1926#define TCP_FLAG_FIN 0x01
1927#define TCP_FLAG_PUSH 0x08
1928
1929/* produces ones' complement sum of data */
1930static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1931{
1932 uint32_t result = 0;
1933
1934 for (; len > 1; data+=2, len-=2)
1935 {
1936 result += *(uint16_t*)data;
1937 }
1938
1939 /* add the remainder byte */
1940 if (len)
1941 {
1942 uint8_t odd[2] = {*data, 0};
1943 result += *(uint16_t*)odd;
1944 }
1945
1946 while (result>>16)
1947 result = (result & 0xffff) + (result >> 16);
1948
1949 return result;
1950}
1951
1952static uint16_t ip_checksum(void *data, size_t len)
1953{
1954 return ~ones_complement_sum((uint8_t*)data, len);
1955}
1956
a41b2ff2
PB		 1957static int rtl8139_cplus_transmit_one(RTL8139State *s)
1958{
1959 if (!rtl8139_transmitter_enabled(s))
1960 {
7cdeb319 1961 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1962 return 0;
1963 }
1964
1965 if (!rtl8139_cp_transmitter_enabled(s))
1966 {
7cdeb319 1967 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1968 return 0 ;
1969 }
1970
88a411a8 1971 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 1972 int descriptor = s->currCPlusTxDesc;
1973
3ada003a 1974 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
a41b2ff2
PB		 1975
1976 /* Normal priority ring */
1977 cplus_tx_ring_desc += 16 * descriptor;
1978
7cdeb319 1979 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
4abf12f4 1980 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
7cdeb319 1981 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1982
1983 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1984
88a411a8 1985 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1986 txdw0 = le32_to_cpu(val);
88a411a8 1987 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1988 txdw1 = le32_to_cpu(val);
88a411a8 1989 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
a41b2ff2 1990 txbufLO = le32_to_cpu(val);
88a411a8 1991 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
a41b2ff2
PB		 1992 txbufHI = le32_to_cpu(val);
1993
7cdeb319
BP		 1994 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1995 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1996
1997/* w0 ownership flag */
1998#define CP_TX_OWN (1<<31)
1999/* w0 end of ring flag */
2000#define CP_TX_EOR (1<<30)
2001/* first segment of received packet flag */
2002#define CP_TX_FS (1<<29)
2003/* last segment of received packet flag */
2004#define CP_TX_LS (1<<28)
2005/* large send packet flag */
2006#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 2007/* large send MSS mask, bits 16...25 */
2008#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
2009
a41b2ff2
PB		 2010/* IP checksum offload flag */
2011#define CP_TX_IPCS (1<<18)
2012/* UDP checksum offload flag */
2013#define CP_TX_UDPCS (1<<17)
2014/* TCP checksum offload flag */
2015#define CP_TX_TCPCS (1<<16)
2016
2017/* w0 bits 0...15 : buffer size */
2018#define CP_TX_BUFFER_SIZE (1<<16)
2019#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 2020/* w1 add tag flag */
2021#define CP_TX_TAGC (1<<17)
2022/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 2023#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2024/* w2 low 32bit of Rx buffer ptr */
2025/* w3 high 32bit of Rx buffer ptr */
2026
2027/* set after transmission */
2028/* FIFO underrun flag */
2029#define CP_TX_STATUS_UNF (1<<25)
2030/* transmit error summary flag, valid if set any of three below */
2031#define CP_TX_STATUS_TES (1<<23)
2032/* out-of-window collision flag */
2033#define CP_TX_STATUS_OWC (1<<22)
2034/* link failure flag */
2035#define CP_TX_STATUS_LNKF (1<<21)
2036/* excessive collisions flag */
2037#define CP_TX_STATUS_EXC (1<<20)
2038
2039 if (!(txdw0 & CP_TX_OWN))
2040 {
7cdeb319 2041 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 2042 return 0 ;
2043 }
2044
7cdeb319 2045 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 2046
2047 if (txdw0 & CP_TX_FS)
2048 {
7cdeb319
BP		 2049 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2050 "descriptor\n", descriptor);
6cadb320
FB		 2051
2052 /* reset internal buffer offset */
2053 s->cplus_txbuffer_offset = 0;
2054 }
a41b2ff2
PB		 2055
2056 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
3ada003a 2057 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2058
6cadb320
FB		 2059 /* make sure we have enough space to assemble the packet */
2060 if (!s->cplus_txbuffer)
2061 {
2062 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
7267c094 2063 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
6cadb320 2064 s->cplus_txbuffer_offset = 0;
718da2b9 2065
7cdeb319
BP		 2066 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2067 s->cplus_txbuffer_len);
6cadb320
FB		 2068 }
2069
cde31a0e 2070 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
6cadb320 2071 {
cde31a0e
JW		 2072 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2073 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2074 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2075 "length to %d\n", txsize);
6cadb320
FB		 2076 }
2077
6cadb320
FB		 2078 /* append more data to the packet */
2079
7cdeb319 2080 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
3ada003a
EGM		 2081 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2082 s->cplus_txbuffer_offset);
6cadb320 2083
88a411a8 2084 pci_dma_read(d, tx_addr,
3ada003a 2085 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
6cadb320
FB		 2086 s->cplus_txbuffer_offset += txsize;
2087
2088 /* seek to next Rx descriptor */
2089 if (txdw0 & CP_TX_EOR)
2090 {
2091 s->currCPlusTxDesc = 0;
2092 }
2093 else
2094 {
2095 ++s->currCPlusTxDesc;
2096 if (s->currCPlusTxDesc >= 64)
2097 s->currCPlusTxDesc = 0;
2098 }
a41b2ff2
PB		 2099
2100 /* transfer ownership to target */
2101 txdw0 &= ~CP_RX_OWN;
2102
2103 /* reset error indicator bits */
2104 txdw0 &= ~CP_TX_STATUS_UNF;
2105 txdw0 &= ~CP_TX_STATUS_TES;
2106 txdw0 &= ~CP_TX_STATUS_OWC;
2107 txdw0 &= ~CP_TX_STATUS_LNKF;
2108 txdw0 &= ~CP_TX_STATUS_EXC;
2109
2110 /* update ring data */
2111 val = cpu_to_le32(txdw0);
88a411a8 2112 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2113
6cadb320
FB		 2114 /* Now decide if descriptor being processed is holding the last segment of packet */
2115 if (txdw0 & CP_TX_LS)
a41b2ff2 2116 {
bf6b87a8
BP		 2117 uint8_t dot1q_buffer_space[VLAN_HLEN];
2118 uint16_t *dot1q_buffer;
2119
7cdeb319
BP		 2120 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2121 descriptor);
6cadb320
FB		 2122
2123 /* can transfer fully assembled packet */
2124
2125 uint8_t *saved_buffer = s->cplus_txbuffer;
2126 int saved_size = s->cplus_txbuffer_offset;
2127 int saved_buffer_len = s->cplus_txbuffer_len;
2128
bf6b87a8
BP		 2129 /* create vlan tag */
2130 if (txdw1 & CP_TX_TAGC) {
2131 /* the vlan tag is in BE byte order in the descriptor
2132 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2133 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2134 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2135
2136 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2137 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2138 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2139 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2140 } else {
2141 dot1q_buffer = NULL;
2142 }
2143
6cadb320
FB		 2144 /* reset the card space to protect from recursive call */
2145 s->cplus_txbuffer = NULL;
2146 s->cplus_txbuffer_offset = 0;
2147 s->cplus_txbuffer_len = 0;
2148
718da2b9 2149 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2150 {
7cdeb319 2151 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2152
6cadb320 2153 /* ip packet header */
660f11be 2154 ip_header *ip = NULL;
6cadb320 2155 int hlen = 0;
718da2b9
FB		 2156 uint8_t ip_protocol = 0;
2157 uint16_t ip_data_len = 0;
6cadb320 2158
660f11be 2159 uint8_t *eth_payload_data = NULL;
718da2b9 2160 size_t eth_payload_len = 0;
6cadb320 2161
718da2b9 2162 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2163 if (proto == ETH_P_IP)
2164 {
7cdeb319 2165 DPRINTF("+++ C+ mode has IP packet\n");
6cadb320
FB		 2166
2167 /* not aligned */
718da2b9
FB		 2168 eth_payload_data = saved_buffer + ETH_HLEN;
2169 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2170
718da2b9 2171 ip = (ip_header*)eth_payload_data;
6cadb320 2172
718da2b9 2173 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
7cdeb319
BP		 2174 DPRINTF("+++ C+ mode packet has bad IP version %d "
2175 "expected %d\n", IP_HEADER_VERSION(ip),
2176 IP_HEADER_VERSION_4);
6cadb320
FB		 2177 ip = NULL;
2178 } else {
718da2b9
FB		 2179 hlen = IP_HEADER_LENGTH(ip);
2180 ip_protocol = ip->ip_p;
2181 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2182 }
2183 }
2184
2185 if (ip)
2186 {
2187 if (txdw0 & CP_TX_IPCS)
2188 {
7cdeb319 2189 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2190
718da2b9 2191 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2192 /* bad packet header len */
2193 /* or packet too short */
2194 }
2195 else
2196 {
2197 ip->ip_sum = 0;
718da2b9 2198 ip->ip_sum = ip_checksum(ip, hlen);
7cdeb319
BP		 2199 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2200 hlen, ip->ip_sum);
6cadb320
FB		 2201 }
2202 }
2203
718da2b9 2204 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2205 {
718da2b9 2206 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
ec48c774 2207
7cdeb319
BP		 2208 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2209 "frame data %d specified MSS=%d\n", ETH_MTU,
2210 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2211
718da2b9
FB		 2212 int tcp_send_offset = 0;
2213 int send_count = 0;
6cadb320
FB		 2214
2215 /* maximum IP header length is 60 bytes */
2216 uint8_t saved_ip_header[60];
6cadb320 2217
718da2b9
FB		 2218 /* save IP header template; data area is used in tcp checksum calculation */
2219 memcpy(saved_ip_header, eth_payload_data, hlen);
2220
2221 /* a placeholder for checksum calculation routine in tcp case */
2222 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2223 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2224
2225 /* pointer to TCP header */
2226 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2227
2228 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2229
2230 /* ETH_MTU = ip header len + tcp header len + payload */
2231 int tcp_data_len = ip_data_len - tcp_hlen;
2232 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2233
7cdeb319
BP		 2234 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2235 "data len %d TCP chunk size %d\n", ip_data_len,
2236 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9
FB		 2237
2238 /* note the cycle below overwrites IP header data,
2239 but restores it from saved_ip_header before sending packet */
2240
2241 int is_last_frame = 0;
2242
2243 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2244 {
2245 uint16_t chunk_size = tcp_chunk_size;
2246
2247 /* check if this is the last frame */
2248 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2249 {
2250 is_last_frame = 1;
2251 chunk_size = tcp_data_len - tcp_send_offset;
2252 }
2253
7cdeb319
BP		 2254 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2255 be32_to_cpu(p_tcp_hdr->th_seq));
718da2b9
FB		 2256
2257 /* add 4 TCP pseudoheader fields */
2258 /* copy IP source and destination fields */
2259 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2260
7cdeb319
BP		 2261 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2262 "packet with %d bytes data\n", tcp_hlen +
2263 chunk_size);
718da2b9
FB		 2264
2265 if (tcp_send_offset)
2266 {
2267 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2268 }
2269
2270 /* keep PUSH and FIN flags only for the last frame */
2271 if (!is_last_frame)
2272 {
2273 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2274 }
6cadb320 2275
718da2b9
FB		 2276 /* recalculate TCP checksum */
2277 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2278 p_tcpip_hdr->zeros = 0;
2279 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2280 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2281
2282 p_tcp_hdr->th_sum = 0;
2283
2284 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
7cdeb319
BP		 2285 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2286 tcp_checksum);
718da2b9
FB		 2287
2288 p_tcp_hdr->th_sum = tcp_checksum;
2289
2290 /* restore IP header */
2291 memcpy(eth_payload_data, saved_ip_header, hlen);
2292
2293 /* set IP data length and recalculate IP checksum */
2294 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2295
2296 /* increment IP id for subsequent frames */
2297 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2298
2299 ip->ip_sum = 0;
2300 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
7cdeb319
BP		 2301 DPRINTF("+++ C+ mode TSO IP header len=%d "
2302 "checksum=%04x\n", hlen, ip->ip_sum);
718da2b9
FB		 2303
2304 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
7cdeb319
BP		 2305 DPRINTF("+++ C+ mode TSO transferring packet size "
2306 "%d\n", tso_send_size);
bf6b87a8
BP		 2307 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2308 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2309
2310 /* add transferred count to TCP sequence number */
2311 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2312 ++send_count;
2313 }
2314
2315 /* Stop sending this frame */
2316 saved_size = 0;
2317 }
2318 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2319 {
7cdeb319 2320 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
718da2b9
FB		 2321
2322 /* maximum IP header length is 60 bytes */
2323 uint8_t saved_ip_header[60];
2324 memcpy(saved_ip_header, eth_payload_data, hlen);
2325
2326 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2327 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2328
2329 /* add 4 TCP pseudoheader fields */
2330 /* copy IP source and destination fields */
718da2b9 2331 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2332
718da2b9 2333 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320 2334 {
7cdeb319
BP		 2335 DPRINTF("+++ C+ mode calculating TCP checksum for "
2336 "packet with %d bytes data\n", ip_data_len);
6cadb320 2337
718da2b9
FB		 2338 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2339 p_tcpip_hdr->zeros = 0;
2340 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2341 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2342
718da2b9 2343 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2344
2345 p_tcp_hdr->th_sum = 0;
2346
718da2b9 2347 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2348 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2349 tcp_checksum);
6cadb320
FB		 2350
2351 p_tcp_hdr->th_sum = tcp_checksum;
2352 }
718da2b9 2353 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320 2354 {
7cdeb319
BP		 2355 DPRINTF("+++ C+ mode calculating UDP checksum for "
2356 "packet with %d bytes data\n", ip_data_len);
6cadb320 2357
718da2b9
FB		 2358 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2359 p_udpip_hdr->zeros = 0;
2360 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2361 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2362
718da2b9 2363 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2364
6cadb320
FB		 2365 p_udp_hdr->uh_sum = 0;
2366
718da2b9 2367 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2368 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2369 udp_checksum);
6cadb320 2370
6cadb320
FB		 2371 p_udp_hdr->uh_sum = udp_checksum;
2372 }
2373
2374 /* restore IP header */
718da2b9 2375 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2376 }
2377 }
2378 }
2379
2380 /* update tally counter */
2381 ++s->tally_counters.TxOk;
2382
7cdeb319 2383 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2384
bf6b87a8
BP		 2385 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2386 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2387
2388 /* restore card space if there was no recursion and reset offset */
2389 if (!s->cplus_txbuffer)
2390 {
2391 s->cplus_txbuffer = saved_buffer;
2392 s->cplus_txbuffer_len = saved_buffer_len;
2393 s->cplus_txbuffer_offset = 0;
2394 }
2395 else
2396 {
7267c094 2397 g_free(saved_buffer);
6cadb320 2398 }
a41b2ff2
PB		 2399 }
2400 else
2401 {
7cdeb319 2402 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2403 }
2404
a41b2ff2
PB		 2405 return 1;
2406}
2407
2408static void rtl8139_cplus_transmit(RTL8139State *s)
2409{
2410 int txcount = 0;
2411
2412 while (rtl8139_cplus_transmit_one(s))
2413 {
2414 ++txcount;
2415 }
2416
2417 /* Mark transfer completed */
2418 if (!txcount)
2419 {
7cdeb319
BP		 2420 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2421 s->currCPlusTxDesc);
a41b2ff2
PB		 2422 }
2423 else
2424 {
2425 /* update interrupt status */
2426 s->IntrStatus |= TxOK;
2427 rtl8139_update_irq(s);
2428 }
2429}
2430
2431static void rtl8139_transmit(RTL8139State *s)
2432{
2433 int descriptor = s->currTxDesc, txcount = 0;
2434
2435 /*while*/
2436 if (rtl8139_transmit_one(s, descriptor))
2437 {
2438 ++s->currTxDesc;
2439 s->currTxDesc %= 4;
2440 ++txcount;
2441 }
2442
2443 /* Mark transfer completed */
2444 if (!txcount)
2445 {
7cdeb319
BP		 2446 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2447 s->currTxDesc);
a41b2ff2
PB		 2448 }
2449}
2450
2451static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2452{
2453
2454 int descriptor = txRegOffset/4;
6cadb320
FB		 2455
2456 /* handle C+ transmit mode register configuration */
2457
2c3891ab 2458 if (s->cplus_enabled)
6cadb320 2459 {
7cdeb319
BP		 2460 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2461 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2462
2463 /* handle Dump Tally Counters command */
2464 s->TxStatus[descriptor] = val;
2465
2466 if (descriptor == 0 && (val & 0x8))
2467 {
a8170e5e 2468 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2469
2470 /* dump tally counters to specified memory location */
3ada003a 2471 RTL8139TallyCounters_dma_write(s, tc_addr);
6cadb320
FB		 2472
2473 /* mark dump completed */
2474 s->TxStatus[0] &= ~0x8;
2475 }
2476
2477 return;
2478 }
2479
7cdeb319
BP		 2480 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2481 txRegOffset, val, descriptor);
a41b2ff2
PB		 2482
2483 /* mask only reserved bits */
2484 val &= ~0xff00c000; /* these bits are reset on write */
2485 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2486
2487 s->TxStatus[descriptor] = val;
2488
2489 /* attempt to start transmission */
2490 rtl8139_transmit(s);
2491}
2492
3e48dd4a
SH		 2493static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2494 uint32_t base, uint8_t addr,
2495 int size)
a41b2ff2 2496{
3e48dd4a 2497 uint32_t reg = (addr - base) / 4;
afe0a595
JW		 2498 uint32_t offset = addr & 0x3;
2499 uint32_t ret = 0;
2500
2501 if (addr & (size - 1)) {
3e48dd4a
SH		 2502 DPRINTF("not implemented read for TxStatus/TxAddr "
2503 "addr=0x%x size=0x%x\n", addr, size);
afe0a595
JW		 2504 return ret;
2505 }
a41b2ff2 2506
afe0a595
JW		 2507 switch (size) {
2508 case 1: /* fall through */
2509 case 2: /* fall through */
2510 case 4:
bdc62e62 2511 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
3e48dd4a
SH		 2512 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2513 reg, addr, size, ret);
afe0a595
JW		 2514 break;
2515 default:
3e48dd4a 2516 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
afe0a595
JW		 2517 break;
2518 }
a41b2ff2
PB		 2519
2520 return ret;
2521}
2522
2523static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2524{
2525 uint16_t ret = 0;
2526
2527 /* Simulate TSAD, it is read only anyway */
2528
2529 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2530 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2531 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2532 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2533
2534 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2535 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2536 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2537 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2538
a41b2ff2
PB		 2539 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2540 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2541 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2542 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2543
a41b2ff2
PB		 2544 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2545 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2546 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2547 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2548
a41b2ff2 2549
7cdeb319 2550 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2551
2552 return ret;
2553}
2554
2555static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2556{
2557 uint16_t ret = s->CSCR;
2558
7cdeb319 2559 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2560
2561 return ret;
2562}
2563
2564static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2565{
7cdeb319 2566 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2567
290a0933 2568 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2569}
2570
2571static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2572{
290a0933 2573 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2574
7cdeb319 2575 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2576
2577 return ret;
2578}
2579
2580static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2581{
7cdeb319 2582 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2583
2584 /* this value is off by 16 */
2585 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2586
00b7ade8
SH		 2587 /* more buffer space may be available so try to receive */
2588 qemu_flush_queued_packets(qemu_get_queue(s->nic));
2589
7cdeb319
BP		 2590 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2591 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2592}
2593
2594static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2595{
2596 /* this value is off by 16 */
2597 uint32_t ret = s->RxBufPtr - 0x10;
2598
7cdeb319 2599 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2600
2601 return ret;
2602}
2603
2604static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2605{
2606 /* this value is NOT off by 16 */
2607 uint32_t ret = s->RxBufAddr;
2608
7cdeb319 2609 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2610
2611 return ret;
2612}
2613
2614static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2615{
7cdeb319 2616 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2617
2618 s->RxBuf = val;
2619
2620 /* may need to reset rxring here */
2621}
2622
2623static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2624{
2625 uint32_t ret = s->RxBuf;
2626
7cdeb319 2627 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2628
2629 return ret;
2630}
2631
2632static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2633{
7cdeb319 2634 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2 2635
ebabb67a 2636 /* mask unwritable bits */
a41b2ff2
PB		 2637 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2638
2639 s->IntrMask = val;
2640
2641 rtl8139_update_irq(s);
05447803 2642
a41b2ff2
PB		 2643}
2644
2645static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2646{
2647 uint32_t ret = s->IntrMask;
2648
7cdeb319 2649 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2650
2651 return ret;
2652}
2653
2654static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2655{
7cdeb319 2656 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2657
2658#if 0
2659
2660 /* writing to ISR has no effect */
2661
2662 return;
2663
2664#else
2665 uint16_t newStatus = s->IntrStatus & ~val;
2666
ebabb67a 2667 /* mask unwritable bits */
a41b2ff2
PB		 2668 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2669
2670 /* writing 1 to interrupt status register bit clears it */
2671 s->IntrStatus = 0;
2672 rtl8139_update_irq(s);
2673
2674 s->IntrStatus = newStatus;
237c255c 2675 rtl8139_set_next_tctr_time(s);
a41b2ff2 2676 rtl8139_update_irq(s);
05447803 2677
a41b2ff2
PB		 2678#endif
2679}
2680
2681static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2682{
2683 uint32_t ret = s->IntrStatus;
2684
7cdeb319 2685 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2686
2687#if 0
2688
2689 /* reading ISR clears all interrupts */
2690 s->IntrStatus = 0;
2691
2692 rtl8139_update_irq(s);
2693
2694#endif
2695
2696 return ret;
2697}
2698
2699static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2700{
7cdeb319 2701 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2 2702
ebabb67a 2703 /* mask unwritable bits */
a41b2ff2
PB		 2704 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2705
2706 s->MultiIntr = val;
2707}
2708
2709static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2710{
2711 uint32_t ret = s->MultiIntr;
2712
7cdeb319 2713 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2714
2715 return ret;
2716}
2717
2718static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2719{
2720 RTL8139State *s = opaque;
2721
a41b2ff2
PB		 2722 switch (addr)
2723 {
90d131fb
MT		 2724 case MAC0 ... MAC0+4:
2725 s->phys[addr - MAC0] = val;
2726 break;
2727 case MAC0+5:
23c37c37
AK		 2728 s->phys[addr - MAC0] = val;
2729 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
2730 break;
a41b2ff2
PB		 2731 case MAC0+6 ... MAC0+7:
2732 /* reserved */
2733 break;
2734 case MAR0 ... MAR0+7:
2735 s->mult[addr - MAR0] = val;
2736 break;
2737 case ChipCmd:
2738 rtl8139_ChipCmd_write(s, val);
2739 break;
2740 case Cfg9346:
2741 rtl8139_Cfg9346_write(s, val);
2742 break;
2743 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2744 rtl8139_TxConfig_writeb(s, val);
2745 break;
2746 case Config0:
2747 rtl8139_Config0_write(s, val);
2748 break;
2749 case Config1:
2750 rtl8139_Config1_write(s, val);
2751 break;
2752 case Config3:
2753 rtl8139_Config3_write(s, val);
2754 break;
2755 case Config4:
2756 rtl8139_Config4_write(s, val);
2757 break;
2758 case Config5:
2759 rtl8139_Config5_write(s, val);
2760 break;
2761 case MediaStatus:
2762 /* ignore */
7cdeb319
BP		 2763 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2764 val);
a41b2ff2
PB		 2765 break;
2766
2767 case HltClk:
7cdeb319 2768 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2769 if (val == 'R')
2770 {
2771 s->clock_enabled = 1;
2772 }
2773 else if (val == 'H')
2774 {
2775 s->clock_enabled = 0;
2776 }
2777 break;
2778
2779 case TxThresh:
7cdeb319 2780 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2781 s->TxThresh = val;
2782 break;
2783
2784 case TxPoll:
7cdeb319 2785 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2786 if (val & (1 << 7))
2787 {
7cdeb319
BP		 2788 DPRINTF("C+ TxPoll high priority transmission (not "
2789 "implemented)\n");
a41b2ff2
PB		 2790 //rtl8139_cplus_transmit(s);
2791 }
2792 if (val & (1 << 6))
2793 {
7cdeb319 2794 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2795 rtl8139_cplus_transmit(s);
2796 }
2797
2798 break;
2799
2800 default:
7cdeb319
BP		 2801 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2802 val);
a41b2ff2
PB		 2803 break;
2804 }
2805}
2806
2807static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2808{
2809 RTL8139State *s = opaque;
2810
a41b2ff2
PB		 2811 switch (addr)
2812 {
2813 case IntrMask:
2814 rtl8139_IntrMask_write(s, val);
2815 break;
2816
2817 case IntrStatus:
2818 rtl8139_IntrStatus_write(s, val);
2819 break;
2820
2821 case MultiIntr:
2822 rtl8139_MultiIntr_write(s, val);
2823 break;
2824
2825 case RxBufPtr:
2826 rtl8139_RxBufPtr_write(s, val);
2827 break;
2828
2829 case BasicModeCtrl:
2830 rtl8139_BasicModeCtrl_write(s, val);
2831 break;
2832 case BasicModeStatus:
2833 rtl8139_BasicModeStatus_write(s, val);
2834 break;
2835 case NWayAdvert:
7cdeb319 2836 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2837 s->NWayAdvert = val;
2838 break;
2839 case NWayLPAR:
7cdeb319 2840 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2841 break;
2842 case NWayExpansion:
7cdeb319 2843 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2844 s->NWayExpansion = val;
2845 break;
2846
2847 case CpCmd:
2848 rtl8139_CpCmd_write(s, val);
2849 break;
2850
6cadb320
FB		 2851 case IntrMitigate:
2852 rtl8139_IntrMitigate_write(s, val);
2853 break;
2854
a41b2ff2 2855 default:
7cdeb319
BP		 2856 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2857 addr, val);
a41b2ff2 2858
a41b2ff2
PB		 2859 rtl8139_io_writeb(opaque, addr, val & 0xff);
2860 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2861 break;
2862 }
2863}
2864
237c255c 2865static void rtl8139_set_next_tctr_time(RTL8139State *s)
05447803 2866{
237c255c
PB		 2867 const uint64_t ns_per_period =
2868 muldiv64(0x100000000LL, get_ticks_per_sec(), PCI_FREQUENCY);
05447803 2869
7cdeb319 2870 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803 2871
237c255c
PB		 2872 /* This function is called at least once per period, so it is a good
2873 * place to update the timer base.
2874 *
2875 * After one iteration of this loop the value in the Timer register does
2876 * not change, but the device model is counting up by 2^32 ticks (approx.
2877 * 130 seconds).
05447803 2878 */
237c255c
PB		 2879 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2880 s->TCTR_base += ns_per_period;
05447803 2881 }
05447803 2882
237c255c
PB		 2883 if (!s->TimerInt) {
2884 timer_del(s->timer);
2885 } else {
2886 uint64_t delta = muldiv64(s->TimerInt, get_ticks_per_sec(), PCI_FREQUENCY);
2887 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2888 delta += ns_per_period;
2889 }
2890 timer_mod(s->timer, s->TCTR_base + delta);
05447803
FZ		 2891 }
2892}
2893
a41b2ff2
PB		 2894static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2895{
2896 RTL8139State *s = opaque;
2897
a41b2ff2
PB		 2898 switch (addr)
2899 {
2900 case RxMissed:
7cdeb319 2901 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2902 s->RxMissed = 0;
2903 break;
2904
2905 case TxConfig:
2906 rtl8139_TxConfig_write(s, val);
2907 break;
2908
2909 case RxConfig:
2910 rtl8139_RxConfig_write(s, val);
2911 break;
2912
2913 case TxStatus0 ... TxStatus0+4*4-1:
2914 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2915 break;
2916
2917 case TxAddr0 ... TxAddr0+4*4-1:
2918 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2919 break;
2920
2921 case RxBuf:
2922 rtl8139_RxBuf_write(s, val);
2923 break;
2924
2925 case RxRingAddrLO:
7cdeb319 2926 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2927 s->RxRingAddrLO = val;
2928 break;
2929
2930 case RxRingAddrHI:
7cdeb319 2931 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2932 s->RxRingAddrHI = val;
2933 break;
2934
6cadb320 2935 case Timer:
7cdeb319 2936 DPRINTF("TCTR Timer reset on write\n");
bc72ad67 2937 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
237c255c 2938 rtl8139_set_next_tctr_time(s);
6cadb320
FB		 2939 break;
2940
2941 case FlashReg:
7cdeb319 2942 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2943 if (s->TimerInt != val) {
2944 s->TimerInt = val;
237c255c 2945 rtl8139_set_next_tctr_time(s);
05447803 2946 }
6cadb320
FB		 2947 break;
2948
a41b2ff2 2949 default:
7cdeb319
BP		 2950 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2951 addr, val);
a41b2ff2
PB		 2952 rtl8139_io_writeb(opaque, addr, val & 0xff);
2953 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2954 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2955 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2956 break;
2957 }
2958}
2959
2960static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2961{
2962 RTL8139State *s = opaque;
2963 int ret;
2964
a41b2ff2
PB		 2965 switch (addr)
2966 {
2967 case MAC0 ... MAC0+5:
2968 ret = s->phys[addr - MAC0];
2969 break;
2970 case MAC0+6 ... MAC0+7:
2971 ret = 0;
2972 break;
2973 case MAR0 ... MAR0+7:
2974 ret = s->mult[addr - MAR0];
2975 break;
afe0a595 2976 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 2977 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2978 addr, 1);
afe0a595 2979 break;
a41b2ff2
PB		 2980 case ChipCmd:
2981 ret = rtl8139_ChipCmd_read(s);
2982 break;
2983 case Cfg9346:
2984 ret = rtl8139_Cfg9346_read(s);
2985 break;
2986 case Config0:
2987 ret = rtl8139_Config0_read(s);
2988 break;
2989 case Config1:
2990 ret = rtl8139_Config1_read(s);
2991 break;
2992 case Config3:
2993 ret = rtl8139_Config3_read(s);
2994 break;
2995 case Config4:
2996 ret = rtl8139_Config4_read(s);
2997 break;
2998 case Config5:
2999 ret = rtl8139_Config5_read(s);
3000 break;
3001
3002 case MediaStatus:
9e12c5af
JW		 3003 /* The LinkDown bit of MediaStatus is inverse with link status */
3004 ret = 0xd0 | (~s->BasicModeStatus & 0x04);
7cdeb319 3005 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 3006 break;
3007
3008 case HltClk:
3009 ret = s->clock_enabled;
7cdeb319 3010 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 3011 break;
3012
3013 case PCIRevisionID:
6cadb320 3014 ret = RTL8139_PCI_REVID;
7cdeb319 3015 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 3016 break;
3017
3018 case TxThresh:
3019 ret = s->TxThresh;
7cdeb319 3020 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3021 break;
3022
3023 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3024 ret = s->TxConfig >> 24;
7cdeb319 3025 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3026 break;
3027
3028 default:
7cdeb319 3029 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 3030 ret = 0;
3031 break;
3032 }
3033
3034 return ret;
3035}
3036
3037static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3038{
3039 RTL8139State *s = opaque;
3040 uint32_t ret;
3041
a41b2ff2
PB		 3042 switch (addr)
3043 {
afe0a595 3044 case TxAddr0 ... TxAddr0+4*4-1:
3e48dd4a 3045 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
afe0a595 3046 break;
a41b2ff2
PB		 3047 case IntrMask:
3048 ret = rtl8139_IntrMask_read(s);
3049 break;
3050
3051 case IntrStatus:
3052 ret = rtl8139_IntrStatus_read(s);
3053 break;
3054
3055 case MultiIntr:
3056 ret = rtl8139_MultiIntr_read(s);
3057 break;
3058
3059 case RxBufPtr:
3060 ret = rtl8139_RxBufPtr_read(s);
3061 break;
3062
6cadb320
FB		 3063 case RxBufAddr:
3064 ret = rtl8139_RxBufAddr_read(s);
3065 break;
3066
a41b2ff2
PB		 3067 case BasicModeCtrl:
3068 ret = rtl8139_BasicModeCtrl_read(s);
3069 break;
3070 case BasicModeStatus:
3071 ret = rtl8139_BasicModeStatus_read(s);
3072 break;
3073 case NWayAdvert:
3074 ret = s->NWayAdvert;
7cdeb319 3075 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3076 break;
3077 case NWayLPAR:
3078 ret = s->NWayLPAR;
7cdeb319 3079 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3080 break;
3081 case NWayExpansion:
3082 ret = s->NWayExpansion;
7cdeb319 3083 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3084 break;
3085
3086 case CpCmd:
3087 ret = rtl8139_CpCmd_read(s);
3088 break;
3089
6cadb320
FB		 3090 case IntrMitigate:
3091 ret = rtl8139_IntrMitigate_read(s);
3092 break;
3093
a41b2ff2
PB		 3094 case TxSummary:
3095 ret = rtl8139_TSAD_read(s);
3096 break;
3097
3098 case CSCR:
3099 ret = rtl8139_CSCR_read(s);
3100 break;
3101
3102 default:
7cdeb319 3103 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3104
a41b2ff2
PB		 3105 ret = rtl8139_io_readb(opaque, addr);
3106 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3107
7cdeb319 3108 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3109 break;
3110 }
3111
3112 return ret;
3113}
3114
3115static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3116{
3117 RTL8139State *s = opaque;
3118 uint32_t ret;
3119
a41b2ff2
PB		 3120 switch (addr)
3121 {
3122 case RxMissed:
3123 ret = s->RxMissed;
3124
7cdeb319 3125 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3126 break;
3127
3128 case TxConfig:
3129 ret = rtl8139_TxConfig_read(s);
3130 break;
3131
3132 case RxConfig:
3133 ret = rtl8139_RxConfig_read(s);
3134 break;
3135
3136 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 3137 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3138 addr, 4);
a41b2ff2
PB		 3139 break;
3140
3141 case TxAddr0 ... TxAddr0+4*4-1:
3142 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3143 break;
3144
3145 case RxBuf:
3146 ret = rtl8139_RxBuf_read(s);
3147 break;
3148
3149 case RxRingAddrLO:
3150 ret = s->RxRingAddrLO;
7cdeb319 3151 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3152 break;
3153
3154 case RxRingAddrHI:
3155 ret = s->RxRingAddrHI;
7cdeb319 3156 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3157 break;
3158
3159 case Timer:
bc72ad67 3160 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base,
05447803 3161 PCI_FREQUENCY, get_ticks_per_sec());
7cdeb319 3162 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3163 break;
3164
3165 case FlashReg:
3166 ret = s->TimerInt;
7cdeb319 3167 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3168 break;
3169
3170 default:
7cdeb319 3171 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3172
a41b2ff2
PB		 3173 ret = rtl8139_io_readb(opaque, addr);
3174 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3175 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3176 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3177
7cdeb319 3178 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3179 break;
3180 }
3181
3182 return ret;
3183}
3184
3185/* */
3186
a8170e5e 3187static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
a41b2ff2
PB		 3188{
3189 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3190}
3191
a8170e5e 3192static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
a41b2ff2
PB		 3193{
3194 rtl8139_io_writew(opaque, addr & 0xFF, val);
3195}
3196
a8170e5e 3197static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
a41b2ff2
PB		 3198{
3199 rtl8139_io_writel(opaque, addr & 0xFF, val);
3200}
3201
a8170e5e 3202static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr)
a41b2ff2
PB		 3203{
3204 return rtl8139_io_readb(opaque, addr & 0xFF);
3205}
3206
a8170e5e 3207static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr)
a41b2ff2 3208{
5fedc612 3209 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3210 return val;
a41b2ff2
PB		 3211}
3212
a8170e5e 3213static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr)
a41b2ff2 3214{
5fedc612 3215 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3216 return val;
a41b2ff2
PB		 3217}
3218
060110c3 3219static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3220{
6597ebbb 3221 RTL8139State* s = opaque;
237c255c 3222 rtl8139_set_next_tctr_time(s);
060110c3 3223 if (version_id < 4) {
2c3891ab
AL		 3224 s->cplus_enabled = s->CpCmd != 0;
3225 }
3226
9e12c5af
JW		 3227 /* nc.link_down can't be migrated, so infer link_down according
3228 * to link status bit in BasicModeStatus */
b356f76d 3229 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0;
9e12c5af 3230
a41b2ff2
PB		 3231 return 0;
3232}
3233
c574ba5a
AW		 3234static bool rtl8139_hotplug_ready_needed(void *opaque)
3235{
3236 return qdev_machine_modified();
3237}
3238
3239static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3240 .name = "rtl8139/hotplug_ready",
3241 .version_id = 1,
3242 .minimum_version_id = 1,
5cd8cada 3243 .needed = rtl8139_hotplug_ready_needed,
d49805ae 3244 .fields = (VMStateField[]) {
c574ba5a
AW		 3245 VMSTATE_END_OF_LIST()
3246 }
3247};
3248
05447803
FZ		 3249static void rtl8139_pre_save(void *opaque)
3250{
3251 RTL8139State* s = opaque;
bc72ad67 3252 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
05447803 3253
237c255c 3254 /* for migration to older versions */
05447803
FZ		 3255 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3256 get_ticks_per_sec());
bd80f3fc 3257 s->rtl8139_mmio_io_addr_dummy = 0;
05447803
FZ		 3258}
3259
060110c3
JQ		 3260static const VMStateDescription vmstate_rtl8139 = {
3261 .name = "rtl8139",
3262 .version_id = 4,
3263 .minimum_version_id = 3,
060110c3 3264 .post_load = rtl8139_post_load,
05447803 3265 .pre_save = rtl8139_pre_save,
d49805ae 3266 .fields = (VMStateField[]) {
88a411a8 3267 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
060110c3
JQ		 3268 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3269 VMSTATE_BUFFER(mult, RTL8139State),
3270 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3271 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3272
3273 VMSTATE_UINT32(RxBuf, RTL8139State),
3274 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3275 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3276 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3277
3278 VMSTATE_UINT16(IntrStatus, RTL8139State),
3279 VMSTATE_UINT16(IntrMask, RTL8139State),
3280
3281 VMSTATE_UINT32(TxConfig, RTL8139State),
3282 VMSTATE_UINT32(RxConfig, RTL8139State),
3283 VMSTATE_UINT32(RxMissed, RTL8139State),
3284 VMSTATE_UINT16(CSCR, RTL8139State),
3285
3286 VMSTATE_UINT8(Cfg9346, RTL8139State),
3287 VMSTATE_UINT8(Config0, RTL8139State),
3288 VMSTATE_UINT8(Config1, RTL8139State),
3289 VMSTATE_UINT8(Config3, RTL8139State),
3290 VMSTATE_UINT8(Config4, RTL8139State),
3291 VMSTATE_UINT8(Config5, RTL8139State),
3292
3293 VMSTATE_UINT8(clock_enabled, RTL8139State),
3294 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3295
3296 VMSTATE_UINT16(MultiIntr, RTL8139State),
3297
3298 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3299 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3300 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3301 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3302 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3303
3304 VMSTATE_UINT16(CpCmd, RTL8139State),
3305 VMSTATE_UINT8(TxThresh, RTL8139State),
3306
3307 VMSTATE_UNUSED(4),
3308 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3309 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3310
3311 VMSTATE_UINT32(currTxDesc, RTL8139State),
3312 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3313 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3314 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3315 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3316
3317 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3318 VMSTATE_INT32(eeprom.mode, RTL8139State),
3319 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3320 VMSTATE_UINT8(eeprom.address, RTL8139State),
3321 VMSTATE_UINT16(eeprom.input, RTL8139State),
3322 VMSTATE_UINT16(eeprom.output, RTL8139State),
3323
3324 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3325 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3326 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3327 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3328
3329 VMSTATE_UINT32(TCTR, RTL8139State),
3330 VMSTATE_UINT32(TimerInt, RTL8139State),
3331 VMSTATE_INT64(TCTR_base, RTL8139State),
3332
3333 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3334 vmstate_tally_counters, RTL8139TallyCounters),
3335
3336 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3337 VMSTATE_END_OF_LIST()
c574ba5a 3338 },
5cd8cada
JQ		 3339 .subsections = (const VMStateDescription*[]) {
3340 &vmstate_rtl8139_hotplug_ready,
3341 NULL
060110c3
JQ		 3342 }
3343};
3344
a41b2ff2
PB		 3345/***********************************************************/
3346/* PCI RTL8139 definitions */
3347
1bebb0ad
AG		 3348static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3349 uint64_t val, unsigned size)
3350{
3351 switch (size) {
3352 case 1:
3353 rtl8139_io_writeb(opaque, addr, val);
3354 break;
3355 case 2:
3356 rtl8139_io_writew(opaque, addr, val);
3357 break;
3358 case 4:
3359 rtl8139_io_writel(opaque, addr, val);
3360 break;
3361 }
3362}
3363
3364static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3365 unsigned size)
3366{
3367 switch (size) {
3368 case 1:
3369 return rtl8139_io_readb(opaque, addr);
3370 case 2:
3371 return rtl8139_io_readw(opaque, addr);
3372 case 4:
3373 return rtl8139_io_readl(opaque, addr);
3374 }
3375
3376 return -1;
3377}
a41b2ff2 3378
bd80f3fc 3379static const MemoryRegionOps rtl8139_io_ops = {
1bebb0ad
AG		 3380 .read = rtl8139_ioport_read,
3381 .write = rtl8139_ioport_write,
3382 .impl = {
3383 .min_access_size = 1,
3384 .max_access_size = 4,
3385 },
bd80f3fc 3386 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3387};
3388
bd80f3fc
AK		 3389static const MemoryRegionOps rtl8139_mmio_ops = {
3390 .old_mmio = {
3391 .read = {
3392 rtl8139_mmio_readb,
3393 rtl8139_mmio_readw,
3394 rtl8139_mmio_readl,
3395 },
3396 .write = {
3397 rtl8139_mmio_writeb,
3398 rtl8139_mmio_writew,
3399 rtl8139_mmio_writel,
3400 },
3401 },
3402 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3403};
3404
6cadb320
FB		 3405static void rtl8139_timer(void *opaque)
3406{
3407 RTL8139State *s = opaque;
3408
6cadb320
FB		 3409 if (!s->clock_enabled)
3410 {
7cdeb319 3411 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3412 return;
3413 }
3414
05447803
FZ		 3415 s->IntrStatus |= PCSTimeout;
3416 rtl8139_update_irq(s);
237c255c 3417 rtl8139_set_next_tctr_time(s);
6cadb320 3418}
6cadb320 3419
f90c2bcd 3420static void pci_rtl8139_uninit(PCIDevice *dev)
254111ec 3421{
39257515 3422 RTL8139State *s = RTL8139(dev);
254111ec 3423
b946a153 3424 if (s->cplus_txbuffer) {
7267c094 3425 g_free(s->cplus_txbuffer);
b946a153
AL		 3426 s->cplus_txbuffer = NULL;
3427 }
bc72ad67
AB		 3428 timer_del(s->timer);
3429 timer_free(s->timer);
948ecf21 3430 qemu_del_nic(s->nic);
b946a153
AL		 3431}
3432
9e12c5af
JW		 3433static void rtl8139_set_link_status(NetClientState *nc)
3434{
cc1f0f45 3435 RTL8139State *s = qemu_get_nic_opaque(nc);
9e12c5af
JW		 3436
3437 if (nc->link_down) {
3438 s->BasicModeStatus &= ~0x04;
3439 } else {
3440 s->BasicModeStatus |= 0x04;
3441 }
3442
3443 s->IntrStatus |= RxUnderrun;
3444 rtl8139_update_irq(s);
3445}
3446
1673ad51 3447static NetClientInfo net_rtl8139_info = {
2be64a68 3448 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1673ad51
MM		 3449 .size = sizeof(NICState),
3450 .can_receive = rtl8139_can_receive,
3451 .receive = rtl8139_receive,
9e12c5af 3452 .link_status_changed = rtl8139_set_link_status,
1673ad51
MM		 3453};
3454
9af21dbe 3455static void pci_rtl8139_realize(PCIDevice *dev, Error **errp)
a41b2ff2 3456{
39257515
PC		 3457 RTL8139State *s = RTL8139(dev);
3458 DeviceState *d = DEVICE(dev);
a41b2ff2 3459 uint8_t *pci_conf;
3b46e624 3460
88a411a8 3461 pci_conf = dev->config;
817e0b6f 3462 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
0b5b3547
MT		 3463 /* TODO: start of capability list, but no capability
3464 * list bit in status register, and offset 0xdc seems unused. */
3465 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3466
eedfac6f
PB		 3467 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s,
3468 "rtl8139", 0x100);
3469 memory_region_init_io(&s->bar_mem, OBJECT(s), &rtl8139_mmio_ops, s,
3470 "rtl8139", 0x100);
88a411a8
AF		 3471 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3472 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
a41b2ff2 3473
254111ec 3474 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3475
7165448a
WD		 3476 /* prepare eeprom */
3477 s->eeprom.contents[0] = 0x8129;
3478#if 1
3479 /* PCI vendor and device ID should be mirrored here */
3480 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3481 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3482#endif
3483 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3484 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3485 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3486
1673ad51 3487 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
39257515 3488 object_get_typename(OBJECT(dev)), d->id, s);
b356f76d 3489 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
6cadb320
FB		 3490
3491 s->cplus_txbuffer = NULL;
3492 s->cplus_txbuffer_len = 0;
3493 s->cplus_txbuffer_offset = 0;
3b46e624 3494
bc72ad67 3495 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
a41b2ff2 3496}
9d07d757 3497
afd7c850
GA		 3498static void rtl8139_instance_init(Object *obj)
3499{
3500 RTL8139State *s = RTL8139(obj);
3501
3502 device_add_bootindex_property(obj, &s->conf.bootindex,
3503 "bootindex", "/ethernet-phy@0",
3504 DEVICE(obj), NULL);
3505}
3506
40021f08
AL		 3507static Property rtl8139_properties[] = {
3508 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3509 DEFINE_PROP_END_OF_LIST(),
3510};
3511
3512static void rtl8139_class_init(ObjectClass *klass, void *data)
3513{
39bffca2 3514 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3515 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3516
9af21dbe 3517 k->realize = pci_rtl8139_realize;
40021f08 3518 k->exit = pci_rtl8139_uninit;
c45e5b5b 3519 k->romfile = "efi-rtl8139.rom";
40021f08
AL		 3520 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3521 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3522 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3523 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 3524 dc->reset = rtl8139_reset;
3525 dc->vmsd = &vmstate_rtl8139;
3526 dc->props = rtl8139_properties;
125ee0ed 3527 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
40021f08
AL		 3528}
3529
8c43a6f0 3530static const TypeInfo rtl8139_info = {
39257515 3531 .name = TYPE_RTL8139,
39bffca2
AL		 3532 .parent = TYPE_PCI_DEVICE,
3533 .instance_size = sizeof(RTL8139State),
3534 .class_init = rtl8139_class_init,
afd7c850 3535 .instance_init = rtl8139_instance_init,
0aab0d3a
GH		 3536};
3537
83f7d43a 3538static void rtl8139_register_types(void)
9d07d757 3539{
39bffca2 3540 type_register_static(&rtl8139_info);
9d07d757
PB		 3541}
3542
83f7d43a 3543type_init(rtl8139_register_types)
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