[mirror_qemu.git] / hw / net / xilinx_ethlite.c

/*
 * QEMU model of the Xilinx Ethernet Lite MAC.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "qom/object.h"
#include "cpu.h" /* FIXME should not use tswap* */
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "net/net.h"

#define D(x)
#define R_TX_BUF0     0
#define R_TX_LEN0     (0x07f4 / 4)
#define R_TX_GIE0     (0x07f8 / 4)
#define R_TX_CTRL0    (0x07fc / 4)
#define R_TX_BUF1     (0x0800 / 4)
#define R_TX_LEN1     (0x0ff4 / 4)
#define R_TX_CTRL1    (0x0ffc / 4)

#define R_RX_BUF0     (0x1000 / 4)
#define R_RX_CTRL0    (0x17fc / 4)
#define R_RX_BUF1     (0x1800 / 4)
#define R_RX_CTRL1    (0x1ffc / 4)
#define R_MAX         (0x2000 / 4)

#define GIE_GIE    0x80000000

#define CTRL_I     0x8
#define CTRL_P     0x2
#define CTRL_S     0x1

#define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
DECLARE_INSTANCE_CHECKER(struct xlx_ethlite, XILINX_ETHLITE,
                         TYPE_XILINX_ETHLITE)

struct xlx_ethlite
{
    SysBusDevice parent_obj;

    MemoryRegion mmio;
    qemu_irq irq;
    NICState *nic;
    NICConf conf;

    uint32_t c_tx_pingpong;
    uint32_t c_rx_pingpong;
    unsigned int txbuf;
    unsigned int rxbuf;

    uint32_t regs[R_MAX];
};

static inline void eth_pulse_irq(struct xlx_ethlite *s)
{
    /* Only the first gie reg is active.  */
    if (s->regs[R_TX_GIE0] & GIE_GIE) {
        qemu_irq_pulse(s->irq);
    }
}

static uint64_t
eth_read(void *opaque, hwaddr addr, unsigned int size)
{
    struct xlx_ethlite *s = opaque;
    uint32_t r = 0;

    addr >>= 2;

    switch (addr)
    {
        case R_TX_GIE0:
        case R_TX_LEN0:
        case R_TX_LEN1:
        case R_TX_CTRL1:
        case R_TX_CTRL0:
        case R_RX_CTRL1:
        case R_RX_CTRL0:
            r = s->regs[addr];
            D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr * 4, r));
            break;

        default:
            r = tswap32(s->regs[addr]);
            break;
    }
    return r;
}

static void
eth_write(void *opaque, hwaddr addr,
          uint64_t val64, unsigned int size)
{
    struct xlx_ethlite *s = opaque;
    unsigned int base = 0;
    uint32_t value = val64;

    addr >>= 2;
    switch (addr) 
    {
        case R_TX_CTRL0:
        case R_TX_CTRL1:
            if (addr == R_TX_CTRL1)
                base = 0x800 / 4;

            D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
                       __func__, addr * 4, value));
            if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
                qemu_send_packet(qemu_get_queue(s->nic),
                                 (void *) &s->regs[base],
                                 s->regs[base + R_TX_LEN0]);
                D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
                if (s->regs[base + R_TX_CTRL0] & CTRL_I)
                    eth_pulse_irq(s);
            } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
                memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
                if (s->regs[base + R_TX_CTRL0] & CTRL_I)
                    eth_pulse_irq(s);
            }

            /* We are fast and get ready pretty much immediately so
               we actually never flip the S nor P bits to one.  */
            s->regs[addr] = value & ~(CTRL_P | CTRL_S);
            break;

        /* Keep these native.  */
        case R_RX_CTRL0:
        case R_RX_CTRL1:
            if (!(value & CTRL_S)) {
                qemu_flush_queued_packets(qemu_get_queue(s->nic));
            }
            /* fall through */
        case R_TX_LEN0:
        case R_TX_LEN1:
        case R_TX_GIE0:
            D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
                       __func__, addr * 4, value));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = tswap32(value);
            break;
    }
}

static const MemoryRegionOps eth_ops = {
    .read = eth_read,
    .write = eth_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static bool eth_can_rx(NetClientState *nc)
{
    struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
    unsigned int rxbase = s->rxbuf * (0x800 / 4);

    return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
}

static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
{
    struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
    unsigned int rxbase = s->rxbuf * (0x800 / 4);

    /* DA filter.  */
    if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
        return size;

    if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
        D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
        return -1;
    }

    D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase));
    if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) {
        D(qemu_log("ethlite packet is too big, size=%x\n", size));
        return -1;
    }
    memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);

    s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
    if (s->regs[R_RX_CTRL0] & CTRL_I) {
        eth_pulse_irq(s);
    }

    /* If c_rx_pingpong was set flip buffers.  */
    s->rxbuf ^= s->c_rx_pingpong;
    return size;
}

static void xilinx_ethlite_reset(DeviceState *dev)
{
    struct xlx_ethlite *s = XILINX_ETHLITE(dev);

    s->rxbuf = 0;
}

static NetClientInfo net_xilinx_ethlite_info = {
    .type = NET_CLIENT_DRIVER_NIC,
    .size = sizeof(NICState),
    .can_receive = eth_can_rx,
    .receive = eth_rx,
};

static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
{
    struct xlx_ethlite *s = XILINX_ETHLITE(dev);

    qemu_macaddr_default_if_unset(&s->conf.macaddr);
    s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
                          object_get_typename(OBJECT(dev)), dev->id, s);
    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
}

static void xilinx_ethlite_init(Object *obj)
{
    struct xlx_ethlite *s = XILINX_ETHLITE(obj);

    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

    memory_region_init_io(&s->mmio, obj, &eth_ops, s,
                          "xlnx.xps-ethernetlite", R_MAX * 4);
    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}

static Property xilinx_ethlite_properties[] = {
    DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
    DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
    DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = xilinx_ethlite_realize;
    dc->reset = xilinx_ethlite_reset;
    device_class_set_props(dc, xilinx_ethlite_properties);
}

static const TypeInfo xilinx_ethlite_info = {
    .name          = TYPE_XILINX_ETHLITE,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(struct xlx_ethlite),
    .instance_init = xilinx_ethlite_init,
    .class_init    = xilinx_ethlite_class_init,
};

static void xilinx_ethlite_register_types(void)
{
    type_register_static(&xilinx_ethlite_info);
}

type_init(xilinx_ethlite_register_types)
Commit	Line	Data
b43848a1 EI	1	/*
	2	* QEMU model of the Xilinx Ethernet Lite MAC.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
e8d40465	25	#include "qemu/osdep.h"
0b8fa32f	26	#include "qemu/module.h"
db1015e9	27	#include "qom/object.h"
4771d756	28	#include "cpu.h" /* FIXME should not use tswap* */
83c9f4ca	29	#include "hw/sysbus.h"
64552b6b	30	#include "hw/irq.h"
a27bd6c7	31	#include "hw/qdev-properties.h"
1422e32d	32	#include "net/net.h"
b43848a1 EI	33
	34	#define D(x)
	35	#define R_TX_BUF0 0
	36	#define R_TX_LEN0 (0x07f4 / 4)
	37	#define R_TX_GIE0 (0x07f8 / 4)
	38	#define R_TX_CTRL0 (0x07fc / 4)
	39	#define R_TX_BUF1 (0x0800 / 4)
	40	#define R_TX_LEN1 (0x0ff4 / 4)
	41	#define R_TX_CTRL1 (0x0ffc / 4)
	42
	43	#define R_RX_BUF0 (0x1000 / 4)
	44	#define R_RX_CTRL0 (0x17fc / 4)
	45	#define R_RX_BUF1 (0x1800 / 4)
	46	#define R_RX_CTRL1 (0x1ffc / 4)
	47	#define R_MAX (0x2000 / 4)
	48
	49	#define GIE_GIE 0x80000000
	50
	51	#define CTRL_I 0x8
	52	#define CTRL_P 0x2
	53	#define CTRL_S 0x1
	54
91a28042	55	#define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
8110fa1d EH	56	DECLARE_INSTANCE_CHECKER(struct xlx_ethlite, XILINX_ETHLITE,
8110fa1d EH	57	TYPE_XILINX_ETHLITE)
91a28042	58
b43848a1 EI	59	struct xlx_ethlite
b43848a1 EI	60	{
91a28042 AF	61	SysBusDevice parent_obj;
91a28042 AF	62
010f3f5f	63	MemoryRegion mmio;
b43848a1	64	qemu_irq irq;
d7539ab4	65	NICState *nic;
17d1ae3c	66	NICConf conf;
b43848a1	67
ee6847d1 GH	68	uint32_t c_tx_pingpong;
ee6847d1 GH	69	uint32_t c_rx_pingpong;
b43848a1 EI	70	unsigned int txbuf;
	71	unsigned int rxbuf;
	72
b43848a1 EI	73	uint32_t regs[R_MAX];
	74	};
	75
	76	static inline void eth_pulse_irq(struct xlx_ethlite *s)
	77	{
	78	/* Only the first gie reg is active. */
	79	if (s->regs[R_TX_GIE0] & GIE_GIE) {
	80	qemu_irq_pulse(s->irq);
	81	}
	82	}
	83
010f3f5f	84	static uint64_t
a8170e5e	85	eth_read(void *opaque, hwaddr addr, unsigned int size)
b43848a1 EI	86	{
	87	struct xlx_ethlite *s = opaque;
	88	uint32_t r = 0;
	89
	90	addr >>= 2;
	91
	92	switch (addr)
	93	{
	94	case R_TX_GIE0:
	95	case R_TX_LEN0:
	96	case R_TX_LEN1:
	97	case R_TX_CTRL1:
	98	case R_TX_CTRL0:
	99	case R_RX_CTRL1:
	100	case R_RX_CTRL0:
	101	r = s->regs[addr];
883f2c59	102	D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr * 4, r));
b43848a1 EI	103	break;
b43848a1 EI	104
b43848a1	105	default:
d48751ed	106	r = tswap32(s->regs[addr]);
b43848a1 EI	107	break;
	108	}
	109	return r;
	110	}
	111
	112	static void
a8170e5e	113	eth_write(void *opaque, hwaddr addr,
010f3f5f	114	uint64_t val64, unsigned int size)
b43848a1 EI	115	{
	116	struct xlx_ethlite *s = opaque;
	117	unsigned int base = 0;
010f3f5f	118	uint32_t value = val64;
b43848a1 EI	119
	120	addr >>= 2;
	121	switch (addr)
	122	{
	123	case R_TX_CTRL0:
	124	case R_TX_CTRL1:
	125	if (addr == R_TX_CTRL1)
	126	base = 0x800 / 4;
	127
883f2c59	128	D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
6034fe7b	129	__func__, addr * 4, value));
b43848a1	130	if ((value & (CTRL_P \| CTRL_S)) == CTRL_S) {
b356f76d	131	qemu_send_packet(qemu_get_queue(s->nic),
b43848a1 EI	132	(void *) &s->regs[base],
	133	s->regs[base + R_TX_LEN0]);
	134	D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
	135	if (s->regs[base + R_TX_CTRL0] & CTRL_I)
	136	eth_pulse_irq(s);
	137	} else if ((value & (CTRL_P \| CTRL_S)) == (CTRL_P \| CTRL_S)) {
17d1ae3c	138	memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
b43848a1 EI	139	if (s->regs[base + R_TX_CTRL0] & CTRL_I)
	140	eth_pulse_irq(s);
	141	}
	142
	143	/* We are fast and get ready pretty much immediately so
	144	we actually never flip the S nor P bits to one. */
	145	s->regs[addr] = value & ~(CTRL_P \| CTRL_S);
	146	break;
	147
	148	/* Keep these native. */
2f991adb PC	149	case R_RX_CTRL0:
	150	case R_RX_CTRL1:
	151	if (!(value & CTRL_S)) {
b356f76d	152	qemu_flush_queued_packets(qemu_get_queue(s->nic));
2f991adb	153	}
31da45ce	154	/* fall through */
b43848a1 EI	155	case R_TX_LEN0:
	156	case R_TX_LEN1:
	157	case R_TX_GIE0:
883f2c59	158	D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
6034fe7b	159	__func__, addr * 4, value));
b43848a1 EI	160	s->regs[addr] = value;
	161	break;
	162
b43848a1	163	default:
d48751ed	164	s->regs[addr] = tswap32(value);
b43848a1 EI	165	break;
	166	}
	167	}
	168
010f3f5f EI	169	static const MemoryRegionOps eth_ops = {
	170	.read = eth_read,
	171	.write = eth_write,
	172	.endianness = DEVICE_NATIVE_ENDIAN,
	173	.valid = {
	174	.min_access_size = 4,
	175	.max_access_size = 4
	176	}
b43848a1 EI	177	};
b43848a1 EI	178
b8c4b67e	179	static bool eth_can_rx(NetClientState *nc)
b43848a1	180	{
cc1f0f45	181	struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
808fb9f2 PC	182	unsigned int rxbase = s->rxbuf * (0x800 / 4);
	183
	184	return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
b43848a1 EI	185	}
b43848a1 EI	186
4e68f7a0	187	static ssize_t eth_rx(NetClientState nc, const uint8_t buf, size_t size)
b43848a1	188	{
cc1f0f45	189	struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
b43848a1	190	unsigned int rxbase = s->rxbuf * (0x800 / 4);
b43848a1 EI	191
b43848a1 EI	192	/* DA filter. */
17d1ae3c	193	if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
df12c1f5	194	return size;
b43848a1 EI	195
	196	if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
	197	D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
df12c1f5	198	return -1;
b43848a1 EI	199	}
b43848a1 EI	200
6034fe7b	201	D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase));
a0d1cbda	202	if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) {
	203	D(qemu_log("ethlite packet is too big, size=%x\n", size));
	204	return -1;
	205	}
b43848a1 EI	206	memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
b43848a1 EI	207
b43848a1	208	s->regs[rxbase + R_RX_CTRL0] \|= CTRL_S;
40e76f73	209	if (s->regs[R_RX_CTRL0] & CTRL_I) {
b43848a1	210	eth_pulse_irq(s);
40e76f73	211	}
b43848a1 EI	212
	213	/* If c_rx_pingpong was set flip buffers. */
	214	s->rxbuf ^= s->c_rx_pingpong;
df12c1f5	215	return size;
b43848a1 EI	216	}
b43848a1 EI	217
8c6d9672 PC	218	static void xilinx_ethlite_reset(DeviceState *dev)
	219	{
	220	struct xlx_ethlite *s = XILINX_ETHLITE(dev);
	221
	222	s->rxbuf = 0;
	223	}
	224
d7539ab4	225	static NetClientInfo net_xilinx_ethlite_info = {
f394b2e2	226	.type = NET_CLIENT_DRIVER_NIC,
d7539ab4 MM	227	.size = sizeof(NICState),
	228	.can_receive = eth_can_rx,
	229	.receive = eth_rx,
d7539ab4 MM	230	};
d7539ab4 MM	231
e8198f6e	232	static void xilinx_ethlite_realize(DeviceState dev, Error *errp)
b43848a1	233	{
91a28042	234	struct xlx_ethlite *s = XILINX_ETHLITE(dev);
b43848a1	235
17d1ae3c	236	qemu_macaddr_default_if_unset(&s->conf.macaddr);
d7539ab4	237	s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
91a28042	238	object_get_typename(OBJECT(dev)), dev->id, s);
b356f76d	239	qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
e8198f6e PC	240	}
	241
	242	static void xilinx_ethlite_init(Object *obj)
	243	{
	244	struct xlx_ethlite *s = XILINX_ETHLITE(obj);
	245
	246	sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
	247
	248	memory_region_init_io(&s->mmio, obj, &eth_ops, s,
	249	"xlnx.xps-ethernetlite", R_MAX * 4);
	250	sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
b43848a1 EI	251	}
b43848a1 EI	252
999e12bb	253	static Property xilinx_ethlite_properties[] = {
b2d85c34 PC	254	DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
b2d85c34 PC	255	DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
999e12bb AL	256	DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
	257	DEFINE_PROP_END_OF_LIST(),
	258	};
	259
	260	static void xilinx_ethlite_class_init(ObjectClass klass, void data)
	261	{
39bffca2	262	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	263
e8198f6e	264	dc->realize = xilinx_ethlite_realize;
8c6d9672	265	dc->reset = xilinx_ethlite_reset;
4f67d30b	266	device_class_set_props(dc, xilinx_ethlite_properties);
999e12bb AL	267	}
999e12bb AL	268
8c43a6f0	269	static const TypeInfo xilinx_ethlite_info = {
91a28042	270	.name = TYPE_XILINX_ETHLITE,
39bffca2 AL	271	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	272	.instance_size = sizeof(struct xlx_ethlite),
e8198f6e	273	.instance_init = xilinx_ethlite_init,
39bffca2	274	.class_init = xilinx_ethlite_class_init,
ee6847d1 GH	275	};
ee6847d1 GH	276
83f7d43a	277	static void xilinx_ethlite_register_types(void)
b43848a1	278	{
39bffca2	279	type_register_static(&xilinx_ethlite_info);
b43848a1 EI	280	}
b43848a1 EI	281
83f7d43a	282	type_init(xilinx_ethlite_register_types)