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b7862564 MV |
1 | /* |
2 | * Altera 10M50 Nios2 GHRD | |
3 | * | |
4 | * Copyright (c) 2016 Marek Vasut <marek.vasut@gmail.com> | |
5 | * | |
6 | * Based on LabX device code | |
7 | * | |
8 | * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com> | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2.1 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, see | |
22 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
23 | */ | |
24 | ||
25 | #include "qemu/osdep.h" | |
26 | #include "qapi/error.h" | |
b7862564 MV |
27 | #include "cpu.h" |
28 | ||
29 | #include "hw/sysbus.h" | |
b7862564 | 30 | #include "hw/char/serial.h" |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
b7862564 MV |
32 | #include "sysemu/sysemu.h" |
33 | #include "hw/boards.h" | |
34 | #include "exec/memory.h" | |
35 | #include "exec/address-spaces.h" | |
36 | #include "qemu/config-file.h" | |
37 | ||
38 | #include "boot.h" | |
39 | ||
40 | #define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb" | |
41 | ||
42 | static void nios2_10m50_ghrd_init(MachineState *machine) | |
43 | { | |
44 | Nios2CPU *cpu; | |
45 | DeviceState *dev; | |
46 | MemoryRegion *address_space_mem = get_system_memory(); | |
47 | MemoryRegion *phys_tcm = g_new(MemoryRegion, 1); | |
48 | MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1); | |
49 | MemoryRegion *phys_ram = g_new(MemoryRegion, 1); | |
50 | MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1); | |
51 | ram_addr_t tcm_base = 0x0; | |
52 | ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ | |
53 | ram_addr_t ram_base = 0x08000000; | |
54 | ram_addr_t ram_size = 0x08000000; | |
cd2528de | 55 | qemu_irq irq[32]; |
b7862564 MV |
56 | int i; |
57 | ||
58 | /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ | |
98a99ce0 PM |
59 | memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size, |
60 | &error_abort); | |
b7862564 MV |
61 | memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias", |
62 | phys_tcm, 0, tcm_size); | |
b7862564 MV |
63 | memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm); |
64 | memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base, | |
65 | phys_tcm_alias); | |
66 | ||
67 | /* Physical DRAM with alias at 0xc0000000 */ | |
98a99ce0 PM |
68 | memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size, |
69 | &error_abort); | |
b7862564 MV |
70 | memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias", |
71 | phys_ram, 0, ram_size); | |
b7862564 MV |
72 | memory_region_add_subregion(address_space_mem, ram_base, phys_ram); |
73 | memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, | |
74 | phys_ram_alias); | |
75 | ||
76 | /* Create CPU -- FIXME */ | |
253a5504 | 77 | cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); |
b7862564 | 78 | for (i = 0; i < 32; i++) { |
cd2528de | 79 | irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); |
b7862564 MV |
80 | } |
81 | ||
82 | /* Register: Altera 16550 UART */ | |
83 | serial_mm_init(address_space_mem, 0xf8001600, 2, irq[1], 115200, | |
9bca0edb | 84 | serial_hd(0), DEVICE_NATIVE_ENDIAN); |
b7862564 MV |
85 | |
86 | /* Register: Timer sys_clk_timer */ | |
3e80f690 | 87 | dev = qdev_new("ALTR.timer"); |
b7862564 | 88 | qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000); |
3c6ef471 | 89 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
b7862564 MV |
90 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xf8001440); |
91 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[0]); | |
92 | ||
93 | /* Register: Timer sys_clk_timer_1 */ | |
3e80f690 | 94 | dev = qdev_new("ALTR.timer"); |
b7862564 | 95 | qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000); |
3c6ef471 | 96 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
b7862564 MV |
97 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880); |
98 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]); | |
99 | ||
100 | /* Configure new exception vectors and reset CPU for it to take effect. */ | |
101 | cpu->reset_addr = 0xd4000000; | |
102 | cpu->exception_addr = 0xc8000120; | |
103 | cpu->fast_tlb_miss_addr = 0xc0000100; | |
104 | ||
105 | nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename, | |
106 | BINARY_DEVICE_TREE_FILE, NULL); | |
107 | } | |
108 | ||
109 | static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc) | |
110 | { | |
111 | mc->desc = "Altera 10M50 GHRD Nios II design"; | |
112 | mc->init = nios2_10m50_ghrd_init; | |
ea0ac7f6 | 113 | mc->is_default = true; |
b7862564 MV |
114 | } |
115 | ||
116 | DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init); |