]> git.proxmox.com Git - mirror_qemu.git/blame - hw/nseries.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
onenand: Pass BlockDriverState to init function
[mirror_qemu.git] / hw / nseries.c
CommitLineData
7e7c5e4c
AZ		 1/*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 19 */
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "omap.h"
24#include "arm-misc.h"
25#include "irq.h"
26#include "console.h"
27#include "boards.h"
28#include "i2c.h"
29#include "devices.h"
30#include "flash.h"
31#include "hw.h"
1ae26a18 32#include "bt.h"
ca20cf32 33#include "loader.h"
af5a75f4 34#include "blockdev.h"
7e7c5e4c
AZ		 35
36/* Nokia N8x0 support */
37struct n800_s {
38 struct omap_mpu_state_s *cpu;
39
40 struct rfbi_chip_s blizzard;
e927bb00
AZ		 41 struct {
42 void *opaque;
43 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
bc24a225 44 uWireSlave *chip;
e927bb00 45 } ts;
7e7c5e4c
AZ		 46 i2c_bus *i2c;
47
48 int keymap[0x80];
c4f05c8c 49 DeviceState *kbd;
7e7c5e4c 50
bc24a225 51 TUSBState *usb;
7e7c5e4c
AZ		 52 void *retu;
53 void *tahvo;
c580d92b 54 void *nand;
7e7c5e4c
AZ		 55};
56
57/* GPIO pins */
e927bb00 58#define N8X0_TUSB_ENABLE_GPIO 0
7e7c5e4c
AZ		 59#define N800_MMC2_WP_GPIO 8
60#define N800_UNKNOWN_GPIO0 9 /* out */
0941041e 61#define N810_MMC2_VIOSD_GPIO 9
99570a40 62#define N810_HEADSET_AMP_GPIO 10
7e7c5e4c 63#define N800_CAM_TURN_GPIO 12
e927bb00 64#define N810_GPS_RESET_GPIO 12
7e7c5e4c
AZ		 65#define N800_BLIZZARD_POWERDOWN_GPIO 15
66#define N800_MMC1_WP_GPIO 23
0941041e 67#define N810_MMC2_VSD_GPIO 23
7e7c5e4c 68#define N8X0_ONENAND_GPIO 26
e927bb00 69#define N810_BLIZZARD_RESET_GPIO 30
7e7c5e4c
AZ		 70#define N800_UNKNOWN_GPIO2 53 /* out */
71#define N8X0_TUSB_INT_GPIO 58
e927bb00
AZ		 72#define N8X0_BT_WKUP_GPIO 61
73#define N8X0_STI_GPIO 62
7e7c5e4c 74#define N8X0_CBUS_SEL_GPIO 64
e927bb00
AZ		 75#define N8X0_CBUS_DAT_GPIO 65
76#define N8X0_CBUS_CLK_GPIO 66
77#define N8X0_WLAN_IRQ_GPIO 87
78#define N8X0_BT_RESET_GPIO 92
79#define N8X0_TEA5761_CS_GPIO 93
7e7c5e4c 80#define N800_UNKNOWN_GPIO 94
e927bb00 81#define N810_TSC_RESET_GPIO 94
7e7c5e4c 82#define N800_CAM_ACT_GPIO 95
e927bb00
AZ		 83#define N810_GPS_WAKEUP_GPIO 95
84#define N8X0_MMC_CS_GPIO 96
85#define N8X0_WLAN_PWR_GPIO 97
7e7c5e4c 86#define N8X0_BT_HOST_WKUP_GPIO 98
99570a40 87#define N810_SPEAKER_AMP_GPIO 101
7e7c5e4c
AZ		 88#define N810_KB_LOCK_GPIO 102
89#define N800_TSC_TS_GPIO 103
e927bb00
AZ		 90#define N810_TSC_TS_GPIO 106
91#define N8X0_HEADPHONE_GPIO 107
7e7c5e4c
AZ		 92#define N8X0_RETU_GPIO 108
93#define N800_TSC_KP_IRQ_GPIO 109
94#define N810_KEYBOARD_GPIO 109
95#define N800_BAT_COVER_GPIO 110
96#define N810_SLIDE_GPIO 110
97#define N8X0_TAHVO_GPIO 111
98#define N800_UNKNOWN_GPIO4 112 /* out */
e927bb00 99#define N810_SLEEPX_LED_GPIO 112
1d4e547b 100#define N800_TSC_RESET_GPIO 118 /* ? */
99570a40 101#define N810_AIC33_RESET_GPIO 118
1d4e547b 102#define N800_TSC_UNKNOWN_GPIO 119 /* out */
7e7c5e4c
AZ		 103#define N8X0_TMP105_GPIO 125
104
105/* Config */
c580d92b 106#define BT_UART 0
7e7c5e4c
AZ		 107#define XLDR_LL_UART 1
108
1d4e547b
AZ		 109/* Addresses on the I2C bus 0 */
110#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
111#define N8X0_TCM825x_ADDR 0x29 /* Camera */
112#define N810_LP5521_ADDR 0x32 /* LEDs */
113#define N810_TSL2563_ADDR 0x3d /* Light sensor */
114#define N810_LM8323_ADDR 0x45 /* Keyboard */
115/* Addresses on the I2C bus 1 */
116#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
117#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
7e7c5e4c
AZ		 118
119/* Chipselects on GPMC NOR interface */
120#define N8X0_ONENAND_CS 0
121#define N8X0_USB_ASYNC_CS 1
122#define N8X0_USB_SYNC_CS 4
123
c580d92b
AZ		 124#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
125
7e7c5e4c
AZ		 126static void n800_mmc_cs_cb(void *opaque, int line, int level)
127{
128 /* TODO: this seems to actually be connected to the menelaus, to
129 * which also both MMC slots connect. */
130 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
131
132 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
133}
134
e927bb00 135static void n8x0_gpio_setup(struct n800_s *s)
7e7c5e4c
AZ		 136{
137 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
77831c20 138 qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
7e7c5e4c 139
77831c20 140 qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO));
7e7c5e4c
AZ		 141}
142
c580d92b
AZ		 143#define MAEMO_CAL_HEADER(...) \
144 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
145 __VA_ARGS__, \
146 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
147
148static const uint8_t n8x0_cal_wlan_mac[] = {
149 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
150 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
151 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
153 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
154 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
155};
156
157static const uint8_t n8x0_cal_bt_id[] = {
158 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
159 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
160 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
161 N8X0_BD_ADDR,
162};
163
7e7c5e4c
AZ		 164static void n8x0_nand_setup(struct n800_s *s)
165{
c580d92b 166 char *otp_region;
af5a75f4 167 DriveInfo *dinfo;
c580d92b 168
af5a75f4 169 dinfo = drive_get(IF_MTD, 0, 0);
7e7c5e4c 170 /* Either ec40xx or ec48xx are OK for the ID */
af5a75f4
PM		 171 s->nand = onenand_init(dinfo ? dinfo->bdrv : 0, 0xec4800, 1,
172 qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
7e7c5e4c 173 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
af5a75f4 174 onenand_base_unmap, s->nand);
c580d92b
AZ		 175 otp_region = onenand_raw_otp(s->nand);
176
177 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
178 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
179 /* XXX: in theory should also update the OOB for both pages */
7e7c5e4c
AZ		 180}
181
e927bb00 182static void n8x0_i2c_setup(struct n800_s *s)
7e7c5e4c 183{
697454eb 184 DeviceState *dev;
77831c20 185 qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
7e7c5e4c
AZ		 186
187 /* Attach the CPU on one end of our I2C bus. */
188 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
189
190 /* Attach a menelaus PM chip */
d3356811
PB		 191 dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
192 qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
7e7c5e4c
AZ		 193
194 /* Attach a TMP105 PM chip (A0 wired to ground) */
697454eb
PB		 195 dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
196 qdev_connect_gpio_out(dev, 0, tmp_irq);
7e7c5e4c
AZ		 197}
198
199/* Touchscreen and keypad controller */
bc24a225 200static MouseTransformInfo n800_pointercal = {
e927bb00
AZ		 201 .x = 800,
202 .y = 480,
203 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
204};
205
bc24a225 206static MouseTransformInfo n810_pointercal = {
e927bb00
AZ		 207 .x = 800,
208 .y = 480,
209 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
210};
211
7e7c5e4c
AZ		 212#define RETU_KEYCODE 61 /* F3 */
213
214static void n800_key_event(void *opaque, int keycode)
215{
216 struct n800_s *s = (struct n800_s *) opaque;
217 int code = s->keymap[keycode & 0x7f];
218
219 if (code == -1) {
220 if ((keycode & 0x7f) == RETU_KEYCODE)
221 retu_key_event(s->retu, !(keycode & 0x80));
222 return;
223 }
224
e927bb00 225 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
7e7c5e4c
AZ		 226}
227
228static const int n800_keys[16] = {
229 -1,
230 72, /* Up */
231 63, /* Home (F5) */
232 -1,
233 75, /* Left */
234 28, /* Enter */
235 77, /* Right */
236 -1,
1d4e547b 237 1, /* Cycle (ESC) */
7e7c5e4c
AZ		 238 80, /* Down */
239 62, /* Menu (F4) */
240 -1,
241 66, /* Zoom- (F8) */
1d4e547b 242 64, /* FullScreen (F6) */
7e7c5e4c
AZ		 243 65, /* Zoom+ (F7) */
244 -1,
245};
246
e927bb00 247static void n800_tsc_kbd_setup(struct n800_s *s)
7e7c5e4c
AZ		 248{
249 int i;
250
251 /* XXX: are the three pins inverted inside the chip between the
252 * tsc and the cpu (N4111)? */
b9d38e95 253 qemu_irq penirq = NULL; /* NC */
77831c20
JR		 254 qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO);
255 qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO);
7e7c5e4c 256
22d83b14 257 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
e927bb00
AZ		 258 s->ts.opaque = s->ts.chip->opaque;
259 s->ts.txrx = tsc210x_txrx;
7e7c5e4c
AZ		 260
261 for (i = 0; i < 0x80; i ++)
262 s->keymap[i] = -1;
263 for (i = 0; i < 0x10; i ++)
264 if (n800_keys[i] >= 0)
265 s->keymap[n800_keys[i]] = i;
266
267 qemu_add_kbd_event_handler(n800_key_event, s);
268
e927bb00
AZ		 269 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
270}
271
272static void n810_tsc_setup(struct n800_s *s)
273{
77831c20 274 qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO);
e927bb00
AZ		 275
276 s->ts.opaque = tsc2005_init(pintdav);
277 s->ts.txrx = tsc2005_txrx;
278
279 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
7e7c5e4c
AZ		 280}
281
1d4e547b
AZ		 282/* N810 Keyboard controller */
283static void n810_key_event(void *opaque, int keycode)
284{
285 struct n800_s *s = (struct n800_s *) opaque;
286 int code = s->keymap[keycode & 0x7f];
287
288 if (code == -1) {
289 if ((keycode & 0x7f) == RETU_KEYCODE)
290 retu_key_event(s->retu, !(keycode & 0x80));
291 return;
292 }
293
294 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
295}
296
297#define M 0
298
299static int n810_keys[0x80] = {
300 [0x01] = 16, /* Q */
301 [0x02] = 37, /* K */
302 [0x03] = 24, /* O */
303 [0x04] = 25, /* P */
304 [0x05] = 14, /* Backspace */
305 [0x06] = 30, /* A */
306 [0x07] = 31, /* S */
307 [0x08] = 32, /* D */
308 [0x09] = 33, /* F */
309 [0x0a] = 34, /* G */
310 [0x0b] = 35, /* H */
311 [0x0c] = 36, /* J */
312
313 [0x11] = 17, /* W */
314 [0x12] = 62, /* Menu (F4) */
315 [0x13] = 38, /* L */
316 [0x14] = 40, /* ' (Apostrophe) */
317 [0x16] = 44, /* Z */
318 [0x17] = 45, /* X */
319 [0x18] = 46, /* C */
320 [0x19] = 47, /* V */
321 [0x1a] = 48, /* B */
322 [0x1b] = 49, /* N */
323 [0x1c] = 42, /* Shift (Left shift) */
324 [0x1f] = 65, /* Zoom+ (F7) */
325
326 [0x21] = 18, /* E */
327 [0x22] = 39, /* ; (Semicolon) */
328 [0x23] = 12, /* - (Minus) */
329 [0x24] = 13, /* = (Equal) */
330 [0x2b] = 56, /* Fn (Left Alt) */
331 [0x2c] = 50, /* M */
332 [0x2f] = 66, /* Zoom- (F8) */
333
334 [0x31] = 19, /* R */
335 [0x32] = 29 | M, /* Right Ctrl */
336 [0x34] = 57, /* Space */
337 [0x35] = 51, /* , (Comma) */
338 [0x37] = 72 | M, /* Up */
339 [0x3c] = 82 | M, /* Compose (Insert) */
340 [0x3f] = 64, /* FullScreen (F6) */
341
342 [0x41] = 20, /* T */
343 [0x44] = 52, /* . (Dot) */
344 [0x46] = 77 | M, /* Right */
345 [0x4f] = 63, /* Home (F5) */
346 [0x51] = 21, /* Y */
347 [0x53] = 80 | M, /* Down */
348 [0x55] = 28, /* Enter */
349 [0x5f] = 1, /* Cycle (ESC) */
350
351 [0x61] = 22, /* U */
352 [0x64] = 75 | M, /* Left */
353
354 [0x71] = 23, /* I */
355#if 0
356 [0x75] = 28 | M, /* KP Enter (KP Enter) */
357#else
358 [0x75] = 15, /* KP Enter (Tab) */
359#endif
360};
361
362#undef M
363
364static void n810_kbd_setup(struct n800_s *s)
365{
77831c20 366 qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO);
1d4e547b
AZ		 367 int i;
368
369 for (i = 0; i < 0x80; i ++)
370 s->keymap[i] = -1;
371 for (i = 0; i < 0x80; i ++)
372 if (n810_keys[i] > 0)
373 s->keymap[n810_keys[i]] = i;
374
375 qemu_add_kbd_event_handler(n810_key_event, s);
376
377 /* Attach the LM8322 keyboard to the I2C bus,
378 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
c4f05c8c
PM		 379 s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
380 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
1d4e547b
AZ		 381}
382
7e7c5e4c
AZ		 383/* LCD MIPI DBI-C controller (URAL) */
384struct mipid_s {
385 int resp[4];
386 int param[4];
387 int p;
388 int pm;
389 int cmd;
390
391 int sleep;
392 int booster;
393 int te;
394 int selfcheck;
395 int partial;
396 int normal;
397 int vscr;
398 int invert;
399 int onoff;
400 int gamma;
401 uint32_t id;
402};
403
404static void mipid_reset(struct mipid_s *s)
405{
406 if (!s->sleep)
407 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
408
409 s->pm = 0;
410 s->cmd = 0;
411
412 s->sleep = 1;
413 s->booster = 0;
414 s->selfcheck =
415 (1 << 7) | /* Register loading OK. */
416 (1 << 5) | /* The chip is attached. */
417 (1 << 4); /* Display glass still in one piece. */
418 s->te = 0;
419 s->partial = 0;
420 s->normal = 1;
421 s->vscr = 0;
422 s->invert = 0;
423 s->onoff = 1;
424 s->gamma = 0;
425}
426
e927bb00 427static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
7e7c5e4c
AZ		 428{
429 struct mipid_s *s = (struct mipid_s *) opaque;
430 uint8_t ret;
431
e927bb00 432 if (len > 9)
2ac71179 433 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
e927bb00 434
b1503cda 435 if (s->p >= ARRAY_SIZE(s->resp))
7e7c5e4c
AZ		 436 ret = 0;
437 else
438 ret = s->resp[s->p ++];
439 if (s->pm --> 0)
440 s->param[s->pm] = cmd;
441 else
442 s->cmd = cmd;
443
444 switch (s->cmd) {
445 case 0x00: /* NOP */
446 break;
447
448 case 0x01: /* SWRESET */
449 mipid_reset(s);
450 break;
451
452 case 0x02: /* BSTROFF */
453 s->booster = 0;
454 break;
455 case 0x03: /* BSTRON */
456 s->booster = 1;
457 break;
458
459 case 0x04: /* RDDID */
460 s->p = 0;
461 s->resp[0] = (s->id >> 16) & 0xff;
462 s->resp[1] = (s->id >> 8) & 0xff;
463 s->resp[2] = (s->id >> 0) & 0xff;
464 break;
465
466 case 0x06: /* RD_RED */
467 case 0x07: /* RD_GREEN */
468 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
469 * for the bootloader one needs to change this. */
470 case 0x08: /* RD_BLUE */
471 s->p = 0;
472 /* TODO: return first pixel components */
473 s->resp[0] = 0x01;
474 break;
475
476 case 0x09: /* RDDST */
477 s->p = 0;
478 s->resp[0] = s->booster << 7;
479 s->resp[1] = (5 << 4) | (s->partial << 2) |
480 (s->sleep << 1) | s->normal;
481 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
482 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
483 s->resp[3] = s->gamma << 6;
484 break;
485
486 case 0x0a: /* RDDPM */
487 s->p = 0;
488 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
489 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
490 break;
491 case 0x0b: /* RDDMADCTR */
492 s->p = 0;
493 s->resp[0] = 0;
494 break;
495 case 0x0c: /* RDDCOLMOD */
496 s->p = 0;
497 s->resp[0] = 5; /* 65K colours */
498 break;
499 case 0x0d: /* RDDIM */
500 s->p = 0;
501 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
502 break;
503 case 0x0e: /* RDDSM */
504 s->p = 0;
505 s->resp[0] = s->te << 7;
506 break;
507 case 0x0f: /* RDDSDR */
508 s->p = 0;
509 s->resp[0] = s->selfcheck;
510 break;
511
512 case 0x10: /* SLPIN */
513 s->sleep = 1;
514 break;
515 case 0x11: /* SLPOUT */
516 s->sleep = 0;
517 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
518 break;
519
520 case 0x12: /* PTLON */
521 s->partial = 1;
522 s->normal = 0;
523 s->vscr = 0;
524 break;
525 case 0x13: /* NORON */
526 s->partial = 0;
527 s->normal = 1;
528 s->vscr = 0;
529 break;
530
531 case 0x20: /* INVOFF */
532 s->invert = 0;
533 break;
534 case 0x21: /* INVON */
535 s->invert = 1;
536 break;
537
538 case 0x22: /* APOFF */
539 case 0x23: /* APON */
540 goto bad_cmd;
541
542 case 0x25: /* WRCNTR */
543 if (s->pm < 0)
544 s->pm = 1;
545 goto bad_cmd;
546
547 case 0x26: /* GAMSET */
548 if (!s->pm)
549 s->gamma = ffs(s->param[0] & 0xf) - 1;
550 else if (s->pm < 0)
551 s->pm = 1;
552 break;
553
554 case 0x28: /* DISPOFF */
555 s->onoff = 0;
556 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
557 break;
558 case 0x29: /* DISPON */
559 s->onoff = 1;
560 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
561 break;
562
563 case 0x2a: /* CASET */
564 case 0x2b: /* RASET */
565 case 0x2c: /* RAMWR */
566 case 0x2d: /* RGBSET */
567 case 0x2e: /* RAMRD */
568 case 0x30: /* PTLAR */
569 case 0x33: /* SCRLAR */
570 goto bad_cmd;
571
572 case 0x34: /* TEOFF */
573 s->te = 0;
574 break;
575 case 0x35: /* TEON */
576 if (!s->pm)
577 s->te = 1;
578 else if (s->pm < 0)
579 s->pm = 1;
580 break;
581
582 case 0x36: /* MADCTR */
583 goto bad_cmd;
584
585 case 0x37: /* VSCSAD */
586 s->partial = 0;
587 s->normal = 0;
588 s->vscr = 1;
589 break;
590
591 case 0x38: /* IDMOFF */
592 case 0x39: /* IDMON */
593 case 0x3a: /* COLMOD */
594 goto bad_cmd;
595
596 case 0xb0: /* CLKINT / DISCTL */
597 case 0xb1: /* CLKEXT */
598 if (s->pm < 0)
599 s->pm = 2;
600 break;
601
602 case 0xb4: /* FRMSEL */
603 break;
604
605 case 0xb5: /* FRM8SEL */
606 case 0xb6: /* TMPRNG / INIESC */
607 case 0xb7: /* TMPHIS / NOP2 */
608 case 0xb8: /* TMPREAD / MADCTL */
609 case 0xba: /* DISTCTR */
610 case 0xbb: /* EPVOL */
611 goto bad_cmd;
612
613 case 0xbd: /* Unknown */
614 s->p = 0;
615 s->resp[0] = 0;
616 s->resp[1] = 1;
617 break;
618
619 case 0xc2: /* IFMOD */
620 if (s->pm < 0)
621 s->pm = 2;
622 break;
623
624 case 0xc6: /* PWRCTL */
625 case 0xc7: /* PPWRCTL */
626 case 0xd0: /* EPWROUT */
627 case 0xd1: /* EPWRIN */
628 case 0xd4: /* RDEV */
629 case 0xd5: /* RDRR */
630 goto bad_cmd;
631
632 case 0xda: /* RDID1 */
633 s->p = 0;
634 s->resp[0] = (s->id >> 16) & 0xff;
635 break;
636 case 0xdb: /* RDID2 */
637 s->p = 0;
638 s->resp[0] = (s->id >> 8) & 0xff;
639 break;
640 case 0xdc: /* RDID3 */
641 s->p = 0;
642 s->resp[0] = (s->id >> 0) & 0xff;
643 break;
644
645 default:
646 bad_cmd:
647 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
648 break;
649 }
650
651 return ret;
652}
653
654static void *mipid_init(void)
655{
656 struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s));
657
658 s->id = 0x838f03;
659 mipid_reset(s);
660
661 return s;
662}
663
e927bb00 664static void n8x0_spi_setup(struct n800_s *s)
7e7c5e4c 665{
e927bb00 666 void *tsc = s->ts.opaque;
7e7c5e4c
AZ		 667 void *mipid = mipid_init();
668
e927bb00 669 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
7e7c5e4c
AZ		 670 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
671}
672
673/* This task is normally performed by the bootloader. If we're loading
674 * a kernel directly, we need to enable the Blizzard ourselves. */
675static void n800_dss_init(struct rfbi_chip_s *chip)
676{
677 uint8_t *fb_blank;
678
679 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
680 chip->write(chip->opaque, 1, 0x64);
681 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
682 chip->write(chip->opaque, 1, 0x1e);
683 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
684 chip->write(chip->opaque, 1, 0xe0);
685 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
686 chip->write(chip->opaque, 1, 0x01);
687 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
688 chip->write(chip->opaque, 1, 0x06);
689 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
690 chip->write(chip->opaque, 1, 1); /* Enable bit */
691
692 chip->write(chip->opaque, 0, 0x6c);
693 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
694 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
695 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
696 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
697 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
698 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
699 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
700 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
701 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
702 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
703 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
704 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
705 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
706 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
707 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
708 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
709 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
710 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
711
712 fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
713 /* Display Memory Data Port */
714 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
6f0953b1 715 qemu_free(fb_blank);
7e7c5e4c
AZ		 716}
717
3023f332 718static void n8x0_dss_setup(struct n800_s *s)
7e7c5e4c 719{
b9d38e95 720 s->blizzard.opaque = s1d13745_init(NULL);
7e7c5e4c
AZ		 721 s->blizzard.block = s1d13745_write_block;
722 s->blizzard.write = s1d13745_write;
723 s->blizzard.read = s1d13745_read;
724
725 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
726}
727
e927bb00 728static void n8x0_cbus_setup(struct n800_s *s)
7e7c5e4c 729{
77831c20
JR		 730 qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO);
731 qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO);
732 qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO);
7e7c5e4c 733
bc24a225 734 CBus *cbus = cbus_init(dat_out);
7e7c5e4c 735
77831c20
JR		 736 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
737 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
738 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
7e7c5e4c
AZ		 739
740 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
741 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
742}
743
58a26b47
AZ		 744static void n8x0_uart_setup(struct n800_s *s)
745{
746 CharDriverState *radio = uart_hci_init(
77831c20 747 qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
58a26b47 748
77831c20 749 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO,
58a26b47 750 csrhci_pins_get(radio)[csrhci_pin_reset]);
77831c20 751 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO,
58a26b47
AZ		 752 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
753
754 omap_uart_attach(s->cpu->uart[BT_UART], radio);
755}
756
e927bb00 757static void n8x0_usb_power_cb(void *opaque, int line, int level)
942ac052
AZ		 758{
759 struct n800_s *s = opaque;
760
761 tusb6010_power(s->usb, level);
762}
763
e927bb00 764static void n8x0_usb_setup(struct n800_s *s)
942ac052 765{
77831c20 766 qemu_irq tusb_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO);
e927bb00 767 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
bc24a225 768 TUSBState *tusb = tusb6010_init(tusb_irq);
942ac052
AZ		 769
770 /* Using the NOR interface */
771 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
b9d38e95 772 tusb6010_async_io(tusb), NULL, NULL, tusb);
942ac052 773 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
b9d38e95 774 tusb6010_sync_io(tusb), NULL, NULL, tusb);
942ac052
AZ		 775
776 s->usb = tusb;
77831c20 777 qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
942ac052
AZ		 778}
779
d238db7f
AZ		 780/* Setup done before the main bootloader starts by some early setup code
781 * - used when we want to run the main bootloader in emulation. This
782 * isn't documented. */
783static uint32_t n800_pinout[104] = {
784 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
785 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
786 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
787 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
788 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
789 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
790 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
791 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
792 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
793 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
794 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
795 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
796 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
797 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
798 0x00000000, 0x00000038, 0x00340000, 0x00000000,
799 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
800 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
801 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
802 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
803 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
804 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
805 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
806 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
807 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
808 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
809 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
810};
811
812static void n800_setup_nolo_tags(void *sram_base)
813{
814 int i;
815 uint32_t *p = sram_base + 0x8000;
816 uint32_t *v = sram_base + 0xa000;
817
818 memset(p, 0, 0x3000);
819
820 strcpy((void *) (p + 0), "QEMU N800");
821
822 strcpy((void *) (p + 8), "F5");
823
824 stl_raw(p + 10, 0x04f70000);
825 strcpy((void *) (p + 9), "RX-34");
826
827 /* RAM size in MB? */
828 stl_raw(p + 12, 0x80);
829
830 /* Pointer to the list of tags */
831 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
832
833 /* The NOLO tags start here */
834 p = sram_base + 0x9000;
835#define ADD_TAG(tag, len) \
836 stw_raw((uint16_t *) p + 0, tag); \
837 stw_raw((uint16_t *) p + 1, len); p ++; \
838 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
839
840 /* OMAP STI console? Pin out settings? */
841 ADD_TAG(0x6e01, 414);
b1503cda 842 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
d238db7f
AZ		 843 stl_raw(v ++, n800_pinout[i]);
844
845 /* Kernel memsize? */
846 ADD_TAG(0x6e05, 1);
847 stl_raw(v ++, 2);
848
849 /* NOLO serial console */
850 ADD_TAG(0x6e02, 4);
851 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
852
853#if 0
854 /* CBUS settings (Retu/AVilma) */
855 ADD_TAG(0x6e03, 6);
856 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
857 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
858 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
859 v += 2;
860#endif
861
862 /* Nokia ASIC BB5 (Retu/Tahvo) */
863 ADD_TAG(0x6e0a, 4);
864 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
865 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
866 v ++;
867
868 /* LCD console? */
869 ADD_TAG(0x6e04, 4);
870 stw_raw((uint16_t *) v + 0, 30); /* ??? */
871 stw_raw((uint16_t *) v + 1, 24); /* ??? */
872 v ++;
873
874#if 0
875 /* LCD settings */
876 ADD_TAG(0x6e06, 2);
877 stw_raw((uint16_t *) (v ++), 15); /* ??? */
878#endif
879
880 /* I^2C (Menelaus) */
881 ADD_TAG(0x6e07, 4);
882 stl_raw(v ++, 0x00720000); /* ??? */
883
884 /* Unknown */
885 ADD_TAG(0x6e0b, 6);
886 stw_raw((uint16_t *) v + 0, 94); /* ??? */
887 stw_raw((uint16_t *) v + 1, 23); /* ??? */
888 stw_raw((uint16_t *) v + 2, 0); /* ??? */
889 v += 2;
890
891 /* OMAP gpio switch info */
892 ADD_TAG(0x6e0c, 80);
893 strcpy((void *) v, "bat_cover"); v += 3;
894 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
895 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
896 v += 2;
897 strcpy((void *) v, "cam_act"); v += 3;
898 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
899 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
900 v += 2;
901 strcpy((void *) v, "cam_turn"); v += 3;
902 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
903 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
904 v += 2;
905 strcpy((void *) v, "headphone"); v += 3;
906 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
907 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
908 v += 2;
909
910 /* Bluetooth */
911 ADD_TAG(0x6e0e, 12);
912 stl_raw(v ++, 0x5c623d01); /* ??? */
913 stl_raw(v ++, 0x00000201); /* ??? */
914 stl_raw(v ++, 0x00000000); /* ??? */
915
916 /* CX3110x WLAN settings */
917 ADD_TAG(0x6e0f, 8);
918 stl_raw(v ++, 0x00610025); /* ??? */
919 stl_raw(v ++, 0xffff0057); /* ??? */
920
921 /* MMC host settings */
922 ADD_TAG(0x6e10, 12);
923 stl_raw(v ++, 0xffff000f); /* ??? */
924 stl_raw(v ++, 0xffffffff); /* ??? */
925 stl_raw(v ++, 0x00000060); /* ??? */
926
927 /* OneNAND chip select */
928 ADD_TAG(0x6e11, 10);
929 stl_raw(v ++, 0x00000401); /* ??? */
930 stl_raw(v ++, 0x0002003a); /* ??? */
931 stl_raw(v ++, 0x00000002); /* ??? */
932
933 /* TEA5761 sensor settings */
934 ADD_TAG(0x6e12, 2);
935 stl_raw(v ++, 93); /* GPIO num ??? */
936
937#if 0
938 /* Unknown tag */
939 ADD_TAG(6e09, 0);
940
941 /* Kernel UART / console */
942 ADD_TAG(6e12, 0);
943#endif
944
945 /* End of the list */
946 stl_raw(p ++, 0x00000000);
947 stl_raw(p ++, 0x00000000);
948}
949
7e7c5e4c
AZ		 950/* This task is normally performed by the bootloader. If we're loading
951 * a kernel directly, we need to set up GPMC mappings ourselves. */
952static void n800_gpmc_init(struct n800_s *s)
953{
954 uint32_t config7 =
955 (0xf << 8) | /* MASKADDRESS */
956 (1 << 6) | /* CSVALID */
957 (4 << 0); /* BASEADDRESS */
958
959 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
960 (void *) &config7, sizeof(config7));
961}
962
963/* Setup sequence done by the bootloader */
e927bb00 964static void n8x0_boot_init(void *opaque)
7e7c5e4c
AZ		 965{
966 struct n800_s *s = (struct n800_s *) opaque;
967 uint32_t buf;
968
969 /* PRCM setup */
970#define omap_writel(addr, val) \
971 buf = (val); \
972 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
973
974 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
975 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
976 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
977 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
978 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
979 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
980 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
981 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
982 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
983 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
984 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
985 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
986 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
987 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
988 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
989 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
990 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
991 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
992 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
993 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
994 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
995 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
996 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
997 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
998 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
999 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1000 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1001 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1002 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1003 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1004 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1005 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1006 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1007 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1008 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1009 (0x78 << 12) | (6 << 8));
1010 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1011
1012 /* GPMC setup */
1013 n800_gpmc_init(s);
1014
1015 /* Video setup */
1016 n800_dss_init(&s->blizzard);
1017
1018 /* CPU setup */
7e7c5e4c 1019 s->cpu->env->GE = 0x5;
0941041e
AZ		 1020
1021 /* If the machine has a slided keyboard, open it */
1022 if (s->kbd)
77831c20 1023 qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO));
7e7c5e4c
AZ		 1024}
1025
1026#define OMAP_TAG_NOKIA_BT 0x4e01
1027#define OMAP_TAG_WLAN_CX3110X 0x4e02
1028#define OMAP_TAG_CBUS 0x4e03
1029#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1030
e927bb00
AZ		 1031static struct omap_gpiosw_info_s {
1032 const char *name;
1033 int line;
1034 int type;
1035} n800_gpiosw_info[] = {
1036 {
1037 "bat_cover", N800_BAT_COVER_GPIO,
1038 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1039 }, {
1040 "cam_act", N800_CAM_ACT_GPIO,
1041 OMAP_GPIOSW_TYPE_ACTIVITY,
1042 }, {
1043 "cam_turn", N800_CAM_TURN_GPIO,
1044 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1045 }, {
1046 "headphone", N8X0_HEADPHONE_GPIO,
1047 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1048 },
b9d38e95 1049 { NULL }
e927bb00
AZ		 1050}, n810_gpiosw_info[] = {
1051 {
1052 "gps_reset", N810_GPS_RESET_GPIO,
1053 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1054 }, {
1055 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1056 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1057 }, {
1058 "headphone", N8X0_HEADPHONE_GPIO,
1059 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1060 }, {
1061 "kb_lock", N810_KB_LOCK_GPIO,
1062 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1063 }, {
1064 "sleepx_led", N810_SLEEPX_LED_GPIO,
1065 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1066 }, {
1067 "slide", N810_SLIDE_GPIO,
1068 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1069 },
b9d38e95 1070 { NULL }
e927bb00
AZ		 1071};
1072
1073static struct omap_partition_info_s {
1074 uint32_t offset;
1075 uint32_t size;
1076 int mask;
1077 const char *name;
1078} n800_part_info[] = {
1079 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1080 { 0x00020000, 0x00060000, 0x0, "config" },
1081 { 0x00080000, 0x00200000, 0x0, "kernel" },
1082 { 0x00280000, 0x00200000, 0x3, "initfs" },
1083 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1084
b9d38e95 1085 { 0, 0, 0, NULL }
e927bb00
AZ		 1086}, n810_part_info[] = {
1087 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1088 { 0x00020000, 0x00060000, 0x0, "config" },
1089 { 0x00080000, 0x00220000, 0x0, "kernel" },
1090 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1091 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1092
b9d38e95 1093 { 0, 0, 0, NULL }
e927bb00
AZ		 1094};
1095
c227f099 1096static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
c580d92b 1097
e927bb00 1098static int n8x0_atag_setup(void *p, int model)
7e7c5e4c
AZ		 1099{
1100 uint8_t *b;
1101 uint16_t *w;
1102 uint32_t *l;
e927bb00
AZ		 1103 struct omap_gpiosw_info_s *gpiosw;
1104 struct omap_partition_info_s *partition;
1105 const char *tag;
7e7c5e4c
AZ		 1106
1107 w = p;
1108
1109 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1110 stw_raw(w ++, 4); /* u16 len */
1111 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1112 w ++;
1113
e927bb00
AZ		 1114#if 0
1115 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
7e7c5e4c 1116 stw_raw(w ++, 4); /* u16 len */
c580d92b 1117 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
e927bb00
AZ		 1118 stw_raw(w ++, 115200); /* u32 console_speed */
1119#endif
1120
1121 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1122 stw_raw(w ++, 36); /* u16 len */
1123 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1124 w += 8;
1125 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1126 w += 8;
1127 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1128 stw_raw(w ++, 24); /* u8 data_lines */
7e7c5e4c
AZ		 1129
1130 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1131 stw_raw(w ++, 8); /* u16 len */
1132 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1133 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1134 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1135 w ++;
1136
e927bb00
AZ		 1137 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1138 stw_raw(w ++, 4); /* u16 len */
1139 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1140 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1141
1142 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1143 for (; gpiosw->name; gpiosw ++) {
1144 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1145 stw_raw(w ++, 20); /* u16 len */
1146 strcpy((void *) w, gpiosw->name); /* char name[12] */
1147 w += 6;
1148 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1149 stw_raw(w ++, gpiosw->type);
1150 stw_raw(w ++, 0);
1151 stw_raw(w ++, 0);
1152 }
7e7c5e4c
AZ		 1153
1154 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1155 stw_raw(w ++, 12); /* u16 len */
1156 b = (void *) w;
1157 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
e927bb00 1158 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
7e7c5e4c 1159 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
e927bb00 1160 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
c580d92b
AZ		 1161 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1162 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
7e7c5e4c
AZ		 1163 b += 6;
1164 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1165 w = (void *) b;
1166
1167 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1168 stw_raw(w ++, 8); /* u16 len */
1169 stw_raw(w ++, 0x25); /* u8 chip_type */
e927bb00
AZ		 1170 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1171 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
7e7c5e4c
AZ		 1172 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1173
1174 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1175 stw_raw(w ++, 16); /* u16 len */
e927bb00
AZ		 1176 if (model == 810) {
1177 stw_raw(w ++, 0x23f); /* unsigned flags */
1178 stw_raw(w ++, -1); /* s16 power_pin */
1179 stw_raw(w ++, -1); /* s16 switch_pin */
1180 stw_raw(w ++, -1); /* s16 wp_pin */
1181 stw_raw(w ++, 0x240); /* unsigned flags */
1182 stw_raw(w ++, 0xc000); /* s16 power_pin */
1183 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1184 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1185 } else {
1186 stw_raw(w ++, 0xf); /* unsigned flags */
1187 stw_raw(w ++, -1); /* s16 power_pin */
1188 stw_raw(w ++, -1); /* s16 switch_pin */
1189 stw_raw(w ++, -1); /* s16 wp_pin */
1190 stw_raw(w ++, 0); /* unsigned flags */
1191 stw_raw(w ++, 0); /* s16 power_pin */
1192 stw_raw(w ++, 0); /* s16 switch_pin */
1193 stw_raw(w ++, 0); /* s16 wp_pin */
1194 }
7e7c5e4c
AZ		 1195
1196 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1197 stw_raw(w ++, 4); /* u16 len */
e927bb00 1198 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
7e7c5e4c
AZ		 1199 w ++;
1200
e927bb00
AZ		 1201 partition = (model == 810) ? n810_part_info : n800_part_info;
1202 for (; partition->name; partition ++) {
1203 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1204 stw_raw(w ++, 28); /* u16 len */
1205 strcpy((void *) w, partition->name); /* char name[16] */
1206 l = (void *) (w + 8);
1207 stl_raw(l ++, partition->size); /* unsigned int size */
1208 stl_raw(l ++, partition->offset); /* unsigned int offset */
1209 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1210 w = (void *) l;
1211 }
7e7c5e4c
AZ		 1212
1213 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1214 stw_raw(w ++, 12); /* u16 len */
1215#if 0
1216 strcpy((void *) w, "por"); /* char reason_str[12] */
1217 strcpy((void *) w, "charger"); /* char reason_str[12] */
1218 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1219 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1220 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1221 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1222 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1223 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1224 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1225 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1226#else
1227 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1228#endif
1229 w += 6;
1230
e927bb00 1231 tag = (model == 810) ? "RX-44" : "RX-34";
7e7c5e4c
AZ		 1232 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1233 stw_raw(w ++, 24); /* u16 len */
1234 strcpy((void *) w, "product"); /* char component[12] */
1235 w += 6;
e927bb00 1236 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c
AZ		 1237 w += 6;
1238
1239 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1240 stw_raw(w ++, 24); /* u16 len */
1241 strcpy((void *) w, "hw-build"); /* char component[12] */
1242 w += 6;
e927bb00 1243 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
7e7c5e4c
AZ		 1244 w += 6;
1245
e927bb00 1246 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
7e7c5e4c
AZ		 1247 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1248 stw_raw(w ++, 24); /* u16 len */
1249 strcpy((void *) w, "nolo"); /* char component[12] */
1250 w += 6;
e927bb00 1251 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c 1252 w += 6;
7e7c5e4c
AZ		 1253
1254 return (void *) w - p;
1255}
1256
462a8bc6 1257static int n800_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1258{
1259 return n8x0_atag_setup(p, 800);
1260}
7e7c5e4c 1261
462a8bc6 1262static int n810_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1263{
1264 return n8x0_atag_setup(p, 810);
1265}
1266
c227f099 1267static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
3023f332 1268 const char *kernel_filename,
e927bb00
AZ		 1269 const char *kernel_cmdline, const char *initrd_filename,
1270 const char *cpu_model, struct arm_boot_info *binfo, int model)
7e7c5e4c
AZ		 1271{
1272 struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
e927bb00 1273 int sdram_size = binfo->ram_size;
09218951 1274 DisplayState *ds;
7e7c5e4c 1275
3023f332 1276 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
7e7c5e4c 1277
0941041e
AZ		 1278 /* Setup peripherals
1279 *
1280 * Believed external peripherals layout in the N810:
1281 * (spi bus 1)
1282 * tsc2005
1283 * lcd_mipid
1284 * (spi bus 2)
1285 * Conexant cx3110x (WLAN)
1286 * optional: pc2400m (WiMAX)
1287 * (i2c bus 0)
1288 * TLV320AIC33 (audio codec)
1289 * TCM825x (camera by Toshiba)
1290 * lp5521 (clever LEDs)
1291 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1292 * lm8323 (keypad, manf 00, rev 04)
1293 * (i2c bus 1)
1294 * tmp105 (temperature sensor, hwmon)
1295 * menelaus (pm)
d238db7f
AZ		 1296 * (somewhere on i2c - maybe N800-only)
1297 * tea5761 (FM tuner)
1298 * (serial 0)
1299 * GPS
1300 * (some serial port)
1301 * csr41814 (Bluetooth)
0941041e 1302 */
e927bb00 1303 n8x0_gpio_setup(s);
7e7c5e4c 1304 n8x0_nand_setup(s);
e927bb00
AZ		 1305 n8x0_i2c_setup(s);
1306 if (model == 800)
1307 n800_tsc_kbd_setup(s);
1d4e547b 1308 else if (model == 810) {
e927bb00 1309 n810_tsc_setup(s);
1d4e547b
AZ		 1310 n810_kbd_setup(s);
1311 }
e927bb00 1312 n8x0_spi_setup(s);
3023f332 1313 n8x0_dss_setup(s);
e927bb00 1314 n8x0_cbus_setup(s);
58a26b47 1315 n8x0_uart_setup(s);
942ac052 1316 if (usb_enabled)
e927bb00 1317 n8x0_usb_setup(s);
7e7c5e4c 1318
7e7c5e4c
AZ		 1319 if (kernel_filename) {
1320 /* Or at the linux loader. */
e927bb00
AZ		 1321 binfo->kernel_filename = kernel_filename;
1322 binfo->kernel_cmdline = kernel_cmdline;
1323 binfo->initrd_filename = initrd_filename;
1324 arm_load_kernel(s->cpu->env, binfo);
7e7c5e4c 1325
a08d4367 1326 qemu_register_reset(n8x0_boot_init, s);
7e7c5e4c
AZ		 1327 }
1328
2e55e842 1329 if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) {
dcac9679 1330 int rom_size;
5c130f65 1331 uint8_t nolo_tags[0x10000];
d238db7f
AZ		 1332 /* No, wait, better start at the ROM. */
1333 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1334
1335 /* This is intended for loading the `secondary.bin' program from
1336 * Nokia images (the NOLO bootloader). The entry point seems
1337 * to be at OMAP2_Q2_BASE + 0x400000.
1338 *
1339 * The `2nd.bin' files contain some kind of earlier boot code and
1340 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1341 *
1342 * The code above is for loading the `zImage' file from Nokia
1343 * images. */
2e55e842 1344 rom_size = load_image_targphys(option_rom[0].name,
dcac9679
PB		 1345 OMAP2_Q2_BASE + 0x400000,
1346 sdram_size - 0x400000);
1347 printf("%i bytes of image loaded\n", rom_size);
d238db7f 1348
5c130f65
PB		 1349 n800_setup_nolo_tags(nolo_tags);
1350 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
d238db7f 1351 }
c60e08d9
PB		 1352 /* FIXME: We shouldn't really be doing this here. The LCD controller
1353 will set the size once configured, so this just sets an initial
1354 size until the guest activates the display. */
09218951 1355 ds = get_displaystate();
7b5d76da 1356 ds->surface = qemu_resize_displaysurface(ds, 800, 480);
7d957bd8 1357 dpy_resize(ds);
7e7c5e4c
AZ		 1358}
1359
e927bb00
AZ		 1360static struct arm_boot_info n800_binfo = {
1361 .loader_start = OMAP2_Q2_BASE,
1362 /* Actually two chips of 0x4000000 bytes each */
1363 .ram_size = 0x08000000,
1364 .board_id = 0x4f7,
1365 .atag_board = n800_atag_setup,
1366};
1367
1368static struct arm_boot_info n810_binfo = {
1369 .loader_start = OMAP2_Q2_BASE,
1370 /* Actually two chips of 0x4000000 bytes each */
1371 .ram_size = 0x08000000,
1372 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1373 * used by some older versions of the bootloader and 5555 is used
1374 * instead (including versions that shipped with many devices). */
1375 .board_id = 0x60c,
1376 .atag_board = n810_atag_setup,
1377};
1378
c227f099 1379static void n800_init(ram_addr_t ram_size,
3023f332 1380 const char *boot_device,
e927bb00
AZ		 1381 const char *kernel_filename, const char *kernel_cmdline,
1382 const char *initrd_filename, const char *cpu_model)
1383{
3023f332 1384 return n8x0_init(ram_size, boot_device,
e927bb00
AZ		 1385 kernel_filename, kernel_cmdline, initrd_filename,
1386 cpu_model, &n800_binfo, 800);
1387}
1388
c227f099 1389static void n810_init(ram_addr_t ram_size,
3023f332 1390 const char *boot_device,
e927bb00
AZ		 1391 const char *kernel_filename, const char *kernel_cmdline,
1392 const char *initrd_filename, const char *cpu_model)
1393{
3023f332 1394 return n8x0_init(ram_size, boot_device,
e927bb00
AZ		 1395 kernel_filename, kernel_cmdline, initrd_filename,
1396 cpu_model, &n810_binfo, 810);
1397}
1398
f80f9ec9 1399static QEMUMachine n800_machine = {
4b32e168
AL		 1400 .name = "n800",
1401 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1402 .init = n800_init,
7e7c5e4c 1403};
e927bb00 1404
f80f9ec9 1405static QEMUMachine n810_machine = {
4b32e168
AL		 1406 .name = "n810",
1407 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1408 .init = n810_init,
e927bb00 1409};
f80f9ec9
AL		 1410
1411static void nseries_machine_init(void)
1412{
1413 qemu_register_machine(&n800_machine);
1414 qemu_register_machine(&n810_machine);
1415}
1416
1417machine_init(nseries_machine_init);
QEMU mirror