]> git.proxmox.com Git - mirror_qemu.git/blame - hw/nseries.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
hw/nand: qdevify
[mirror_qemu.git] / hw / nseries.c
CommitLineData
7e7c5e4c
AZ		 1/*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 19 */
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "omap.h"
24#include "arm-misc.h"
25#include "irq.h"
26#include "console.h"
27#include "boards.h"
28#include "i2c.h"
29#include "devices.h"
30#include "flash.h"
31#include "hw.h"
1ae26a18 32#include "bt.h"
ca20cf32 33#include "loader.h"
7e7c5e4c
AZ		 34
35/* Nokia N8x0 support */
36struct n800_s {
37 struct omap_mpu_state_s *cpu;
38
39 struct rfbi_chip_s blizzard;
e927bb00
AZ		 40 struct {
41 void *opaque;
42 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
bc24a225 43 uWireSlave *chip;
e927bb00 44 } ts;
7e7c5e4c
AZ		 45 i2c_bus *i2c;
46
47 int keymap[0x80];
c4f05c8c 48 DeviceState *kbd;
7e7c5e4c 49
bc24a225 50 TUSBState *usb;
7e7c5e4c
AZ		 51 void *retu;
52 void *tahvo;
c580d92b 53 void *nand;
7e7c5e4c
AZ		 54};
55
56/* GPIO pins */
e927bb00 57#define N8X0_TUSB_ENABLE_GPIO 0
7e7c5e4c
AZ		 58#define N800_MMC2_WP_GPIO 8
59#define N800_UNKNOWN_GPIO0 9 /* out */
0941041e 60#define N810_MMC2_VIOSD_GPIO 9
99570a40 61#define N810_HEADSET_AMP_GPIO 10
7e7c5e4c 62#define N800_CAM_TURN_GPIO 12
e927bb00 63#define N810_GPS_RESET_GPIO 12
7e7c5e4c
AZ		 64#define N800_BLIZZARD_POWERDOWN_GPIO 15
65#define N800_MMC1_WP_GPIO 23
0941041e 66#define N810_MMC2_VSD_GPIO 23
7e7c5e4c 67#define N8X0_ONENAND_GPIO 26
e927bb00 68#define N810_BLIZZARD_RESET_GPIO 30
7e7c5e4c
AZ		 69#define N800_UNKNOWN_GPIO2 53 /* out */
70#define N8X0_TUSB_INT_GPIO 58
e927bb00
AZ		 71#define N8X0_BT_WKUP_GPIO 61
72#define N8X0_STI_GPIO 62
7e7c5e4c 73#define N8X0_CBUS_SEL_GPIO 64
e927bb00
AZ		 74#define N8X0_CBUS_DAT_GPIO 65
75#define N8X0_CBUS_CLK_GPIO 66
76#define N8X0_WLAN_IRQ_GPIO 87
77#define N8X0_BT_RESET_GPIO 92
78#define N8X0_TEA5761_CS_GPIO 93
7e7c5e4c 79#define N800_UNKNOWN_GPIO 94
e927bb00 80#define N810_TSC_RESET_GPIO 94
7e7c5e4c 81#define N800_CAM_ACT_GPIO 95
e927bb00
AZ		 82#define N810_GPS_WAKEUP_GPIO 95
83#define N8X0_MMC_CS_GPIO 96
84#define N8X0_WLAN_PWR_GPIO 97
7e7c5e4c 85#define N8X0_BT_HOST_WKUP_GPIO 98
99570a40 86#define N810_SPEAKER_AMP_GPIO 101
7e7c5e4c
AZ		 87#define N810_KB_LOCK_GPIO 102
88#define N800_TSC_TS_GPIO 103
e927bb00
AZ		 89#define N810_TSC_TS_GPIO 106
90#define N8X0_HEADPHONE_GPIO 107
7e7c5e4c
AZ		 91#define N8X0_RETU_GPIO 108
92#define N800_TSC_KP_IRQ_GPIO 109
93#define N810_KEYBOARD_GPIO 109
94#define N800_BAT_COVER_GPIO 110
95#define N810_SLIDE_GPIO 110
96#define N8X0_TAHVO_GPIO 111
97#define N800_UNKNOWN_GPIO4 112 /* out */
e927bb00 98#define N810_SLEEPX_LED_GPIO 112
1d4e547b 99#define N800_TSC_RESET_GPIO 118 /* ? */
99570a40 100#define N810_AIC33_RESET_GPIO 118
1d4e547b 101#define N800_TSC_UNKNOWN_GPIO 119 /* out */
7e7c5e4c
AZ		 102#define N8X0_TMP105_GPIO 125
103
104/* Config */
c580d92b 105#define BT_UART 0
7e7c5e4c
AZ		 106#define XLDR_LL_UART 1
107
1d4e547b
AZ		 108/* Addresses on the I2C bus 0 */
109#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
110#define N8X0_TCM825x_ADDR 0x29 /* Camera */
111#define N810_LP5521_ADDR 0x32 /* LEDs */
112#define N810_TSL2563_ADDR 0x3d /* Light sensor */
113#define N810_LM8323_ADDR 0x45 /* Keyboard */
114/* Addresses on the I2C bus 1 */
115#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
116#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
7e7c5e4c
AZ		 117
118/* Chipselects on GPMC NOR interface */
119#define N8X0_ONENAND_CS 0
120#define N8X0_USB_ASYNC_CS 1
121#define N8X0_USB_SYNC_CS 4
122
c580d92b
AZ		 123#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
124
7e7c5e4c
AZ		 125static void n800_mmc_cs_cb(void *opaque, int line, int level)
126{
127 /* TODO: this seems to actually be connected to the menelaus, to
128 * which also both MMC slots connect. */
129 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
130
131 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
132}
133
e927bb00 134static void n8x0_gpio_setup(struct n800_s *s)
7e7c5e4c
AZ		 135{
136 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
77831c20 137 qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
7e7c5e4c 138
77831c20 139 qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO));
7e7c5e4c
AZ		 140}
141
c580d92b
AZ		 142#define MAEMO_CAL_HEADER(...) \
143 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
144 __VA_ARGS__, \
145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
146
147static const uint8_t n8x0_cal_wlan_mac[] = {
148 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
149 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
150 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
151 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
152 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
153 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
154};
155
156static const uint8_t n8x0_cal_bt_id[] = {
157 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
158 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
159 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
160 N8X0_BD_ADDR,
161};
162
7e7c5e4c
AZ		 163static void n8x0_nand_setup(struct n800_s *s)
164{
c580d92b
AZ		 165 char *otp_region;
166
7e7c5e4c
AZ		 167 /* Either ec40xx or ec48xx are OK for the ID */
168 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
169 onenand_base_unmap,
c580d92b 170 (s->nand = onenand_init(0xec4800, 1,
77831c20
JR		 171 qdev_get_gpio_in(s->cpu->gpio,
172 N8X0_ONENAND_GPIO))));
c580d92b
AZ		 173 otp_region = onenand_raw_otp(s->nand);
174
175 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
176 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
177 /* XXX: in theory should also update the OOB for both pages */
7e7c5e4c
AZ		 178}
179
e927bb00 180static void n8x0_i2c_setup(struct n800_s *s)
7e7c5e4c 181{
697454eb 182 DeviceState *dev;
77831c20 183 qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
7e7c5e4c
AZ		 184
185 /* Attach the CPU on one end of our I2C bus. */
186 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
187
188 /* Attach a menelaus PM chip */
d3356811
PB		 189 dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
190 qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
7e7c5e4c
AZ		 191
192 /* Attach a TMP105 PM chip (A0 wired to ground) */
697454eb
PB		 193 dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
194 qdev_connect_gpio_out(dev, 0, tmp_irq);
7e7c5e4c
AZ		 195}
196
197/* Touchscreen and keypad controller */
bc24a225 198static MouseTransformInfo n800_pointercal = {
e927bb00
AZ		 199 .x = 800,
200 .y = 480,
201 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
202};
203
bc24a225 204static MouseTransformInfo n810_pointercal = {
e927bb00
AZ		 205 .x = 800,
206 .y = 480,
207 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
208};
209
7e7c5e4c
AZ		 210#define RETU_KEYCODE 61 /* F3 */
211
212static void n800_key_event(void *opaque, int keycode)
213{
214 struct n800_s *s = (struct n800_s *) opaque;
215 int code = s->keymap[keycode & 0x7f];
216
217 if (code == -1) {
218 if ((keycode & 0x7f) == RETU_KEYCODE)
219 retu_key_event(s->retu, !(keycode & 0x80));
220 return;
221 }
222
e927bb00 223 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
7e7c5e4c
AZ		 224}
225
226static const int n800_keys[16] = {
227 -1,
228 72, /* Up */
229 63, /* Home (F5) */
230 -1,
231 75, /* Left */
232 28, /* Enter */
233 77, /* Right */
234 -1,
1d4e547b 235 1, /* Cycle (ESC) */
7e7c5e4c
AZ		 236 80, /* Down */
237 62, /* Menu (F4) */
238 -1,
239 66, /* Zoom- (F8) */
1d4e547b 240 64, /* FullScreen (F6) */
7e7c5e4c
AZ		 241 65, /* Zoom+ (F7) */
242 -1,
243};
244
e927bb00 245static void n800_tsc_kbd_setup(struct n800_s *s)
7e7c5e4c
AZ		 246{
247 int i;
248
249 /* XXX: are the three pins inverted inside the chip between the
250 * tsc and the cpu (N4111)? */
b9d38e95 251 qemu_irq penirq = NULL; /* NC */
77831c20
JR		 252 qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO);
253 qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO);
7e7c5e4c 254
22d83b14 255 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
e927bb00
AZ		 256 s->ts.opaque = s->ts.chip->opaque;
257 s->ts.txrx = tsc210x_txrx;
7e7c5e4c
AZ		 258
259 for (i = 0; i < 0x80; i ++)
260 s->keymap[i] = -1;
261 for (i = 0; i < 0x10; i ++)
262 if (n800_keys[i] >= 0)
263 s->keymap[n800_keys[i]] = i;
264
265 qemu_add_kbd_event_handler(n800_key_event, s);
266
e927bb00
AZ		 267 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
268}
269
270static void n810_tsc_setup(struct n800_s *s)
271{
77831c20 272 qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO);
e927bb00
AZ		 273
274 s->ts.opaque = tsc2005_init(pintdav);
275 s->ts.txrx = tsc2005_txrx;
276
277 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
7e7c5e4c
AZ		 278}
279
1d4e547b
AZ		 280/* N810 Keyboard controller */
281static void n810_key_event(void *opaque, int keycode)
282{
283 struct n800_s *s = (struct n800_s *) opaque;
284 int code = s->keymap[keycode & 0x7f];
285
286 if (code == -1) {
287 if ((keycode & 0x7f) == RETU_KEYCODE)
288 retu_key_event(s->retu, !(keycode & 0x80));
289 return;
290 }
291
292 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
293}
294
295#define M 0
296
297static int n810_keys[0x80] = {
298 [0x01] = 16, /* Q */
299 [0x02] = 37, /* K */
300 [0x03] = 24, /* O */
301 [0x04] = 25, /* P */
302 [0x05] = 14, /* Backspace */
303 [0x06] = 30, /* A */
304 [0x07] = 31, /* S */
305 [0x08] = 32, /* D */
306 [0x09] = 33, /* F */
307 [0x0a] = 34, /* G */
308 [0x0b] = 35, /* H */
309 [0x0c] = 36, /* J */
310
311 [0x11] = 17, /* W */
312 [0x12] = 62, /* Menu (F4) */
313 [0x13] = 38, /* L */
314 [0x14] = 40, /* ' (Apostrophe) */
315 [0x16] = 44, /* Z */
316 [0x17] = 45, /* X */
317 [0x18] = 46, /* C */
318 [0x19] = 47, /* V */
319 [0x1a] = 48, /* B */
320 [0x1b] = 49, /* N */
321 [0x1c] = 42, /* Shift (Left shift) */
322 [0x1f] = 65, /* Zoom+ (F7) */
323
324 [0x21] = 18, /* E */
325 [0x22] = 39, /* ; (Semicolon) */
326 [0x23] = 12, /* - (Minus) */
327 [0x24] = 13, /* = (Equal) */
328 [0x2b] = 56, /* Fn (Left Alt) */
329 [0x2c] = 50, /* M */
330 [0x2f] = 66, /* Zoom- (F8) */
331
332 [0x31] = 19, /* R */
333 [0x32] = 29 | M, /* Right Ctrl */
334 [0x34] = 57, /* Space */
335 [0x35] = 51, /* , (Comma) */
336 [0x37] = 72 | M, /* Up */
337 [0x3c] = 82 | M, /* Compose (Insert) */
338 [0x3f] = 64, /* FullScreen (F6) */
339
340 [0x41] = 20, /* T */
341 [0x44] = 52, /* . (Dot) */
342 [0x46] = 77 | M, /* Right */
343 [0x4f] = 63, /* Home (F5) */
344 [0x51] = 21, /* Y */
345 [0x53] = 80 | M, /* Down */
346 [0x55] = 28, /* Enter */
347 [0x5f] = 1, /* Cycle (ESC) */
348
349 [0x61] = 22, /* U */
350 [0x64] = 75 | M, /* Left */
351
352 [0x71] = 23, /* I */
353#if 0
354 [0x75] = 28 | M, /* KP Enter (KP Enter) */
355#else
356 [0x75] = 15, /* KP Enter (Tab) */
357#endif
358};
359
360#undef M
361
362static void n810_kbd_setup(struct n800_s *s)
363{
77831c20 364 qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO);
1d4e547b
AZ		 365 int i;
366
367 for (i = 0; i < 0x80; i ++)
368 s->keymap[i] = -1;
369 for (i = 0; i < 0x80; i ++)
370 if (n810_keys[i] > 0)
371 s->keymap[n810_keys[i]] = i;
372
373 qemu_add_kbd_event_handler(n810_key_event, s);
374
375 /* Attach the LM8322 keyboard to the I2C bus,
376 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
c4f05c8c
PM		 377 s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
378 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
1d4e547b
AZ		 379}
380
7e7c5e4c
AZ		 381/* LCD MIPI DBI-C controller (URAL) */
382struct mipid_s {
383 int resp[4];
384 int param[4];
385 int p;
386 int pm;
387 int cmd;
388
389 int sleep;
390 int booster;
391 int te;
392 int selfcheck;
393 int partial;
394 int normal;
395 int vscr;
396 int invert;
397 int onoff;
398 int gamma;
399 uint32_t id;
400};
401
402static void mipid_reset(struct mipid_s *s)
403{
404 if (!s->sleep)
405 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
406
407 s->pm = 0;
408 s->cmd = 0;
409
410 s->sleep = 1;
411 s->booster = 0;
412 s->selfcheck =
413 (1 << 7) | /* Register loading OK. */
414 (1 << 5) | /* The chip is attached. */
415 (1 << 4); /* Display glass still in one piece. */
416 s->te = 0;
417 s->partial = 0;
418 s->normal = 1;
419 s->vscr = 0;
420 s->invert = 0;
421 s->onoff = 1;
422 s->gamma = 0;
423}
424
e927bb00 425static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
7e7c5e4c
AZ		 426{
427 struct mipid_s *s = (struct mipid_s *) opaque;
428 uint8_t ret;
429
e927bb00 430 if (len > 9)
2ac71179 431 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
e927bb00 432
b1503cda 433 if (s->p >= ARRAY_SIZE(s->resp))
7e7c5e4c
AZ		 434 ret = 0;
435 else
436 ret = s->resp[s->p ++];
437 if (s->pm --> 0)
438 s->param[s->pm] = cmd;
439 else
440 s->cmd = cmd;
441
442 switch (s->cmd) {
443 case 0x00: /* NOP */
444 break;
445
446 case 0x01: /* SWRESET */
447 mipid_reset(s);
448 break;
449
450 case 0x02: /* BSTROFF */
451 s->booster = 0;
452 break;
453 case 0x03: /* BSTRON */
454 s->booster = 1;
455 break;
456
457 case 0x04: /* RDDID */
458 s->p = 0;
459 s->resp[0] = (s->id >> 16) & 0xff;
460 s->resp[1] = (s->id >> 8) & 0xff;
461 s->resp[2] = (s->id >> 0) & 0xff;
462 break;
463
464 case 0x06: /* RD_RED */
465 case 0x07: /* RD_GREEN */
466 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
467 * for the bootloader one needs to change this. */
468 case 0x08: /* RD_BLUE */
469 s->p = 0;
470 /* TODO: return first pixel components */
471 s->resp[0] = 0x01;
472 break;
473
474 case 0x09: /* RDDST */
475 s->p = 0;
476 s->resp[0] = s->booster << 7;
477 s->resp[1] = (5 << 4) | (s->partial << 2) |
478 (s->sleep << 1) | s->normal;
479 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
480 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
481 s->resp[3] = s->gamma << 6;
482 break;
483
484 case 0x0a: /* RDDPM */
485 s->p = 0;
486 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
487 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
488 break;
489 case 0x0b: /* RDDMADCTR */
490 s->p = 0;
491 s->resp[0] = 0;
492 break;
493 case 0x0c: /* RDDCOLMOD */
494 s->p = 0;
495 s->resp[0] = 5; /* 65K colours */
496 break;
497 case 0x0d: /* RDDIM */
498 s->p = 0;
499 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
500 break;
501 case 0x0e: /* RDDSM */
502 s->p = 0;
503 s->resp[0] = s->te << 7;
504 break;
505 case 0x0f: /* RDDSDR */
506 s->p = 0;
507 s->resp[0] = s->selfcheck;
508 break;
509
510 case 0x10: /* SLPIN */
511 s->sleep = 1;
512 break;
513 case 0x11: /* SLPOUT */
514 s->sleep = 0;
515 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
516 break;
517
518 case 0x12: /* PTLON */
519 s->partial = 1;
520 s->normal = 0;
521 s->vscr = 0;
522 break;
523 case 0x13: /* NORON */
524 s->partial = 0;
525 s->normal = 1;
526 s->vscr = 0;
527 break;
528
529 case 0x20: /* INVOFF */
530 s->invert = 0;
531 break;
532 case 0x21: /* INVON */
533 s->invert = 1;
534 break;
535
536 case 0x22: /* APOFF */
537 case 0x23: /* APON */
538 goto bad_cmd;
539
540 case 0x25: /* WRCNTR */
541 if (s->pm < 0)
542 s->pm = 1;
543 goto bad_cmd;
544
545 case 0x26: /* GAMSET */
546 if (!s->pm)
547 s->gamma = ffs(s->param[0] & 0xf) - 1;
548 else if (s->pm < 0)
549 s->pm = 1;
550 break;
551
552 case 0x28: /* DISPOFF */
553 s->onoff = 0;
554 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
555 break;
556 case 0x29: /* DISPON */
557 s->onoff = 1;
558 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
559 break;
560
561 case 0x2a: /* CASET */
562 case 0x2b: /* RASET */
563 case 0x2c: /* RAMWR */
564 case 0x2d: /* RGBSET */
565 case 0x2e: /* RAMRD */
566 case 0x30: /* PTLAR */
567 case 0x33: /* SCRLAR */
568 goto bad_cmd;
569
570 case 0x34: /* TEOFF */
571 s->te = 0;
572 break;
573 case 0x35: /* TEON */
574 if (!s->pm)
575 s->te = 1;
576 else if (s->pm < 0)
577 s->pm = 1;
578 break;
579
580 case 0x36: /* MADCTR */
581 goto bad_cmd;
582
583 case 0x37: /* VSCSAD */
584 s->partial = 0;
585 s->normal = 0;
586 s->vscr = 1;
587 break;
588
589 case 0x38: /* IDMOFF */
590 case 0x39: /* IDMON */
591 case 0x3a: /* COLMOD */
592 goto bad_cmd;
593
594 case 0xb0: /* CLKINT / DISCTL */
595 case 0xb1: /* CLKEXT */
596 if (s->pm < 0)
597 s->pm = 2;
598 break;
599
600 case 0xb4: /* FRMSEL */
601 break;
602
603 case 0xb5: /* FRM8SEL */
604 case 0xb6: /* TMPRNG / INIESC */
605 case 0xb7: /* TMPHIS / NOP2 */
606 case 0xb8: /* TMPREAD / MADCTL */
607 case 0xba: /* DISTCTR */
608 case 0xbb: /* EPVOL */
609 goto bad_cmd;
610
611 case 0xbd: /* Unknown */
612 s->p = 0;
613 s->resp[0] = 0;
614 s->resp[1] = 1;
615 break;
616
617 case 0xc2: /* IFMOD */
618 if (s->pm < 0)
619 s->pm = 2;
620 break;
621
622 case 0xc6: /* PWRCTL */
623 case 0xc7: /* PPWRCTL */
624 case 0xd0: /* EPWROUT */
625 case 0xd1: /* EPWRIN */
626 case 0xd4: /* RDEV */
627 case 0xd5: /* RDRR */
628 goto bad_cmd;
629
630 case 0xda: /* RDID1 */
631 s->p = 0;
632 s->resp[0] = (s->id >> 16) & 0xff;
633 break;
634 case 0xdb: /* RDID2 */
635 s->p = 0;
636 s->resp[0] = (s->id >> 8) & 0xff;
637 break;
638 case 0xdc: /* RDID3 */
639 s->p = 0;
640 s->resp[0] = (s->id >> 0) & 0xff;
641 break;
642
643 default:
644 bad_cmd:
645 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
646 break;
647 }
648
649 return ret;
650}
651
652static void *mipid_init(void)
653{
654 struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s));
655
656 s->id = 0x838f03;
657 mipid_reset(s);
658
659 return s;
660}
661
e927bb00 662static void n8x0_spi_setup(struct n800_s *s)
7e7c5e4c 663{
e927bb00 664 void *tsc = s->ts.opaque;
7e7c5e4c
AZ		 665 void *mipid = mipid_init();
666
e927bb00 667 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
7e7c5e4c
AZ		 668 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
669}
670
671/* This task is normally performed by the bootloader. If we're loading
672 * a kernel directly, we need to enable the Blizzard ourselves. */
673static void n800_dss_init(struct rfbi_chip_s *chip)
674{
675 uint8_t *fb_blank;
676
677 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
678 chip->write(chip->opaque, 1, 0x64);
679 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
680 chip->write(chip->opaque, 1, 0x1e);
681 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
682 chip->write(chip->opaque, 1, 0xe0);
683 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
684 chip->write(chip->opaque, 1, 0x01);
685 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
686 chip->write(chip->opaque, 1, 0x06);
687 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
688 chip->write(chip->opaque, 1, 1); /* Enable bit */
689
690 chip->write(chip->opaque, 0, 0x6c);
691 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
692 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
693 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
694 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
695 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
696 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
697 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
698 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
699 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
700 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
701 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
702 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
703 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
704 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
705 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
706 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
707 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
708 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
709
710 fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
711 /* Display Memory Data Port */
712 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
6f0953b1 713 qemu_free(fb_blank);
7e7c5e4c
AZ		 714}
715
3023f332 716static void n8x0_dss_setup(struct n800_s *s)
7e7c5e4c 717{
b9d38e95 718 s->blizzard.opaque = s1d13745_init(NULL);
7e7c5e4c
AZ		 719 s->blizzard.block = s1d13745_write_block;
720 s->blizzard.write = s1d13745_write;
721 s->blizzard.read = s1d13745_read;
722
723 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
724}
725
e927bb00 726static void n8x0_cbus_setup(struct n800_s *s)
7e7c5e4c 727{
77831c20
JR		 728 qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO);
729 qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO);
730 qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO);
7e7c5e4c 731
bc24a225 732 CBus *cbus = cbus_init(dat_out);
7e7c5e4c 733
77831c20
JR		 734 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
735 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
736 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
7e7c5e4c
AZ		 737
738 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
739 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
740}
741
58a26b47
AZ		 742static void n8x0_uart_setup(struct n800_s *s)
743{
744 CharDriverState *radio = uart_hci_init(
77831c20 745 qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
58a26b47 746
77831c20 747 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO,
58a26b47 748 csrhci_pins_get(radio)[csrhci_pin_reset]);
77831c20 749 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO,
58a26b47
AZ		 750 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
751
752 omap_uart_attach(s->cpu->uart[BT_UART], radio);
753}
754
e927bb00 755static void n8x0_usb_power_cb(void *opaque, int line, int level)
942ac052
AZ		 756{
757 struct n800_s *s = opaque;
758
759 tusb6010_power(s->usb, level);
760}
761
e927bb00 762static void n8x0_usb_setup(struct n800_s *s)
942ac052 763{
77831c20 764 qemu_irq tusb_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO);
e927bb00 765 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
bc24a225 766 TUSBState *tusb = tusb6010_init(tusb_irq);
942ac052
AZ		 767
768 /* Using the NOR interface */
769 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
b9d38e95 770 tusb6010_async_io(tusb), NULL, NULL, tusb);
942ac052 771 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
b9d38e95 772 tusb6010_sync_io(tusb), NULL, NULL, tusb);
942ac052
AZ		 773
774 s->usb = tusb;
77831c20 775 qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
942ac052
AZ		 776}
777
d238db7f
AZ		 778/* Setup done before the main bootloader starts by some early setup code
779 * - used when we want to run the main bootloader in emulation. This
780 * isn't documented. */
781static uint32_t n800_pinout[104] = {
782 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
783 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
784 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
785 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
786 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
787 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
788 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
789 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
790 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
791 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
792 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
793 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
794 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
795 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
796 0x00000000, 0x00000038, 0x00340000, 0x00000000,
797 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
798 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
799 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
800 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
801 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
802 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
803 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
804 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
805 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
806 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
807 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
808};
809
810static void n800_setup_nolo_tags(void *sram_base)
811{
812 int i;
813 uint32_t *p = sram_base + 0x8000;
814 uint32_t *v = sram_base + 0xa000;
815
816 memset(p, 0, 0x3000);
817
818 strcpy((void *) (p + 0), "QEMU N800");
819
820 strcpy((void *) (p + 8), "F5");
821
822 stl_raw(p + 10, 0x04f70000);
823 strcpy((void *) (p + 9), "RX-34");
824
825 /* RAM size in MB? */
826 stl_raw(p + 12, 0x80);
827
828 /* Pointer to the list of tags */
829 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
830
831 /* The NOLO tags start here */
832 p = sram_base + 0x9000;
833#define ADD_TAG(tag, len) \
834 stw_raw((uint16_t *) p + 0, tag); \
835 stw_raw((uint16_t *) p + 1, len); p ++; \
836 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
837
838 /* OMAP STI console? Pin out settings? */
839 ADD_TAG(0x6e01, 414);
b1503cda 840 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
d238db7f
AZ		 841 stl_raw(v ++, n800_pinout[i]);
842
843 /* Kernel memsize? */
844 ADD_TAG(0x6e05, 1);
845 stl_raw(v ++, 2);
846
847 /* NOLO serial console */
848 ADD_TAG(0x6e02, 4);
849 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
850
851#if 0
852 /* CBUS settings (Retu/AVilma) */
853 ADD_TAG(0x6e03, 6);
854 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
855 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
856 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
857 v += 2;
858#endif
859
860 /* Nokia ASIC BB5 (Retu/Tahvo) */
861 ADD_TAG(0x6e0a, 4);
862 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
863 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
864 v ++;
865
866 /* LCD console? */
867 ADD_TAG(0x6e04, 4);
868 stw_raw((uint16_t *) v + 0, 30); /* ??? */
869 stw_raw((uint16_t *) v + 1, 24); /* ??? */
870 v ++;
871
872#if 0
873 /* LCD settings */
874 ADD_TAG(0x6e06, 2);
875 stw_raw((uint16_t *) (v ++), 15); /* ??? */
876#endif
877
878 /* I^2C (Menelaus) */
879 ADD_TAG(0x6e07, 4);
880 stl_raw(v ++, 0x00720000); /* ??? */
881
882 /* Unknown */
883 ADD_TAG(0x6e0b, 6);
884 stw_raw((uint16_t *) v + 0, 94); /* ??? */
885 stw_raw((uint16_t *) v + 1, 23); /* ??? */
886 stw_raw((uint16_t *) v + 2, 0); /* ??? */
887 v += 2;
888
889 /* OMAP gpio switch info */
890 ADD_TAG(0x6e0c, 80);
891 strcpy((void *) v, "bat_cover"); v += 3;
892 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
893 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
894 v += 2;
895 strcpy((void *) v, "cam_act"); v += 3;
896 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
897 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
898 v += 2;
899 strcpy((void *) v, "cam_turn"); v += 3;
900 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
901 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
902 v += 2;
903 strcpy((void *) v, "headphone"); v += 3;
904 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
905 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
906 v += 2;
907
908 /* Bluetooth */
909 ADD_TAG(0x6e0e, 12);
910 stl_raw(v ++, 0x5c623d01); /* ??? */
911 stl_raw(v ++, 0x00000201); /* ??? */
912 stl_raw(v ++, 0x00000000); /* ??? */
913
914 /* CX3110x WLAN settings */
915 ADD_TAG(0x6e0f, 8);
916 stl_raw(v ++, 0x00610025); /* ??? */
917 stl_raw(v ++, 0xffff0057); /* ??? */
918
919 /* MMC host settings */
920 ADD_TAG(0x6e10, 12);
921 stl_raw(v ++, 0xffff000f); /* ??? */
922 stl_raw(v ++, 0xffffffff); /* ??? */
923 stl_raw(v ++, 0x00000060); /* ??? */
924
925 /* OneNAND chip select */
926 ADD_TAG(0x6e11, 10);
927 stl_raw(v ++, 0x00000401); /* ??? */
928 stl_raw(v ++, 0x0002003a); /* ??? */
929 stl_raw(v ++, 0x00000002); /* ??? */
930
931 /* TEA5761 sensor settings */
932 ADD_TAG(0x6e12, 2);
933 stl_raw(v ++, 93); /* GPIO num ??? */
934
935#if 0
936 /* Unknown tag */
937 ADD_TAG(6e09, 0);
938
939 /* Kernel UART / console */
940 ADD_TAG(6e12, 0);
941#endif
942
943 /* End of the list */
944 stl_raw(p ++, 0x00000000);
945 stl_raw(p ++, 0x00000000);
946}
947
7e7c5e4c
AZ		 948/* This task is normally performed by the bootloader. If we're loading
949 * a kernel directly, we need to set up GPMC mappings ourselves. */
950static void n800_gpmc_init(struct n800_s *s)
951{
952 uint32_t config7 =
953 (0xf << 8) | /* MASKADDRESS */
954 (1 << 6) | /* CSVALID */
955 (4 << 0); /* BASEADDRESS */
956
957 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
958 (void *) &config7, sizeof(config7));
959}
960
961/* Setup sequence done by the bootloader */
e927bb00 962static void n8x0_boot_init(void *opaque)
7e7c5e4c
AZ		 963{
964 struct n800_s *s = (struct n800_s *) opaque;
965 uint32_t buf;
966
967 /* PRCM setup */
968#define omap_writel(addr, val) \
969 buf = (val); \
970 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
971
972 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
973 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
974 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
975 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
976 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
977 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
978 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
979 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
980 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
981 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
982 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
983 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
984 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
985 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
986 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
987 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
988 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
989 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
990 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
991 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
992 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
993 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
994 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
995 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
996 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
997 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
998 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
999 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1000 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1001 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1002 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1003 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1004 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1005 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1006 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1007 (0x78 << 12) | (6 << 8));
1008 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1009
1010 /* GPMC setup */
1011 n800_gpmc_init(s);
1012
1013 /* Video setup */
1014 n800_dss_init(&s->blizzard);
1015
1016 /* CPU setup */
7e7c5e4c 1017 s->cpu->env->GE = 0x5;
0941041e
AZ		 1018
1019 /* If the machine has a slided keyboard, open it */
1020 if (s->kbd)
77831c20 1021 qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO));
7e7c5e4c
AZ		 1022}
1023
1024#define OMAP_TAG_NOKIA_BT 0x4e01
1025#define OMAP_TAG_WLAN_CX3110X 0x4e02
1026#define OMAP_TAG_CBUS 0x4e03
1027#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1028
e927bb00
AZ		 1029static struct omap_gpiosw_info_s {
1030 const char *name;
1031 int line;
1032 int type;
1033} n800_gpiosw_info[] = {
1034 {
1035 "bat_cover", N800_BAT_COVER_GPIO,
1036 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1037 }, {
1038 "cam_act", N800_CAM_ACT_GPIO,
1039 OMAP_GPIOSW_TYPE_ACTIVITY,
1040 }, {
1041 "cam_turn", N800_CAM_TURN_GPIO,
1042 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1043 }, {
1044 "headphone", N8X0_HEADPHONE_GPIO,
1045 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1046 },
b9d38e95 1047 { NULL }
e927bb00
AZ		 1048}, n810_gpiosw_info[] = {
1049 {
1050 "gps_reset", N810_GPS_RESET_GPIO,
1051 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1052 }, {
1053 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1054 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1055 }, {
1056 "headphone", N8X0_HEADPHONE_GPIO,
1057 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1058 }, {
1059 "kb_lock", N810_KB_LOCK_GPIO,
1060 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1061 }, {
1062 "sleepx_led", N810_SLEEPX_LED_GPIO,
1063 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1064 }, {
1065 "slide", N810_SLIDE_GPIO,
1066 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1067 },
b9d38e95 1068 { NULL }
e927bb00
AZ		 1069};
1070
1071static struct omap_partition_info_s {
1072 uint32_t offset;
1073 uint32_t size;
1074 int mask;
1075 const char *name;
1076} n800_part_info[] = {
1077 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1078 { 0x00020000, 0x00060000, 0x0, "config" },
1079 { 0x00080000, 0x00200000, 0x0, "kernel" },
1080 { 0x00280000, 0x00200000, 0x3, "initfs" },
1081 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1082
b9d38e95 1083 { 0, 0, 0, NULL }
e927bb00
AZ		 1084}, n810_part_info[] = {
1085 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1086 { 0x00020000, 0x00060000, 0x0, "config" },
1087 { 0x00080000, 0x00220000, 0x0, "kernel" },
1088 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1089 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1090
b9d38e95 1091 { 0, 0, 0, NULL }
e927bb00
AZ		 1092};
1093
c227f099 1094static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
c580d92b 1095
e927bb00 1096static int n8x0_atag_setup(void *p, int model)
7e7c5e4c
AZ		 1097{
1098 uint8_t *b;
1099 uint16_t *w;
1100 uint32_t *l;
e927bb00
AZ		 1101 struct omap_gpiosw_info_s *gpiosw;
1102 struct omap_partition_info_s *partition;
1103 const char *tag;
7e7c5e4c
AZ		 1104
1105 w = p;
1106
1107 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1108 stw_raw(w ++, 4); /* u16 len */
1109 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1110 w ++;
1111
e927bb00
AZ		 1112#if 0
1113 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
7e7c5e4c 1114 stw_raw(w ++, 4); /* u16 len */
c580d92b 1115 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
e927bb00
AZ		 1116 stw_raw(w ++, 115200); /* u32 console_speed */
1117#endif
1118
1119 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1120 stw_raw(w ++, 36); /* u16 len */
1121 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1122 w += 8;
1123 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1124 w += 8;
1125 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1126 stw_raw(w ++, 24); /* u8 data_lines */
7e7c5e4c
AZ		 1127
1128 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1129 stw_raw(w ++, 8); /* u16 len */
1130 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1131 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1132 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1133 w ++;
1134
e927bb00
AZ		 1135 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1136 stw_raw(w ++, 4); /* u16 len */
1137 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1138 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1139
1140 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1141 for (; gpiosw->name; gpiosw ++) {
1142 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1143 stw_raw(w ++, 20); /* u16 len */
1144 strcpy((void *) w, gpiosw->name); /* char name[12] */
1145 w += 6;
1146 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1147 stw_raw(w ++, gpiosw->type);
1148 stw_raw(w ++, 0);
1149 stw_raw(w ++, 0);
1150 }
7e7c5e4c
AZ		 1151
1152 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1153 stw_raw(w ++, 12); /* u16 len */
1154 b = (void *) w;
1155 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
e927bb00 1156 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
7e7c5e4c 1157 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
e927bb00 1158 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
c580d92b
AZ		 1159 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1160 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
7e7c5e4c
AZ		 1161 b += 6;
1162 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1163 w = (void *) b;
1164
1165 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1166 stw_raw(w ++, 8); /* u16 len */
1167 stw_raw(w ++, 0x25); /* u8 chip_type */
e927bb00
AZ		 1168 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1169 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
7e7c5e4c
AZ		 1170 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1171
1172 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1173 stw_raw(w ++, 16); /* u16 len */
e927bb00
AZ		 1174 if (model == 810) {
1175 stw_raw(w ++, 0x23f); /* unsigned flags */
1176 stw_raw(w ++, -1); /* s16 power_pin */
1177 stw_raw(w ++, -1); /* s16 switch_pin */
1178 stw_raw(w ++, -1); /* s16 wp_pin */
1179 stw_raw(w ++, 0x240); /* unsigned flags */
1180 stw_raw(w ++, 0xc000); /* s16 power_pin */
1181 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1182 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1183 } else {
1184 stw_raw(w ++, 0xf); /* unsigned flags */
1185 stw_raw(w ++, -1); /* s16 power_pin */
1186 stw_raw(w ++, -1); /* s16 switch_pin */
1187 stw_raw(w ++, -1); /* s16 wp_pin */
1188 stw_raw(w ++, 0); /* unsigned flags */
1189 stw_raw(w ++, 0); /* s16 power_pin */
1190 stw_raw(w ++, 0); /* s16 switch_pin */
1191 stw_raw(w ++, 0); /* s16 wp_pin */
1192 }
7e7c5e4c
AZ		 1193
1194 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1195 stw_raw(w ++, 4); /* u16 len */
e927bb00 1196 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
7e7c5e4c
AZ		 1197 w ++;
1198
e927bb00
AZ		 1199 partition = (model == 810) ? n810_part_info : n800_part_info;
1200 for (; partition->name; partition ++) {
1201 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1202 stw_raw(w ++, 28); /* u16 len */
1203 strcpy((void *) w, partition->name); /* char name[16] */
1204 l = (void *) (w + 8);
1205 stl_raw(l ++, partition->size); /* unsigned int size */
1206 stl_raw(l ++, partition->offset); /* unsigned int offset */
1207 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1208 w = (void *) l;
1209 }
7e7c5e4c
AZ		 1210
1211 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1212 stw_raw(w ++, 12); /* u16 len */
1213#if 0
1214 strcpy((void *) w, "por"); /* char reason_str[12] */
1215 strcpy((void *) w, "charger"); /* char reason_str[12] */
1216 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1217 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1218 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1219 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1220 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1221 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1222 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1223 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1224#else
1225 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1226#endif
1227 w += 6;
1228
e927bb00 1229 tag = (model == 810) ? "RX-44" : "RX-34";
7e7c5e4c
AZ		 1230 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1231 stw_raw(w ++, 24); /* u16 len */
1232 strcpy((void *) w, "product"); /* char component[12] */
1233 w += 6;
e927bb00 1234 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c
AZ		 1235 w += 6;
1236
1237 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1238 stw_raw(w ++, 24); /* u16 len */
1239 strcpy((void *) w, "hw-build"); /* char component[12] */
1240 w += 6;
e927bb00 1241 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
7e7c5e4c
AZ		 1242 w += 6;
1243
e927bb00 1244 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
7e7c5e4c
AZ		 1245 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1246 stw_raw(w ++, 24); /* u16 len */
1247 strcpy((void *) w, "nolo"); /* char component[12] */
1248 w += 6;
e927bb00 1249 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c 1250 w += 6;
7e7c5e4c
AZ		 1251
1252 return (void *) w - p;
1253}
1254
462a8bc6 1255static int n800_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1256{
1257 return n8x0_atag_setup(p, 800);
1258}
7e7c5e4c 1259
462a8bc6 1260static int n810_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1261{
1262 return n8x0_atag_setup(p, 810);
1263}
1264
c227f099 1265static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
3023f332 1266 const char *kernel_filename,
e927bb00
AZ		 1267 const char *kernel_cmdline, const char *initrd_filename,
1268 const char *cpu_model, struct arm_boot_info *binfo, int model)
7e7c5e4c
AZ		 1269{
1270 struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
e927bb00 1271 int sdram_size = binfo->ram_size;
09218951 1272 DisplayState *ds;
7e7c5e4c 1273
3023f332 1274 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
7e7c5e4c 1275
0941041e
AZ		 1276 /* Setup peripherals
1277 *
1278 * Believed external peripherals layout in the N810:
1279 * (spi bus 1)
1280 * tsc2005
1281 * lcd_mipid
1282 * (spi bus 2)
1283 * Conexant cx3110x (WLAN)
1284 * optional: pc2400m (WiMAX)
1285 * (i2c bus 0)
1286 * TLV320AIC33 (audio codec)
1287 * TCM825x (camera by Toshiba)
1288 * lp5521 (clever LEDs)
1289 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1290 * lm8323 (keypad, manf 00, rev 04)
1291 * (i2c bus 1)
1292 * tmp105 (temperature sensor, hwmon)
1293 * menelaus (pm)
d238db7f
AZ		 1294 * (somewhere on i2c - maybe N800-only)
1295 * tea5761 (FM tuner)
1296 * (serial 0)
1297 * GPS
1298 * (some serial port)
1299 * csr41814 (Bluetooth)
0941041e 1300 */
e927bb00 1301 n8x0_gpio_setup(s);
7e7c5e4c 1302 n8x0_nand_setup(s);
e927bb00
AZ		 1303 n8x0_i2c_setup(s);
1304 if (model == 800)
1305 n800_tsc_kbd_setup(s);
1d4e547b 1306 else if (model == 810) {
e927bb00 1307 n810_tsc_setup(s);
1d4e547b
AZ		 1308 n810_kbd_setup(s);
1309 }
e927bb00 1310 n8x0_spi_setup(s);
3023f332 1311 n8x0_dss_setup(s);
e927bb00 1312 n8x0_cbus_setup(s);
58a26b47 1313 n8x0_uart_setup(s);
942ac052 1314 if (usb_enabled)
e927bb00 1315 n8x0_usb_setup(s);
7e7c5e4c 1316
7e7c5e4c
AZ		 1317 if (kernel_filename) {
1318 /* Or at the linux loader. */
e927bb00
AZ		 1319 binfo->kernel_filename = kernel_filename;
1320 binfo->kernel_cmdline = kernel_cmdline;
1321 binfo->initrd_filename = initrd_filename;
1322 arm_load_kernel(s->cpu->env, binfo);
7e7c5e4c 1323
a08d4367 1324 qemu_register_reset(n8x0_boot_init, s);
7e7c5e4c
AZ		 1325 }
1326
2e55e842 1327 if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) {
dcac9679 1328 int rom_size;
5c130f65 1329 uint8_t nolo_tags[0x10000];
d238db7f
AZ		 1330 /* No, wait, better start at the ROM. */
1331 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1332
1333 /* This is intended for loading the `secondary.bin' program from
1334 * Nokia images (the NOLO bootloader). The entry point seems
1335 * to be at OMAP2_Q2_BASE + 0x400000.
1336 *
1337 * The `2nd.bin' files contain some kind of earlier boot code and
1338 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1339 *
1340 * The code above is for loading the `zImage' file from Nokia
1341 * images. */
2e55e842 1342 rom_size = load_image_targphys(option_rom[0].name,
dcac9679
PB		 1343 OMAP2_Q2_BASE + 0x400000,
1344 sdram_size - 0x400000);
1345 printf("%i bytes of image loaded\n", rom_size);
d238db7f 1346
5c130f65
PB		 1347 n800_setup_nolo_tags(nolo_tags);
1348 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
d238db7f 1349 }
c60e08d9
PB		 1350 /* FIXME: We shouldn't really be doing this here. The LCD controller
1351 will set the size once configured, so this just sets an initial
1352 size until the guest activates the display. */
09218951 1353 ds = get_displaystate();
7b5d76da 1354 ds->surface = qemu_resize_displaysurface(ds, 800, 480);
7d957bd8 1355 dpy_resize(ds);
7e7c5e4c
AZ		 1356}
1357
e927bb00
AZ		 1358static struct arm_boot_info n800_binfo = {
1359 .loader_start = OMAP2_Q2_BASE,
1360 /* Actually two chips of 0x4000000 bytes each */
1361 .ram_size = 0x08000000,
1362 .board_id = 0x4f7,
1363 .atag_board = n800_atag_setup,
1364};
1365
1366static struct arm_boot_info n810_binfo = {
1367 .loader_start = OMAP2_Q2_BASE,
1368 /* Actually two chips of 0x4000000 bytes each */
1369 .ram_size = 0x08000000,
1370 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1371 * used by some older versions of the bootloader and 5555 is used
1372 * instead (including versions that shipped with many devices). */
1373 .board_id = 0x60c,
1374 .atag_board = n810_atag_setup,
1375};
1376
c227f099 1377static void n800_init(ram_addr_t ram_size,
3023f332 1378 const char *boot_device,
e927bb00
AZ		 1379 const char *kernel_filename, const char *kernel_cmdline,
1380 const char *initrd_filename, const char *cpu_model)
1381{
3023f332 1382 return n8x0_init(ram_size, boot_device,
e927bb00
AZ		 1383 kernel_filename, kernel_cmdline, initrd_filename,
1384 cpu_model, &n800_binfo, 800);
1385}
1386
c227f099 1387static void n810_init(ram_addr_t ram_size,
3023f332 1388 const char *boot_device,
e927bb00
AZ		 1389 const char *kernel_filename, const char *kernel_cmdline,
1390 const char *initrd_filename, const char *cpu_model)
1391{
3023f332 1392 return n8x0_init(ram_size, boot_device,
e927bb00
AZ		 1393 kernel_filename, kernel_cmdline, initrd_filename,
1394 cpu_model, &n810_binfo, 810);
1395}
1396
f80f9ec9 1397static QEMUMachine n800_machine = {
4b32e168
AL		 1398 .name = "n800",
1399 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1400 .init = n800_init,
7e7c5e4c 1401};
e927bb00 1402
f80f9ec9 1403static QEMUMachine n810_machine = {
4b32e168
AL		 1404 .name = "n810",
1405 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1406 .init = n810_init,
e927bb00 1407};
f80f9ec9
AL		 1408
1409static void nseries_machine_init(void)
1410{
1411 qemu_register_machine(&n800_machine);
1412 qemu_register_machine(&n810_machine);
1413}
1414
1415machine_init(nseries_machine_init);
QEMU mirror