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1/*
2 * QEMU NVRAM emulation for DS1225Y chip
02cb1585 3 *
bcc4e41f 4 * Copyright (c) 2007-2008 Hervé Poussineau
02cb1585 5 *
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
0430891c 25#include "qemu/osdep.h"
83c9f4ca 26#include "hw/sysbus.h"
d43ed9ec 27#include "trace.h"
296097f7 28#include "qemu/error-report.h"
0b8fa32f 29#include "qemu/module.h"
30aa5c0d 30
cd3e2409 31typedef struct {
871321ac 32 MemoryRegion iomem;
02cb1585 33 uint32_t chip_size;
cd3e2409 34 char *filename;
3a230256 35 FILE *file;
02cb1585 36 uint8_t *contents;
cd3e2409 37} NvRamState;
30aa5c0d 38
a8170e5e 39static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
30aa5c0d 40{
cd3e2409 41 NvRamState *s = opaque;
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42 uint32_t val;
43
8da3ff18 44 val = s->contents[addr];
d43ed9ec 45 trace_nvram_read(addr, val);
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46 return val;
47}
30aa5c0d 48
a8170e5e 49static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
871321ac 50 unsigned size)
30aa5c0d 51{
cd3e2409 52 NvRamState *s = opaque;
30aa5c0d 53
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54 val &= 0xff;
55 trace_nvram_write(addr, s->contents[addr], val);
02cb1585 56
d43ed9ec 57 s->contents[addr] = val;
02cb1585 58 if (s->file) {
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59 fseek(s->file, addr, SEEK_SET);
60 fputc(val, s->file);
61 fflush(s->file);
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62 }
63}
64
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65static const MemoryRegionOps nvram_ops = {
66 .read = nvram_read,
67 .write = nvram_write,
68 .impl = {
69 .min_access_size = 1,
70 .max_access_size = 1,
71 },
72 .endianness = DEVICE_LITTLE_ENDIAN,
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73};
74
cd3e2409 75static int nvram_post_load(void *opaque, int version_id)
30aa5c0d 76{
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77 NvRamState *s = opaque;
78
79 /* Close file, as filename may has changed in load/store process */
80 if (s->file) {
3a230256 81 fclose(s->file);
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82 }
83
84 /* Write back nvram contents */
b7438458 85 s->file = s->filename ? fopen(s->filename, "wb") : NULL;
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86 if (s->file) {
87 /* Write back contents, as 'wb' mode cleaned the file */
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88 if (fwrite(s->contents, s->chip_size, 1, s->file) != 1) {
89 printf("nvram_post_load: short write\n");
90 }
91 fflush(s->file);
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92 }
93
94 return 0;
95}
96
97static const VMStateDescription vmstate_nvram = {
98 .name = "nvram",
99 .version_id = 0,
100 .minimum_version_id = 0,
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101 .post_load = nvram_post_load,
102 .fields = (VMStateField[]) {
103 VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0,
104 vmstate_info_uint8, uint8_t),
105 VMSTATE_END_OF_LIST()
106 }
107};
108
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109#define TYPE_DS1225Y "ds1225y"
110#define DS1225Y(obj) OBJECT_CHECK(SysBusNvRamState, (obj), TYPE_DS1225Y)
111
cd3e2409 112typedef struct {
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113 SysBusDevice parent_obj;
114
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115 NvRamState nvram;
116} SysBusNvRamState;
117
296097f7 118static void nvram_sysbus_realize(DeviceState *dev, Error **errp)
cd3e2409 119{
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120 SysBusNvRamState *sys = DS1225Y(dev);
121 NvRamState *s = &sys->nvram;
3a230256 122 FILE *file;
30aa5c0d 123
7267c094 124 s->contents = g_malloc0(s->chip_size);
02cb1585 125
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126 memory_region_init_io(&s->iomem, OBJECT(s), &nvram_ops, s,
127 "nvram", s->chip_size);
296097f7 128 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
cd3e2409 129
02cb1585 130 /* Read current file */
b7438458 131 file = s->filename ? fopen(s->filename, "rb") : NULL;
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132 if (file) {
133 /* Read nvram contents */
3a230256 134 if (fread(s->contents, s->chip_size, 1, file) != 1) {
296097f7 135 error_report("nvram_sysbus_realize: short read");
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136 }
137 fclose(file);
02cb1585 138 }
cd3e2409 139 nvram_post_load(s, 0);
30aa5c0d 140}
cd3e2409 141
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142static Property nvram_sysbus_properties[] = {
143 DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
144 DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
145 DEFINE_PROP_END_OF_LIST(),
146};
147
148static void nvram_sysbus_class_init(ObjectClass *klass, void *data)
149{
39bffca2 150 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 151
296097f7 152 dc->realize = nvram_sysbus_realize;
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153 dc->vmsd = &vmstate_nvram;
154 dc->props = nvram_sysbus_properties;
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155}
156
8c43a6f0 157static const TypeInfo nvram_sysbus_info = {
8c1892cf 158 .name = TYPE_DS1225Y,
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159 .parent = TYPE_SYS_BUS_DEVICE,
160 .instance_size = sizeof(SysBusNvRamState),
161 .class_init = nvram_sysbus_class_init,
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162};
163
83f7d43a 164static void nvram_register_types(void)
cd3e2409 165{
39bffca2 166 type_register_static(&nvram_sysbus_info);
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167}
168
83f7d43a 169type_init(nvram_register_types)