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Commit | Line | Data |
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30aa5c0d AJ |
1 | /* |
2 | * QEMU NVRAM emulation for DS1225Y chip | |
02cb1585 | 3 | * |
bcc4e41f | 4 | * Copyright (c) 2007-2008 Hervé Poussineau |
02cb1585 | 5 | * |
30aa5c0d AJ |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
0430891c | 25 | #include "qemu/osdep.h" |
a27bd6c7 | 26 | #include "hw/qdev-properties.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
d43ed9ec | 29 | #include "trace.h" |
296097f7 | 30 | #include "qemu/error-report.h" |
0b8fa32f | 31 | #include "qemu/module.h" |
db1015e9 | 32 | #include "qom/object.h" |
30aa5c0d | 33 | |
cd3e2409 | 34 | typedef struct { |
871321ac | 35 | MemoryRegion iomem; |
02cb1585 | 36 | uint32_t chip_size; |
cd3e2409 | 37 | char *filename; |
3a230256 | 38 | FILE *file; |
02cb1585 | 39 | uint8_t *contents; |
cd3e2409 | 40 | } NvRamState; |
30aa5c0d | 41 | |
a8170e5e | 42 | static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size) |
30aa5c0d | 43 | { |
cd3e2409 | 44 | NvRamState *s = opaque; |
02cb1585 AJ |
45 | uint32_t val; |
46 | ||
8da3ff18 | 47 | val = s->contents[addr]; |
d43ed9ec | 48 | trace_nvram_read(addr, val); |
02cb1585 AJ |
49 | return val; |
50 | } | |
30aa5c0d | 51 | |
a8170e5e | 52 | static void nvram_write(void *opaque, hwaddr addr, uint64_t val, |
871321ac | 53 | unsigned size) |
30aa5c0d | 54 | { |
cd3e2409 | 55 | NvRamState *s = opaque; |
30aa5c0d | 56 | |
d43ed9ec HP |
57 | val &= 0xff; |
58 | trace_nvram_write(addr, s->contents[addr], val); | |
02cb1585 | 59 | |
d43ed9ec | 60 | s->contents[addr] = val; |
02cb1585 | 61 | if (s->file) { |
3a230256 JQ |
62 | fseek(s->file, addr, SEEK_SET); |
63 | fputc(val, s->file); | |
64 | fflush(s->file); | |
30aa5c0d AJ |
65 | } |
66 | } | |
67 | ||
871321ac AK |
68 | static const MemoryRegionOps nvram_ops = { |
69 | .read = nvram_read, | |
70 | .write = nvram_write, | |
71 | .impl = { | |
72 | .min_access_size = 1, | |
73 | .max_access_size = 1, | |
74 | }, | |
75 | .endianness = DEVICE_LITTLE_ENDIAN, | |
30aa5c0d AJ |
76 | }; |
77 | ||
cd3e2409 | 78 | static int nvram_post_load(void *opaque, int version_id) |
30aa5c0d | 79 | { |
cd3e2409 HP |
80 | NvRamState *s = opaque; |
81 | ||
82 | /* Close file, as filename may has changed in load/store process */ | |
83 | if (s->file) { | |
3a230256 | 84 | fclose(s->file); |
cd3e2409 HP |
85 | } |
86 | ||
87 | /* Write back nvram contents */ | |
b7438458 | 88 | s->file = s->filename ? fopen(s->filename, "wb") : NULL; |
cd3e2409 HP |
89 | if (s->file) { |
90 | /* Write back contents, as 'wb' mode cleaned the file */ | |
3a230256 JQ |
91 | if (fwrite(s->contents, s->chip_size, 1, s->file) != 1) { |
92 | printf("nvram_post_load: short write\n"); | |
93 | } | |
94 | fflush(s->file); | |
cd3e2409 HP |
95 | } |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | static const VMStateDescription vmstate_nvram = { | |
101 | .name = "nvram", | |
102 | .version_id = 0, | |
103 | .minimum_version_id = 0, | |
cd3e2409 HP |
104 | .post_load = nvram_post_load, |
105 | .fields = (VMStateField[]) { | |
106 | VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0, | |
107 | vmstate_info_uint8, uint8_t), | |
108 | VMSTATE_END_OF_LIST() | |
109 | } | |
110 | }; | |
111 | ||
8c1892cf | 112 | #define TYPE_DS1225Y "ds1225y" |
db1015e9 | 113 | typedef struct SysBusNvRamState SysBusNvRamState; |
8110fa1d EH |
114 | DECLARE_INSTANCE_CHECKER(SysBusNvRamState, DS1225Y, |
115 | TYPE_DS1225Y) | |
8c1892cf | 116 | |
db1015e9 | 117 | struct SysBusNvRamState { |
8c1892cf AF |
118 | SysBusDevice parent_obj; |
119 | ||
cd3e2409 | 120 | NvRamState nvram; |
db1015e9 | 121 | }; |
cd3e2409 | 122 | |
296097f7 | 123 | static void nvram_sysbus_realize(DeviceState *dev, Error **errp) |
cd3e2409 | 124 | { |
8c1892cf AF |
125 | SysBusNvRamState *sys = DS1225Y(dev); |
126 | NvRamState *s = &sys->nvram; | |
3a230256 | 127 | FILE *file; |
30aa5c0d | 128 | |
7267c094 | 129 | s->contents = g_malloc0(s->chip_size); |
02cb1585 | 130 | |
eedfac6f PB |
131 | memory_region_init_io(&s->iomem, OBJECT(s), &nvram_ops, s, |
132 | "nvram", s->chip_size); | |
296097f7 | 133 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
cd3e2409 | 134 | |
02cb1585 | 135 | /* Read current file */ |
b7438458 | 136 | file = s->filename ? fopen(s->filename, "rb") : NULL; |
02cb1585 AJ |
137 | if (file) { |
138 | /* Read nvram contents */ | |
3a230256 | 139 | if (fread(s->contents, s->chip_size, 1, file) != 1) { |
296097f7 | 140 | error_report("nvram_sysbus_realize: short read"); |
3a230256 JQ |
141 | } |
142 | fclose(file); | |
02cb1585 | 143 | } |
cd3e2409 | 144 | nvram_post_load(s, 0); |
30aa5c0d | 145 | } |
cd3e2409 | 146 | |
999e12bb AL |
147 | static Property nvram_sysbus_properties[] = { |
148 | DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000), | |
149 | DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename), | |
150 | DEFINE_PROP_END_OF_LIST(), | |
151 | }; | |
152 | ||
153 | static void nvram_sysbus_class_init(ObjectClass *klass, void *data) | |
154 | { | |
39bffca2 | 155 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 156 | |
296097f7 | 157 | dc->realize = nvram_sysbus_realize; |
39bffca2 | 158 | dc->vmsd = &vmstate_nvram; |
4f67d30b | 159 | device_class_set_props(dc, nvram_sysbus_properties); |
999e12bb AL |
160 | } |
161 | ||
8c43a6f0 | 162 | static const TypeInfo nvram_sysbus_info = { |
8c1892cf | 163 | .name = TYPE_DS1225Y, |
39bffca2 AL |
164 | .parent = TYPE_SYS_BUS_DEVICE, |
165 | .instance_size = sizeof(SysBusNvRamState), | |
166 | .class_init = nvram_sysbus_class_init, | |
cd3e2409 HP |
167 | }; |
168 | ||
83f7d43a | 169 | static void nvram_register_types(void) |
cd3e2409 | 170 | { |
39bffca2 | 171 | type_register_static(&nvram_sysbus_info); |
cd3e2409 HP |
172 | } |
173 | ||
83f7d43a | 174 | type_init(nvram_register_types) |