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Commit | Line | Data |
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3cce6243 BS |
1 | /* |
2 | * QEMU Firmware configuration device emulation | |
3 | * | |
4 | * Copyright (c) 2008 Gleb Natapov | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
922a01a0 | 24 | |
0430891c | 25 | #include "qemu/osdep.h" |
a8d25326 | 26 | #include "qemu-common.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
a4c0d1de | 28 | #include "sysemu/dma.h" |
71e8a915 | 29 | #include "sysemu/reset.h" |
cfc58cf3 | 30 | #include "hw/boards.h" |
0d09e41a | 31 | #include "hw/nvram/fw_cfg.h" |
a27bd6c7 | 32 | #include "hw/qdev-properties.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
ca77ee28 | 34 | #include "migration/qemu-file-types.h" |
d6454270 | 35 | #include "migration/vmstate.h" |
f6e35343 | 36 | #include "trace.h" |
1de7afc9 | 37 | #include "qemu/error-report.h" |
922a01a0 | 38 | #include "qemu/option.h" |
1de7afc9 | 39 | #include "qemu/config-file.h" |
f348b6d1 | 40 | #include "qemu/cutils.h" |
e12f3a13 | 41 | #include "qapi/error.h" |
394f0f72 | 42 | #include "hw/acpi/aml-build.h" |
3cce6243 | 43 | |
a5b3ebfd LE |
44 | #define FW_CFG_FILE_SLOTS_DFLT 0x20 |
45 | ||
a4c0d1de MM |
46 | /* FW_CFG_VERSION bits */ |
47 | #define FW_CFG_VERSION 0x01 | |
48 | #define FW_CFG_VERSION_DMA 0x02 | |
49 | ||
50 | /* FW_CFG_DMA_CONTROL bits */ | |
51 | #define FW_CFG_DMA_CTL_ERROR 0x01 | |
52 | #define FW_CFG_DMA_CTL_READ 0x02 | |
53 | #define FW_CFG_DMA_CTL_SKIP 0x04 | |
54 | #define FW_CFG_DMA_CTL_SELECT 0x08 | |
baf2d5bf | 55 | #define FW_CFG_DMA_CTL_WRITE 0x10 |
a4c0d1de | 56 | |
2cc06a88 KC |
57 | #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */ |
58 | ||
39736e18 | 59 | struct FWCfgEntry { |
ff06108b | 60 | uint32_t len; |
baf2d5bf | 61 | bool allow_write; |
3cce6243 BS |
62 | uint8_t *data; |
63 | void *callback_opaque; | |
6f6f4aec | 64 | FWCfgCallback select_cb; |
5f9252f7 | 65 | FWCfgWriteCallback write_cb; |
5712db6a LE |
66 | }; |
67 | ||
1f80b0d6 PMD |
68 | /** |
69 | * key_name: | |
70 | * | |
71 | * @key: The uint16 selector key. | |
72 | * | |
73 | * Returns: The stringified name if the selector refers to a well-known | |
74 | * numerically defined item, or NULL on key lookup failure. | |
75 | */ | |
76 | static const char *key_name(uint16_t key) | |
77 | { | |
78 | static const char *fw_cfg_wellknown_keys[FW_CFG_FILE_FIRST] = { | |
79 | [FW_CFG_SIGNATURE] = "signature", | |
80 | [FW_CFG_ID] = "id", | |
81 | [FW_CFG_UUID] = "uuid", | |
82 | [FW_CFG_RAM_SIZE] = "ram_size", | |
83 | [FW_CFG_NOGRAPHIC] = "nographic", | |
84 | [FW_CFG_NB_CPUS] = "nb_cpus", | |
85 | [FW_CFG_MACHINE_ID] = "machine_id", | |
86 | [FW_CFG_KERNEL_ADDR] = "kernel_addr", | |
87 | [FW_CFG_KERNEL_SIZE] = "kernel_size", | |
88 | [FW_CFG_KERNEL_CMDLINE] = "kernel_cmdline", | |
89 | [FW_CFG_INITRD_ADDR] = "initrd_addr", | |
90 | [FW_CFG_INITRD_SIZE] = "initdr_size", | |
91 | [FW_CFG_BOOT_DEVICE] = "boot_device", | |
92 | [FW_CFG_NUMA] = "numa", | |
93 | [FW_CFG_BOOT_MENU] = "boot_menu", | |
94 | [FW_CFG_MAX_CPUS] = "max_cpus", | |
95 | [FW_CFG_KERNEL_ENTRY] = "kernel_entry", | |
96 | [FW_CFG_KERNEL_DATA] = "kernel_data", | |
97 | [FW_CFG_INITRD_DATA] = "initrd_data", | |
98 | [FW_CFG_CMDLINE_ADDR] = "cmdline_addr", | |
99 | [FW_CFG_CMDLINE_SIZE] = "cmdline_size", | |
100 | [FW_CFG_CMDLINE_DATA] = "cmdline_data", | |
101 | [FW_CFG_SETUP_ADDR] = "setup_addr", | |
102 | [FW_CFG_SETUP_SIZE] = "setup_size", | |
103 | [FW_CFG_SETUP_DATA] = "setup_data", | |
104 | [FW_CFG_FILE_DIR] = "file_dir", | |
105 | }; | |
106 | ||
107 | if (key & FW_CFG_ARCH_LOCAL) { | |
b15c0f7d | 108 | return fw_cfg_arch_key_name(key); |
1f80b0d6 PMD |
109 | } |
110 | if (key < FW_CFG_FILE_FIRST) { | |
111 | return fw_cfg_wellknown_keys[key]; | |
112 | } | |
113 | ||
114 | return NULL; | |
115 | } | |
116 | ||
117 | static inline const char *trace_key_name(uint16_t key) | |
118 | { | |
119 | const char *name = key_name(key); | |
120 | ||
121 | return name ? name : "unknown"; | |
122 | } | |
123 | ||
3d3b8303 WX |
124 | #define JPG_FILE 0 |
125 | #define BMP_FILE 1 | |
126 | ||
3d1bba20 | 127 | static char *read_splashfile(char *filename, gsize *file_sizep, |
d09acb9b | 128 | int *file_typep) |
3d3b8303 | 129 | { |
9477c87e | 130 | GError *err = NULL; |
9477c87e | 131 | gchar *content; |
9f8863eb MA |
132 | int file_type; |
133 | unsigned int filehead; | |
3d3b8303 WX |
134 | int bmp_bpp; |
135 | ||
bed66336 LQ |
136 | if (!g_file_get_contents(filename, &content, file_sizep, &err)) { |
137 | error_report("failed to read splash file '%s': %s", | |
138 | filename, err->message); | |
9477c87e PB |
139 | g_error_free(err); |
140 | return NULL; | |
3d3b8303 | 141 | } |
9477c87e | 142 | |
3d3b8303 | 143 | /* check file size */ |
9477c87e PB |
144 | if (*file_sizep < 30) { |
145 | goto error; | |
3d3b8303 | 146 | } |
9477c87e | 147 | |
3d3b8303 | 148 | /* check magic ID */ |
3b777a79 | 149 | filehead = lduw_le_p(content); |
9477c87e | 150 | if (filehead == 0xd8ff) { |
3d3b8303 | 151 | file_type = JPG_FILE; |
9477c87e PB |
152 | } else if (filehead == 0x4d42) { |
153 | file_type = BMP_FILE; | |
3d3b8303 | 154 | } else { |
9477c87e | 155 | goto error; |
3d3b8303 | 156 | } |
9477c87e | 157 | |
3d3b8303 WX |
158 | /* check BMP bpp */ |
159 | if (file_type == BMP_FILE) { | |
3b777a79 | 160 | bmp_bpp = lduw_le_p(&content[28]); |
3d3b8303 | 161 | if (bmp_bpp != 24) { |
9477c87e | 162 | goto error; |
3d3b8303 WX |
163 | } |
164 | } | |
9477c87e | 165 | |
3d3b8303 | 166 | /* return values */ |
3d3b8303 | 167 | *file_typep = file_type; |
9477c87e PB |
168 | |
169 | return content; | |
170 | ||
171 | error: | |
172 | error_report("splash file '%s' format not recognized; must be JPEG " | |
173 | "or 24 bit BMP", filename); | |
174 | g_free(content); | |
175 | return NULL; | |
3d3b8303 WX |
176 | } |
177 | ||
178 | static void fw_cfg_bootsplash(FWCfgState *s) | |
179 | { | |
3d3b8303 | 180 | const char *boot_splash_filename = NULL; |
6912bb0b | 181 | const char *boot_splash_time = NULL; |
9477c87e | 182 | char *filename, *file_data; |
3d1bba20 | 183 | gsize file_size; |
9f8863eb | 184 | int file_type; |
3d3b8303 WX |
185 | |
186 | /* get user configuration */ | |
187 | QemuOptsList *plist = qemu_find_opts("boot-opts"); | |
188 | QemuOpts *opts = QTAILQ_FIRST(&plist->head); | |
6912bb0b LQ |
189 | boot_splash_filename = qemu_opt_get(opts, "splash"); |
190 | boot_splash_time = qemu_opt_get(opts, "splash-time"); | |
3d3b8303 WX |
191 | |
192 | /* insert splash time if user configurated */ | |
6912bb0b LQ |
193 | if (boot_splash_time) { |
194 | int64_t bst_val = qemu_opt_get_number(opts, "splash-time", -1); | |
3b3df3e5 LE |
195 | uint16_t bst_le16; |
196 | ||
3d3b8303 | 197 | /* validate the input */ |
6912bb0b LQ |
198 | if (bst_val < 0 || bst_val > 0xffff) { |
199 | error_report("splash-time is invalid," | |
200 | "it should be a value between 0 and 65535"); | |
201 | exit(1); | |
3d3b8303 WX |
202 | } |
203 | /* use little endian format */ | |
3b3df3e5 LE |
204 | bst_le16 = cpu_to_le16(bst_val); |
205 | fw_cfg_add_file(s, "etc/boot-menu-wait", | |
206 | g_memdup(&bst_le16, sizeof bst_le16), sizeof bst_le16); | |
3d3b8303 WX |
207 | } |
208 | ||
209 | /* insert splash file if user configurated */ | |
6912bb0b | 210 | if (boot_splash_filename) { |
3d3b8303 WX |
211 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename); |
212 | if (filename == NULL) { | |
6912bb0b | 213 | error_report("failed to find file '%s'", boot_splash_filename); |
3d3b8303 WX |
214 | return; |
215 | } | |
9477c87e PB |
216 | |
217 | /* loading file data */ | |
218 | file_data = read_splashfile(filename, &file_size, &file_type); | |
219 | if (file_data == NULL) { | |
7267c094 | 220 | g_free(filename); |
3d3b8303 WX |
221 | return; |
222 | } | |
ef1e1e07 | 223 | g_free(boot_splash_filedata); |
9477c87e | 224 | boot_splash_filedata = (uint8_t *)file_data; |
9477c87e | 225 | |
3d3b8303 WX |
226 | /* insert data */ |
227 | if (file_type == JPG_FILE) { | |
228 | fw_cfg_add_file(s, "bootsplash.jpg", | |
96f209b9 | 229 | boot_splash_filedata, file_size); |
3d3b8303 WX |
230 | } else { |
231 | fw_cfg_add_file(s, "bootsplash.bmp", | |
96f209b9 | 232 | boot_splash_filedata, file_size); |
3d3b8303 | 233 | } |
7267c094 | 234 | g_free(filename); |
3d3b8303 WX |
235 | } |
236 | } | |
237 | ||
ac05f349 AK |
238 | static void fw_cfg_reboot(FWCfgState *s) |
239 | { | |
ee5d0f89 | 240 | const char *reboot_timeout = NULL; |
20a19220 | 241 | uint64_t rt_val = -1; |
04da9735 | 242 | uint32_t rt_le32; |
ac05f349 AK |
243 | |
244 | /* get user configuration */ | |
245 | QemuOptsList *plist = qemu_find_opts("boot-opts"); | |
246 | QemuOpts *opts = QTAILQ_FIRST(&plist->head); | |
ee5d0f89 LQ |
247 | reboot_timeout = qemu_opt_get(opts, "reboot-timeout"); |
248 | ||
249 | if (reboot_timeout) { | |
250 | rt_val = qemu_opt_get_number(opts, "reboot-timeout", -1); | |
20a19220 | 251 | |
ee5d0f89 | 252 | /* validate the input */ |
20a19220 | 253 | if (rt_val > 0xffff && rt_val != (uint64_t)-1) { |
ee5d0f89 | 254 | error_report("reboot timeout is invalid," |
20a19220 | 255 | "it should be a value between -1 and 65535"); |
ee5d0f89 | 256 | exit(1); |
ac05f349 AK |
257 | } |
258 | } | |
ee5d0f89 | 259 | |
04da9735 LQ |
260 | rt_le32 = cpu_to_le32(rt_val); |
261 | fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&rt_le32, 4), 4); | |
ac05f349 AK |
262 | } |
263 | ||
3cce6243 BS |
264 | static void fw_cfg_write(FWCfgState *s, uint8_t value) |
265 | { | |
023e3148 | 266 | /* nothing, write support removed in QEMU v2.4+ */ |
3cce6243 BS |
267 | } |
268 | ||
e12f3a13 LE |
269 | static inline uint16_t fw_cfg_file_slots(const FWCfgState *s) |
270 | { | |
271 | return s->file_slots; | |
272 | } | |
273 | ||
274 | /* Note: this function returns an exclusive limit. */ | |
275 | static inline uint32_t fw_cfg_max_entry(const FWCfgState *s) | |
276 | { | |
277 | return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s); | |
278 | } | |
279 | ||
3cce6243 BS |
280 | static int fw_cfg_select(FWCfgState *s, uint16_t key) |
281 | { | |
3bef7e8a GS |
282 | int arch, ret; |
283 | FWCfgEntry *e; | |
3cce6243 BS |
284 | |
285 | s->cur_offset = 0; | |
e12f3a13 | 286 | if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) { |
3cce6243 BS |
287 | s->cur_entry = FW_CFG_INVALID; |
288 | ret = 0; | |
289 | } else { | |
290 | s->cur_entry = key; | |
291 | ret = 1; | |
3bef7e8a GS |
292 | /* entry successfully selected, now run callback if present */ |
293 | arch = !!(key & FW_CFG_ARCH_LOCAL); | |
294 | e = &s->entries[arch][key & FW_CFG_ENTRY_MASK]; | |
6f6f4aec MAL |
295 | if (e->select_cb) { |
296 | e->select_cb(e->callback_opaque); | |
3bef7e8a | 297 | } |
3cce6243 BS |
298 | } |
299 | ||
1f80b0d6 | 300 | trace_fw_cfg_select(s, key, trace_key_name(key), ret); |
3cce6243 BS |
301 | return ret; |
302 | } | |
303 | ||
38bf2093 GS |
304 | static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size) |
305 | { | |
306 | FWCfgState *s = opaque; | |
307 | int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); | |
308 | FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL : | |
309 | &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; | |
310 | uint64_t value = 0; | |
311 | ||
312 | assert(size > 0 && size <= sizeof(value)); | |
313 | if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) { | |
314 | /* The least significant 'size' bytes of the return value are | |
315 | * expected to contain a string preserving portion of the item | |
316 | * data, padded with zeros on the right in case we run out early. | |
317 | * In technical terms, we're composing the host-endian representation | |
318 | * of the big endian interpretation of the fw_cfg string. | |
319 | */ | |
320 | do { | |
321 | value = (value << 8) | e->data[s->cur_offset++]; | |
322 | } while (--size && s->cur_offset < e->len); | |
323 | /* If size is still not zero, we *did* run out early, so continue | |
324 | * left-shifting, to add the appropriate number of padding zeros | |
325 | * on the right. | |
326 | */ | |
327 | value <<= 8 * size; | |
328 | } | |
329 | ||
330 | trace_fw_cfg_read(s, value); | |
331 | return value; | |
332 | } | |
333 | ||
a8170e5e | 334 | static void fw_cfg_data_mem_write(void *opaque, hwaddr addr, |
561e1827 | 335 | uint64_t value, unsigned size) |
3cce6243 | 336 | { |
cfaadf0e | 337 | FWCfgState *s = opaque; |
36b62ae6 | 338 | unsigned i = size; |
cfaadf0e | 339 | |
36b62ae6 LE |
340 | do { |
341 | fw_cfg_write(s, value >> (8 * --i)); | |
342 | } while (i); | |
cfaadf0e LE |
343 | } |
344 | ||
a4c0d1de MM |
345 | static void fw_cfg_dma_transfer(FWCfgState *s) |
346 | { | |
347 | dma_addr_t len; | |
348 | FWCfgDmaAccess dma; | |
349 | int arch; | |
350 | FWCfgEntry *e; | |
baf2d5bf | 351 | int read = 0, write = 0; |
a4c0d1de MM |
352 | dma_addr_t dma_addr; |
353 | ||
354 | /* Reset the address before the next access */ | |
355 | dma_addr = s->dma_addr; | |
356 | s->dma_addr = 0; | |
357 | ||
358 | if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) { | |
359 | stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), | |
360 | FW_CFG_DMA_CTL_ERROR); | |
361 | return; | |
362 | } | |
363 | ||
364 | dma.address = be64_to_cpu(dma.address); | |
365 | dma.length = be32_to_cpu(dma.length); | |
366 | dma.control = be32_to_cpu(dma.control); | |
367 | ||
368 | if (dma.control & FW_CFG_DMA_CTL_SELECT) { | |
369 | fw_cfg_select(s, dma.control >> 16); | |
370 | } | |
371 | ||
372 | arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); | |
66f8fd9d GS |
373 | e = (s->cur_entry == FW_CFG_INVALID) ? NULL : |
374 | &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; | |
a4c0d1de MM |
375 | |
376 | if (dma.control & FW_CFG_DMA_CTL_READ) { | |
377 | read = 1; | |
baf2d5bf MT |
378 | write = 0; |
379 | } else if (dma.control & FW_CFG_DMA_CTL_WRITE) { | |
380 | read = 0; | |
381 | write = 1; | |
a4c0d1de MM |
382 | } else if (dma.control & FW_CFG_DMA_CTL_SKIP) { |
383 | read = 0; | |
baf2d5bf | 384 | write = 0; |
a4c0d1de MM |
385 | } else { |
386 | dma.length = 0; | |
387 | } | |
388 | ||
389 | dma.control = 0; | |
390 | ||
391 | while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) { | |
392 | if (s->cur_entry == FW_CFG_INVALID || !e->data || | |
393 | s->cur_offset >= e->len) { | |
394 | len = dma.length; | |
395 | ||
396 | /* If the access is not a read access, it will be a skip access, | |
397 | * tested before. | |
398 | */ | |
399 | if (read) { | |
400 | if (dma_memory_set(s->dma_as, dma.address, 0, len)) { | |
401 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
402 | } | |
403 | } | |
baf2d5bf MT |
404 | if (write) { |
405 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
406 | } | |
a4c0d1de MM |
407 | } else { |
408 | if (dma.length <= (e->len - s->cur_offset)) { | |
409 | len = dma.length; | |
410 | } else { | |
411 | len = (e->len - s->cur_offset); | |
412 | } | |
413 | ||
a4c0d1de MM |
414 | /* If the access is not a read access, it will be a skip access, |
415 | * tested before. | |
416 | */ | |
417 | if (read) { | |
418 | if (dma_memory_write(s->dma_as, dma.address, | |
419 | &e->data[s->cur_offset], len)) { | |
420 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
421 | } | |
422 | } | |
baf2d5bf MT |
423 | if (write) { |
424 | if (!e->allow_write || | |
425 | len != dma.length || | |
426 | dma_memory_read(s->dma_as, dma.address, | |
427 | &e->data[s->cur_offset], len)) { | |
428 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
5f9252f7 MAL |
429 | } else if (e->write_cb) { |
430 | e->write_cb(e->callback_opaque, s->cur_offset, len); | |
baf2d5bf MT |
431 | } |
432 | } | |
a4c0d1de MM |
433 | |
434 | s->cur_offset += len; | |
435 | } | |
436 | ||
437 | dma.address += len; | |
438 | dma.length -= len; | |
439 | ||
440 | } | |
441 | ||
442 | stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), | |
443 | dma.control); | |
444 | ||
445 | trace_fw_cfg_read(s, 0); | |
446 | } | |
447 | ||
2cc06a88 KC |
448 | static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr, |
449 | unsigned size) | |
450 | { | |
451 | /* Return a signature value (and handle various read sizes) */ | |
452 | return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8); | |
453 | } | |
454 | ||
a4c0d1de MM |
455 | static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, |
456 | uint64_t value, unsigned size) | |
457 | { | |
458 | FWCfgState *s = opaque; | |
459 | ||
460 | if (size == 4) { | |
461 | if (addr == 0) { | |
462 | /* FWCfgDmaAccess high address */ | |
463 | s->dma_addr = value << 32; | |
464 | } else if (addr == 4) { | |
465 | /* FWCfgDmaAccess low address */ | |
466 | s->dma_addr |= value; | |
467 | fw_cfg_dma_transfer(s); | |
468 | } | |
469 | } else if (size == 8 && addr == 0) { | |
470 | s->dma_addr = value; | |
471 | fw_cfg_dma_transfer(s); | |
472 | } | |
473 | } | |
474 | ||
475 | static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, | |
8372d383 PM |
476 | unsigned size, bool is_write, |
477 | MemTxAttrs attrs) | |
a4c0d1de | 478 | { |
2cc06a88 KC |
479 | return !is_write || ((size == 4 && (addr == 0 || addr == 4)) || |
480 | (size == 8 && addr == 0)); | |
a4c0d1de MM |
481 | } |
482 | ||
cfaadf0e | 483 | static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, |
8372d383 PM |
484 | unsigned size, bool is_write, |
485 | MemTxAttrs attrs) | |
cfaadf0e LE |
486 | { |
487 | return addr == 0; | |
3cce6243 BS |
488 | } |
489 | ||
2247936a LQ |
490 | static uint64_t fw_cfg_ctl_mem_read(void *opaque, hwaddr addr, unsigned size) |
491 | { | |
492 | return 0; | |
493 | } | |
494 | ||
a8170e5e | 495 | static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr, |
561e1827 | 496 | uint64_t value, unsigned size) |
3cce6243 BS |
497 | { |
498 | fw_cfg_select(opaque, (uint16_t)value); | |
499 | } | |
500 | ||
a8170e5e | 501 | static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr, |
8372d383 PM |
502 | unsigned size, bool is_write, |
503 | MemTxAttrs attrs) | |
3cce6243 | 504 | { |
561e1827 | 505 | return is_write && size == 2; |
3cce6243 BS |
506 | } |
507 | ||
a8170e5e | 508 | static void fw_cfg_comb_write(void *opaque, hwaddr addr, |
561e1827 | 509 | uint64_t value, unsigned size) |
3cce6243 | 510 | { |
561e1827 AK |
511 | switch (size) { |
512 | case 1: | |
513 | fw_cfg_write(opaque, (uint8_t)value); | |
514 | break; | |
515 | case 2: | |
516 | fw_cfg_select(opaque, (uint16_t)value); | |
517 | break; | |
518 | } | |
3cce6243 BS |
519 | } |
520 | ||
a8170e5e | 521 | static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, |
8372d383 PM |
522 | unsigned size, bool is_write, |
523 | MemTxAttrs attrs) | |
561e1827 AK |
524 | { |
525 | return (size == 1) || (is_write && size == 2); | |
526 | } | |
3cce6243 | 527 | |
561e1827 | 528 | static const MemoryRegionOps fw_cfg_ctl_mem_ops = { |
2247936a | 529 | .read = fw_cfg_ctl_mem_read, |
561e1827 | 530 | .write = fw_cfg_ctl_mem_write, |
d789c845 | 531 | .endianness = DEVICE_BIG_ENDIAN, |
561e1827 | 532 | .valid.accepts = fw_cfg_ctl_mem_valid, |
3cce6243 BS |
533 | }; |
534 | ||
561e1827 | 535 | static const MemoryRegionOps fw_cfg_data_mem_ops = { |
38bf2093 | 536 | .read = fw_cfg_data_read, |
561e1827 | 537 | .write = fw_cfg_data_mem_write, |
d789c845 | 538 | .endianness = DEVICE_BIG_ENDIAN, |
561e1827 AK |
539 | .valid = { |
540 | .min_access_size = 1, | |
541 | .max_access_size = 1, | |
cfaadf0e | 542 | .accepts = fw_cfg_data_mem_valid, |
561e1827 | 543 | }, |
3cce6243 BS |
544 | }; |
545 | ||
561e1827 | 546 | static const MemoryRegionOps fw_cfg_comb_mem_ops = { |
6c8d56a2 | 547 | .read = fw_cfg_data_read, |
561e1827 | 548 | .write = fw_cfg_comb_write, |
6fdf98f2 | 549 | .endianness = DEVICE_LITTLE_ENDIAN, |
561e1827 | 550 | .valid.accepts = fw_cfg_comb_valid, |
3cce6243 BS |
551 | }; |
552 | ||
a4c0d1de | 553 | static const MemoryRegionOps fw_cfg_dma_mem_ops = { |
2cc06a88 | 554 | .read = fw_cfg_dma_mem_read, |
a4c0d1de MM |
555 | .write = fw_cfg_dma_mem_write, |
556 | .endianness = DEVICE_BIG_ENDIAN, | |
557 | .valid.accepts = fw_cfg_dma_mem_valid, | |
558 | .valid.max_access_size = 8, | |
559 | .impl.max_access_size = 8, | |
560 | }; | |
561 | ||
3a5c16fc | 562 | static void fw_cfg_reset(DeviceState *d) |
3cce6243 | 563 | { |
2ce92a11 | 564 | FWCfgState *s = FW_CFG(d); |
3cce6243 | 565 | |
3bef7e8a GS |
566 | /* we never register a read callback for FW_CFG_SIGNATURE */ |
567 | fw_cfg_select(s, FW_CFG_SIGNATURE); | |
3cce6243 BS |
568 | } |
569 | ||
ff06108b JQ |
570 | /* Save restore 32 bit int as uint16_t |
571 | This is a Big hack, but it is how the old state did it. | |
572 | Or we broke compatibility in the state, or we can't use struct tm | |
573 | */ | |
574 | ||
2c21ee76 | 575 | static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size, |
03fee66f | 576 | const VMStateField *field) |
ff06108b JQ |
577 | { |
578 | uint32_t *v = pv; | |
579 | *v = qemu_get_be16(f); | |
580 | return 0; | |
581 | } | |
582 | ||
03fee66f MAL |
583 | static int put_unused(QEMUFile *f, void *pv, size_t size, |
584 | const VMStateField *field, QJSON *vmdesc) | |
ff06108b | 585 | { |
66c80e75 | 586 | fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n"); |
ff06108b | 587 | fprintf(stderr, "This functions shouldn't be called.\n"); |
2c21ee76 JD |
588 | |
589 | return 0; | |
ff06108b JQ |
590 | } |
591 | ||
d05ac8fa | 592 | static const VMStateInfo vmstate_hack_uint32_as_uint16 = { |
ff06108b JQ |
593 | .name = "int32_as_uint16", |
594 | .get = get_uint32_as_uint16, | |
595 | .put = put_unused, | |
596 | }; | |
597 | ||
598 | #define VMSTATE_UINT16_HACK(_f, _s, _t) \ | |
599 | VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t) | |
600 | ||
601 | ||
602 | static bool is_version_1(void *opaque, int version_id) | |
603 | { | |
604 | return version_id == 1; | |
605 | } | |
606 | ||
b2a575a1 | 607 | bool fw_cfg_dma_enabled(void *opaque) |
a4c0d1de MM |
608 | { |
609 | FWCfgState *s = opaque; | |
610 | ||
611 | return s->dma_enabled; | |
612 | } | |
613 | ||
394f0f72 SK |
614 | static bool fw_cfg_acpi_mr_restore(void *opaque) |
615 | { | |
616 | FWCfgState *s = opaque; | |
617 | bool mr_aligned; | |
618 | ||
619 | mr_aligned = QEMU_IS_ALIGNED(s->table_mr_size, qemu_real_host_page_size) && | |
620 | QEMU_IS_ALIGNED(s->linker_mr_size, qemu_real_host_page_size) && | |
621 | QEMU_IS_ALIGNED(s->rsdp_mr_size, qemu_real_host_page_size); | |
622 | return s->acpi_mr_restore && !mr_aligned; | |
623 | } | |
624 | ||
625 | static void fw_cfg_update_mr(FWCfgState *s, uint16_t key, size_t size) | |
626 | { | |
627 | MemoryRegion *mr; | |
628 | ram_addr_t offset; | |
629 | int arch = !!(key & FW_CFG_ARCH_LOCAL); | |
630 | void *ptr; | |
631 | ||
632 | key &= FW_CFG_ENTRY_MASK; | |
633 | assert(key < fw_cfg_max_entry(s)); | |
634 | ||
635 | ptr = s->entries[arch][key].data; | |
636 | mr = memory_region_from_host(ptr, &offset); | |
637 | ||
638 | memory_region_ram_resize(mr, size, &error_abort); | |
639 | } | |
640 | ||
641 | static int fw_cfg_acpi_mr_restore_post_load(void *opaque, int version_id) | |
642 | { | |
643 | FWCfgState *s = opaque; | |
644 | int i, index; | |
645 | ||
646 | assert(s->files); | |
647 | ||
648 | index = be32_to_cpu(s->files->count); | |
649 | ||
650 | for (i = 0; i < index; i++) { | |
651 | if (!strcmp(s->files->f[i].name, ACPI_BUILD_TABLE_FILE)) { | |
652 | fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->table_mr_size); | |
653 | } else if (!strcmp(s->files->f[i].name, ACPI_BUILD_LOADER_FILE)) { | |
654 | fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->linker_mr_size); | |
655 | } else if (!strcmp(s->files->f[i].name, ACPI_BUILD_RSDP_FILE)) { | |
656 | fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->rsdp_mr_size); | |
657 | } | |
658 | } | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
a4c0d1de MM |
663 | static const VMStateDescription vmstate_fw_cfg_dma = { |
664 | .name = "fw_cfg/dma", | |
665 | .needed = fw_cfg_dma_enabled, | |
666 | .fields = (VMStateField[]) { | |
667 | VMSTATE_UINT64(dma_addr, FWCfgState), | |
668 | VMSTATE_END_OF_LIST() | |
669 | }, | |
670 | }; | |
671 | ||
394f0f72 SK |
672 | static const VMStateDescription vmstate_fw_cfg_acpi_mr = { |
673 | .name = "fw_cfg/acpi_mr", | |
674 | .version_id = 1, | |
675 | .minimum_version_id = 1, | |
676 | .needed = fw_cfg_acpi_mr_restore, | |
677 | .post_load = fw_cfg_acpi_mr_restore_post_load, | |
678 | .fields = (VMStateField[]) { | |
679 | VMSTATE_UINT64(table_mr_size, FWCfgState), | |
680 | VMSTATE_UINT64(linker_mr_size, FWCfgState), | |
681 | VMSTATE_UINT64(rsdp_mr_size, FWCfgState), | |
682 | VMSTATE_END_OF_LIST() | |
683 | }, | |
684 | }; | |
685 | ||
7d2edd40 JQ |
686 | static const VMStateDescription vmstate_fw_cfg = { |
687 | .name = "fw_cfg", | |
ff06108b | 688 | .version_id = 2, |
7d2edd40 | 689 | .minimum_version_id = 1, |
d49805ae | 690 | .fields = (VMStateField[]) { |
7d2edd40 | 691 | VMSTATE_UINT16(cur_entry, FWCfgState), |
ff06108b JQ |
692 | VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1), |
693 | VMSTATE_UINT32_V(cur_offset, FWCfgState, 2), | |
7d2edd40 | 694 | VMSTATE_END_OF_LIST() |
a4c0d1de MM |
695 | }, |
696 | .subsections = (const VMStateDescription*[]) { | |
697 | &vmstate_fw_cfg_dma, | |
394f0f72 | 698 | &vmstate_fw_cfg_acpi_mr, |
a4c0d1de | 699 | NULL, |
7d2edd40 JQ |
700 | } |
701 | }; | |
3cce6243 | 702 | |
6f6f4aec MAL |
703 | static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key, |
704 | FWCfgCallback select_cb, | |
5f9252f7 | 705 | FWCfgWriteCallback write_cb, |
6f6f4aec MAL |
706 | void *callback_opaque, |
707 | void *data, size_t len, | |
708 | bool read_only) | |
3cce6243 | 709 | { |
3cce6243 BS |
710 | int arch = !!(key & FW_CFG_ARCH_LOCAL); |
711 | ||
712 | key &= FW_CFG_ENTRY_MASK; | |
713 | ||
e12f3a13 | 714 | assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); |
0f9b2141 | 715 | assert(s->entries[arch][key].data == NULL); /* avoid key conflict */ |
3cce6243 BS |
716 | |
717 | s->entries[arch][key].data = data; | |
089da572 | 718 | s->entries[arch][key].len = (uint32_t)len; |
6f6f4aec | 719 | s->entries[arch][key].select_cb = select_cb; |
5f9252f7 | 720 | s->entries[arch][key].write_cb = write_cb; |
d87072ce | 721 | s->entries[arch][key].callback_opaque = callback_opaque; |
baf2d5bf | 722 | s->entries[arch][key].allow_write = !read_only; |
d87072ce MT |
723 | } |
724 | ||
bdbb5b17 GA |
725 | static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key, |
726 | void *data, size_t len) | |
727 | { | |
728 | void *ptr; | |
729 | int arch = !!(key & FW_CFG_ARCH_LOCAL); | |
730 | ||
731 | key &= FW_CFG_ENTRY_MASK; | |
732 | ||
e12f3a13 | 733 | assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); |
bdbb5b17 GA |
734 | |
735 | /* return the old data to the function caller, avoid memory leak */ | |
736 | ptr = s->entries[arch][key].data; | |
737 | s->entries[arch][key].data = data; | |
738 | s->entries[arch][key].len = len; | |
739 | s->entries[arch][key].callback_opaque = NULL; | |
baf2d5bf | 740 | s->entries[arch][key].allow_write = false; |
bdbb5b17 GA |
741 | |
742 | return ptr; | |
743 | } | |
744 | ||
d87072ce MT |
745 | void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len) |
746 | { | |
1f80b0d6 | 747 | trace_fw_cfg_add_bytes(key, trace_key_name(key), len); |
5f9252f7 | 748 | fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true); |
3cce6243 BS |
749 | } |
750 | ||
44687f75 MA |
751 | void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value) |
752 | { | |
753 | size_t sz = strlen(value) + 1; | |
754 | ||
1f80b0d6 | 755 | trace_fw_cfg_add_string(key, trace_key_name(key), value); |
e7ae771f | 756 | fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz); |
44687f75 MA |
757 | } |
758 | ||
e5f6aa31 SL |
759 | void fw_cfg_modify_string(FWCfgState *s, uint16_t key, const char *value) |
760 | { | |
761 | size_t sz = strlen(value) + 1; | |
762 | char *old; | |
763 | ||
764 | old = fw_cfg_modify_bytes_read(s, key, g_memdup(value, sz), sz); | |
765 | g_free(old); | |
766 | } | |
767 | ||
4cad3867 | 768 | void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value) |
3cce6243 BS |
769 | { |
770 | uint16_t *copy; | |
771 | ||
7267c094 | 772 | copy = g_malloc(sizeof(value)); |
3cce6243 | 773 | *copy = cpu_to_le16(value); |
1f80b0d6 | 774 | trace_fw_cfg_add_i16(key, trace_key_name(key), value); |
089da572 | 775 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
776 | } |
777 | ||
1edd34b6 GS |
778 | void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value) |
779 | { | |
780 | uint16_t *copy, *old; | |
781 | ||
782 | copy = g_malloc(sizeof(value)); | |
783 | *copy = cpu_to_le16(value); | |
784 | old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); | |
785 | g_free(old); | |
786 | } | |
787 | ||
4cad3867 | 788 | void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value) |
3cce6243 BS |
789 | { |
790 | uint32_t *copy; | |
791 | ||
7267c094 | 792 | copy = g_malloc(sizeof(value)); |
3cce6243 | 793 | *copy = cpu_to_le32(value); |
1f80b0d6 | 794 | trace_fw_cfg_add_i32(key, trace_key_name(key), value); |
089da572 | 795 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
796 | } |
797 | ||
e5f6aa31 SL |
798 | void fw_cfg_modify_i32(FWCfgState *s, uint16_t key, uint32_t value) |
799 | { | |
800 | uint32_t *copy, *old; | |
801 | ||
802 | copy = g_malloc(sizeof(value)); | |
803 | *copy = cpu_to_le32(value); | |
804 | old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); | |
805 | g_free(old); | |
806 | } | |
807 | ||
4cad3867 | 808 | void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value) |
3cce6243 BS |
809 | { |
810 | uint64_t *copy; | |
811 | ||
7267c094 | 812 | copy = g_malloc(sizeof(value)); |
3cce6243 | 813 | *copy = cpu_to_le64(value); |
1f80b0d6 | 814 | trace_fw_cfg_add_i64(key, trace_key_name(key), value); |
089da572 | 815 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
816 | } |
817 | ||
e5f6aa31 SL |
818 | void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value) |
819 | { | |
820 | uint64_t *copy, *old; | |
821 | ||
822 | copy = g_malloc(sizeof(value)); | |
823 | *copy = cpu_to_le64(value); | |
824 | old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); | |
825 | g_free(old); | |
826 | } | |
827 | ||
bab47d9a GH |
828 | void fw_cfg_set_order_override(FWCfgState *s, int order) |
829 | { | |
830 | assert(s->fw_cfg_order_override == 0); | |
831 | s->fw_cfg_order_override = order; | |
832 | } | |
833 | ||
834 | void fw_cfg_reset_order_override(FWCfgState *s) | |
835 | { | |
836 | assert(s->fw_cfg_order_override != 0); | |
837 | s->fw_cfg_order_override = 0; | |
838 | } | |
839 | ||
840 | /* | |
841 | * This is the legacy order list. For legacy systems, files are in | |
842 | * the fw_cfg in the order defined below, by the "order" value. Note | |
843 | * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a | |
844 | * specific area, but there may be more than one and they occur in the | |
845 | * order that the user specifies them on the command line. Those are | |
846 | * handled in a special manner, using the order override above. | |
847 | * | |
848 | * For non-legacy, the files are sorted by filename to avoid this kind | |
849 | * of complexity in the future. | |
850 | * | |
851 | * This is only for x86, other arches don't implement versioning so | |
852 | * they won't set legacy mode. | |
853 | */ | |
854 | static struct { | |
855 | const char *name; | |
856 | int order; | |
857 | } fw_cfg_order[] = { | |
858 | { "etc/boot-menu-wait", 10 }, | |
859 | { "bootsplash.jpg", 11 }, | |
860 | { "bootsplash.bmp", 12 }, | |
861 | { "etc/boot-fail-wait", 15 }, | |
862 | { "etc/smbios/smbios-tables", 20 }, | |
863 | { "etc/smbios/smbios-anchor", 30 }, | |
864 | { "etc/e820", 40 }, | |
865 | { "etc/reserved-memory-end", 50 }, | |
866 | { "genroms/kvmvapic.bin", 55 }, | |
867 | { "genroms/linuxboot.bin", 60 }, | |
868 | { }, /* VGA ROMs from pc_vga_init come here, 70. */ | |
869 | { }, /* NIC option ROMs from pc_nic_init come here, 80. */ | |
870 | { "etc/system-states", 90 }, | |
871 | { }, /* User ROMs come here, 100. */ | |
872 | { }, /* Device FW comes here, 110. */ | |
873 | { "etc/extra-pci-roots", 120 }, | |
874 | { "etc/acpi/tables", 130 }, | |
875 | { "etc/table-loader", 140 }, | |
876 | { "etc/tpm/log", 150 }, | |
877 | { "etc/acpi/rsdp", 160 }, | |
878 | { "bootorder", 170 }, | |
879 | ||
880 | #define FW_CFG_ORDER_OVERRIDE_LAST 200 | |
881 | }; | |
882 | ||
394f0f72 SK |
883 | /* |
884 | * Any sub-page size update to these table MRs will be lost during migration, | |
885 | * as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path. | |
886 | * In order to avoid the inconsistency in sizes save them seperately and | |
887 | * migrate over in vmstate post_load(). | |
888 | */ | |
889 | static void fw_cfg_acpi_mr_save(FWCfgState *s, const char *filename, size_t len) | |
890 | { | |
891 | if (!strcmp(filename, ACPI_BUILD_TABLE_FILE)) { | |
892 | s->table_mr_size = len; | |
893 | } else if (!strcmp(filename, ACPI_BUILD_LOADER_FILE)) { | |
894 | s->linker_mr_size = len; | |
895 | } else if (!strcmp(filename, ACPI_BUILD_RSDP_FILE)) { | |
896 | s->rsdp_mr_size = len; | |
897 | } | |
898 | } | |
899 | ||
bab47d9a GH |
900 | static int get_fw_cfg_order(FWCfgState *s, const char *name) |
901 | { | |
902 | int i; | |
903 | ||
a8d38f3b C |
904 | if (s->fw_cfg_order_override > 0) { |
905 | return s->fw_cfg_order_override; | |
906 | } | |
bab47d9a GH |
907 | |
908 | for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) { | |
a8d38f3b C |
909 | if (fw_cfg_order[i].name == NULL) { |
910 | continue; | |
911 | } | |
912 | ||
913 | if (strcmp(name, fw_cfg_order[i].name) == 0) { | |
914 | return fw_cfg_order[i].order; | |
915 | } | |
bab47d9a | 916 | } |
a8d38f3b | 917 | |
bab47d9a | 918 | /* Stick unknown stuff at the end. */ |
3dc6f869 | 919 | warn_report("Unknown firmware file in legacy mode: %s", name); |
bab47d9a GH |
920 | return FW_CFG_ORDER_OVERRIDE_LAST; |
921 | } | |
922 | ||
d87072ce | 923 | void fw_cfg_add_file_callback(FWCfgState *s, const char *filename, |
6f6f4aec | 924 | FWCfgCallback select_cb, |
5f9252f7 | 925 | FWCfgWriteCallback write_cb, |
6f6f4aec | 926 | void *callback_opaque, |
baf2d5bf | 927 | void *data, size_t len, bool read_only) |
abe147e0 | 928 | { |
bab47d9a | 929 | int i, index, count; |
089da572 | 930 | size_t dsize; |
bab47d9a GH |
931 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
932 | int order = 0; | |
abe147e0 GH |
933 | |
934 | if (!s->files) { | |
e12f3a13 | 935 | dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s); |
7267c094 | 936 | s->files = g_malloc0(dsize); |
089da572 | 937 | fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize); |
abe147e0 GH |
938 | } |
939 | ||
bab47d9a | 940 | count = be32_to_cpu(s->files->count); |
e12f3a13 | 941 | assert(count < fw_cfg_file_slots(s)); |
bab47d9a GH |
942 | |
943 | /* Find the insertion point. */ | |
944 | if (mc->legacy_fw_cfg_order) { | |
945 | /* | |
946 | * Sort by order. For files with the same order, we keep them | |
947 | * in the sequence in which they were added. | |
948 | */ | |
949 | order = get_fw_cfg_order(s, filename); | |
950 | for (index = count; | |
951 | index > 0 && order < s->entry_order[index - 1]; | |
952 | index--); | |
953 | } else { | |
954 | /* Sort by file name. */ | |
955 | for (index = count; | |
956 | index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0; | |
957 | index--); | |
958 | } | |
959 | ||
960 | /* | |
961 | * Move all the entries from the index point and after down one | |
962 | * to create a slot for the new entry. Because calculations are | |
963 | * being done with the index, make it so that "i" is the current | |
964 | * index and "i - 1" is the one being copied from, thus the | |
965 | * unusual start and end in the for statement. | |
966 | */ | |
d6b6abc5 | 967 | for (i = count; i > index; i--) { |
bab47d9a GH |
968 | s->files->f[i] = s->files->f[i - 1]; |
969 | s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i); | |
970 | s->entries[0][FW_CFG_FILE_FIRST + i] = | |
971 | s->entries[0][FW_CFG_FILE_FIRST + i - 1]; | |
972 | s->entry_order[i] = s->entry_order[i - 1]; | |
973 | } | |
974 | ||
975 | memset(&s->files->f[index], 0, sizeof(FWCfgFile)); | |
976 | memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry)); | |
abe147e0 | 977 | |
bab47d9a GH |
978 | pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename); |
979 | for (i = 0; i <= count; i++) { | |
980 | if (i != index && | |
981 | strcmp(s->files->f[index].name, s->files->f[i].name) == 0) { | |
0eb973f9 GS |
982 | error_report("duplicate fw_cfg file name: %s", |
983 | s->files->f[index].name); | |
984 | exit(1); | |
de9352bc | 985 | } |
abe147e0 | 986 | } |
de9352bc | 987 | |
6f6f4aec | 988 | fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index, |
5f9252f7 | 989 | select_cb, write_cb, |
6f6f4aec MAL |
990 | callback_opaque, data, len, |
991 | read_only); | |
0eb973f9 | 992 | |
abe147e0 GH |
993 | s->files->f[index].size = cpu_to_be32(len); |
994 | s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index); | |
bab47d9a | 995 | s->entry_order[index] = order; |
f6e35343 | 996 | trace_fw_cfg_add_file(s, index, s->files->f[index].name, len); |
abe147e0 | 997 | |
bab47d9a | 998 | s->files->count = cpu_to_be32(count+1); |
394f0f72 | 999 | fw_cfg_acpi_mr_save(s, filename, len); |
abe147e0 GH |
1000 | } |
1001 | ||
d87072ce MT |
1002 | void fw_cfg_add_file(FWCfgState *s, const char *filename, |
1003 | void *data, size_t len) | |
1004 | { | |
5f9252f7 | 1005 | fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); |
d87072ce MT |
1006 | } |
1007 | ||
bdbb5b17 GA |
1008 | void *fw_cfg_modify_file(FWCfgState *s, const char *filename, |
1009 | void *data, size_t len) | |
1010 | { | |
1011 | int i, index; | |
f3b37668 | 1012 | void *ptr = NULL; |
bdbb5b17 GA |
1013 | |
1014 | assert(s->files); | |
1015 | ||
1016 | index = be32_to_cpu(s->files->count); | |
bdbb5b17 GA |
1017 | |
1018 | for (i = 0; i < index; i++) { | |
1019 | if (strcmp(filename, s->files->f[i].name) == 0) { | |
f3b37668 GA |
1020 | ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i, |
1021 | data, len); | |
1022 | s->files->f[i].size = cpu_to_be32(len); | |
394f0f72 | 1023 | fw_cfg_acpi_mr_save(s, filename, len); |
f3b37668 | 1024 | return ptr; |
bdbb5b17 GA |
1025 | } |
1026 | } | |
d6b6abc5 MA |
1027 | |
1028 | assert(index < fw_cfg_file_slots(s)); | |
1029 | ||
bdbb5b17 | 1030 | /* add new one */ |
5f9252f7 | 1031 | fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); |
bdbb5b17 GA |
1032 | return NULL; |
1033 | } | |
1034 | ||
1035 | static void fw_cfg_machine_reset(void *opaque) | |
962630f2 | 1036 | { |
aea60a13 SE |
1037 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
1038 | FWCfgState *s = opaque; | |
bdbb5b17 | 1039 | void *ptr; |
0e7a7592 | 1040 | size_t len; |
aea60a13 | 1041 | char *buf; |
962630f2 | 1042 | |
aea60a13 SE |
1043 | buf = get_boot_devices_list(&len); |
1044 | ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len); | |
bdbb5b17 | 1045 | g_free(ptr); |
aea60a13 SE |
1046 | |
1047 | if (!mc->legacy_fw_cfg_order) { | |
1048 | buf = get_boot_devices_lchs_list(&len); | |
1049 | ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len); | |
1050 | g_free(ptr); | |
1051 | } | |
bdbb5b17 GA |
1052 | } |
1053 | ||
1054 | static void fw_cfg_machine_ready(struct Notifier *n, void *data) | |
1055 | { | |
1056 | FWCfgState *s = container_of(n, FWCfgState, machine_ready); | |
1057 | qemu_register_reset(fw_cfg_machine_reset, s); | |
962630f2 GN |
1058 | } |
1059 | ||
394f0f72 SK |
1060 | static Property fw_cfg_properties[] = { |
1061 | DEFINE_PROP_BOOL("acpi-mr-restore", FWCfgState, acpi_mr_restore, true), | |
1062 | DEFINE_PROP_END_OF_LIST(), | |
1063 | }; | |
3a5c16fc | 1064 | |
38f3adc3 | 1065 | static void fw_cfg_common_realize(DeviceState *dev, Error **errp) |
5712db6a LE |
1066 | { |
1067 | FWCfgState *s = FW_CFG(dev); | |
cfc58cf3 | 1068 | MachineState *machine = MACHINE(qdev_get_machine()); |
3c1aa733 | 1069 | uint32_t version = FW_CFG_VERSION; |
3cce6243 | 1070 | |
38f3adc3 MCA |
1071 | if (!fw_cfg_find()) { |
1072 | error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG); | |
1073 | return; | |
1074 | } | |
10a584b2 | 1075 | |
089da572 | 1076 | fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4); |
9c5ce8db | 1077 | fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16); |
cfc58cf3 | 1078 | fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics); |
95387491 | 1079 | fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu); |
3d3b8303 | 1080 | fw_cfg_bootsplash(s); |
ac05f349 | 1081 | fw_cfg_reboot(s); |
962630f2 | 1082 | |
3c1aa733 MCA |
1083 | if (s->dma_enabled) { |
1084 | version |= FW_CFG_VERSION_DMA; | |
1085 | } | |
1086 | ||
1087 | fw_cfg_add_i32(s, FW_CFG_ID, version); | |
1088 | ||
962630f2 GN |
1089 | s->machine_ready.notify = fw_cfg_machine_ready; |
1090 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
3cce6243 | 1091 | } |
3a5c16fc | 1092 | |
a4c0d1de MM |
1093 | FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, |
1094 | AddressSpace *dma_as) | |
3a5c16fc | 1095 | { |
5712db6a | 1096 | DeviceState *dev; |
91685323 MCA |
1097 | SysBusDevice *sbd; |
1098 | FWCfgIoState *ios; | |
a4c0d1de | 1099 | FWCfgState *s; |
e6915b5f | 1100 | bool dma_requested = dma_iobase && dma_as; |
3a5c16fc | 1101 | |
3e80f690 | 1102 | dev = qdev_new(TYPE_FW_CFG_IO); |
e6915b5f LE |
1103 | if (!dma_requested) { |
1104 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
1105 | } | |
a4c0d1de | 1106 | |
38f3adc3 | 1107 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, |
d2623129 | 1108 | OBJECT(dev)); |
3e80f690 | 1109 | qdev_realize_and_unref(dev, NULL, &error_fatal); |
91685323 MCA |
1110 | |
1111 | sbd = SYS_BUS_DEVICE(dev); | |
1112 | ios = FW_CFG_IO(dev); | |
1113 | sysbus_add_io(sbd, iobase, &ios->comb_iomem); | |
1114 | ||
a4c0d1de MM |
1115 | s = FW_CFG(dev); |
1116 | ||
e6915b5f | 1117 | if (s->dma_enabled) { |
a4c0d1de MM |
1118 | /* 64 bits for the address field */ |
1119 | s->dma_as = dma_as; | |
1120 | s->dma_addr = 0; | |
91685323 | 1121 | sysbus_add_io(sbd, dma_iobase, &s->dma_iomem); |
a4c0d1de MM |
1122 | } |
1123 | ||
a4c0d1de MM |
1124 | return s; |
1125 | } | |
1126 | ||
1127 | FWCfgState *fw_cfg_init_io(uint32_t iobase) | |
1128 | { | |
1129 | return fw_cfg_init_io_dma(iobase, 0, NULL); | |
56383955 HT |
1130 | } |
1131 | ||
a4c0d1de MM |
1132 | FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, |
1133 | hwaddr data_addr, uint32_t data_width, | |
1134 | hwaddr dma_addr, AddressSpace *dma_as) | |
56383955 | 1135 | { |
5712db6a LE |
1136 | DeviceState *dev; |
1137 | SysBusDevice *sbd; | |
a4c0d1de | 1138 | FWCfgState *s; |
e6915b5f | 1139 | bool dma_requested = dma_addr && dma_as; |
56383955 | 1140 | |
3e80f690 | 1141 | dev = qdev_new(TYPE_FW_CFG_MEM); |
6c87e3d5 | 1142 | qdev_prop_set_uint32(dev, "data_width", data_width); |
e6915b5f LE |
1143 | if (!dma_requested) { |
1144 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
1145 | } | |
cfaadf0e | 1146 | |
38f3adc3 | 1147 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, |
d2623129 | 1148 | OBJECT(dev)); |
3e80f690 | 1149 | qdev_realize_and_unref(dev, NULL, &error_fatal); |
5712db6a LE |
1150 | |
1151 | sbd = SYS_BUS_DEVICE(dev); | |
1152 | sysbus_mmio_map(sbd, 0, ctl_addr); | |
1153 | sysbus_mmio_map(sbd, 1, data_addr); | |
1154 | ||
a4c0d1de MM |
1155 | s = FW_CFG(dev); |
1156 | ||
e6915b5f | 1157 | if (s->dma_enabled) { |
a4c0d1de MM |
1158 | s->dma_as = dma_as; |
1159 | s->dma_addr = 0; | |
1160 | sysbus_mmio_map(sbd, 2, dma_addr); | |
a4c0d1de MM |
1161 | } |
1162 | ||
a4c0d1de | 1163 | return s; |
5712db6a LE |
1164 | } |
1165 | ||
6c87e3d5 LE |
1166 | FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr) |
1167 | { | |
1168 | return fw_cfg_init_mem_wide(ctl_addr, data_addr, | |
a4c0d1de MM |
1169 | fw_cfg_data_mem_ops.valid.max_access_size, |
1170 | 0, NULL); | |
6c87e3d5 LE |
1171 | } |
1172 | ||
5712db6a | 1173 | |
600c60b7 MT |
1174 | FWCfgState *fw_cfg_find(void) |
1175 | { | |
6e99c075 MCA |
1176 | /* Returns NULL unless there is exactly one fw_cfg device */ |
1177 | return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL)); | |
600c60b7 MT |
1178 | } |
1179 | ||
38f3adc3 | 1180 | |
999e12bb AL |
1181 | static void fw_cfg_class_init(ObjectClass *klass, void *data) |
1182 | { | |
39bffca2 | 1183 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1184 | |
39bffca2 AL |
1185 | dc->reset = fw_cfg_reset; |
1186 | dc->vmsd = &vmstate_fw_cfg; | |
394f0f72 SK |
1187 | |
1188 | device_class_set_props(dc, fw_cfg_properties); | |
999e12bb AL |
1189 | } |
1190 | ||
8c43a6f0 | 1191 | static const TypeInfo fw_cfg_info = { |
600c60b7 | 1192 | .name = TYPE_FW_CFG, |
39bffca2 | 1193 | .parent = TYPE_SYS_BUS_DEVICE, |
e061fa3c | 1194 | .abstract = true, |
39bffca2 AL |
1195 | .instance_size = sizeof(FWCfgState), |
1196 | .class_init = fw_cfg_class_init, | |
3a5c16fc BS |
1197 | }; |
1198 | ||
e12f3a13 LE |
1199 | static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp) |
1200 | { | |
1201 | uint16_t file_slots_max; | |
1202 | ||
1203 | if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) { | |
1204 | error_setg(errp, "\"file_slots\" must be at least 0x%x", | |
1205 | FW_CFG_FILE_SLOTS_MIN); | |
1206 | return; | |
1207 | } | |
1208 | ||
1209 | /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value | |
1210 | * that we permit. The actual (exclusive) value coming from the | |
1211 | * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */ | |
1212 | file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1; | |
1213 | if (fw_cfg_file_slots(s) > file_slots_max) { | |
1214 | error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16, | |
1215 | file_slots_max); | |
1216 | return; | |
1217 | } | |
1218 | ||
1219 | s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); | |
1220 | s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); | |
1221 | s->entry_order = g_new0(int, fw_cfg_max_entry(s)); | |
1222 | } | |
5712db6a LE |
1223 | |
1224 | static Property fw_cfg_io_properties[] = { | |
a4c0d1de | 1225 | DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, |
e6915b5f | 1226 | true), |
e12f3a13 | 1227 | DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots, |
a5b3ebfd | 1228 | FW_CFG_FILE_SLOTS_DFLT), |
5712db6a LE |
1229 | DEFINE_PROP_END_OF_LIST(), |
1230 | }; | |
1231 | ||
1232 | static void fw_cfg_io_realize(DeviceState *dev, Error **errp) | |
1233 | { | |
1234 | FWCfgIoState *s = FW_CFG_IO(dev); | |
e12f3a13 LE |
1235 | Error *local_err = NULL; |
1236 | ||
1237 | fw_cfg_file_slots_allocate(FW_CFG(s), &local_err); | |
1238 | if (local_err) { | |
1239 | error_propagate(errp, local_err); | |
1240 | return; | |
1241 | } | |
5712db6a | 1242 | |
ce9a2aa3 GS |
1243 | /* when using port i/o, the 8-bit data register ALWAYS overlaps |
1244 | * with half of the 16-bit control register. Hence, the total size | |
1245 | * of the i/o region used is FW_CFG_CTL_SIZE */ | |
5712db6a | 1246 | memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops, |
a4c0d1de | 1247 | FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE); |
a4c0d1de MM |
1248 | |
1249 | if (FW_CFG(s)->dma_enabled) { | |
1250 | memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), | |
1251 | &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", | |
1252 | sizeof(dma_addr_t)); | |
a4c0d1de | 1253 | } |
38f3adc3 MCA |
1254 | |
1255 | fw_cfg_common_realize(dev, errp); | |
5712db6a LE |
1256 | } |
1257 | ||
1258 | static void fw_cfg_io_class_init(ObjectClass *klass, void *data) | |
1259 | { | |
1260 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1261 | ||
1262 | dc->realize = fw_cfg_io_realize; | |
4f67d30b | 1263 | device_class_set_props(dc, fw_cfg_io_properties); |
5712db6a LE |
1264 | } |
1265 | ||
1266 | static const TypeInfo fw_cfg_io_info = { | |
1267 | .name = TYPE_FW_CFG_IO, | |
1268 | .parent = TYPE_FW_CFG, | |
1269 | .instance_size = sizeof(FWCfgIoState), | |
1270 | .class_init = fw_cfg_io_class_init, | |
1271 | }; | |
1272 | ||
1273 | ||
cfaadf0e LE |
1274 | static Property fw_cfg_mem_properties[] = { |
1275 | DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1), | |
a4c0d1de | 1276 | DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled, |
e6915b5f | 1277 | true), |
e12f3a13 | 1278 | DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots, |
a5b3ebfd | 1279 | FW_CFG_FILE_SLOTS_DFLT), |
cfaadf0e LE |
1280 | DEFINE_PROP_END_OF_LIST(), |
1281 | }; | |
1282 | ||
5712db6a LE |
1283 | static void fw_cfg_mem_realize(DeviceState *dev, Error **errp) |
1284 | { | |
1285 | FWCfgMemState *s = FW_CFG_MEM(dev); | |
1286 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
cfaadf0e | 1287 | const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops; |
e12f3a13 LE |
1288 | Error *local_err = NULL; |
1289 | ||
1290 | fw_cfg_file_slots_allocate(FW_CFG(s), &local_err); | |
1291 | if (local_err) { | |
1292 | error_propagate(errp, local_err); | |
1293 | return; | |
1294 | } | |
5712db6a LE |
1295 | |
1296 | memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops, | |
a4c0d1de | 1297 | FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE); |
5712db6a LE |
1298 | sysbus_init_mmio(sbd, &s->ctl_iomem); |
1299 | ||
cfaadf0e | 1300 | if (s->data_width > data_ops->valid.max_access_size) { |
695e2fc2 | 1301 | s->wide_data_ops = *data_ops; |
cfaadf0e LE |
1302 | |
1303 | s->wide_data_ops.valid.max_access_size = s->data_width; | |
1304 | s->wide_data_ops.impl.max_access_size = s->data_width; | |
1305 | data_ops = &s->wide_data_ops; | |
1306 | } | |
1307 | memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s), | |
1308 | "fwcfg.data", data_ops->valid.max_access_size); | |
5712db6a | 1309 | sysbus_init_mmio(sbd, &s->data_iomem); |
a4c0d1de MM |
1310 | |
1311 | if (FW_CFG(s)->dma_enabled) { | |
1312 | memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), | |
1313 | &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", | |
1314 | sizeof(dma_addr_t)); | |
1315 | sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem); | |
1316 | } | |
38f3adc3 MCA |
1317 | |
1318 | fw_cfg_common_realize(dev, errp); | |
5712db6a LE |
1319 | } |
1320 | ||
1321 | static void fw_cfg_mem_class_init(ObjectClass *klass, void *data) | |
1322 | { | |
1323 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1324 | ||
1325 | dc->realize = fw_cfg_mem_realize; | |
4f67d30b | 1326 | device_class_set_props(dc, fw_cfg_mem_properties); |
5712db6a LE |
1327 | } |
1328 | ||
1329 | static const TypeInfo fw_cfg_mem_info = { | |
1330 | .name = TYPE_FW_CFG_MEM, | |
1331 | .parent = TYPE_FW_CFG, | |
1332 | .instance_size = sizeof(FWCfgMemState), | |
1333 | .class_init = fw_cfg_mem_class_init, | |
1334 | }; | |
1335 | ||
1336 | ||
83f7d43a | 1337 | static void fw_cfg_register_types(void) |
3a5c16fc | 1338 | { |
39bffca2 | 1339 | type_register_static(&fw_cfg_info); |
5712db6a LE |
1340 | type_register_static(&fw_cfg_io_info); |
1341 | type_register_static(&fw_cfg_mem_info); | |
3a5c16fc BS |
1342 | } |
1343 | ||
83f7d43a | 1344 | type_init(fw_cfg_register_types) |