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fw_cfg: remove offset argument from callback prototype
[mirror_qemu.git] / hw / nvram / fw_cfg.c
CommitLineData
3cce6243
BS
1/*
2 * QEMU Firmware configuration device emulation
3 *
4 * Copyright (c) 2008 Gleb Natapov
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
83c9f4ca 24#include "hw/hw.h"
9c17d615 25#include "sysemu/sysemu.h"
a4c0d1de 26#include "sysemu/dma.h"
0d09e41a
PB
27#include "hw/isa/isa.h"
28#include "hw/nvram/fw_cfg.h"
83c9f4ca 29#include "hw/sysbus.h"
f6e35343 30#include "trace.h"
1de7afc9
PB
31#include "qemu/error-report.h"
32#include "qemu/config-file.h"
3cce6243 33
a4c0d1de 34#define FW_CFG_CTL_SIZE 2
600c60b7
MT
35#define FW_CFG_NAME "fw_cfg"
36#define FW_CFG_PATH "/machine/" FW_CFG_NAME
5712db6a
LE
37
38#define TYPE_FW_CFG "fw_cfg"
39#define TYPE_FW_CFG_IO "fw_cfg_io"
40#define TYPE_FW_CFG_MEM "fw_cfg_mem"
41
42#define FW_CFG(obj) OBJECT_CHECK(FWCfgState, (obj), TYPE_FW_CFG)
43#define FW_CFG_IO(obj) OBJECT_CHECK(FWCfgIoState, (obj), TYPE_FW_CFG_IO)
44#define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_MEM)
3cce6243 45
a4c0d1de
MM
46/* FW_CFG_VERSION bits */
47#define FW_CFG_VERSION 0x01
48#define FW_CFG_VERSION_DMA 0x02
49
50/* FW_CFG_DMA_CONTROL bits */
51#define FW_CFG_DMA_CTL_ERROR 0x01
52#define FW_CFG_DMA_CTL_READ 0x02
53#define FW_CFG_DMA_CTL_SKIP 0x04
54#define FW_CFG_DMA_CTL_SELECT 0x08
55
2cc06a88
KC
56#define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
57
b96ae2da 58typedef struct FWCfgEntry {
ff06108b 59 uint32_t len;
3cce6243
BS
60 uint8_t *data;
61 void *callback_opaque;
d87072ce 62 FWCfgReadCallback read_callback;
3cce6243
BS
63} FWCfgEntry;
64
b96ae2da 65struct FWCfgState {
2ce92a11
HT
66 /*< private >*/
67 SysBusDevice parent_obj;
68 /*< public >*/
69
3cce6243 70 FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
abe147e0 71 FWCfgFiles *files;
3cce6243 72 uint16_t cur_entry;
ff06108b 73 uint32_t cur_offset;
962630f2 74 Notifier machine_ready;
a4c0d1de
MM
75
76 bool dma_enabled;
77 dma_addr_t dma_addr;
78 AddressSpace *dma_as;
79 MemoryRegion dma_iomem;
c2b5bda4 80};
3cce6243 81
5712db6a
LE
82struct FWCfgIoState {
83 /*< private >*/
84 FWCfgState parent_obj;
85 /*< public >*/
86
87 MemoryRegion comb_iomem;
a4c0d1de 88 uint32_t iobase, dma_iobase;
5712db6a
LE
89};
90
91struct FWCfgMemState {
92 /*< private >*/
93 FWCfgState parent_obj;
94 /*< public >*/
95
96 MemoryRegion ctl_iomem, data_iomem;
cfaadf0e
LE
97 uint32_t data_width;
98 MemoryRegionOps wide_data_ops;
5712db6a
LE
99};
100
3d3b8303
WX
101#define JPG_FILE 0
102#define BMP_FILE 1
103
3d1bba20 104static char *read_splashfile(char *filename, gsize *file_sizep,
d09acb9b 105 int *file_typep)
3d3b8303 106{
9477c87e
PB
107 GError *err = NULL;
108 gboolean res;
109 gchar *content;
9f8863eb
MA
110 int file_type;
111 unsigned int filehead;
3d3b8303
WX
112 int bmp_bpp;
113
d09acb9b 114 res = g_file_get_contents(filename, &content, file_sizep, &err);
9477c87e
PB
115 if (res == FALSE) {
116 error_report("failed to read splash file '%s'", filename);
117 g_error_free(err);
118 return NULL;
3d3b8303 119 }
9477c87e 120
3d3b8303 121 /* check file size */
9477c87e
PB
122 if (*file_sizep < 30) {
123 goto error;
3d3b8303 124 }
9477c87e 125
3d3b8303 126 /* check magic ID */
9477c87e
PB
127 filehead = ((content[0] & 0xff) + (content[1] << 8)) & 0xffff;
128 if (filehead == 0xd8ff) {
3d3b8303 129 file_type = JPG_FILE;
9477c87e
PB
130 } else if (filehead == 0x4d42) {
131 file_type = BMP_FILE;
3d3b8303 132 } else {
9477c87e 133 goto error;
3d3b8303 134 }
9477c87e 135
3d3b8303
WX
136 /* check BMP bpp */
137 if (file_type == BMP_FILE) {
9477c87e 138 bmp_bpp = (content[28] + (content[29] << 8)) & 0xffff;
3d3b8303 139 if (bmp_bpp != 24) {
9477c87e 140 goto error;
3d3b8303
WX
141 }
142 }
9477c87e 143
3d3b8303 144 /* return values */
3d3b8303 145 *file_typep = file_type;
9477c87e
PB
146
147 return content;
148
149error:
150 error_report("splash file '%s' format not recognized; must be JPEG "
151 "or 24 bit BMP", filename);
152 g_free(content);
153 return NULL;
3d3b8303
WX
154}
155
156static void fw_cfg_bootsplash(FWCfgState *s)
157{
158 int boot_splash_time = -1;
159 const char *boot_splash_filename = NULL;
160 char *p;
9477c87e 161 char *filename, *file_data;
3d1bba20 162 gsize file_size;
9f8863eb 163 int file_type;
3d3b8303
WX
164 const char *temp;
165
166 /* get user configuration */
167 QemuOptsList *plist = qemu_find_opts("boot-opts");
168 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
169 if (opts != NULL) {
170 temp = qemu_opt_get(opts, "splash");
171 if (temp != NULL) {
172 boot_splash_filename = temp;
173 }
174 temp = qemu_opt_get(opts, "splash-time");
175 if (temp != NULL) {
176 p = (char *)temp;
177 boot_splash_time = strtol(p, (char **)&p, 10);
178 }
179 }
180
181 /* insert splash time if user configurated */
182 if (boot_splash_time >= 0) {
183 /* validate the input */
184 if (boot_splash_time > 0xffff) {
185 error_report("splash time is big than 65535, force it to 65535.");
186 boot_splash_time = 0xffff;
187 }
188 /* use little endian format */
189 qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff);
190 qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff);
191 fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2);
192 }
193
194 /* insert splash file if user configurated */
195 if (boot_splash_filename != NULL) {
196 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
197 if (filename == NULL) {
198 error_report("failed to find file '%s'.", boot_splash_filename);
199 return;
200 }
9477c87e
PB
201
202 /* loading file data */
203 file_data = read_splashfile(filename, &file_size, &file_type);
204 if (file_data == NULL) {
7267c094 205 g_free(filename);
3d3b8303
WX
206 return;
207 }
ef1e1e07 208 g_free(boot_splash_filedata);
9477c87e 209 boot_splash_filedata = (uint8_t *)file_data;
3d3b8303 210 boot_splash_filedata_size = file_size;
9477c87e 211
3d3b8303
WX
212 /* insert data */
213 if (file_type == JPG_FILE) {
214 fw_cfg_add_file(s, "bootsplash.jpg",
215 boot_splash_filedata, boot_splash_filedata_size);
216 } else {
217 fw_cfg_add_file(s, "bootsplash.bmp",
218 boot_splash_filedata, boot_splash_filedata_size);
219 }
7267c094 220 g_free(filename);
3d3b8303
WX
221 }
222}
223
ac05f349
AK
224static void fw_cfg_reboot(FWCfgState *s)
225{
226 int reboot_timeout = -1;
227 char *p;
228 const char *temp;
229
230 /* get user configuration */
231 QemuOptsList *plist = qemu_find_opts("boot-opts");
232 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
233 if (opts != NULL) {
234 temp = qemu_opt_get(opts, "reboot-timeout");
235 if (temp != NULL) {
236 p = (char *)temp;
237 reboot_timeout = strtol(p, (char **)&p, 10);
238 }
239 }
240 /* validate the input */
241 if (reboot_timeout > 0xffff) {
242 error_report("reboot timeout is larger than 65535, force it to 65535.");
243 reboot_timeout = 0xffff;
244 }
245 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4);
246}
247
3cce6243
BS
248static void fw_cfg_write(FWCfgState *s, uint8_t value)
249{
023e3148 250 /* nothing, write support removed in QEMU v2.4+ */
3cce6243
BS
251}
252
253static int fw_cfg_select(FWCfgState *s, uint16_t key)
254{
3bef7e8a
GS
255 int arch, ret;
256 FWCfgEntry *e;
3cce6243
BS
257
258 s->cur_offset = 0;
259 if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
260 s->cur_entry = FW_CFG_INVALID;
261 ret = 0;
262 } else {
263 s->cur_entry = key;
264 ret = 1;
3bef7e8a
GS
265 /* entry successfully selected, now run callback if present */
266 arch = !!(key & FW_CFG_ARCH_LOCAL);
267 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK];
268 if (e->read_callback) {
3f8752b4 269 e->read_callback(e->callback_opaque);
3bef7e8a 270 }
3cce6243
BS
271 }
272
f6e35343 273 trace_fw_cfg_select(s, key, ret);
3cce6243
BS
274 return ret;
275}
276
277static uint8_t fw_cfg_read(FWCfgState *s)
278{
279 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
280 FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
281 uint8_t ret;
282
283 if (s->cur_entry == FW_CFG_INVALID || !e->data || s->cur_offset >= e->len)
284 ret = 0;
d87072ce 285 else {
3cce6243 286 ret = e->data[s->cur_offset++];
d87072ce 287 }
3cce6243 288
f6e35343 289 trace_fw_cfg_read(s, ret);
3cce6243
BS
290 return ret;
291}
292
a8170e5e 293static uint64_t fw_cfg_data_mem_read(void *opaque, hwaddr addr,
561e1827 294 unsigned size)
3cce6243 295{
cfaadf0e 296 FWCfgState *s = opaque;
36b62ae6 297 uint64_t value = 0;
cfaadf0e
LE
298 unsigned i;
299
300 for (i = 0; i < size; ++i) {
36b62ae6 301 value = (value << 8) | fw_cfg_read(s);
cfaadf0e 302 }
36b62ae6 303 return value;
3cce6243
BS
304}
305
a8170e5e 306static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
561e1827 307 uint64_t value, unsigned size)
3cce6243 308{
cfaadf0e 309 FWCfgState *s = opaque;
36b62ae6 310 unsigned i = size;
cfaadf0e 311
36b62ae6
LE
312 do {
313 fw_cfg_write(s, value >> (8 * --i));
314 } while (i);
cfaadf0e
LE
315}
316
a4c0d1de
MM
317static void fw_cfg_dma_transfer(FWCfgState *s)
318{
319 dma_addr_t len;
320 FWCfgDmaAccess dma;
321 int arch;
322 FWCfgEntry *e;
323 int read;
324 dma_addr_t dma_addr;
325
326 /* Reset the address before the next access */
327 dma_addr = s->dma_addr;
328 s->dma_addr = 0;
329
330 if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) {
331 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
332 FW_CFG_DMA_CTL_ERROR);
333 return;
334 }
335
336 dma.address = be64_to_cpu(dma.address);
337 dma.length = be32_to_cpu(dma.length);
338 dma.control = be32_to_cpu(dma.control);
339
340 if (dma.control & FW_CFG_DMA_CTL_SELECT) {
341 fw_cfg_select(s, dma.control >> 16);
342 }
343
344 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
345 e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
346
347 if (dma.control & FW_CFG_DMA_CTL_READ) {
348 read = 1;
349 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
350 read = 0;
351 } else {
352 dma.length = 0;
353 }
354
355 dma.control = 0;
356
357 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
358 if (s->cur_entry == FW_CFG_INVALID || !e->data ||
359 s->cur_offset >= e->len) {
360 len = dma.length;
361
362 /* If the access is not a read access, it will be a skip access,
363 * tested before.
364 */
365 if (read) {
366 if (dma_memory_set(s->dma_as, dma.address, 0, len)) {
367 dma.control |= FW_CFG_DMA_CTL_ERROR;
368 }
369 }
370
371 } else {
372 if (dma.length <= (e->len - s->cur_offset)) {
373 len = dma.length;
374 } else {
375 len = (e->len - s->cur_offset);
376 }
377
a4c0d1de
MM
378 /* If the access is not a read access, it will be a skip access,
379 * tested before.
380 */
381 if (read) {
382 if (dma_memory_write(s->dma_as, dma.address,
383 &e->data[s->cur_offset], len)) {
384 dma.control |= FW_CFG_DMA_CTL_ERROR;
385 }
386 }
387
388 s->cur_offset += len;
389 }
390
391 dma.address += len;
392 dma.length -= len;
393
394 }
395
396 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
397 dma.control);
398
399 trace_fw_cfg_read(s, 0);
400}
401
2cc06a88
KC
402static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
403 unsigned size)
404{
405 /* Return a signature value (and handle various read sizes) */
406 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
407}
408
a4c0d1de
MM
409static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
410 uint64_t value, unsigned size)
411{
412 FWCfgState *s = opaque;
413
414 if (size == 4) {
415 if (addr == 0) {
416 /* FWCfgDmaAccess high address */
417 s->dma_addr = value << 32;
418 } else if (addr == 4) {
419 /* FWCfgDmaAccess low address */
420 s->dma_addr |= value;
421 fw_cfg_dma_transfer(s);
422 }
423 } else if (size == 8 && addr == 0) {
424 s->dma_addr = value;
425 fw_cfg_dma_transfer(s);
426 }
427}
428
429static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
430 unsigned size, bool is_write)
431{
2cc06a88
KC
432 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
433 (size == 8 && addr == 0));
a4c0d1de
MM
434}
435
cfaadf0e
LE
436static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
437 unsigned size, bool is_write)
438{
439 return addr == 0;
3cce6243
BS
440}
441
a8170e5e 442static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
561e1827 443 uint64_t value, unsigned size)
3cce6243
BS
444{
445 fw_cfg_select(opaque, (uint16_t)value);
446}
447
a8170e5e 448static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
561e1827 449 unsigned size, bool is_write)
3cce6243 450{
561e1827 451 return is_write && size == 2;
3cce6243
BS
452}
453
a8170e5e 454static uint64_t fw_cfg_comb_read(void *opaque, hwaddr addr,
561e1827 455 unsigned size)
3cce6243 456{
561e1827 457 return fw_cfg_read(opaque);
3cce6243
BS
458}
459
a8170e5e 460static void fw_cfg_comb_write(void *opaque, hwaddr addr,
561e1827 461 uint64_t value, unsigned size)
3cce6243 462{
561e1827
AK
463 switch (size) {
464 case 1:
465 fw_cfg_write(opaque, (uint8_t)value);
466 break;
467 case 2:
468 fw_cfg_select(opaque, (uint16_t)value);
469 break;
470 }
3cce6243
BS
471}
472
a8170e5e 473static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
561e1827
AK
474 unsigned size, bool is_write)
475{
476 return (size == 1) || (is_write && size == 2);
477}
3cce6243 478
561e1827
AK
479static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
480 .write = fw_cfg_ctl_mem_write,
d789c845 481 .endianness = DEVICE_BIG_ENDIAN,
561e1827 482 .valid.accepts = fw_cfg_ctl_mem_valid,
3cce6243
BS
483};
484
561e1827
AK
485static const MemoryRegionOps fw_cfg_data_mem_ops = {
486 .read = fw_cfg_data_mem_read,
487 .write = fw_cfg_data_mem_write,
d789c845 488 .endianness = DEVICE_BIG_ENDIAN,
561e1827
AK
489 .valid = {
490 .min_access_size = 1,
491 .max_access_size = 1,
cfaadf0e 492 .accepts = fw_cfg_data_mem_valid,
561e1827 493 },
3cce6243
BS
494};
495
561e1827
AK
496static const MemoryRegionOps fw_cfg_comb_mem_ops = {
497 .read = fw_cfg_comb_read,
498 .write = fw_cfg_comb_write,
6fdf98f2 499 .endianness = DEVICE_LITTLE_ENDIAN,
561e1827 500 .valid.accepts = fw_cfg_comb_valid,
3cce6243
BS
501};
502
a4c0d1de 503static const MemoryRegionOps fw_cfg_dma_mem_ops = {
2cc06a88 504 .read = fw_cfg_dma_mem_read,
a4c0d1de
MM
505 .write = fw_cfg_dma_mem_write,
506 .endianness = DEVICE_BIG_ENDIAN,
507 .valid.accepts = fw_cfg_dma_mem_valid,
508 .valid.max_access_size = 8,
509 .impl.max_access_size = 8,
510};
511
3a5c16fc 512static void fw_cfg_reset(DeviceState *d)
3cce6243 513{
2ce92a11 514 FWCfgState *s = FW_CFG(d);
3cce6243 515
3bef7e8a
GS
516 /* we never register a read callback for FW_CFG_SIGNATURE */
517 fw_cfg_select(s, FW_CFG_SIGNATURE);
3cce6243
BS
518}
519
ff06108b
JQ
520/* Save restore 32 bit int as uint16_t
521 This is a Big hack, but it is how the old state did it.
522 Or we broke compatibility in the state, or we can't use struct tm
523 */
524
525static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size)
526{
527 uint32_t *v = pv;
528 *v = qemu_get_be16(f);
529 return 0;
530}
531
532static void put_unused(QEMUFile *f, void *pv, size_t size)
533{
66c80e75 534 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
ff06108b
JQ
535 fprintf(stderr, "This functions shouldn't be called.\n");
536}
537
d05ac8fa 538static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
ff06108b
JQ
539 .name = "int32_as_uint16",
540 .get = get_uint32_as_uint16,
541 .put = put_unused,
542};
543
544#define VMSTATE_UINT16_HACK(_f, _s, _t) \
545 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
546
547
548static bool is_version_1(void *opaque, int version_id)
549{
550 return version_id == 1;
551}
552
a4c0d1de
MM
553static bool fw_cfg_dma_enabled(void *opaque)
554{
555 FWCfgState *s = opaque;
556
557 return s->dma_enabled;
558}
559
560static const VMStateDescription vmstate_fw_cfg_dma = {
561 .name = "fw_cfg/dma",
562 .needed = fw_cfg_dma_enabled,
563 .fields = (VMStateField[]) {
564 VMSTATE_UINT64(dma_addr, FWCfgState),
565 VMSTATE_END_OF_LIST()
566 },
567};
568
7d2edd40
JQ
569static const VMStateDescription vmstate_fw_cfg = {
570 .name = "fw_cfg",
ff06108b 571 .version_id = 2,
7d2edd40 572 .minimum_version_id = 1,
d49805ae 573 .fields = (VMStateField[]) {
7d2edd40 574 VMSTATE_UINT16(cur_entry, FWCfgState),
ff06108b
JQ
575 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
576 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
7d2edd40 577 VMSTATE_END_OF_LIST()
a4c0d1de
MM
578 },
579 .subsections = (const VMStateDescription*[]) {
580 &vmstate_fw_cfg_dma,
581 NULL,
7d2edd40
JQ
582 }
583};
3cce6243 584
d87072ce
MT
585static void fw_cfg_add_bytes_read_callback(FWCfgState *s, uint16_t key,
586 FWCfgReadCallback callback,
587 void *callback_opaque,
588 void *data, size_t len)
3cce6243 589{
3cce6243
BS
590 int arch = !!(key & FW_CFG_ARCH_LOCAL);
591
592 key &= FW_CFG_ENTRY_MASK;
593
089da572 594 assert(key < FW_CFG_MAX_ENTRY && len < UINT32_MAX);
0f9b2141 595 assert(s->entries[arch][key].data == NULL); /* avoid key conflict */
3cce6243
BS
596
597 s->entries[arch][key].data = data;
089da572 598 s->entries[arch][key].len = (uint32_t)len;
d87072ce
MT
599 s->entries[arch][key].read_callback = callback;
600 s->entries[arch][key].callback_opaque = callback_opaque;
601}
602
bdbb5b17
GA
603static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
604 void *data, size_t len)
605{
606 void *ptr;
607 int arch = !!(key & FW_CFG_ARCH_LOCAL);
608
609 key &= FW_CFG_ENTRY_MASK;
610
611 assert(key < FW_CFG_MAX_ENTRY && len < UINT32_MAX);
612
613 /* return the old data to the function caller, avoid memory leak */
614 ptr = s->entries[arch][key].data;
615 s->entries[arch][key].data = data;
616 s->entries[arch][key].len = len;
617 s->entries[arch][key].callback_opaque = NULL;
bdbb5b17
GA
618
619 return ptr;
620}
621
d87072ce
MT
622void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
623{
624 fw_cfg_add_bytes_read_callback(s, key, NULL, NULL, data, len);
3cce6243
BS
625}
626
44687f75
MA
627void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
628{
629 size_t sz = strlen(value) + 1;
630
e7ae771f 631 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
44687f75
MA
632}
633
4cad3867 634void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
3cce6243
BS
635{
636 uint16_t *copy;
637
7267c094 638 copy = g_malloc(sizeof(value));
3cce6243 639 *copy = cpu_to_le16(value);
089da572 640 fw_cfg_add_bytes(s, key, copy, sizeof(value));
3cce6243
BS
641}
642
1edd34b6
GS
643void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value)
644{
645 uint16_t *copy, *old;
646
647 copy = g_malloc(sizeof(value));
648 *copy = cpu_to_le16(value);
649 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
650 g_free(old);
651}
652
4cad3867 653void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
3cce6243
BS
654{
655 uint32_t *copy;
656
7267c094 657 copy = g_malloc(sizeof(value));
3cce6243 658 *copy = cpu_to_le32(value);
089da572 659 fw_cfg_add_bytes(s, key, copy, sizeof(value));
3cce6243
BS
660}
661
4cad3867 662void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
3cce6243
BS
663{
664 uint64_t *copy;
665
7267c094 666 copy = g_malloc(sizeof(value));
3cce6243 667 *copy = cpu_to_le64(value);
089da572 668 fw_cfg_add_bytes(s, key, copy, sizeof(value));
3cce6243
BS
669}
670
d87072ce
MT
671void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
672 FWCfgReadCallback callback, void *callback_opaque,
673 void *data, size_t len)
abe147e0 674{
de9352bc 675 int i, index;
089da572 676 size_t dsize;
abe147e0
GH
677
678 if (!s->files) {
089da572 679 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * FW_CFG_FILE_SLOTS;
7267c094 680 s->files = g_malloc0(dsize);
089da572 681 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
abe147e0
GH
682 }
683
684 index = be32_to_cpu(s->files->count);
4cad3867 685 assert(index < FW_CFG_FILE_SLOTS);
abe147e0 686
de1f34cb
GN
687 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name),
688 filename);
de9352bc
GH
689 for (i = 0; i < index; i++) {
690 if (strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
0eb973f9
GS
691 error_report("duplicate fw_cfg file name: %s",
692 s->files->f[index].name);
693 exit(1);
de9352bc 694 }
abe147e0 695 }
de9352bc 696
0eb973f9
GS
697 fw_cfg_add_bytes_read_callback(s, FW_CFG_FILE_FIRST + index,
698 callback, callback_opaque, data, len);
699
abe147e0
GH
700 s->files->f[index].size = cpu_to_be32(len);
701 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
f6e35343 702 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
abe147e0
GH
703
704 s->files->count = cpu_to_be32(index+1);
abe147e0
GH
705}
706
d87072ce
MT
707void fw_cfg_add_file(FWCfgState *s, const char *filename,
708 void *data, size_t len)
709{
710 fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len);
711}
712
bdbb5b17
GA
713void *fw_cfg_modify_file(FWCfgState *s, const char *filename,
714 void *data, size_t len)
715{
716 int i, index;
f3b37668 717 void *ptr = NULL;
bdbb5b17
GA
718
719 assert(s->files);
720
721 index = be32_to_cpu(s->files->count);
722 assert(index < FW_CFG_FILE_SLOTS);
723
724 for (i = 0; i < index; i++) {
725 if (strcmp(filename, s->files->f[i].name) == 0) {
f3b37668
GA
726 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i,
727 data, len);
728 s->files->f[i].size = cpu_to_be32(len);
729 return ptr;
bdbb5b17
GA
730 }
731 }
732 /* add new one */
733 fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len);
734 return NULL;
735}
736
737static void fw_cfg_machine_reset(void *opaque)
962630f2 738{
bdbb5b17 739 void *ptr;
0e7a7592 740 size_t len;
bdbb5b17 741 FWCfgState *s = opaque;
30e32af7 742 char *bootindex = get_boot_devices_list(&len, false);
962630f2 743
bdbb5b17
GA
744 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)bootindex, len);
745 g_free(ptr);
746}
747
748static void fw_cfg_machine_ready(struct Notifier *n, void *data)
749{
750 FWCfgState *s = container_of(n, FWCfgState, machine_ready);
751 qemu_register_reset(fw_cfg_machine_reset, s);
962630f2
GN
752}
753
3cce6243 754
3a5c16fc 755
5712db6a
LE
756static void fw_cfg_init1(DeviceState *dev)
757{
758 FWCfgState *s = FW_CFG(dev);
3cce6243 759
cac12210
MT
760 assert(!object_resolve_path(FW_CFG_PATH, NULL));
761
762 object_property_add_child(qdev_get_machine(), FW_CFG_NAME, OBJECT(s), NULL);
10a584b2
HT
763
764 qdev_init_nofail(dev);
765
089da572 766 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
084a197a 767 fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
993fbfdb 768 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));
905fdcb5 769 fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
95387491 770 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
3d3b8303 771 fw_cfg_bootsplash(s);
ac05f349 772 fw_cfg_reboot(s);
962630f2
GN
773
774 s->machine_ready.notify = fw_cfg_machine_ready;
775 qemu_add_machine_init_done_notifier(&s->machine_ready);
3cce6243 776}
3a5c16fc 777
a4c0d1de
MM
778FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
779 AddressSpace *dma_as)
3a5c16fc 780{
5712db6a 781 DeviceState *dev;
a4c0d1de
MM
782 FWCfgState *s;
783 uint32_t version = FW_CFG_VERSION;
784 bool dma_enabled = dma_iobase && dma_as;
3a5c16fc 785
5712db6a
LE
786 dev = qdev_create(NULL, TYPE_FW_CFG_IO);
787 qdev_prop_set_uint32(dev, "iobase", iobase);
a4c0d1de
MM
788 qdev_prop_set_uint32(dev, "dma_iobase", dma_iobase);
789 qdev_prop_set_bit(dev, "dma_enabled", dma_enabled);
790
5712db6a 791 fw_cfg_init1(dev);
a4c0d1de
MM
792 s = FW_CFG(dev);
793
794 if (dma_enabled) {
795 /* 64 bits for the address field */
796 s->dma_as = dma_as;
797 s->dma_addr = 0;
798
799 version |= FW_CFG_VERSION_DMA;
800 }
801
802 fw_cfg_add_i32(s, FW_CFG_ID, version);
5712db6a 803
a4c0d1de
MM
804 return s;
805}
806
807FWCfgState *fw_cfg_init_io(uint32_t iobase)
808{
809 return fw_cfg_init_io_dma(iobase, 0, NULL);
56383955
HT
810}
811
a4c0d1de
MM
812FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
813 hwaddr data_addr, uint32_t data_width,
814 hwaddr dma_addr, AddressSpace *dma_as)
56383955 815{
5712db6a
LE
816 DeviceState *dev;
817 SysBusDevice *sbd;
a4c0d1de
MM
818 FWCfgState *s;
819 uint32_t version = FW_CFG_VERSION;
820 bool dma_enabled = dma_addr && dma_as;
56383955 821
5712db6a 822 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
6c87e3d5 823 qdev_prop_set_uint32(dev, "data_width", data_width);
a4c0d1de 824 qdev_prop_set_bit(dev, "dma_enabled", dma_enabled);
cfaadf0e 825
5712db6a
LE
826 fw_cfg_init1(dev);
827
828 sbd = SYS_BUS_DEVICE(dev);
829 sysbus_mmio_map(sbd, 0, ctl_addr);
830 sysbus_mmio_map(sbd, 1, data_addr);
831
a4c0d1de
MM
832 s = FW_CFG(dev);
833
834 if (dma_enabled) {
835 s->dma_as = dma_as;
836 s->dma_addr = 0;
837 sysbus_mmio_map(sbd, 2, dma_addr);
838 version |= FW_CFG_VERSION_DMA;
839 }
840
841 fw_cfg_add_i32(s, FW_CFG_ID, version);
842
843 return s;
5712db6a
LE
844}
845
6c87e3d5
LE
846FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
847{
848 return fw_cfg_init_mem_wide(ctl_addr, data_addr,
a4c0d1de
MM
849 fw_cfg_data_mem_ops.valid.max_access_size,
850 0, NULL);
6c87e3d5
LE
851}
852
5712db6a 853
600c60b7
MT
854FWCfgState *fw_cfg_find(void)
855{
2ce92a11 856 return FW_CFG(object_resolve_path(FW_CFG_PATH, NULL));
600c60b7
MT
857}
858
999e12bb
AL
859static void fw_cfg_class_init(ObjectClass *klass, void *data)
860{
39bffca2 861 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 862
39bffca2
AL
863 dc->reset = fw_cfg_reset;
864 dc->vmsd = &vmstate_fw_cfg;
999e12bb
AL
865}
866
8c43a6f0 867static const TypeInfo fw_cfg_info = {
600c60b7 868 .name = TYPE_FW_CFG,
39bffca2
AL
869 .parent = TYPE_SYS_BUS_DEVICE,
870 .instance_size = sizeof(FWCfgState),
871 .class_init = fw_cfg_class_init,
3a5c16fc
BS
872};
873
5712db6a
LE
874
875static Property fw_cfg_io_properties[] = {
876 DEFINE_PROP_UINT32("iobase", FWCfgIoState, iobase, -1),
a4c0d1de
MM
877 DEFINE_PROP_UINT32("dma_iobase", FWCfgIoState, dma_iobase, -1),
878 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
879 false),
5712db6a
LE
880 DEFINE_PROP_END_OF_LIST(),
881};
882
883static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
884{
885 FWCfgIoState *s = FW_CFG_IO(dev);
886 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
887
888 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
a4c0d1de 889 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
5712db6a 890 sysbus_add_io(sbd, s->iobase, &s->comb_iomem);
a4c0d1de
MM
891
892 if (FW_CFG(s)->dma_enabled) {
893 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
894 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
895 sizeof(dma_addr_t));
896 sysbus_add_io(sbd, s->dma_iobase, &FW_CFG(s)->dma_iomem);
897 }
5712db6a
LE
898}
899
900static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
901{
902 DeviceClass *dc = DEVICE_CLASS(klass);
903
904 dc->realize = fw_cfg_io_realize;
905 dc->props = fw_cfg_io_properties;
906}
907
908static const TypeInfo fw_cfg_io_info = {
909 .name = TYPE_FW_CFG_IO,
910 .parent = TYPE_FW_CFG,
911 .instance_size = sizeof(FWCfgIoState),
912 .class_init = fw_cfg_io_class_init,
913};
914
915
cfaadf0e
LE
916static Property fw_cfg_mem_properties[] = {
917 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
a4c0d1de
MM
918 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
919 false),
cfaadf0e
LE
920 DEFINE_PROP_END_OF_LIST(),
921};
922
5712db6a
LE
923static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
924{
925 FWCfgMemState *s = FW_CFG_MEM(dev);
926 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
cfaadf0e 927 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
5712db6a
LE
928
929 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
a4c0d1de 930 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
5712db6a
LE
931 sysbus_init_mmio(sbd, &s->ctl_iomem);
932
cfaadf0e
LE
933 if (s->data_width > data_ops->valid.max_access_size) {
934 /* memberwise copy because the "old_mmio" member is const */
935 s->wide_data_ops.read = data_ops->read;
936 s->wide_data_ops.write = data_ops->write;
937 s->wide_data_ops.endianness = data_ops->endianness;
938 s->wide_data_ops.valid = data_ops->valid;
939 s->wide_data_ops.impl = data_ops->impl;
940
941 s->wide_data_ops.valid.max_access_size = s->data_width;
942 s->wide_data_ops.impl.max_access_size = s->data_width;
943 data_ops = &s->wide_data_ops;
944 }
945 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
946 "fwcfg.data", data_ops->valid.max_access_size);
5712db6a 947 sysbus_init_mmio(sbd, &s->data_iomem);
a4c0d1de
MM
948
949 if (FW_CFG(s)->dma_enabled) {
950 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
951 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
952 sizeof(dma_addr_t));
953 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
954 }
5712db6a
LE
955}
956
957static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
958{
959 DeviceClass *dc = DEVICE_CLASS(klass);
960
961 dc->realize = fw_cfg_mem_realize;
cfaadf0e 962 dc->props = fw_cfg_mem_properties;
5712db6a
LE
963}
964
965static const TypeInfo fw_cfg_mem_info = {
966 .name = TYPE_FW_CFG_MEM,
967 .parent = TYPE_FW_CFG,
968 .instance_size = sizeof(FWCfgMemState),
969 .class_init = fw_cfg_mem_class_init,
970};
971
972
83f7d43a 973static void fw_cfg_register_types(void)
3a5c16fc 974{
39bffca2 975 type_register_static(&fw_cfg_info);
5712db6a
LE
976 type_register_static(&fw_cfg_io_info);
977 type_register_static(&fw_cfg_mem_info);
3a5c16fc
BS
978}
979
83f7d43a 980type_init(fw_cfg_register_types)