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Commit | Line | Data |
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3cce6243 BS |
1 | /* |
2 | * QEMU Firmware configuration device emulation | |
3 | * | |
4 | * Copyright (c) 2008 Gleb Natapov | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
0430891c | 24 | #include "qemu/osdep.h" |
83c9f4ca | 25 | #include "hw/hw.h" |
9c17d615 | 26 | #include "sysemu/sysemu.h" |
a4c0d1de | 27 | #include "sysemu/dma.h" |
0d09e41a PB |
28 | #include "hw/isa/isa.h" |
29 | #include "hw/nvram/fw_cfg.h" | |
83c9f4ca | 30 | #include "hw/sysbus.h" |
f6e35343 | 31 | #include "trace.h" |
1de7afc9 PB |
32 | #include "qemu/error-report.h" |
33 | #include "qemu/config-file.h" | |
f348b6d1 | 34 | #include "qemu/cutils.h" |
3cce6243 | 35 | |
600c60b7 MT |
36 | #define FW_CFG_NAME "fw_cfg" |
37 | #define FW_CFG_PATH "/machine/" FW_CFG_NAME | |
5712db6a LE |
38 | |
39 | #define TYPE_FW_CFG "fw_cfg" | |
40 | #define TYPE_FW_CFG_IO "fw_cfg_io" | |
41 | #define TYPE_FW_CFG_MEM "fw_cfg_mem" | |
42 | ||
43 | #define FW_CFG(obj) OBJECT_CHECK(FWCfgState, (obj), TYPE_FW_CFG) | |
44 | #define FW_CFG_IO(obj) OBJECT_CHECK(FWCfgIoState, (obj), TYPE_FW_CFG_IO) | |
45 | #define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_MEM) | |
3cce6243 | 46 | |
a4c0d1de MM |
47 | /* FW_CFG_VERSION bits */ |
48 | #define FW_CFG_VERSION 0x01 | |
49 | #define FW_CFG_VERSION_DMA 0x02 | |
50 | ||
51 | /* FW_CFG_DMA_CONTROL bits */ | |
52 | #define FW_CFG_DMA_CTL_ERROR 0x01 | |
53 | #define FW_CFG_DMA_CTL_READ 0x02 | |
54 | #define FW_CFG_DMA_CTL_SKIP 0x04 | |
55 | #define FW_CFG_DMA_CTL_SELECT 0x08 | |
56 | ||
2cc06a88 KC |
57 | #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */ |
58 | ||
b96ae2da | 59 | typedef struct FWCfgEntry { |
ff06108b | 60 | uint32_t len; |
3cce6243 BS |
61 | uint8_t *data; |
62 | void *callback_opaque; | |
d87072ce | 63 | FWCfgReadCallback read_callback; |
3cce6243 BS |
64 | } FWCfgEntry; |
65 | ||
b96ae2da | 66 | struct FWCfgState { |
2ce92a11 HT |
67 | /*< private >*/ |
68 | SysBusDevice parent_obj; | |
69 | /*< public >*/ | |
70 | ||
3cce6243 | 71 | FWCfgEntry entries[2][FW_CFG_MAX_ENTRY]; |
abe147e0 | 72 | FWCfgFiles *files; |
3cce6243 | 73 | uint16_t cur_entry; |
ff06108b | 74 | uint32_t cur_offset; |
962630f2 | 75 | Notifier machine_ready; |
a4c0d1de MM |
76 | |
77 | bool dma_enabled; | |
78 | dma_addr_t dma_addr; | |
79 | AddressSpace *dma_as; | |
80 | MemoryRegion dma_iomem; | |
c2b5bda4 | 81 | }; |
3cce6243 | 82 | |
5712db6a LE |
83 | struct FWCfgIoState { |
84 | /*< private >*/ | |
85 | FWCfgState parent_obj; | |
86 | /*< public >*/ | |
87 | ||
88 | MemoryRegion comb_iomem; | |
a4c0d1de | 89 | uint32_t iobase, dma_iobase; |
5712db6a LE |
90 | }; |
91 | ||
92 | struct FWCfgMemState { | |
93 | /*< private >*/ | |
94 | FWCfgState parent_obj; | |
95 | /*< public >*/ | |
96 | ||
97 | MemoryRegion ctl_iomem, data_iomem; | |
cfaadf0e LE |
98 | uint32_t data_width; |
99 | MemoryRegionOps wide_data_ops; | |
5712db6a LE |
100 | }; |
101 | ||
3d3b8303 WX |
102 | #define JPG_FILE 0 |
103 | #define BMP_FILE 1 | |
104 | ||
3d1bba20 | 105 | static char *read_splashfile(char *filename, gsize *file_sizep, |
d09acb9b | 106 | int *file_typep) |
3d3b8303 | 107 | { |
9477c87e PB |
108 | GError *err = NULL; |
109 | gboolean res; | |
110 | gchar *content; | |
9f8863eb MA |
111 | int file_type; |
112 | unsigned int filehead; | |
3d3b8303 WX |
113 | int bmp_bpp; |
114 | ||
d09acb9b | 115 | res = g_file_get_contents(filename, &content, file_sizep, &err); |
9477c87e PB |
116 | if (res == FALSE) { |
117 | error_report("failed to read splash file '%s'", filename); | |
118 | g_error_free(err); | |
119 | return NULL; | |
3d3b8303 | 120 | } |
9477c87e | 121 | |
3d3b8303 | 122 | /* check file size */ |
9477c87e PB |
123 | if (*file_sizep < 30) { |
124 | goto error; | |
3d3b8303 | 125 | } |
9477c87e | 126 | |
3d3b8303 | 127 | /* check magic ID */ |
9477c87e PB |
128 | filehead = ((content[0] & 0xff) + (content[1] << 8)) & 0xffff; |
129 | if (filehead == 0xd8ff) { | |
3d3b8303 | 130 | file_type = JPG_FILE; |
9477c87e PB |
131 | } else if (filehead == 0x4d42) { |
132 | file_type = BMP_FILE; | |
3d3b8303 | 133 | } else { |
9477c87e | 134 | goto error; |
3d3b8303 | 135 | } |
9477c87e | 136 | |
3d3b8303 WX |
137 | /* check BMP bpp */ |
138 | if (file_type == BMP_FILE) { | |
9477c87e | 139 | bmp_bpp = (content[28] + (content[29] << 8)) & 0xffff; |
3d3b8303 | 140 | if (bmp_bpp != 24) { |
9477c87e | 141 | goto error; |
3d3b8303 WX |
142 | } |
143 | } | |
9477c87e | 144 | |
3d3b8303 | 145 | /* return values */ |
3d3b8303 | 146 | *file_typep = file_type; |
9477c87e PB |
147 | |
148 | return content; | |
149 | ||
150 | error: | |
151 | error_report("splash file '%s' format not recognized; must be JPEG " | |
152 | "or 24 bit BMP", filename); | |
153 | g_free(content); | |
154 | return NULL; | |
3d3b8303 WX |
155 | } |
156 | ||
157 | static void fw_cfg_bootsplash(FWCfgState *s) | |
158 | { | |
159 | int boot_splash_time = -1; | |
160 | const char *boot_splash_filename = NULL; | |
161 | char *p; | |
9477c87e | 162 | char *filename, *file_data; |
3d1bba20 | 163 | gsize file_size; |
9f8863eb | 164 | int file_type; |
3d3b8303 WX |
165 | const char *temp; |
166 | ||
167 | /* get user configuration */ | |
168 | QemuOptsList *plist = qemu_find_opts("boot-opts"); | |
169 | QemuOpts *opts = QTAILQ_FIRST(&plist->head); | |
170 | if (opts != NULL) { | |
171 | temp = qemu_opt_get(opts, "splash"); | |
172 | if (temp != NULL) { | |
173 | boot_splash_filename = temp; | |
174 | } | |
175 | temp = qemu_opt_get(opts, "splash-time"); | |
176 | if (temp != NULL) { | |
177 | p = (char *)temp; | |
178 | boot_splash_time = strtol(p, (char **)&p, 10); | |
179 | } | |
180 | } | |
181 | ||
182 | /* insert splash time if user configurated */ | |
183 | if (boot_splash_time >= 0) { | |
184 | /* validate the input */ | |
185 | if (boot_splash_time > 0xffff) { | |
186 | error_report("splash time is big than 65535, force it to 65535."); | |
187 | boot_splash_time = 0xffff; | |
188 | } | |
189 | /* use little endian format */ | |
190 | qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff); | |
191 | qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff); | |
192 | fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2); | |
193 | } | |
194 | ||
195 | /* insert splash file if user configurated */ | |
196 | if (boot_splash_filename != NULL) { | |
197 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename); | |
198 | if (filename == NULL) { | |
199 | error_report("failed to find file '%s'.", boot_splash_filename); | |
200 | return; | |
201 | } | |
9477c87e PB |
202 | |
203 | /* loading file data */ | |
204 | file_data = read_splashfile(filename, &file_size, &file_type); | |
205 | if (file_data == NULL) { | |
7267c094 | 206 | g_free(filename); |
3d3b8303 WX |
207 | return; |
208 | } | |
ef1e1e07 | 209 | g_free(boot_splash_filedata); |
9477c87e | 210 | boot_splash_filedata = (uint8_t *)file_data; |
3d3b8303 | 211 | boot_splash_filedata_size = file_size; |
9477c87e | 212 | |
3d3b8303 WX |
213 | /* insert data */ |
214 | if (file_type == JPG_FILE) { | |
215 | fw_cfg_add_file(s, "bootsplash.jpg", | |
216 | boot_splash_filedata, boot_splash_filedata_size); | |
217 | } else { | |
218 | fw_cfg_add_file(s, "bootsplash.bmp", | |
219 | boot_splash_filedata, boot_splash_filedata_size); | |
220 | } | |
7267c094 | 221 | g_free(filename); |
3d3b8303 WX |
222 | } |
223 | } | |
224 | ||
ac05f349 AK |
225 | static void fw_cfg_reboot(FWCfgState *s) |
226 | { | |
227 | int reboot_timeout = -1; | |
228 | char *p; | |
229 | const char *temp; | |
230 | ||
231 | /* get user configuration */ | |
232 | QemuOptsList *plist = qemu_find_opts("boot-opts"); | |
233 | QemuOpts *opts = QTAILQ_FIRST(&plist->head); | |
234 | if (opts != NULL) { | |
235 | temp = qemu_opt_get(opts, "reboot-timeout"); | |
236 | if (temp != NULL) { | |
237 | p = (char *)temp; | |
238 | reboot_timeout = strtol(p, (char **)&p, 10); | |
239 | } | |
240 | } | |
241 | /* validate the input */ | |
242 | if (reboot_timeout > 0xffff) { | |
243 | error_report("reboot timeout is larger than 65535, force it to 65535."); | |
244 | reboot_timeout = 0xffff; | |
245 | } | |
246 | fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4); | |
247 | } | |
248 | ||
3cce6243 BS |
249 | static void fw_cfg_write(FWCfgState *s, uint8_t value) |
250 | { | |
023e3148 | 251 | /* nothing, write support removed in QEMU v2.4+ */ |
3cce6243 BS |
252 | } |
253 | ||
254 | static int fw_cfg_select(FWCfgState *s, uint16_t key) | |
255 | { | |
3bef7e8a GS |
256 | int arch, ret; |
257 | FWCfgEntry *e; | |
3cce6243 BS |
258 | |
259 | s->cur_offset = 0; | |
260 | if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) { | |
261 | s->cur_entry = FW_CFG_INVALID; | |
262 | ret = 0; | |
263 | } else { | |
264 | s->cur_entry = key; | |
265 | ret = 1; | |
3bef7e8a GS |
266 | /* entry successfully selected, now run callback if present */ |
267 | arch = !!(key & FW_CFG_ARCH_LOCAL); | |
268 | e = &s->entries[arch][key & FW_CFG_ENTRY_MASK]; | |
269 | if (e->read_callback) { | |
3f8752b4 | 270 | e->read_callback(e->callback_opaque); |
3bef7e8a | 271 | } |
3cce6243 BS |
272 | } |
273 | ||
f6e35343 | 274 | trace_fw_cfg_select(s, key, ret); |
3cce6243 BS |
275 | return ret; |
276 | } | |
277 | ||
38bf2093 GS |
278 | static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size) |
279 | { | |
280 | FWCfgState *s = opaque; | |
281 | int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); | |
282 | FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL : | |
283 | &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; | |
284 | uint64_t value = 0; | |
285 | ||
286 | assert(size > 0 && size <= sizeof(value)); | |
287 | if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) { | |
288 | /* The least significant 'size' bytes of the return value are | |
289 | * expected to contain a string preserving portion of the item | |
290 | * data, padded with zeros on the right in case we run out early. | |
291 | * In technical terms, we're composing the host-endian representation | |
292 | * of the big endian interpretation of the fw_cfg string. | |
293 | */ | |
294 | do { | |
295 | value = (value << 8) | e->data[s->cur_offset++]; | |
296 | } while (--size && s->cur_offset < e->len); | |
297 | /* If size is still not zero, we *did* run out early, so continue | |
298 | * left-shifting, to add the appropriate number of padding zeros | |
299 | * on the right. | |
300 | */ | |
301 | value <<= 8 * size; | |
302 | } | |
303 | ||
304 | trace_fw_cfg_read(s, value); | |
305 | return value; | |
306 | } | |
307 | ||
a8170e5e | 308 | static void fw_cfg_data_mem_write(void *opaque, hwaddr addr, |
561e1827 | 309 | uint64_t value, unsigned size) |
3cce6243 | 310 | { |
cfaadf0e | 311 | FWCfgState *s = opaque; |
36b62ae6 | 312 | unsigned i = size; |
cfaadf0e | 313 | |
36b62ae6 LE |
314 | do { |
315 | fw_cfg_write(s, value >> (8 * --i)); | |
316 | } while (i); | |
cfaadf0e LE |
317 | } |
318 | ||
a4c0d1de MM |
319 | static void fw_cfg_dma_transfer(FWCfgState *s) |
320 | { | |
321 | dma_addr_t len; | |
322 | FWCfgDmaAccess dma; | |
323 | int arch; | |
324 | FWCfgEntry *e; | |
325 | int read; | |
326 | dma_addr_t dma_addr; | |
327 | ||
328 | /* Reset the address before the next access */ | |
329 | dma_addr = s->dma_addr; | |
330 | s->dma_addr = 0; | |
331 | ||
332 | if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) { | |
333 | stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), | |
334 | FW_CFG_DMA_CTL_ERROR); | |
335 | return; | |
336 | } | |
337 | ||
338 | dma.address = be64_to_cpu(dma.address); | |
339 | dma.length = be32_to_cpu(dma.length); | |
340 | dma.control = be32_to_cpu(dma.control); | |
341 | ||
342 | if (dma.control & FW_CFG_DMA_CTL_SELECT) { | |
343 | fw_cfg_select(s, dma.control >> 16); | |
344 | } | |
345 | ||
346 | arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); | |
66f8fd9d GS |
347 | e = (s->cur_entry == FW_CFG_INVALID) ? NULL : |
348 | &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; | |
a4c0d1de MM |
349 | |
350 | if (dma.control & FW_CFG_DMA_CTL_READ) { | |
351 | read = 1; | |
352 | } else if (dma.control & FW_CFG_DMA_CTL_SKIP) { | |
353 | read = 0; | |
354 | } else { | |
355 | dma.length = 0; | |
356 | } | |
357 | ||
358 | dma.control = 0; | |
359 | ||
360 | while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) { | |
361 | if (s->cur_entry == FW_CFG_INVALID || !e->data || | |
362 | s->cur_offset >= e->len) { | |
363 | len = dma.length; | |
364 | ||
365 | /* If the access is not a read access, it will be a skip access, | |
366 | * tested before. | |
367 | */ | |
368 | if (read) { | |
369 | if (dma_memory_set(s->dma_as, dma.address, 0, len)) { | |
370 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
371 | } | |
372 | } | |
373 | ||
374 | } else { | |
375 | if (dma.length <= (e->len - s->cur_offset)) { | |
376 | len = dma.length; | |
377 | } else { | |
378 | len = (e->len - s->cur_offset); | |
379 | } | |
380 | ||
a4c0d1de MM |
381 | /* If the access is not a read access, it will be a skip access, |
382 | * tested before. | |
383 | */ | |
384 | if (read) { | |
385 | if (dma_memory_write(s->dma_as, dma.address, | |
386 | &e->data[s->cur_offset], len)) { | |
387 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
388 | } | |
389 | } | |
390 | ||
391 | s->cur_offset += len; | |
392 | } | |
393 | ||
394 | dma.address += len; | |
395 | dma.length -= len; | |
396 | ||
397 | } | |
398 | ||
399 | stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), | |
400 | dma.control); | |
401 | ||
402 | trace_fw_cfg_read(s, 0); | |
403 | } | |
404 | ||
2cc06a88 KC |
405 | static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr, |
406 | unsigned size) | |
407 | { | |
408 | /* Return a signature value (and handle various read sizes) */ | |
409 | return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8); | |
410 | } | |
411 | ||
a4c0d1de MM |
412 | static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, |
413 | uint64_t value, unsigned size) | |
414 | { | |
415 | FWCfgState *s = opaque; | |
416 | ||
417 | if (size == 4) { | |
418 | if (addr == 0) { | |
419 | /* FWCfgDmaAccess high address */ | |
420 | s->dma_addr = value << 32; | |
421 | } else if (addr == 4) { | |
422 | /* FWCfgDmaAccess low address */ | |
423 | s->dma_addr |= value; | |
424 | fw_cfg_dma_transfer(s); | |
425 | } | |
426 | } else if (size == 8 && addr == 0) { | |
427 | s->dma_addr = value; | |
428 | fw_cfg_dma_transfer(s); | |
429 | } | |
430 | } | |
431 | ||
432 | static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, | |
433 | unsigned size, bool is_write) | |
434 | { | |
2cc06a88 KC |
435 | return !is_write || ((size == 4 && (addr == 0 || addr == 4)) || |
436 | (size == 8 && addr == 0)); | |
a4c0d1de MM |
437 | } |
438 | ||
cfaadf0e LE |
439 | static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, |
440 | unsigned size, bool is_write) | |
441 | { | |
442 | return addr == 0; | |
3cce6243 BS |
443 | } |
444 | ||
a8170e5e | 445 | static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr, |
561e1827 | 446 | uint64_t value, unsigned size) |
3cce6243 BS |
447 | { |
448 | fw_cfg_select(opaque, (uint16_t)value); | |
449 | } | |
450 | ||
a8170e5e | 451 | static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr, |
561e1827 | 452 | unsigned size, bool is_write) |
3cce6243 | 453 | { |
561e1827 | 454 | return is_write && size == 2; |
3cce6243 BS |
455 | } |
456 | ||
a8170e5e | 457 | static void fw_cfg_comb_write(void *opaque, hwaddr addr, |
561e1827 | 458 | uint64_t value, unsigned size) |
3cce6243 | 459 | { |
561e1827 AK |
460 | switch (size) { |
461 | case 1: | |
462 | fw_cfg_write(opaque, (uint8_t)value); | |
463 | break; | |
464 | case 2: | |
465 | fw_cfg_select(opaque, (uint16_t)value); | |
466 | break; | |
467 | } | |
3cce6243 BS |
468 | } |
469 | ||
a8170e5e | 470 | static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, |
561e1827 AK |
471 | unsigned size, bool is_write) |
472 | { | |
473 | return (size == 1) || (is_write && size == 2); | |
474 | } | |
3cce6243 | 475 | |
561e1827 AK |
476 | static const MemoryRegionOps fw_cfg_ctl_mem_ops = { |
477 | .write = fw_cfg_ctl_mem_write, | |
d789c845 | 478 | .endianness = DEVICE_BIG_ENDIAN, |
561e1827 | 479 | .valid.accepts = fw_cfg_ctl_mem_valid, |
3cce6243 BS |
480 | }; |
481 | ||
561e1827 | 482 | static const MemoryRegionOps fw_cfg_data_mem_ops = { |
38bf2093 | 483 | .read = fw_cfg_data_read, |
561e1827 | 484 | .write = fw_cfg_data_mem_write, |
d789c845 | 485 | .endianness = DEVICE_BIG_ENDIAN, |
561e1827 AK |
486 | .valid = { |
487 | .min_access_size = 1, | |
488 | .max_access_size = 1, | |
cfaadf0e | 489 | .accepts = fw_cfg_data_mem_valid, |
561e1827 | 490 | }, |
3cce6243 BS |
491 | }; |
492 | ||
561e1827 | 493 | static const MemoryRegionOps fw_cfg_comb_mem_ops = { |
6c8d56a2 | 494 | .read = fw_cfg_data_read, |
561e1827 | 495 | .write = fw_cfg_comb_write, |
6fdf98f2 | 496 | .endianness = DEVICE_LITTLE_ENDIAN, |
561e1827 | 497 | .valid.accepts = fw_cfg_comb_valid, |
3cce6243 BS |
498 | }; |
499 | ||
a4c0d1de | 500 | static const MemoryRegionOps fw_cfg_dma_mem_ops = { |
2cc06a88 | 501 | .read = fw_cfg_dma_mem_read, |
a4c0d1de MM |
502 | .write = fw_cfg_dma_mem_write, |
503 | .endianness = DEVICE_BIG_ENDIAN, | |
504 | .valid.accepts = fw_cfg_dma_mem_valid, | |
505 | .valid.max_access_size = 8, | |
506 | .impl.max_access_size = 8, | |
507 | }; | |
508 | ||
3a5c16fc | 509 | static void fw_cfg_reset(DeviceState *d) |
3cce6243 | 510 | { |
2ce92a11 | 511 | FWCfgState *s = FW_CFG(d); |
3cce6243 | 512 | |
3bef7e8a GS |
513 | /* we never register a read callback for FW_CFG_SIGNATURE */ |
514 | fw_cfg_select(s, FW_CFG_SIGNATURE); | |
3cce6243 BS |
515 | } |
516 | ||
ff06108b JQ |
517 | /* Save restore 32 bit int as uint16_t |
518 | This is a Big hack, but it is how the old state did it. | |
519 | Or we broke compatibility in the state, or we can't use struct tm | |
520 | */ | |
521 | ||
522 | static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size) | |
523 | { | |
524 | uint32_t *v = pv; | |
525 | *v = qemu_get_be16(f); | |
526 | return 0; | |
527 | } | |
528 | ||
529 | static void put_unused(QEMUFile *f, void *pv, size_t size) | |
530 | { | |
66c80e75 | 531 | fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n"); |
ff06108b JQ |
532 | fprintf(stderr, "This functions shouldn't be called.\n"); |
533 | } | |
534 | ||
d05ac8fa | 535 | static const VMStateInfo vmstate_hack_uint32_as_uint16 = { |
ff06108b JQ |
536 | .name = "int32_as_uint16", |
537 | .get = get_uint32_as_uint16, | |
538 | .put = put_unused, | |
539 | }; | |
540 | ||
541 | #define VMSTATE_UINT16_HACK(_f, _s, _t) \ | |
542 | VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t) | |
543 | ||
544 | ||
545 | static bool is_version_1(void *opaque, int version_id) | |
546 | { | |
547 | return version_id == 1; | |
548 | } | |
549 | ||
a4c0d1de MM |
550 | static bool fw_cfg_dma_enabled(void *opaque) |
551 | { | |
552 | FWCfgState *s = opaque; | |
553 | ||
554 | return s->dma_enabled; | |
555 | } | |
556 | ||
557 | static const VMStateDescription vmstate_fw_cfg_dma = { | |
558 | .name = "fw_cfg/dma", | |
559 | .needed = fw_cfg_dma_enabled, | |
560 | .fields = (VMStateField[]) { | |
561 | VMSTATE_UINT64(dma_addr, FWCfgState), | |
562 | VMSTATE_END_OF_LIST() | |
563 | }, | |
564 | }; | |
565 | ||
7d2edd40 JQ |
566 | static const VMStateDescription vmstate_fw_cfg = { |
567 | .name = "fw_cfg", | |
ff06108b | 568 | .version_id = 2, |
7d2edd40 | 569 | .minimum_version_id = 1, |
d49805ae | 570 | .fields = (VMStateField[]) { |
7d2edd40 | 571 | VMSTATE_UINT16(cur_entry, FWCfgState), |
ff06108b JQ |
572 | VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1), |
573 | VMSTATE_UINT32_V(cur_offset, FWCfgState, 2), | |
7d2edd40 | 574 | VMSTATE_END_OF_LIST() |
a4c0d1de MM |
575 | }, |
576 | .subsections = (const VMStateDescription*[]) { | |
577 | &vmstate_fw_cfg_dma, | |
578 | NULL, | |
7d2edd40 JQ |
579 | } |
580 | }; | |
3cce6243 | 581 | |
d87072ce MT |
582 | static void fw_cfg_add_bytes_read_callback(FWCfgState *s, uint16_t key, |
583 | FWCfgReadCallback callback, | |
584 | void *callback_opaque, | |
585 | void *data, size_t len) | |
3cce6243 | 586 | { |
3cce6243 BS |
587 | int arch = !!(key & FW_CFG_ARCH_LOCAL); |
588 | ||
589 | key &= FW_CFG_ENTRY_MASK; | |
590 | ||
089da572 | 591 | assert(key < FW_CFG_MAX_ENTRY && len < UINT32_MAX); |
0f9b2141 | 592 | assert(s->entries[arch][key].data == NULL); /* avoid key conflict */ |
3cce6243 BS |
593 | |
594 | s->entries[arch][key].data = data; | |
089da572 | 595 | s->entries[arch][key].len = (uint32_t)len; |
d87072ce MT |
596 | s->entries[arch][key].read_callback = callback; |
597 | s->entries[arch][key].callback_opaque = callback_opaque; | |
598 | } | |
599 | ||
bdbb5b17 GA |
600 | static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key, |
601 | void *data, size_t len) | |
602 | { | |
603 | void *ptr; | |
604 | int arch = !!(key & FW_CFG_ARCH_LOCAL); | |
605 | ||
606 | key &= FW_CFG_ENTRY_MASK; | |
607 | ||
608 | assert(key < FW_CFG_MAX_ENTRY && len < UINT32_MAX); | |
609 | ||
610 | /* return the old data to the function caller, avoid memory leak */ | |
611 | ptr = s->entries[arch][key].data; | |
612 | s->entries[arch][key].data = data; | |
613 | s->entries[arch][key].len = len; | |
614 | s->entries[arch][key].callback_opaque = NULL; | |
bdbb5b17 GA |
615 | |
616 | return ptr; | |
617 | } | |
618 | ||
d87072ce MT |
619 | void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len) |
620 | { | |
621 | fw_cfg_add_bytes_read_callback(s, key, NULL, NULL, data, len); | |
3cce6243 BS |
622 | } |
623 | ||
44687f75 MA |
624 | void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value) |
625 | { | |
626 | size_t sz = strlen(value) + 1; | |
627 | ||
e7ae771f | 628 | fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz); |
44687f75 MA |
629 | } |
630 | ||
4cad3867 | 631 | void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value) |
3cce6243 BS |
632 | { |
633 | uint16_t *copy; | |
634 | ||
7267c094 | 635 | copy = g_malloc(sizeof(value)); |
3cce6243 | 636 | *copy = cpu_to_le16(value); |
089da572 | 637 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
638 | } |
639 | ||
1edd34b6 GS |
640 | void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value) |
641 | { | |
642 | uint16_t *copy, *old; | |
643 | ||
644 | copy = g_malloc(sizeof(value)); | |
645 | *copy = cpu_to_le16(value); | |
646 | old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); | |
647 | g_free(old); | |
648 | } | |
649 | ||
4cad3867 | 650 | void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value) |
3cce6243 BS |
651 | { |
652 | uint32_t *copy; | |
653 | ||
7267c094 | 654 | copy = g_malloc(sizeof(value)); |
3cce6243 | 655 | *copy = cpu_to_le32(value); |
089da572 | 656 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
657 | } |
658 | ||
4cad3867 | 659 | void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value) |
3cce6243 BS |
660 | { |
661 | uint64_t *copy; | |
662 | ||
7267c094 | 663 | copy = g_malloc(sizeof(value)); |
3cce6243 | 664 | *copy = cpu_to_le64(value); |
089da572 | 665 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
666 | } |
667 | ||
d87072ce MT |
668 | void fw_cfg_add_file_callback(FWCfgState *s, const char *filename, |
669 | FWCfgReadCallback callback, void *callback_opaque, | |
670 | void *data, size_t len) | |
abe147e0 | 671 | { |
de9352bc | 672 | int i, index; |
089da572 | 673 | size_t dsize; |
abe147e0 GH |
674 | |
675 | if (!s->files) { | |
089da572 | 676 | dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * FW_CFG_FILE_SLOTS; |
7267c094 | 677 | s->files = g_malloc0(dsize); |
089da572 | 678 | fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize); |
abe147e0 GH |
679 | } |
680 | ||
681 | index = be32_to_cpu(s->files->count); | |
4cad3867 | 682 | assert(index < FW_CFG_FILE_SLOTS); |
abe147e0 | 683 | |
de1f34cb GN |
684 | pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), |
685 | filename); | |
de9352bc GH |
686 | for (i = 0; i < index; i++) { |
687 | if (strcmp(s->files->f[index].name, s->files->f[i].name) == 0) { | |
0eb973f9 GS |
688 | error_report("duplicate fw_cfg file name: %s", |
689 | s->files->f[index].name); | |
690 | exit(1); | |
de9352bc | 691 | } |
abe147e0 | 692 | } |
de9352bc | 693 | |
0eb973f9 GS |
694 | fw_cfg_add_bytes_read_callback(s, FW_CFG_FILE_FIRST + index, |
695 | callback, callback_opaque, data, len); | |
696 | ||
abe147e0 GH |
697 | s->files->f[index].size = cpu_to_be32(len); |
698 | s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index); | |
f6e35343 | 699 | trace_fw_cfg_add_file(s, index, s->files->f[index].name, len); |
abe147e0 GH |
700 | |
701 | s->files->count = cpu_to_be32(index+1); | |
abe147e0 GH |
702 | } |
703 | ||
d87072ce MT |
704 | void fw_cfg_add_file(FWCfgState *s, const char *filename, |
705 | void *data, size_t len) | |
706 | { | |
707 | fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len); | |
708 | } | |
709 | ||
bdbb5b17 GA |
710 | void *fw_cfg_modify_file(FWCfgState *s, const char *filename, |
711 | void *data, size_t len) | |
712 | { | |
713 | int i, index; | |
f3b37668 | 714 | void *ptr = NULL; |
bdbb5b17 GA |
715 | |
716 | assert(s->files); | |
717 | ||
718 | index = be32_to_cpu(s->files->count); | |
719 | assert(index < FW_CFG_FILE_SLOTS); | |
720 | ||
721 | for (i = 0; i < index; i++) { | |
722 | if (strcmp(filename, s->files->f[i].name) == 0) { | |
f3b37668 GA |
723 | ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i, |
724 | data, len); | |
725 | s->files->f[i].size = cpu_to_be32(len); | |
726 | return ptr; | |
bdbb5b17 GA |
727 | } |
728 | } | |
729 | /* add new one */ | |
730 | fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len); | |
731 | return NULL; | |
732 | } | |
733 | ||
734 | static void fw_cfg_machine_reset(void *opaque) | |
962630f2 | 735 | { |
bdbb5b17 | 736 | void *ptr; |
0e7a7592 | 737 | size_t len; |
bdbb5b17 | 738 | FWCfgState *s = opaque; |
30e32af7 | 739 | char *bootindex = get_boot_devices_list(&len, false); |
962630f2 | 740 | |
bdbb5b17 GA |
741 | ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)bootindex, len); |
742 | g_free(ptr); | |
743 | } | |
744 | ||
745 | static void fw_cfg_machine_ready(struct Notifier *n, void *data) | |
746 | { | |
747 | FWCfgState *s = container_of(n, FWCfgState, machine_ready); | |
748 | qemu_register_reset(fw_cfg_machine_reset, s); | |
962630f2 GN |
749 | } |
750 | ||
3cce6243 | 751 | |
3a5c16fc | 752 | |
5712db6a LE |
753 | static void fw_cfg_init1(DeviceState *dev) |
754 | { | |
755 | FWCfgState *s = FW_CFG(dev); | |
3cce6243 | 756 | |
cac12210 MT |
757 | assert(!object_resolve_path(FW_CFG_PATH, NULL)); |
758 | ||
759 | object_property_add_child(qdev_get_machine(), FW_CFG_NAME, OBJECT(s), NULL); | |
10a584b2 HT |
760 | |
761 | qdev_init_nofail(dev); | |
762 | ||
089da572 | 763 | fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4); |
084a197a | 764 | fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16); |
993fbfdb | 765 | fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC)); |
905fdcb5 | 766 | fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
95387491 | 767 | fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu); |
3d3b8303 | 768 | fw_cfg_bootsplash(s); |
ac05f349 | 769 | fw_cfg_reboot(s); |
962630f2 GN |
770 | |
771 | s->machine_ready.notify = fw_cfg_machine_ready; | |
772 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
3cce6243 | 773 | } |
3a5c16fc | 774 | |
a4c0d1de MM |
775 | FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, |
776 | AddressSpace *dma_as) | |
3a5c16fc | 777 | { |
5712db6a | 778 | DeviceState *dev; |
a4c0d1de MM |
779 | FWCfgState *s; |
780 | uint32_t version = FW_CFG_VERSION; | |
e6915b5f | 781 | bool dma_requested = dma_iobase && dma_as; |
3a5c16fc | 782 | |
5712db6a LE |
783 | dev = qdev_create(NULL, TYPE_FW_CFG_IO); |
784 | qdev_prop_set_uint32(dev, "iobase", iobase); | |
a4c0d1de | 785 | qdev_prop_set_uint32(dev, "dma_iobase", dma_iobase); |
e6915b5f LE |
786 | if (!dma_requested) { |
787 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
788 | } | |
a4c0d1de | 789 | |
5712db6a | 790 | fw_cfg_init1(dev); |
a4c0d1de MM |
791 | s = FW_CFG(dev); |
792 | ||
e6915b5f | 793 | if (s->dma_enabled) { |
a4c0d1de MM |
794 | /* 64 bits for the address field */ |
795 | s->dma_as = dma_as; | |
796 | s->dma_addr = 0; | |
797 | ||
798 | version |= FW_CFG_VERSION_DMA; | |
799 | } | |
800 | ||
801 | fw_cfg_add_i32(s, FW_CFG_ID, version); | |
5712db6a | 802 | |
a4c0d1de MM |
803 | return s; |
804 | } | |
805 | ||
806 | FWCfgState *fw_cfg_init_io(uint32_t iobase) | |
807 | { | |
808 | return fw_cfg_init_io_dma(iobase, 0, NULL); | |
56383955 HT |
809 | } |
810 | ||
a4c0d1de MM |
811 | FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, |
812 | hwaddr data_addr, uint32_t data_width, | |
813 | hwaddr dma_addr, AddressSpace *dma_as) | |
56383955 | 814 | { |
5712db6a LE |
815 | DeviceState *dev; |
816 | SysBusDevice *sbd; | |
a4c0d1de MM |
817 | FWCfgState *s; |
818 | uint32_t version = FW_CFG_VERSION; | |
e6915b5f | 819 | bool dma_requested = dma_addr && dma_as; |
56383955 | 820 | |
5712db6a | 821 | dev = qdev_create(NULL, TYPE_FW_CFG_MEM); |
6c87e3d5 | 822 | qdev_prop_set_uint32(dev, "data_width", data_width); |
e6915b5f LE |
823 | if (!dma_requested) { |
824 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
825 | } | |
cfaadf0e | 826 | |
5712db6a LE |
827 | fw_cfg_init1(dev); |
828 | ||
829 | sbd = SYS_BUS_DEVICE(dev); | |
830 | sysbus_mmio_map(sbd, 0, ctl_addr); | |
831 | sysbus_mmio_map(sbd, 1, data_addr); | |
832 | ||
a4c0d1de MM |
833 | s = FW_CFG(dev); |
834 | ||
e6915b5f | 835 | if (s->dma_enabled) { |
a4c0d1de MM |
836 | s->dma_as = dma_as; |
837 | s->dma_addr = 0; | |
838 | sysbus_mmio_map(sbd, 2, dma_addr); | |
839 | version |= FW_CFG_VERSION_DMA; | |
840 | } | |
841 | ||
842 | fw_cfg_add_i32(s, FW_CFG_ID, version); | |
843 | ||
844 | return s; | |
5712db6a LE |
845 | } |
846 | ||
6c87e3d5 LE |
847 | FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr) |
848 | { | |
849 | return fw_cfg_init_mem_wide(ctl_addr, data_addr, | |
a4c0d1de MM |
850 | fw_cfg_data_mem_ops.valid.max_access_size, |
851 | 0, NULL); | |
6c87e3d5 LE |
852 | } |
853 | ||
5712db6a | 854 | |
600c60b7 MT |
855 | FWCfgState *fw_cfg_find(void) |
856 | { | |
2ce92a11 | 857 | return FW_CFG(object_resolve_path(FW_CFG_PATH, NULL)); |
600c60b7 MT |
858 | } |
859 | ||
999e12bb AL |
860 | static void fw_cfg_class_init(ObjectClass *klass, void *data) |
861 | { | |
39bffca2 | 862 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 863 | |
39bffca2 AL |
864 | dc->reset = fw_cfg_reset; |
865 | dc->vmsd = &vmstate_fw_cfg; | |
999e12bb AL |
866 | } |
867 | ||
8c43a6f0 | 868 | static const TypeInfo fw_cfg_info = { |
600c60b7 | 869 | .name = TYPE_FW_CFG, |
39bffca2 AL |
870 | .parent = TYPE_SYS_BUS_DEVICE, |
871 | .instance_size = sizeof(FWCfgState), | |
872 | .class_init = fw_cfg_class_init, | |
3a5c16fc BS |
873 | }; |
874 | ||
5712db6a LE |
875 | |
876 | static Property fw_cfg_io_properties[] = { | |
877 | DEFINE_PROP_UINT32("iobase", FWCfgIoState, iobase, -1), | |
a4c0d1de MM |
878 | DEFINE_PROP_UINT32("dma_iobase", FWCfgIoState, dma_iobase, -1), |
879 | DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, | |
e6915b5f | 880 | true), |
5712db6a LE |
881 | DEFINE_PROP_END_OF_LIST(), |
882 | }; | |
883 | ||
884 | static void fw_cfg_io_realize(DeviceState *dev, Error **errp) | |
885 | { | |
886 | FWCfgIoState *s = FW_CFG_IO(dev); | |
887 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
888 | ||
ce9a2aa3 GS |
889 | /* when using port i/o, the 8-bit data register ALWAYS overlaps |
890 | * with half of the 16-bit control register. Hence, the total size | |
891 | * of the i/o region used is FW_CFG_CTL_SIZE */ | |
5712db6a | 892 | memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops, |
a4c0d1de | 893 | FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE); |
5712db6a | 894 | sysbus_add_io(sbd, s->iobase, &s->comb_iomem); |
a4c0d1de MM |
895 | |
896 | if (FW_CFG(s)->dma_enabled) { | |
897 | memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), | |
898 | &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", | |
899 | sizeof(dma_addr_t)); | |
900 | sysbus_add_io(sbd, s->dma_iobase, &FW_CFG(s)->dma_iomem); | |
901 | } | |
5712db6a LE |
902 | } |
903 | ||
904 | static void fw_cfg_io_class_init(ObjectClass *klass, void *data) | |
905 | { | |
906 | DeviceClass *dc = DEVICE_CLASS(klass); | |
907 | ||
908 | dc->realize = fw_cfg_io_realize; | |
909 | dc->props = fw_cfg_io_properties; | |
910 | } | |
911 | ||
912 | static const TypeInfo fw_cfg_io_info = { | |
913 | .name = TYPE_FW_CFG_IO, | |
914 | .parent = TYPE_FW_CFG, | |
915 | .instance_size = sizeof(FWCfgIoState), | |
916 | .class_init = fw_cfg_io_class_init, | |
917 | }; | |
918 | ||
919 | ||
cfaadf0e LE |
920 | static Property fw_cfg_mem_properties[] = { |
921 | DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1), | |
a4c0d1de | 922 | DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled, |
e6915b5f | 923 | true), |
cfaadf0e LE |
924 | DEFINE_PROP_END_OF_LIST(), |
925 | }; | |
926 | ||
5712db6a LE |
927 | static void fw_cfg_mem_realize(DeviceState *dev, Error **errp) |
928 | { | |
929 | FWCfgMemState *s = FW_CFG_MEM(dev); | |
930 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
cfaadf0e | 931 | const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops; |
5712db6a LE |
932 | |
933 | memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops, | |
a4c0d1de | 934 | FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE); |
5712db6a LE |
935 | sysbus_init_mmio(sbd, &s->ctl_iomem); |
936 | ||
cfaadf0e LE |
937 | if (s->data_width > data_ops->valid.max_access_size) { |
938 | /* memberwise copy because the "old_mmio" member is const */ | |
939 | s->wide_data_ops.read = data_ops->read; | |
940 | s->wide_data_ops.write = data_ops->write; | |
941 | s->wide_data_ops.endianness = data_ops->endianness; | |
942 | s->wide_data_ops.valid = data_ops->valid; | |
943 | s->wide_data_ops.impl = data_ops->impl; | |
944 | ||
945 | s->wide_data_ops.valid.max_access_size = s->data_width; | |
946 | s->wide_data_ops.impl.max_access_size = s->data_width; | |
947 | data_ops = &s->wide_data_ops; | |
948 | } | |
949 | memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s), | |
950 | "fwcfg.data", data_ops->valid.max_access_size); | |
5712db6a | 951 | sysbus_init_mmio(sbd, &s->data_iomem); |
a4c0d1de MM |
952 | |
953 | if (FW_CFG(s)->dma_enabled) { | |
954 | memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), | |
955 | &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", | |
956 | sizeof(dma_addr_t)); | |
957 | sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem); | |
958 | } | |
5712db6a LE |
959 | } |
960 | ||
961 | static void fw_cfg_mem_class_init(ObjectClass *klass, void *data) | |
962 | { | |
963 | DeviceClass *dc = DEVICE_CLASS(klass); | |
964 | ||
965 | dc->realize = fw_cfg_mem_realize; | |
cfaadf0e | 966 | dc->props = fw_cfg_mem_properties; |
5712db6a LE |
967 | } |
968 | ||
969 | static const TypeInfo fw_cfg_mem_info = { | |
970 | .name = TYPE_FW_CFG_MEM, | |
971 | .parent = TYPE_FW_CFG, | |
972 | .instance_size = sizeof(FWCfgMemState), | |
973 | .class_init = fw_cfg_mem_class_init, | |
974 | }; | |
975 | ||
976 | ||
83f7d43a | 977 | static void fw_cfg_register_types(void) |
3a5c16fc | 978 | { |
39bffca2 | 979 | type_register_static(&fw_cfg_info); |
5712db6a LE |
980 | type_register_static(&fw_cfg_io_info); |
981 | type_register_static(&fw_cfg_mem_info); | |
3a5c16fc BS |
982 | } |
983 | ||
83f7d43a | 984 | type_init(fw_cfg_register_types) |