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639e8102 DG |
1 | /* |
2 | * QEMU sPAPR NVRAM emulation | |
3 | * | |
4 | * Copyright (C) 2012 David Gibson, IBM Corporation. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e2af7a4d | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
0b8fa32f | 26 | #include "qemu/module.h" |
ab3dd749 | 27 | #include "qemu/units.h" |
da34e65c | 28 | #include "qapi/error.h" |
639e8102 DG |
29 | #include <libfdt.h> |
30 | ||
4be74634 | 31 | #include "sysemu/block-backend.h" |
9c17d615 | 32 | #include "sysemu/device_tree.h" |
54d31236 MA |
33 | #include "sysemu/sysemu.h" |
34 | #include "sysemu/runstate.h" | |
d6454270 | 35 | #include "migration/vmstate.h" |
61f20b9d | 36 | #include "hw/nvram/chrp_nvram.h" |
0d09e41a PB |
37 | #include "hw/ppc/spapr.h" |
38 | #include "hw/ppc/spapr_vio.h" | |
a27bd6c7 | 39 | #include "hw/qdev-properties.h" |
ce35e229 | 40 | #include "hw/qdev-properties-system.h" |
db1015e9 | 41 | #include "qom/object.h" |
639e8102 | 42 | |
db1015e9 | 43 | struct SpaprNvram { |
ce2918cb | 44 | SpaprVioDevice sdev; |
639e8102 DG |
45 | uint32_t size; |
46 | uint8_t *buf; | |
4be74634 | 47 | BlockBackend *blk; |
cf472f48 | 48 | VMChangeStateEntry *vmstate; |
db1015e9 | 49 | }; |
639e8102 | 50 | |
fd506b4f | 51 | #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram" |
8063396b | 52 | OBJECT_DECLARE_SIMPLE_TYPE(SpaprNvram, VIO_SPAPR_NVRAM) |
fd506b4f | 53 | |
ab3dd749 PMD |
54 | #define MIN_NVRAM_SIZE (8 * KiB) |
55 | #define DEFAULT_NVRAM_SIZE (64 * KiB) | |
56 | #define MAX_NVRAM_SIZE (1 * MiB) | |
639e8102 | 57 | |
ce2918cb | 58 | static void rtas_nvram_fetch(PowerPCCPU *cpu, SpaprMachineState *spapr, |
639e8102 DG |
59 | uint32_t token, uint32_t nargs, |
60 | target_ulong args, | |
61 | uint32_t nret, target_ulong rets) | |
62 | { | |
ce2918cb | 63 | SpaprNvram *nvram = spapr->nvram; |
639e8102 | 64 | hwaddr offset, buffer, len; |
639e8102 DG |
65 | void *membuf; |
66 | ||
67 | if ((nargs != 3) || (nret != 2)) { | |
a64d325d | 68 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
69 | return; |
70 | } | |
71 | ||
72 | if (!nvram) { | |
a64d325d | 73 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
639e8102 DG |
74 | rtas_st(rets, 1, 0); |
75 | return; | |
76 | } | |
77 | ||
78 | offset = rtas_ld(args, 0); | |
79 | buffer = rtas_ld(args, 1); | |
80 | len = rtas_ld(args, 2); | |
81 | ||
82 | if (((offset + len) < offset) | |
83 | || ((offset + len) > nvram->size)) { | |
a64d325d | 84 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
85 | rtas_st(rets, 1, 0); |
86 | return; | |
87 | } | |
88 | ||
f58aa483 | 89 | assert(nvram->buf); |
639e8102 | 90 | |
85eb7c18 | 91 | membuf = cpu_physical_memory_map(buffer, &len, true); |
f58aa483 | 92 | memcpy(membuf, nvram->buf + offset, len); |
639e8102 DG |
93 | cpu_physical_memory_unmap(membuf, len, 1, len); |
94 | ||
f58aa483 AK |
95 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
96 | rtas_st(rets, 1, len); | |
639e8102 DG |
97 | } |
98 | ||
ce2918cb | 99 | static void rtas_nvram_store(PowerPCCPU *cpu, SpaprMachineState *spapr, |
639e8102 DG |
100 | uint32_t token, uint32_t nargs, |
101 | target_ulong args, | |
102 | uint32_t nret, target_ulong rets) | |
103 | { | |
ce2918cb | 104 | SpaprNvram *nvram = spapr->nvram; |
639e8102 | 105 | hwaddr offset, buffer, len; |
bf5b16fa | 106 | int ret; |
639e8102 DG |
107 | void *membuf; |
108 | ||
109 | if ((nargs != 3) || (nret != 2)) { | |
a64d325d | 110 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
111 | return; |
112 | } | |
113 | ||
114 | if (!nvram) { | |
a64d325d | 115 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
639e8102 DG |
116 | return; |
117 | } | |
118 | ||
119 | offset = rtas_ld(args, 0); | |
120 | buffer = rtas_ld(args, 1); | |
121 | len = rtas_ld(args, 2); | |
122 | ||
123 | if (((offset + len) < offset) | |
124 | || ((offset + len) > nvram->size)) { | |
a64d325d | 125 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
126 | return; |
127 | } | |
128 | ||
85eb7c18 | 129 | membuf = cpu_physical_memory_map(buffer, &len, false); |
f58aa483 | 130 | |
bf5b16fa | 131 | ret = 0; |
4be74634 | 132 | if (nvram->blk) { |
a9262f55 | 133 | ret = blk_pwrite(nvram->blk, offset, len, membuf, 0); |
639e8102 | 134 | } |
f58aa483 AK |
135 | |
136 | assert(nvram->buf); | |
137 | memcpy(nvram->buf + offset, membuf, len); | |
138 | ||
639e8102 DG |
139 | cpu_physical_memory_unmap(membuf, len, 0, len); |
140 | ||
bf5b16fa AF |
141 | rtas_st(rets, 0, (ret < 0) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS); |
142 | rtas_st(rets, 1, (ret < 0) ? 0 : len); | |
639e8102 DG |
143 | } |
144 | ||
ce2918cb | 145 | static void spapr_nvram_realize(SpaprVioDevice *dev, Error **errp) |
639e8102 | 146 | { |
ce2918cb | 147 | SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev); |
a17c17a2 | 148 | int ret; |
639e8102 | 149 | |
4be74634 | 150 | if (nvram->blk) { |
05249517 PM |
151 | int64_t len = blk_getlength(nvram->blk); |
152 | ||
153 | if (len < 0) { | |
154 | error_setg_errno(errp, -len, | |
155 | "could not get length of backing image"); | |
156 | return; | |
157 | } | |
158 | ||
159 | nvram->size = len; | |
a17c17a2 KW |
160 | |
161 | ret = blk_set_perm(nvram->blk, | |
162 | BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, | |
163 | BLK_PERM_ALL, errp); | |
164 | if (ret < 0) { | |
165 | return; | |
166 | } | |
639e8102 DG |
167 | } else { |
168 | nvram->size = DEFAULT_NVRAM_SIZE; | |
639e8102 DG |
169 | } |
170 | ||
f58aa483 AK |
171 | nvram->buf = g_malloc0(nvram->size); |
172 | ||
639e8102 | 173 | if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) { |
ab3dd749 PMD |
174 | error_setg(errp, |
175 | "spapr-nvram must be between %" PRId64 | |
176 | " and %" PRId64 " bytes in size", | |
28b07e73 MA |
177 | MIN_NVRAM_SIZE, MAX_NVRAM_SIZE); |
178 | return; | |
639e8102 DG |
179 | } |
180 | ||
f58aa483 | 181 | if (nvram->blk) { |
a9262f55 | 182 | ret = blk_pread(nvram->blk, 0, nvram->size, nvram->buf, 0); |
f58aa483 | 183 | |
bf5b16fa | 184 | if (ret < 0) { |
28b07e73 MA |
185 | error_setg(errp, "can't read spapr-nvram contents"); |
186 | return; | |
f58aa483 | 187 | } |
61f20b9d TH |
188 | } else if (nb_prom_envs > 0) { |
189 | /* Create a system partition to pass the -prom-env variables */ | |
37035df5 GK |
190 | chrp_nvram_create_system_partition(nvram->buf, MIN_NVRAM_SIZE / 4, |
191 | nvram->size); | |
61f20b9d TH |
192 | chrp_nvram_create_free_partition(&nvram->buf[MIN_NVRAM_SIZE / 4], |
193 | nvram->size - MIN_NVRAM_SIZE / 4); | |
f58aa483 AK |
194 | } |
195 | ||
3a3b8502 AK |
196 | spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch); |
197 | spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store); | |
639e8102 DG |
198 | } |
199 | ||
ce2918cb | 200 | static int spapr_nvram_devnode(SpaprVioDevice *dev, void *fdt, int node_off) |
639e8102 | 201 | { |
ce2918cb | 202 | SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev); |
639e8102 DG |
203 | |
204 | return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size); | |
205 | } | |
206 | ||
f58aa483 AK |
207 | static int spapr_nvram_pre_load(void *opaque) |
208 | { | |
ce2918cb | 209 | SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque); |
f58aa483 AK |
210 | |
211 | g_free(nvram->buf); | |
212 | nvram->buf = NULL; | |
213 | nvram->size = 0; | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
538f0497 | 218 | static void postload_update_cb(void *opaque, bool running, RunState state) |
cf472f48 | 219 | { |
ce2918cb | 220 | SpaprNvram *nvram = opaque; |
cf472f48 | 221 | |
3b717194 | 222 | /* This is called after bdrv_activate_all. */ |
cf472f48 | 223 | |
224 | qemu_del_vm_change_state_handler(nvram->vmstate); | |
225 | nvram->vmstate = NULL; | |
226 | ||
a9262f55 | 227 | blk_pwrite(nvram->blk, 0, nvram->size, nvram->buf, 0); |
cf472f48 | 228 | } |
229 | ||
f58aa483 AK |
230 | static int spapr_nvram_post_load(void *opaque, int version_id) |
231 | { | |
ce2918cb | 232 | SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque); |
f58aa483 AK |
233 | |
234 | if (nvram->blk) { | |
cf472f48 | 235 | nvram->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, |
236 | nvram); | |
f58aa483 AK |
237 | } |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | static const VMStateDescription vmstate_spapr_nvram = { | |
243 | .name = "spapr_nvram", | |
244 | .version_id = 1, | |
245 | .minimum_version_id = 1, | |
246 | .pre_load = spapr_nvram_pre_load, | |
247 | .post_load = spapr_nvram_post_load, | |
248 | .fields = (VMStateField[]) { | |
ce2918cb DG |
249 | VMSTATE_UINT32(size, SpaprNvram), |
250 | VMSTATE_VBUFFER_ALLOC_UINT32(buf, SpaprNvram, 1, NULL, size), | |
f58aa483 AK |
251 | VMSTATE_END_OF_LIST() |
252 | }, | |
253 | }; | |
254 | ||
639e8102 | 255 | static Property spapr_nvram_properties[] = { |
ce2918cb DG |
256 | DEFINE_SPAPR_PROPERTIES(SpaprNvram, sdev), |
257 | DEFINE_PROP_DRIVE("drive", SpaprNvram, blk), | |
639e8102 DG |
258 | DEFINE_PROP_END_OF_LIST(), |
259 | }; | |
260 | ||
261 | static void spapr_nvram_class_init(ObjectClass *klass, void *data) | |
262 | { | |
263 | DeviceClass *dc = DEVICE_CLASS(klass); | |
ce2918cb | 264 | SpaprVioDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass); |
639e8102 | 265 | |
28b07e73 | 266 | k->realize = spapr_nvram_realize; |
639e8102 DG |
267 | k->devnode = spapr_nvram_devnode; |
268 | k->dt_name = "nvram"; | |
269 | k->dt_type = "nvram"; | |
270 | k->dt_compatible = "qemu,spapr-nvram"; | |
29fdedfe | 271 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
4f67d30b | 272 | device_class_set_props(dc, spapr_nvram_properties); |
f58aa483 | 273 | dc->vmsd = &vmstate_spapr_nvram; |
280503ee TH |
274 | /* Reason: Internal device only, uses spapr_rtas_register() in realize() */ |
275 | dc->user_creatable = false; | |
639e8102 DG |
276 | } |
277 | ||
278 | static const TypeInfo spapr_nvram_type_info = { | |
fd506b4f | 279 | .name = TYPE_VIO_SPAPR_NVRAM, |
639e8102 | 280 | .parent = TYPE_VIO_SPAPR_DEVICE, |
ce2918cb | 281 | .instance_size = sizeof(SpaprNvram), |
639e8102 DG |
282 | .class_init = spapr_nvram_class_init, |
283 | }; | |
284 | ||
285 | static void spapr_nvram_register_types(void) | |
286 | { | |
287 | type_register_static(&spapr_nvram_type_info); | |
288 | } | |
289 | ||
290 | type_init(spapr_nvram_register_types) |