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639e8102 DG |
1 | /* |
2 | * QEMU sPAPR NVRAM emulation | |
3 | * | |
4 | * Copyright (C) 2012 David Gibson, IBM Corporation. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e2af7a4d | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
0b8fa32f | 26 | #include "qemu/module.h" |
ab3dd749 | 27 | #include "qemu/units.h" |
da34e65c | 28 | #include "qapi/error.h" |
4771d756 | 29 | #include "cpu.h" |
639e8102 DG |
30 | #include <libfdt.h> |
31 | ||
4be74634 | 32 | #include "sysemu/block-backend.h" |
9c17d615 | 33 | #include "sysemu/device_tree.h" |
54d31236 MA |
34 | #include "sysemu/sysemu.h" |
35 | #include "sysemu/runstate.h" | |
639e8102 | 36 | #include "hw/sysbus.h" |
d6454270 | 37 | #include "migration/vmstate.h" |
61f20b9d | 38 | #include "hw/nvram/chrp_nvram.h" |
0d09e41a PB |
39 | #include "hw/ppc/spapr.h" |
40 | #include "hw/ppc/spapr_vio.h" | |
a27bd6c7 | 41 | #include "hw/qdev-properties.h" |
db1015e9 | 42 | #include "qom/object.h" |
639e8102 | 43 | |
db1015e9 | 44 | struct SpaprNvram { |
ce2918cb | 45 | SpaprVioDevice sdev; |
639e8102 DG |
46 | uint32_t size; |
47 | uint8_t *buf; | |
4be74634 | 48 | BlockBackend *blk; |
cf472f48 | 49 | VMChangeStateEntry *vmstate; |
db1015e9 EH |
50 | }; |
51 | typedef struct SpaprNvram SpaprNvram; | |
639e8102 | 52 | |
fd506b4f | 53 | #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram" |
8110fa1d EH |
54 | DECLARE_INSTANCE_CHECKER(SpaprNvram, VIO_SPAPR_NVRAM, |
55 | TYPE_VIO_SPAPR_NVRAM) | |
fd506b4f | 56 | |
ab3dd749 PMD |
57 | #define MIN_NVRAM_SIZE (8 * KiB) |
58 | #define DEFAULT_NVRAM_SIZE (64 * KiB) | |
59 | #define MAX_NVRAM_SIZE (1 * MiB) | |
639e8102 | 60 | |
ce2918cb | 61 | static void rtas_nvram_fetch(PowerPCCPU *cpu, SpaprMachineState *spapr, |
639e8102 DG |
62 | uint32_t token, uint32_t nargs, |
63 | target_ulong args, | |
64 | uint32_t nret, target_ulong rets) | |
65 | { | |
ce2918cb | 66 | SpaprNvram *nvram = spapr->nvram; |
639e8102 | 67 | hwaddr offset, buffer, len; |
639e8102 DG |
68 | void *membuf; |
69 | ||
70 | if ((nargs != 3) || (nret != 2)) { | |
a64d325d | 71 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
72 | return; |
73 | } | |
74 | ||
75 | if (!nvram) { | |
a64d325d | 76 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
639e8102 DG |
77 | rtas_st(rets, 1, 0); |
78 | return; | |
79 | } | |
80 | ||
81 | offset = rtas_ld(args, 0); | |
82 | buffer = rtas_ld(args, 1); | |
83 | len = rtas_ld(args, 2); | |
84 | ||
85 | if (((offset + len) < offset) | |
86 | || ((offset + len) > nvram->size)) { | |
a64d325d | 87 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
88 | rtas_st(rets, 1, 0); |
89 | return; | |
90 | } | |
91 | ||
f58aa483 | 92 | assert(nvram->buf); |
639e8102 | 93 | |
85eb7c18 | 94 | membuf = cpu_physical_memory_map(buffer, &len, true); |
f58aa483 | 95 | memcpy(membuf, nvram->buf + offset, len); |
639e8102 DG |
96 | cpu_physical_memory_unmap(membuf, len, 1, len); |
97 | ||
f58aa483 AK |
98 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
99 | rtas_st(rets, 1, len); | |
639e8102 DG |
100 | } |
101 | ||
ce2918cb | 102 | static void rtas_nvram_store(PowerPCCPU *cpu, SpaprMachineState *spapr, |
639e8102 DG |
103 | uint32_t token, uint32_t nargs, |
104 | target_ulong args, | |
105 | uint32_t nret, target_ulong rets) | |
106 | { | |
ce2918cb | 107 | SpaprNvram *nvram = spapr->nvram; |
639e8102 DG |
108 | hwaddr offset, buffer, len; |
109 | int alen; | |
110 | void *membuf; | |
111 | ||
112 | if ((nargs != 3) || (nret != 2)) { | |
a64d325d | 113 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
114 | return; |
115 | } | |
116 | ||
117 | if (!nvram) { | |
a64d325d | 118 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
639e8102 DG |
119 | return; |
120 | } | |
121 | ||
122 | offset = rtas_ld(args, 0); | |
123 | buffer = rtas_ld(args, 1); | |
124 | len = rtas_ld(args, 2); | |
125 | ||
126 | if (((offset + len) < offset) | |
127 | || ((offset + len) > nvram->size)) { | |
a64d325d | 128 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
129 | return; |
130 | } | |
131 | ||
85eb7c18 | 132 | membuf = cpu_physical_memory_map(buffer, &len, false); |
f58aa483 AK |
133 | |
134 | alen = len; | |
4be74634 | 135 | if (nvram->blk) { |
8341f00d | 136 | alen = blk_pwrite(nvram->blk, offset, membuf, len, 0); |
639e8102 | 137 | } |
f58aa483 AK |
138 | |
139 | assert(nvram->buf); | |
140 | memcpy(nvram->buf + offset, membuf, len); | |
141 | ||
639e8102 DG |
142 | cpu_physical_memory_unmap(membuf, len, 0, len); |
143 | ||
a64d325d | 144 | rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS); |
639e8102 DG |
145 | rtas_st(rets, 1, (alen < 0) ? 0 : alen); |
146 | } | |
147 | ||
ce2918cb | 148 | static void spapr_nvram_realize(SpaprVioDevice *dev, Error **errp) |
639e8102 | 149 | { |
ce2918cb | 150 | SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev); |
a17c17a2 | 151 | int ret; |
639e8102 | 152 | |
4be74634 | 153 | if (nvram->blk) { |
05249517 PM |
154 | int64_t len = blk_getlength(nvram->blk); |
155 | ||
156 | if (len < 0) { | |
157 | error_setg_errno(errp, -len, | |
158 | "could not get length of backing image"); | |
159 | return; | |
160 | } | |
161 | ||
162 | nvram->size = len; | |
a17c17a2 KW |
163 | |
164 | ret = blk_set_perm(nvram->blk, | |
165 | BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, | |
166 | BLK_PERM_ALL, errp); | |
167 | if (ret < 0) { | |
168 | return; | |
169 | } | |
639e8102 DG |
170 | } else { |
171 | nvram->size = DEFAULT_NVRAM_SIZE; | |
639e8102 DG |
172 | } |
173 | ||
f58aa483 AK |
174 | nvram->buf = g_malloc0(nvram->size); |
175 | ||
639e8102 | 176 | if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) { |
ab3dd749 PMD |
177 | error_setg(errp, |
178 | "spapr-nvram must be between %" PRId64 | |
179 | " and %" PRId64 " bytes in size", | |
28b07e73 MA |
180 | MIN_NVRAM_SIZE, MAX_NVRAM_SIZE); |
181 | return; | |
639e8102 DG |
182 | } |
183 | ||
f58aa483 AK |
184 | if (nvram->blk) { |
185 | int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size); | |
186 | ||
187 | if (alen != nvram->size) { | |
28b07e73 MA |
188 | error_setg(errp, "can't read spapr-nvram contents"); |
189 | return; | |
f58aa483 | 190 | } |
61f20b9d TH |
191 | } else if (nb_prom_envs > 0) { |
192 | /* Create a system partition to pass the -prom-env variables */ | |
37035df5 GK |
193 | chrp_nvram_create_system_partition(nvram->buf, MIN_NVRAM_SIZE / 4, |
194 | nvram->size); | |
61f20b9d TH |
195 | chrp_nvram_create_free_partition(&nvram->buf[MIN_NVRAM_SIZE / 4], |
196 | nvram->size - MIN_NVRAM_SIZE / 4); | |
f58aa483 AK |
197 | } |
198 | ||
3a3b8502 AK |
199 | spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch); |
200 | spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store); | |
639e8102 DG |
201 | } |
202 | ||
ce2918cb | 203 | static int spapr_nvram_devnode(SpaprVioDevice *dev, void *fdt, int node_off) |
639e8102 | 204 | { |
ce2918cb | 205 | SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev); |
639e8102 DG |
206 | |
207 | return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size); | |
208 | } | |
209 | ||
f58aa483 AK |
210 | static int spapr_nvram_pre_load(void *opaque) |
211 | { | |
ce2918cb | 212 | SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque); |
f58aa483 AK |
213 | |
214 | g_free(nvram->buf); | |
215 | nvram->buf = NULL; | |
216 | nvram->size = 0; | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
cf472f48 | 221 | static void postload_update_cb(void *opaque, int running, RunState state) |
222 | { | |
ce2918cb | 223 | SpaprNvram *nvram = opaque; |
cf472f48 | 224 | |
225 | /* This is called after bdrv_invalidate_cache_all. */ | |
226 | ||
227 | qemu_del_vm_change_state_handler(nvram->vmstate); | |
228 | nvram->vmstate = NULL; | |
229 | ||
230 | blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size, 0); | |
231 | } | |
232 | ||
f58aa483 AK |
233 | static int spapr_nvram_post_load(void *opaque, int version_id) |
234 | { | |
ce2918cb | 235 | SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque); |
f58aa483 AK |
236 | |
237 | if (nvram->blk) { | |
cf472f48 | 238 | nvram->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, |
239 | nvram); | |
f58aa483 AK |
240 | } |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static const VMStateDescription vmstate_spapr_nvram = { | |
246 | .name = "spapr_nvram", | |
247 | .version_id = 1, | |
248 | .minimum_version_id = 1, | |
249 | .pre_load = spapr_nvram_pre_load, | |
250 | .post_load = spapr_nvram_post_load, | |
251 | .fields = (VMStateField[]) { | |
ce2918cb DG |
252 | VMSTATE_UINT32(size, SpaprNvram), |
253 | VMSTATE_VBUFFER_ALLOC_UINT32(buf, SpaprNvram, 1, NULL, size), | |
f58aa483 AK |
254 | VMSTATE_END_OF_LIST() |
255 | }, | |
256 | }; | |
257 | ||
639e8102 | 258 | static Property spapr_nvram_properties[] = { |
ce2918cb DG |
259 | DEFINE_SPAPR_PROPERTIES(SpaprNvram, sdev), |
260 | DEFINE_PROP_DRIVE("drive", SpaprNvram, blk), | |
639e8102 DG |
261 | DEFINE_PROP_END_OF_LIST(), |
262 | }; | |
263 | ||
264 | static void spapr_nvram_class_init(ObjectClass *klass, void *data) | |
265 | { | |
266 | DeviceClass *dc = DEVICE_CLASS(klass); | |
ce2918cb | 267 | SpaprVioDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass); |
639e8102 | 268 | |
28b07e73 | 269 | k->realize = spapr_nvram_realize; |
639e8102 DG |
270 | k->devnode = spapr_nvram_devnode; |
271 | k->dt_name = "nvram"; | |
272 | k->dt_type = "nvram"; | |
273 | k->dt_compatible = "qemu,spapr-nvram"; | |
29fdedfe | 274 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
4f67d30b | 275 | device_class_set_props(dc, spapr_nvram_properties); |
f58aa483 | 276 | dc->vmsd = &vmstate_spapr_nvram; |
280503ee TH |
277 | /* Reason: Internal device only, uses spapr_rtas_register() in realize() */ |
278 | dc->user_creatable = false; | |
639e8102 DG |
279 | } |
280 | ||
281 | static const TypeInfo spapr_nvram_type_info = { | |
fd506b4f | 282 | .name = TYPE_VIO_SPAPR_NVRAM, |
639e8102 | 283 | .parent = TYPE_VIO_SPAPR_DEVICE, |
ce2918cb | 284 | .instance_size = sizeof(SpaprNvram), |
639e8102 DG |
285 | .class_init = spapr_nvram_class_init, |
286 | }; | |
287 | ||
288 | static void spapr_nvram_register_types(void) | |
289 | { | |
290 | type_register_static(&spapr_nvram_type_info); | |
291 | } | |
292 | ||
293 | type_init(spapr_nvram_register_types) |