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639e8102 DG |
1 | /* |
2 | * QEMU sPAPR NVRAM emulation | |
3 | * | |
4 | * Copyright (C) 2012 David Gibson, IBM Corporation. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e2af7a4d | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
639e8102 DG |
27 | #include <libfdt.h> |
28 | ||
4be74634 | 29 | #include "sysemu/block-backend.h" |
9c17d615 | 30 | #include "sysemu/device_tree.h" |
639e8102 | 31 | #include "hw/sysbus.h" |
0d09e41a PB |
32 | #include "hw/ppc/spapr.h" |
33 | #include "hw/ppc/spapr_vio.h" | |
639e8102 DG |
34 | |
35 | typedef struct sPAPRNVRAM { | |
36 | VIOsPAPRDevice sdev; | |
37 | uint32_t size; | |
38 | uint8_t *buf; | |
4be74634 | 39 | BlockBackend *blk; |
639e8102 DG |
40 | } sPAPRNVRAM; |
41 | ||
fd506b4f DG |
42 | #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram" |
43 | #define VIO_SPAPR_NVRAM(obj) \ | |
44 | OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM) | |
45 | ||
639e8102 | 46 | #define MIN_NVRAM_SIZE 8192 |
a64ae610 | 47 | #define DEFAULT_NVRAM_SIZE 65536 |
4e2ca127 | 48 | #define MAX_NVRAM_SIZE 1048576 |
639e8102 | 49 | |
28e02042 | 50 | static void rtas_nvram_fetch(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
639e8102 DG |
51 | uint32_t token, uint32_t nargs, |
52 | target_ulong args, | |
53 | uint32_t nret, target_ulong rets) | |
54 | { | |
55 | sPAPRNVRAM *nvram = spapr->nvram; | |
56 | hwaddr offset, buffer, len; | |
639e8102 DG |
57 | void *membuf; |
58 | ||
59 | if ((nargs != 3) || (nret != 2)) { | |
a64d325d | 60 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
61 | return; |
62 | } | |
63 | ||
64 | if (!nvram) { | |
a64d325d | 65 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
639e8102 DG |
66 | rtas_st(rets, 1, 0); |
67 | return; | |
68 | } | |
69 | ||
70 | offset = rtas_ld(args, 0); | |
71 | buffer = rtas_ld(args, 1); | |
72 | len = rtas_ld(args, 2); | |
73 | ||
74 | if (((offset + len) < offset) | |
75 | || ((offset + len) > nvram->size)) { | |
a64d325d | 76 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
77 | rtas_st(rets, 1, 0); |
78 | return; | |
79 | } | |
80 | ||
f58aa483 | 81 | assert(nvram->buf); |
639e8102 | 82 | |
f58aa483 AK |
83 | membuf = cpu_physical_memory_map(buffer, &len, 1); |
84 | memcpy(membuf, nvram->buf + offset, len); | |
639e8102 DG |
85 | cpu_physical_memory_unmap(membuf, len, 1, len); |
86 | ||
f58aa483 AK |
87 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
88 | rtas_st(rets, 1, len); | |
639e8102 DG |
89 | } |
90 | ||
28e02042 | 91 | static void rtas_nvram_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
639e8102 DG |
92 | uint32_t token, uint32_t nargs, |
93 | target_ulong args, | |
94 | uint32_t nret, target_ulong rets) | |
95 | { | |
96 | sPAPRNVRAM *nvram = spapr->nvram; | |
97 | hwaddr offset, buffer, len; | |
98 | int alen; | |
99 | void *membuf; | |
100 | ||
101 | if ((nargs != 3) || (nret != 2)) { | |
a64d325d | 102 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
103 | return; |
104 | } | |
105 | ||
106 | if (!nvram) { | |
a64d325d | 107 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
639e8102 DG |
108 | return; |
109 | } | |
110 | ||
111 | offset = rtas_ld(args, 0); | |
112 | buffer = rtas_ld(args, 1); | |
113 | len = rtas_ld(args, 2); | |
114 | ||
115 | if (((offset + len) < offset) | |
116 | || ((offset + len) > nvram->size)) { | |
a64d325d | 117 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
118 | return; |
119 | } | |
120 | ||
121 | membuf = cpu_physical_memory_map(buffer, &len, 0); | |
f58aa483 AK |
122 | |
123 | alen = len; | |
4be74634 MA |
124 | if (nvram->blk) { |
125 | alen = blk_pwrite(nvram->blk, offset, membuf, len); | |
639e8102 | 126 | } |
f58aa483 AK |
127 | |
128 | assert(nvram->buf); | |
129 | memcpy(nvram->buf + offset, membuf, len); | |
130 | ||
639e8102 DG |
131 | cpu_physical_memory_unmap(membuf, len, 0, len); |
132 | ||
a64d325d | 133 | rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS); |
639e8102 DG |
134 | rtas_st(rets, 1, (alen < 0) ? 0 : alen); |
135 | } | |
136 | ||
28b07e73 | 137 | static void spapr_nvram_realize(VIOsPAPRDevice *dev, Error **errp) |
639e8102 | 138 | { |
fd506b4f | 139 | sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev); |
639e8102 | 140 | |
4be74634 MA |
141 | if (nvram->blk) { |
142 | nvram->size = blk_getlength(nvram->blk); | |
639e8102 DG |
143 | } else { |
144 | nvram->size = DEFAULT_NVRAM_SIZE; | |
639e8102 DG |
145 | } |
146 | ||
f58aa483 AK |
147 | nvram->buf = g_malloc0(nvram->size); |
148 | ||
639e8102 | 149 | if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) { |
28b07e73 MA |
150 | error_setg(errp, "spapr-nvram must be between %d and %d bytes in size", |
151 | MIN_NVRAM_SIZE, MAX_NVRAM_SIZE); | |
152 | return; | |
639e8102 DG |
153 | } |
154 | ||
f58aa483 AK |
155 | if (nvram->blk) { |
156 | int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size); | |
157 | ||
158 | if (alen != nvram->size) { | |
28b07e73 MA |
159 | error_setg(errp, "can't read spapr-nvram contents"); |
160 | return; | |
f58aa483 AK |
161 | } |
162 | } | |
163 | ||
3a3b8502 AK |
164 | spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch); |
165 | spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store); | |
639e8102 DG |
166 | } |
167 | ||
168 | static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off) | |
169 | { | |
fd506b4f | 170 | sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev); |
639e8102 DG |
171 | |
172 | return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size); | |
173 | } | |
174 | ||
f58aa483 AK |
175 | static int spapr_nvram_pre_load(void *opaque) |
176 | { | |
177 | sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque); | |
178 | ||
179 | g_free(nvram->buf); | |
180 | nvram->buf = NULL; | |
181 | nvram->size = 0; | |
182 | ||
183 | return 0; | |
184 | } | |
185 | ||
186 | static int spapr_nvram_post_load(void *opaque, int version_id) | |
187 | { | |
188 | sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque); | |
189 | ||
190 | if (nvram->blk) { | |
191 | int alen = blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size); | |
192 | ||
193 | if (alen < 0) { | |
194 | return alen; | |
195 | } | |
196 | if (alen != nvram->size) { | |
197 | return -1; | |
198 | } | |
199 | } | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | static const VMStateDescription vmstate_spapr_nvram = { | |
205 | .name = "spapr_nvram", | |
206 | .version_id = 1, | |
207 | .minimum_version_id = 1, | |
208 | .pre_load = spapr_nvram_pre_load, | |
209 | .post_load = spapr_nvram_post_load, | |
210 | .fields = (VMStateField[]) { | |
211 | VMSTATE_UINT32(size, sPAPRNVRAM), | |
212 | VMSTATE_VBUFFER_ALLOC_UINT32(buf, sPAPRNVRAM, 1, NULL, 0, size), | |
213 | VMSTATE_END_OF_LIST() | |
214 | }, | |
215 | }; | |
216 | ||
639e8102 DG |
217 | static Property spapr_nvram_properties[] = { |
218 | DEFINE_SPAPR_PROPERTIES(sPAPRNVRAM, sdev), | |
4be74634 | 219 | DEFINE_PROP_DRIVE("drive", sPAPRNVRAM, blk), |
639e8102 DG |
220 | DEFINE_PROP_END_OF_LIST(), |
221 | }; | |
222 | ||
223 | static void spapr_nvram_class_init(ObjectClass *klass, void *data) | |
224 | { | |
225 | DeviceClass *dc = DEVICE_CLASS(klass); | |
226 | VIOsPAPRDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass); | |
227 | ||
28b07e73 | 228 | k->realize = spapr_nvram_realize; |
639e8102 DG |
229 | k->devnode = spapr_nvram_devnode; |
230 | k->dt_name = "nvram"; | |
231 | k->dt_type = "nvram"; | |
232 | k->dt_compatible = "qemu,spapr-nvram"; | |
29fdedfe | 233 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
639e8102 | 234 | dc->props = spapr_nvram_properties; |
f58aa483 | 235 | dc->vmsd = &vmstate_spapr_nvram; |
639e8102 DG |
236 | } |
237 | ||
238 | static const TypeInfo spapr_nvram_type_info = { | |
fd506b4f | 239 | .name = TYPE_VIO_SPAPR_NVRAM, |
639e8102 DG |
240 | .parent = TYPE_VIO_SPAPR_DEVICE, |
241 | .instance_size = sizeof(sPAPRNVRAM), | |
242 | .class_init = spapr_nvram_class_init, | |
243 | }; | |
244 | ||
245 | static void spapr_nvram_register_types(void) | |
246 | { | |
247 | type_register_static(&spapr_nvram_type_info); | |
248 | } | |
249 | ||
250 | type_init(spapr_nvram_register_types) |