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[mirror_qemu.git] / hw / omap1.c
CommitLineData
c3d2689d
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
b4e3104b 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
c3d2689d
AZ		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
827df9f3
AZ		 8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
c3d2689d
AZ		 10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
fad6cb1a 16 * You should have received a copy of the GNU General Public License along
8167ee88 17 * with this program; if not, see <http://www.gnu.org/licenses/>.
c3d2689d 18 */
87ecb68b
PB		 19#include "hw.h"
20#include "arm-misc.h"
21#include "omap.h"
22#include "sysemu.h"
23#include "qemu-timer.h"
827df9f3 24#include "qemu-char.h"
afbb5194 25#include "soc_dma.h"
87ecb68b
PB		 26/* We use pc-style serial ports. */
27#include "pc.h"
c3d2689d 28
827df9f3 29/* Should signal the TCMI/GPMC */
c227f099 30uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
66450b15 31{
02645926
AZ		 32 uint8_t ret;
33
66450b15 34 OMAP_8B_REG(addr);
b854bc19 35 cpu_physical_memory_read(addr, (void *) &ret, 1);
02645926 36 return ret;
66450b15
AZ		 37}
38
c227f099 39void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
66450b15
AZ		 40 uint32_t value)
41{
b854bc19
AZ		 42 uint8_t val8 = value;
43
66450b15 44 OMAP_8B_REG(addr);
b854bc19 45 cpu_physical_memory_write(addr, (void *) &val8, 1);
66450b15
AZ		 46}
47
c227f099 48uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
c3d2689d 49{
b854bc19
AZ		 50 uint16_t ret;
51
c3d2689d 52 OMAP_16B_REG(addr);
b854bc19
AZ		 53 cpu_physical_memory_read(addr, (void *) &ret, 2);
54 return ret;
c3d2689d
AZ		 55}
56
c227f099 57void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 58 uint32_t value)
59{
b854bc19
AZ		 60 uint16_t val16 = value;
61
c3d2689d 62 OMAP_16B_REG(addr);
b854bc19 63 cpu_physical_memory_write(addr, (void *) &val16, 2);
c3d2689d
AZ		 64}
65
c227f099 66uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
c3d2689d 67{
b854bc19
AZ		 68 uint32_t ret;
69
c3d2689d 70 OMAP_32B_REG(addr);
b854bc19
AZ		 71 cpu_physical_memory_read(addr, (void *) &ret, 4);
72 return ret;
c3d2689d
AZ		 73}
74
c227f099 75void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 76 uint32_t value)
77{
78 OMAP_32B_REG(addr);
b854bc19 79 cpu_physical_memory_write(addr, (void *) &value, 4);
c3d2689d
AZ		 80}
81
c3d2689d 82/* Interrupt Handlers */
106627d0 83struct omap_intr_handler_bank_s {
c3d2689d 84 uint32_t irqs;
106627d0 85 uint32_t inputs;
c3d2689d 86 uint32_t mask;
c3d2689d 87 uint32_t fiq;
106627d0 88 uint32_t sens_edge;
827df9f3 89 uint32_t swi;
106627d0 90 unsigned char priority[32];
c3d2689d
AZ		 91};
92
106627d0
AZ		 93struct omap_intr_handler_s {
94 qemu_irq *pins;
95 qemu_irq parent_intr[2];
106627d0 96 unsigned char nbanks;
827df9f3 97 int level_only;
c3d2689d 98
106627d0
AZ		 99 /* state */
100 uint32_t new_agr[2];
101 int sir_intr[2];
827df9f3
AZ		 102 int autoidle;
103 uint32_t mask;
104 struct omap_intr_handler_bank_s bank[];
106627d0 105};
c3d2689d 106
106627d0
AZ		 107static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
108{
109 int i, j, sir_intr, p_intr, p, f;
110 uint32_t level;
111 sir_intr = 0;
112 p_intr = 255;
113
114 /* Find the interrupt line with the highest dynamic priority.
115 * Note: 0 denotes the hightest priority.
116 * If all interrupts have the same priority, the default order is IRQ_N,
117 * IRQ_N-1,...,IRQ_0. */
118 for (j = 0; j < s->nbanks; ++j) {
827df9f3
AZ		 119 level = s->bank[j].irqs & ~s->bank[j].mask &
120 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
106627d0
AZ		 121 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
122 level >>= f) {
827df9f3 123 p = s->bank[j].priority[i];
106627d0
AZ		 124 if (p <= p_intr) {
125 p_intr = p;
126 sir_intr = 32 * j + i;
127 }
128 f = ffs(level >> 1);
129 }
cfa0b71d 130 }
106627d0 131 s->sir_intr[is_fiq] = sir_intr;
c3d2689d
AZ		 132}
133
106627d0 134static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
c3d2689d 135{
106627d0
AZ		 136 int i;
137 uint32_t has_intr = 0;
c3d2689d 138
106627d0 139 for (i = 0; i < s->nbanks; ++i)
827df9f3
AZ		 140 has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
141 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
c3d2689d 142
827df9f3 143 if (s->new_agr[is_fiq] & has_intr & s->mask) {
106627d0
AZ		 144 s->new_agr[is_fiq] = 0;
145 omap_inth_sir_update(s, is_fiq);
146 qemu_set_irq(s->parent_intr[is_fiq], 1);
c3d2689d 147 }
c3d2689d
AZ		 148}
149
150#define INT_FALLING_EDGE 0
151#define INT_LOW_LEVEL 1
152
153static void omap_set_intr(void *opaque, int irq, int req)
154{
155 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
156 uint32_t rise;
157
827df9f3 158 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
106627d0
AZ		 159 int n = irq & 31;
160
c3d2689d 161 if (req) {
106627d0
AZ		 162 rise = ~bank->irqs & (1 << n);
163 if (~bank->sens_edge & (1 << n))
827df9f3 164 rise &= ~bank->inputs;
106627d0
AZ		 165
166 bank->inputs |= (1 << n);
167 if (rise) {
168 bank->irqs |= rise;
169 omap_inth_update(ih, 0);
170 omap_inth_update(ih, 1);
171 }
c3d2689d 172 } else {
106627d0
AZ		 173 rise = bank->sens_edge & bank->irqs & (1 << n);
174 bank->irqs &= ~rise;
175 bank->inputs &= ~(1 << n);
c3d2689d
AZ		 176 }
177}
178
827df9f3
AZ		 179/* Simplified version with no edge detection */
180static void omap_set_intr_noedge(void *opaque, int irq, int req)
181{
182 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
183 uint32_t rise;
184
185 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
186 int n = irq & 31;
187
188 if (req) {
189 rise = ~bank->inputs & (1 << n);
190 if (rise) {
191 bank->irqs |= bank->inputs |= rise;
192 omap_inth_update(ih, 0);
193 omap_inth_update(ih, 1);
194 }
195 } else
196 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
197}
198
c227f099 199static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 200{
201 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
8da3ff18 202 int i, offset = addr;
106627d0
AZ		 203 int bank_no = offset >> 8;
204 int line_no;
827df9f3 205 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
106627d0 206 offset &= 0xff;
c3d2689d
AZ		 207
208 switch (offset) {
209 case 0x00: /* ITR */
106627d0 210 return bank->irqs;
c3d2689d
AZ		 211
212 case 0x04: /* MIR */
106627d0 213 return bank->mask;
c3d2689d
AZ		 214
215 case 0x10: /* SIR_IRQ_CODE */
106627d0
AZ		 216 case 0x14: /* SIR_FIQ_CODE */
217 if (bank_no != 0)
218 break;
219 line_no = s->sir_intr[(offset - 0x10) >> 2];
827df9f3 220 bank = &s->bank[line_no >> 5];
106627d0
AZ		 221 i = line_no & 31;
222 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
223 bank->irqs &= ~(1 << i);
f2df5260 224 return line_no;
c3d2689d
AZ		 225
226 case 0x18: /* CONTROL_REG */
106627d0
AZ		 227 if (bank_no != 0)
228 break;
c3d2689d
AZ		 229 return 0;
230
231 case 0x1c: /* ILR0 */
232 case 0x20: /* ILR1 */
233 case 0x24: /* ILR2 */
234 case 0x28: /* ILR3 */
235 case 0x2c: /* ILR4 */
236 case 0x30: /* ILR5 */
237 case 0x34: /* ILR6 */
238 case 0x38: /* ILR7 */
239 case 0x3c: /* ILR8 */
240 case 0x40: /* ILR9 */
241 case 0x44: /* ILR10 */
242 case 0x48: /* ILR11 */
243 case 0x4c: /* ILR12 */
244 case 0x50: /* ILR13 */
245 case 0x54: /* ILR14 */
246 case 0x58: /* ILR15 */
247 case 0x5c: /* ILR16 */
248 case 0x60: /* ILR17 */
249 case 0x64: /* ILR18 */
250 case 0x68: /* ILR19 */
251 case 0x6c: /* ILR20 */
252 case 0x70: /* ILR21 */
253 case 0x74: /* ILR22 */
254 case 0x78: /* ILR23 */
255 case 0x7c: /* ILR24 */
256 case 0x80: /* ILR25 */
257 case 0x84: /* ILR26 */
258 case 0x88: /* ILR27 */
259 case 0x8c: /* ILR28 */
260 case 0x90: /* ILR29 */
261 case 0x94: /* ILR30 */
262 case 0x98: /* ILR31 */
263 i = (offset - 0x1c) >> 2;
106627d0
AZ		 264 return (bank->priority[i] << 2) |
265 (((bank->sens_edge >> i) & 1) << 1) |
266 ((bank->fiq >> i) & 1);
c3d2689d
AZ		 267
268 case 0x9c: /* ISR */
269 return 0x00000000;
270
c3d2689d 271 }
106627d0 272 OMAP_BAD_REG(addr);
c3d2689d
AZ		 273 return 0;
274}
275
c227f099 276static void omap_inth_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 277 uint32_t value)
278{
279 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
8da3ff18 280 int i, offset = addr;
106627d0 281 int bank_no = offset >> 8;
827df9f3 282 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
106627d0 283 offset &= 0xff;
c3d2689d
AZ		 284
285 switch (offset) {
286 case 0x00: /* ITR */
106627d0
AZ		 287 /* Important: ignore the clearing if the IRQ is level-triggered and
288 the input bit is 1 */
289 bank->irqs &= value | (bank->inputs & bank->sens_edge);
c3d2689d
AZ		 290 return;
291
292 case 0x04: /* MIR */
106627d0
AZ		 293 bank->mask = value;
294 omap_inth_update(s, 0);
295 omap_inth_update(s, 1);
c3d2689d
AZ		 296 return;
297
298 case 0x10: /* SIR_IRQ_CODE */
299 case 0x14: /* SIR_FIQ_CODE */
300 OMAP_RO_REG(addr);
301 break;
302
303 case 0x18: /* CONTROL_REG */
106627d0
AZ		 304 if (bank_no != 0)
305 break;
306 if (value & 2) {
307 qemu_set_irq(s->parent_intr[1], 0);
308 s->new_agr[1] = ~0;
309 omap_inth_update(s, 1);
310 }
311 if (value & 1) {
312 qemu_set_irq(s->parent_intr[0], 0);
313 s->new_agr[0] = ~0;
314 omap_inth_update(s, 0);
315 }
c3d2689d
AZ		 316 return;
317
318 case 0x1c: /* ILR0 */
319 case 0x20: /* ILR1 */
320 case 0x24: /* ILR2 */
321 case 0x28: /* ILR3 */
322 case 0x2c: /* ILR4 */
323 case 0x30: /* ILR5 */
324 case 0x34: /* ILR6 */
325 case 0x38: /* ILR7 */
326 case 0x3c: /* ILR8 */
327 case 0x40: /* ILR9 */
328 case 0x44: /* ILR10 */
329 case 0x48: /* ILR11 */
330 case 0x4c: /* ILR12 */
331 case 0x50: /* ILR13 */
332 case 0x54: /* ILR14 */
333 case 0x58: /* ILR15 */
334 case 0x5c: /* ILR16 */
335 case 0x60: /* ILR17 */
336 case 0x64: /* ILR18 */
337 case 0x68: /* ILR19 */
338 case 0x6c: /* ILR20 */
339 case 0x70: /* ILR21 */
340 case 0x74: /* ILR22 */
341 case 0x78: /* ILR23 */
342 case 0x7c: /* ILR24 */
343 case 0x80: /* ILR25 */
344 case 0x84: /* ILR26 */
345 case 0x88: /* ILR27 */
346 case 0x8c: /* ILR28 */
347 case 0x90: /* ILR29 */
348 case 0x94: /* ILR30 */
349 case 0x98: /* ILR31 */
350 i = (offset - 0x1c) >> 2;
106627d0
AZ		 351 bank->priority[i] = (value >> 2) & 0x1f;
352 bank->sens_edge &= ~(1 << i);
353 bank->sens_edge |= ((value >> 1) & 1) << i;
354 bank->fiq &= ~(1 << i);
355 bank->fiq |= (value & 1) << i;
c3d2689d
AZ		 356 return;
357
358 case 0x9c: /* ISR */
359 for (i = 0; i < 32; i ++)
360 if (value & (1 << i)) {
106627d0 361 omap_set_intr(s, 32 * bank_no + i, 1);
c3d2689d
AZ		 362 return;
363 }
364 return;
c3d2689d 365 }
106627d0 366 OMAP_BAD_REG(addr);
c3d2689d
AZ		 367}
368
d60efc6b 369static CPUReadMemoryFunc * const omap_inth_readfn[] = {
c3d2689d
AZ		 370 omap_badwidth_read32,
371 omap_badwidth_read32,
372 omap_inth_read,
373};
374
d60efc6b 375static CPUWriteMemoryFunc * const omap_inth_writefn[] = {
c3d2689d
AZ		 376 omap_inth_write,
377 omap_inth_write,
378 omap_inth_write,
379};
380
106627d0 381void omap_inth_reset(struct omap_intr_handler_s *s)
c3d2689d 382{
106627d0
AZ		 383 int i;
384
385 for (i = 0; i < s->nbanks; ++i){
827df9f3
AZ		 386 s->bank[i].irqs = 0x00000000;
387 s->bank[i].mask = 0xffffffff;
388 s->bank[i].sens_edge = 0x00000000;
389 s->bank[i].fiq = 0x00000000;
390 s->bank[i].inputs = 0x00000000;
391 s->bank[i].swi = 0x00000000;
392 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
393
394 if (s->level_only)
395 s->bank[i].sens_edge = 0xffffffff;
106627d0 396 }
c3d2689d 397
106627d0
AZ		 398 s->new_agr[0] = ~0;
399 s->new_agr[1] = ~0;
400 s->sir_intr[0] = 0;
401 s->sir_intr[1] = 0;
827df9f3
AZ		 402 s->autoidle = 0;
403 s->mask = ~0;
106627d0
AZ		 404
405 qemu_set_irq(s->parent_intr[0], 0);
406 qemu_set_irq(s->parent_intr[1], 0);
c3d2689d
AZ		 407}
408
c227f099 409struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
827df9f3 410 unsigned long size, unsigned char nbanks, qemu_irq **pins,
106627d0 411 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
c3d2689d
AZ		 412{
413 int iomemtype;
414 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
106627d0
AZ		 415 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
416 sizeof(struct omap_intr_handler_bank_s) * nbanks);
c3d2689d 417
106627d0
AZ		 418 s->parent_intr[0] = parent_irq;
419 s->parent_intr[1] = parent_fiq;
106627d0
AZ		 420 s->nbanks = nbanks;
421 s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
827df9f3
AZ		 422 if (pins)
423 *pins = s->pins;
106627d0 424
c3d2689d
AZ		 425 omap_inth_reset(s);
426
1eed09cb 427 iomemtype = cpu_register_io_memory(omap_inth_readfn,
c3d2689d 428 omap_inth_writefn, s);
8da3ff18 429 cpu_register_physical_memory(base, size, iomemtype);
c3d2689d
AZ		 430
431 return s;
432}
433
c227f099 434static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
827df9f3
AZ		 435{
436 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
8da3ff18 437 int offset = addr;
827df9f3 438 int bank_no, line_no;
b9d38e95 439 struct omap_intr_handler_bank_s *bank = NULL;
827df9f3
AZ		 440
441 if ((offset & 0xf80) == 0x80) {
442 bank_no = (offset & 0x60) >> 5;
443 if (bank_no < s->nbanks) {
444 offset &= ~0x60;
445 bank = &s->bank[bank_no];
446 }
447 }
448
449 switch (offset) {
450 case 0x00: /* INTC_REVISION */
451 return 0x21;
452
453 case 0x10: /* INTC_SYSCONFIG */
454 return (s->autoidle >> 2) & 1;
455
456 case 0x14: /* INTC_SYSSTATUS */
457 return 1; /* RESETDONE */
458
459 case 0x40: /* INTC_SIR_IRQ */
460 return s->sir_intr[0];
461
462 case 0x44: /* INTC_SIR_FIQ */
463 return s->sir_intr[1];
464
465 case 0x48: /* INTC_CONTROL */
466 return (!s->mask) << 2; /* GLOBALMASK */
467
468 case 0x4c: /* INTC_PROTECTION */
469 return 0;
470
471 case 0x50: /* INTC_IDLE */
472 return s->autoidle & 3;
473
474 /* Per-bank registers */
475 case 0x80: /* INTC_ITR */
476 return bank->inputs;
477
478 case 0x84: /* INTC_MIR */
479 return bank->mask;
480
481 case 0x88: /* INTC_MIR_CLEAR */
482 case 0x8c: /* INTC_MIR_SET */
483 return 0;
484
485 case 0x90: /* INTC_ISR_SET */
486 return bank->swi;
487
488 case 0x94: /* INTC_ISR_CLEAR */
489 return 0;
490
491 case 0x98: /* INTC_PENDING_IRQ */
492 return bank->irqs & ~bank->mask & ~bank->fiq;
493
494 case 0x9c: /* INTC_PENDING_FIQ */
495 return bank->irqs & ~bank->mask & bank->fiq;
496
497 /* Per-line registers */
498 case 0x100 ... 0x300: /* INTC_ILR */
499 bank_no = (offset - 0x100) >> 7;
500 if (bank_no > s->nbanks)
501 break;
502 bank = &s->bank[bank_no];
503 line_no = (offset & 0x7f) >> 2;
504 return (bank->priority[line_no] << 2) |
505 ((bank->fiq >> line_no) & 1);
506 }
507 OMAP_BAD_REG(addr);
508 return 0;
509}
510
c227f099 511static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
827df9f3
AZ		 512 uint32_t value)
513{
514 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
8da3ff18 515 int offset = addr;
827df9f3 516 int bank_no, line_no;
b9d38e95 517 struct omap_intr_handler_bank_s *bank = NULL;
827df9f3
AZ		 518
519 if ((offset & 0xf80) == 0x80) {
520 bank_no = (offset & 0x60) >> 5;
521 if (bank_no < s->nbanks) {
522 offset &= ~0x60;
523 bank = &s->bank[bank_no];
524 }
525 }
526
527 switch (offset) {
528 case 0x10: /* INTC_SYSCONFIG */
529 s->autoidle &= 4;
530 s->autoidle |= (value & 1) << 2;
531 if (value & 2) /* SOFTRESET */
532 omap_inth_reset(s);
533 return;
534
535 case 0x48: /* INTC_CONTROL */
536 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
537 if (value & 2) { /* NEWFIQAGR */
538 qemu_set_irq(s->parent_intr[1], 0);
539 s->new_agr[1] = ~0;
540 omap_inth_update(s, 1);
541 }
542 if (value & 1) { /* NEWIRQAGR */
543 qemu_set_irq(s->parent_intr[0], 0);
544 s->new_agr[0] = ~0;
545 omap_inth_update(s, 0);
546 }
547 return;
548
549 case 0x4c: /* INTC_PROTECTION */
550 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
551 * for every register, see Chapter 3 and 4 for privileged mode. */
552 if (value & 1)
553 fprintf(stderr, "%s: protection mode enable attempt\n",
554 __FUNCTION__);
555 return;
556
557 case 0x50: /* INTC_IDLE */
558 s->autoidle &= ~3;
559 s->autoidle |= value & 3;
560 return;
561
562 /* Per-bank registers */
563 case 0x84: /* INTC_MIR */
564 bank->mask = value;
565 omap_inth_update(s, 0);
566 omap_inth_update(s, 1);
567 return;
568
569 case 0x88: /* INTC_MIR_CLEAR */
570 bank->mask &= ~value;
571 omap_inth_update(s, 0);
572 omap_inth_update(s, 1);
573 return;
574
575 case 0x8c: /* INTC_MIR_SET */
576 bank->mask |= value;
577 return;
578
579 case 0x90: /* INTC_ISR_SET */
580 bank->irqs |= bank->swi |= value;
581 omap_inth_update(s, 0);
582 omap_inth_update(s, 1);
583 return;
584
585 case 0x94: /* INTC_ISR_CLEAR */
586 bank->swi &= ~value;
587 bank->irqs = bank->swi & bank->inputs;
588 return;
589
590 /* Per-line registers */
591 case 0x100 ... 0x300: /* INTC_ILR */
592 bank_no = (offset - 0x100) >> 7;
593 if (bank_no > s->nbanks)
594 break;
595 bank = &s->bank[bank_no];
596 line_no = (offset & 0x7f) >> 2;
597 bank->priority[line_no] = (value >> 2) & 0x3f;
598 bank->fiq &= ~(1 << line_no);
599 bank->fiq |= (value & 1) << line_no;
600 return;
601
602 case 0x00: /* INTC_REVISION */
603 case 0x14: /* INTC_SYSSTATUS */
604 case 0x40: /* INTC_SIR_IRQ */
605 case 0x44: /* INTC_SIR_FIQ */
606 case 0x80: /* INTC_ITR */
607 case 0x98: /* INTC_PENDING_IRQ */
608 case 0x9c: /* INTC_PENDING_FIQ */
609 OMAP_RO_REG(addr);
610 return;
611 }
612 OMAP_BAD_REG(addr);
613}
614
d60efc6b 615static CPUReadMemoryFunc * const omap2_inth_readfn[] = {
827df9f3
AZ		 616 omap_badwidth_read32,
617 omap_badwidth_read32,
618 omap2_inth_read,
619};
620
d60efc6b 621static CPUWriteMemoryFunc * const omap2_inth_writefn[] = {
827df9f3
AZ		 622 omap2_inth_write,
623 omap2_inth_write,
624 omap2_inth_write,
625};
626
c227f099 627struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
827df9f3
AZ		 628 int size, int nbanks, qemu_irq **pins,
629 qemu_irq parent_irq, qemu_irq parent_fiq,
630 omap_clk fclk, omap_clk iclk)
631{
632 int iomemtype;
633 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
634 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
635 sizeof(struct omap_intr_handler_bank_s) * nbanks);
636
637 s->parent_intr[0] = parent_irq;
638 s->parent_intr[1] = parent_fiq;
827df9f3
AZ		 639 s->nbanks = nbanks;
640 s->level_only = 1;
641 s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
642 if (pins)
643 *pins = s->pins;
644
645 omap_inth_reset(s);
646
1eed09cb 647 iomemtype = cpu_register_io_memory(omap2_inth_readfn,
827df9f3 648 omap2_inth_writefn, s);
8da3ff18 649 cpu_register_physical_memory(base, size, iomemtype);
827df9f3
AZ		 650
651 return s;
652}
653
c3d2689d
AZ		 654/* MPU OS timers */
655struct omap_mpu_timer_s {
656 qemu_irq irq;
657 omap_clk clk;
c3d2689d
AZ		 658 uint32_t val;
659 int64_t time;
660 QEMUTimer *timer;
e856f2ad 661 QEMUBH *tick;
c3d2689d
AZ		 662 int64_t rate;
663 int it_ena;
664
665 int enable;
666 int ptv;
667 int ar;
668 int st;
669 uint32_t reset_val;
670};
671
672static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
673{
674 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
675
676 if (timer->st && timer->enable && timer->rate)
677 return timer->val - muldiv64(distance >> (timer->ptv + 1),
6ee093c9 678 timer->rate, get_ticks_per_sec());
c3d2689d
AZ		 679 else
680 return timer->val;
681}
682
683static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
684{
685 timer->val = omap_timer_read(timer);
686 timer->time = qemu_get_clock(vm_clock);
687}
688
689static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
690{
691 int64_t expires;
692
693 if (timer->enable && timer->st && timer->rate) {
694 timer->val = timer->reset_val; /* Should skip this on clk enable */
b8b137d6 695 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
6ee093c9 696 get_ticks_per_sec(), timer->rate);
b854bc19
AZ		 697
698 /* If timer expiry would be sooner than in about 1 ms and
699 * auto-reload isn't set, then fire immediately. This is a hack
700 * to make systems like PalmOS run in acceptable time. PalmOS
701 * sets the interval to a very low value and polls the status bit
702 * in a busy loop when it wants to sleep just a couple of CPU
703 * ticks. */
6ee093c9 704 if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
b854bc19 705 qemu_mod_timer(timer->timer, timer->time + expires);
e856f2ad
AZ		 706 else
707 qemu_bh_schedule(timer->tick);
c3d2689d
AZ		 708 } else
709 qemu_del_timer(timer->timer);
710}
711
e856f2ad 712static void omap_timer_fire(void *opaque)
c3d2689d 713{
e856f2ad 714 struct omap_mpu_timer_s *timer = opaque;
c3d2689d
AZ		 715
716 if (!timer->ar) {
717 timer->val = 0;
718 timer->st = 0;
719 }
720
721 if (timer->it_ena)
106627d0
AZ		 722 /* Edge-triggered irq */
723 qemu_irq_pulse(timer->irq);
e856f2ad
AZ		 724}
725
726static void omap_timer_tick(void *opaque)
727{
728 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
729
730 omap_timer_sync(timer);
731 omap_timer_fire(timer);
c3d2689d
AZ		 732 omap_timer_update(timer);
733}
734
735static void omap_timer_clk_update(void *opaque, int line, int on)
736{
737 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
738
739 omap_timer_sync(timer);
740 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
741 omap_timer_update(timer);
742}
743
744static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
745{
746 omap_clk_adduser(timer->clk,
747 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
748 timer->rate = omap_clk_getrate(timer->clk);
749}
750
c227f099 751static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 752{
753 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 754
8da3ff18 755 switch (addr) {
c3d2689d
AZ		 756 case 0x00: /* CNTL_TIMER */
757 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
758
759 case 0x04: /* LOAD_TIM */
760 break;
761
762 case 0x08: /* READ_TIM */
763 return omap_timer_read(s);
764 }
765
766 OMAP_BAD_REG(addr);
767 return 0;
768}
769
c227f099 770static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 771 uint32_t value)
772{
773 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 774
8da3ff18 775 switch (addr) {
c3d2689d
AZ		 776 case 0x00: /* CNTL_TIMER */
777 omap_timer_sync(s);
778 s->enable = (value >> 5) & 1;
779 s->ptv = (value >> 2) & 7;
780 s->ar = (value >> 1) & 1;
781 s->st = value & 1;
782 omap_timer_update(s);
783 return;
784
785 case 0x04: /* LOAD_TIM */
786 s->reset_val = value;
787 return;
788
789 case 0x08: /* READ_TIM */
790 OMAP_RO_REG(addr);
791 break;
792
793 default:
794 OMAP_BAD_REG(addr);
795 }
796}
797
d60efc6b 798static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = {
c3d2689d
AZ		 799 omap_badwidth_read32,
800 omap_badwidth_read32,
801 omap_mpu_timer_read,
802};
803
d60efc6b 804static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = {
c3d2689d
AZ		 805 omap_badwidth_write32,
806 omap_badwidth_write32,
807 omap_mpu_timer_write,
808};
809
810static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
811{
812 qemu_del_timer(s->timer);
813 s->enable = 0;
814 s->reset_val = 31337;
815 s->val = 0;
816 s->ptv = 0;
817 s->ar = 0;
818 s->st = 0;
819 s->it_ena = 1;
820}
821
c227f099 822struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
c3d2689d
AZ		 823 qemu_irq irq, omap_clk clk)
824{
825 int iomemtype;
826 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
827 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
828
829 s->irq = irq;
830 s->clk = clk;
c3d2689d 831 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
e856f2ad 832 s->tick = qemu_bh_new(omap_timer_fire, s);
c3d2689d
AZ		 833 omap_mpu_timer_reset(s);
834 omap_timer_clk_setup(s);
835
1eed09cb 836 iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,
c3d2689d 837 omap_mpu_timer_writefn, s);
8da3ff18 838 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 839
840 return s;
841}
842
843/* Watchdog timer */
844struct omap_watchdog_timer_s {
845 struct omap_mpu_timer_s timer;
846 uint8_t last_wr;
847 int mode;
848 int free;
849 int reset;
850};
851
c227f099 852static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 853{
854 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 855
8da3ff18 856 switch (addr) {
c3d2689d
AZ		 857 case 0x00: /* CNTL_TIMER */
858 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
859 (s->timer.st << 7) | (s->free << 1);
860
861 case 0x04: /* READ_TIMER */
862 return omap_timer_read(&s->timer);
863
864 case 0x08: /* TIMER_MODE */
865 return s->mode << 15;
866 }
867
868 OMAP_BAD_REG(addr);
869 return 0;
870}
871
c227f099 872static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 873 uint32_t value)
874{
875 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 876
8da3ff18 877 switch (addr) {
c3d2689d
AZ		 878 case 0x00: /* CNTL_TIMER */
879 omap_timer_sync(&s->timer);
880 s->timer.ptv = (value >> 9) & 7;
881 s->timer.ar = (value >> 8) & 1;
882 s->timer.st = (value >> 7) & 1;
883 s->free = (value >> 1) & 1;
884 omap_timer_update(&s->timer);
885 break;
886
887 case 0x04: /* LOAD_TIMER */
888 s->timer.reset_val = value & 0xffff;
889 break;
890
891 case 0x08: /* TIMER_MODE */
892 if (!s->mode && ((value >> 15) & 1))
893 omap_clk_get(s->timer.clk);
894 s->mode |= (value >> 15) & 1;
895 if (s->last_wr == 0xf5) {
896 if ((value & 0xff) == 0xa0) {
d8f699cb
AZ		 897 if (s->mode) {
898 s->mode = 0;
899 omap_clk_put(s->timer.clk);
900 }
c3d2689d
AZ		 901 } else {
902 /* XXX: on T|E hardware somehow this has no effect,
903 * on Zire 71 it works as specified. */
904 s->reset = 1;
905 qemu_system_reset_request();
906 }
907 }
908 s->last_wr = value & 0xff;
909 break;
910
911 default:
912 OMAP_BAD_REG(addr);
913 }
914}
915
d60efc6b 916static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = {
c3d2689d
AZ		 917 omap_badwidth_read16,
918 omap_wd_timer_read,
919 omap_badwidth_read16,
920};
921
d60efc6b 922static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = {
c3d2689d
AZ		 923 omap_badwidth_write16,
924 omap_wd_timer_write,
925 omap_badwidth_write16,
926};
927
928static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
929{
930 qemu_del_timer(s->timer.timer);
931 if (!s->mode)
932 omap_clk_get(s->timer.clk);
933 s->mode = 1;
934 s->free = 1;
935 s->reset = 0;
936 s->timer.enable = 1;
937 s->timer.it_ena = 1;
938 s->timer.reset_val = 0xffff;
939 s->timer.val = 0;
940 s->timer.st = 0;
941 s->timer.ptv = 0;
942 s->timer.ar = 0;
943 omap_timer_update(&s->timer);
944}
945
c227f099 946struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
c3d2689d
AZ		 947 qemu_irq irq, omap_clk clk)
948{
949 int iomemtype;
950 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
951 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
952
953 s->timer.irq = irq;
954 s->timer.clk = clk;
c3d2689d
AZ		 955 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
956 omap_wd_timer_reset(s);
957 omap_timer_clk_setup(&s->timer);
958
1eed09cb 959 iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,
c3d2689d 960 omap_wd_timer_writefn, s);
8da3ff18 961 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 962
963 return s;
964}
965
966/* 32-kHz timer */
967struct omap_32khz_timer_s {
968 struct omap_mpu_timer_s timer;
969};
970
c227f099 971static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 972{
973 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 974 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d
AZ		 975
976 switch (offset) {
977 case 0x00: /* TVR */
978 return s->timer.reset_val;
979
980 case 0x04: /* TCR */
981 return omap_timer_read(&s->timer);
982
983 case 0x08: /* CR */
984 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
985
986 default:
987 break;
988 }
989 OMAP_BAD_REG(addr);
990 return 0;
991}
992
c227f099 993static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 994 uint32_t value)
995{
996 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 997 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d
AZ		 998
999 switch (offset) {
1000 case 0x00: /* TVR */
1001 s->timer.reset_val = value & 0x00ffffff;
1002 break;
1003
1004 case 0x04: /* TCR */
1005 OMAP_RO_REG(addr);
1006 break;
1007
1008 case 0x08: /* CR */
1009 s->timer.ar = (value >> 3) & 1;
1010 s->timer.it_ena = (value >> 2) & 1;
1011 if (s->timer.st != (value & 1) || (value & 2)) {
1012 omap_timer_sync(&s->timer);
1013 s->timer.enable = value & 1;
1014 s->timer.st = value & 1;
1015 omap_timer_update(&s->timer);
1016 }
1017 break;
1018
1019 default:
1020 OMAP_BAD_REG(addr);
1021 }
1022}
1023
d60efc6b 1024static CPUReadMemoryFunc * const omap_os_timer_readfn[] = {
c3d2689d
AZ		 1025 omap_badwidth_read32,
1026 omap_badwidth_read32,
1027 omap_os_timer_read,
1028};
1029
d60efc6b 1030static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = {
c3d2689d
AZ		 1031 omap_badwidth_write32,
1032 omap_badwidth_write32,
1033 omap_os_timer_write,
1034};
1035
1036static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
1037{
1038 qemu_del_timer(s->timer.timer);
1039 s->timer.enable = 0;
1040 s->timer.it_ena = 0;
1041 s->timer.reset_val = 0x00ffffff;
1042 s->timer.val = 0;
1043 s->timer.st = 0;
1044 s->timer.ptv = 0;
1045 s->timer.ar = 1;
1046}
1047
c227f099 1048struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
c3d2689d
AZ		 1049 qemu_irq irq, omap_clk clk)
1050{
1051 int iomemtype;
1052 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
1053 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
1054
1055 s->timer.irq = irq;
1056 s->timer.clk = clk;
c3d2689d
AZ		 1057 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1058 omap_os_timer_reset(s);
1059 omap_timer_clk_setup(&s->timer);
1060
1eed09cb 1061 iomemtype = cpu_register_io_memory(omap_os_timer_readfn,
c3d2689d 1062 omap_os_timer_writefn, s);
8da3ff18 1063 cpu_register_physical_memory(base, 0x800, iomemtype);
c3d2689d
AZ		 1064
1065 return s;
1066}
1067
1068/* Ultra Low-Power Device Module */
c227f099 1069static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1070{
1071 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1072 uint16_t ret;
1073
8da3ff18 1074 switch (addr) {
c3d2689d 1075 case 0x14: /* IT_STATUS */
8da3ff18
PB		 1076 ret = s->ulpd_pm_regs[addr >> 2];
1077 s->ulpd_pm_regs[addr >> 2] = 0;
c3d2689d
AZ		 1078 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
1079 return ret;
1080
1081 case 0x18: /* Reserved */
1082 case 0x1c: /* Reserved */
1083 case 0x20: /* Reserved */
1084 case 0x28: /* Reserved */
1085 case 0x2c: /* Reserved */
1086 OMAP_BAD_REG(addr);
1087 case 0x00: /* COUNTER_32_LSB */
1088 case 0x04: /* COUNTER_32_MSB */
1089 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1090 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1091 case 0x10: /* GAUGING_CTRL */
1092 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1093 case 0x30: /* CLOCK_CTRL */
1094 case 0x34: /* SOFT_REQ */
1095 case 0x38: /* COUNTER_32_FIQ */
1096 case 0x3c: /* DPLL_CTRL */
1097 case 0x40: /* STATUS_REQ */
1098 /* XXX: check clk::usecount state for every clock */
1099 case 0x48: /* LOCL_TIME */
1100 case 0x4c: /* APLL_CTRL */
1101 case 0x50: /* POWER_CTRL */
8da3ff18 1102 return s->ulpd_pm_regs[addr >> 2];
c3d2689d
AZ		 1103 }
1104
1105 OMAP_BAD_REG(addr);
1106 return 0;
1107}
1108
1109static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
1110 uint16_t diff, uint16_t value)
1111{
1112 if (diff & (1 << 4)) /* USB_MCLK_EN */
1113 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
1114 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
1115 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
1116}
1117
1118static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
1119 uint16_t diff, uint16_t value)
1120{
1121 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
1122 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
1123 if (diff & (1 << 1)) /* SOFT_COM_REQ */
1124 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
1125 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
1126 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
1127 if (diff & (1 << 3)) /* SOFT_USB_REQ */
1128 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
1129}
1130
c227f099 1131static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1132 uint32_t value)
1133{
1134 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1135 int64_t now, ticks;
1136 int div, mult;
1137 static const int bypass_div[4] = { 1, 2, 4, 4 };
1138 uint16_t diff;
1139
8da3ff18 1140 switch (addr) {
c3d2689d
AZ		 1141 case 0x00: /* COUNTER_32_LSB */
1142 case 0x04: /* COUNTER_32_MSB */
1143 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1144 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1145 case 0x14: /* IT_STATUS */
1146 case 0x40: /* STATUS_REQ */
1147 OMAP_RO_REG(addr);
1148 break;
1149
1150 case 0x10: /* GAUGING_CTRL */
1151 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
8da3ff18 1152 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
c3d2689d
AZ		 1153 now = qemu_get_clock(vm_clock);
1154
1155 if (value & 1)
1156 s->ulpd_gauge_start = now;
1157 else {
1158 now -= s->ulpd_gauge_start;
1159
1160 /* 32-kHz ticks */
6ee093c9 1161 ticks = muldiv64(now, 32768, get_ticks_per_sec());
c3d2689d
AZ		 1162 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
1163 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
1164 if (ticks >> 32) /* OVERFLOW_32K */
1165 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
1166
1167 /* High frequency ticks */
6ee093c9 1168 ticks = muldiv64(now, 12000000, get_ticks_per_sec());
c3d2689d
AZ		 1169 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
1170 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
1171 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
1172 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
1173
1174 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1175 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
1176 }
1177 }
8da3ff18 1178 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 1179 break;
1180
1181 case 0x18: /* Reserved */
1182 case 0x1c: /* Reserved */
1183 case 0x20: /* Reserved */
1184 case 0x28: /* Reserved */
1185 case 0x2c: /* Reserved */
1186 OMAP_BAD_REG(addr);
1187 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1188 case 0x38: /* COUNTER_32_FIQ */
1189 case 0x48: /* LOCL_TIME */
1190 case 0x50: /* POWER_CTRL */
8da3ff18 1191 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 1192 break;
1193
1194 case 0x30: /* CLOCK_CTRL */
8da3ff18
PB		 1195 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
1196 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
c3d2689d
AZ		 1197 omap_ulpd_clk_update(s, diff, value);
1198 break;
1199
1200 case 0x34: /* SOFT_REQ */
8da3ff18
PB		 1201 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
1202 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
c3d2689d
AZ		 1203 omap_ulpd_req_update(s, diff, value);
1204 break;
1205
1206 case 0x3c: /* DPLL_CTRL */
1207 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1208 * omitted altogether, probably a typo. */
1209 /* This register has identical semantics with DPLL(1:3) control
1210 * registers, see omap_dpll_write() */
8da3ff18
PB		 1211 diff = s->ulpd_pm_regs[addr >> 2] & value;
1212 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
c3d2689d
AZ		 1213 if (diff & (0x3ff << 2)) {
1214 if (value & (1 << 4)) { /* PLL_ENABLE */
1215 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1216 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1217 } else {
1218 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1219 mult = 1;
1220 }
1221 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
1222 }
1223
1224 /* Enter the desired mode. */
8da3ff18
PB		 1225 s->ulpd_pm_regs[addr >> 2] =
1226 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
1227 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
c3d2689d
AZ		 1228
1229 /* Act as if the lock is restored. */
8da3ff18 1230 s->ulpd_pm_regs[addr >> 2] |= 2;
c3d2689d
AZ		 1231 break;
1232
1233 case 0x4c: /* APLL_CTRL */
8da3ff18
PB		 1234 diff = s->ulpd_pm_regs[addr >> 2] & value;
1235 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
c3d2689d
AZ		 1236 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
1237 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
1238 (value & (1 << 0)) ? "apll" : "dpll4"));
1239 break;
1240
1241 default:
1242 OMAP_BAD_REG(addr);
1243 }
1244}
1245
d60efc6b 1246static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = {
c3d2689d
AZ		 1247 omap_badwidth_read16,
1248 omap_ulpd_pm_read,
1249 omap_badwidth_read16,
1250};
1251
d60efc6b 1252static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = {
c3d2689d
AZ		 1253 omap_badwidth_write16,
1254 omap_ulpd_pm_write,
1255 omap_badwidth_write16,
1256};
1257
1258static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
1259{
1260 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
1261 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
1262 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
1263 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
1264 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
1265 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
1266 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
1267 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
1268 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
1269 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
1270 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
1271 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
1272 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
1273 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
1274 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
1275 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
1276 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
1277 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1278 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
1279 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
1280 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
1281 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
1282 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
1283}
1284
c227f099 1285static void omap_ulpd_pm_init(target_phys_addr_t base,
c3d2689d
AZ		 1286 struct omap_mpu_state_s *mpu)
1287{
1eed09cb 1288 int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
c3d2689d
AZ		 1289 omap_ulpd_pm_writefn, mpu);
1290
8da3ff18 1291 cpu_register_physical_memory(base, 0x800, iomemtype);
c3d2689d
AZ		 1292 omap_ulpd_pm_reset(mpu);
1293}
1294
1295/* OMAP Pin Configuration */
c227f099 1296static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1297{
1298 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1299
8da3ff18 1300 switch (addr) {
c3d2689d
AZ		 1301 case 0x00: /* FUNC_MUX_CTRL_0 */
1302 case 0x04: /* FUNC_MUX_CTRL_1 */
1303 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 1304 return s->func_mux_ctrl[addr >> 2];
c3d2689d
AZ		 1305
1306 case 0x0c: /* COMP_MODE_CTRL_0 */
1307 return s->comp_mode_ctrl[0];
1308
1309 case 0x10: /* FUNC_MUX_CTRL_3 */
1310 case 0x14: /* FUNC_MUX_CTRL_4 */
1311 case 0x18: /* FUNC_MUX_CTRL_5 */
1312 case 0x1c: /* FUNC_MUX_CTRL_6 */
1313 case 0x20: /* FUNC_MUX_CTRL_7 */
1314 case 0x24: /* FUNC_MUX_CTRL_8 */
1315 case 0x28: /* FUNC_MUX_CTRL_9 */
1316 case 0x2c: /* FUNC_MUX_CTRL_A */
1317 case 0x30: /* FUNC_MUX_CTRL_B */
1318 case 0x34: /* FUNC_MUX_CTRL_C */
1319 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 1320 return s->func_mux_ctrl[(addr >> 2) - 1];
c3d2689d
AZ		 1321
1322 case 0x40: /* PULL_DWN_CTRL_0 */
1323 case 0x44: /* PULL_DWN_CTRL_1 */
1324 case 0x48: /* PULL_DWN_CTRL_2 */
1325 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 1326 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
c3d2689d
AZ		 1327
1328 case 0x50: /* GATE_INH_CTRL_0 */
1329 return s->gate_inh_ctrl[0];
1330
1331 case 0x60: /* VOLTAGE_CTRL_0 */
1332 return s->voltage_ctrl[0];
1333
1334 case 0x70: /* TEST_DBG_CTRL_0 */
1335 return s->test_dbg_ctrl[0];
1336
1337 case 0x80: /* MOD_CONF_CTRL_0 */
1338 return s->mod_conf_ctrl[0];
1339 }
1340
1341 OMAP_BAD_REG(addr);
1342 return 0;
1343}
1344
1345static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
1346 uint32_t diff, uint32_t value)
1347{
1348 if (s->compat1509) {
1349 if (diff & (1 << 9)) /* BLUETOOTH */
1350 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
1351 (~value >> 9) & 1);
1352 if (diff & (1 << 7)) /* USB.CLKO */
1353 omap_clk_onoff(omap_findclk(s, "usb.clko"),
1354 (value >> 7) & 1);
1355 }
1356}
1357
1358static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
1359 uint32_t diff, uint32_t value)
1360{
1361 if (s->compat1509) {
1362 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1363 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
1364 (value >> 31) & 1);
1365 if (diff & (1 << 1)) /* CLK32K */
1366 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
1367 (~value >> 1) & 1);
1368 }
1369}
1370
1371static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
1372 uint32_t diff, uint32_t value)
1373{
1374 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1375 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
1376 omap_findclk(s, ((value >> 31) & 1) ?
1377 "ck_48m" : "armper_ck"));
1378 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1379 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
1380 omap_findclk(s, ((value >> 30) & 1) ?
1381 "ck_48m" : "armper_ck"));
1382 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1383 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
1384 omap_findclk(s, ((value >> 29) & 1) ?
1385 "ck_48m" : "armper_ck"));
1386 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1387 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
1388 omap_findclk(s, ((value >> 23) & 1) ?
1389 "ck_48m" : "armper_ck"));
1390 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1391 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
1392 omap_findclk(s, ((value >> 12) & 1) ?
1393 "ck_48m" : "armper_ck"));
1394 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1395 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
1396}
1397
c227f099 1398static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1399 uint32_t value)
1400{
1401 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1402 uint32_t diff;
1403
8da3ff18 1404 switch (addr) {
c3d2689d 1405 case 0x00: /* FUNC_MUX_CTRL_0 */
8da3ff18
PB		 1406 diff = s->func_mux_ctrl[addr >> 2] ^ value;
1407 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 1408 omap_pin_funcmux0_update(s, diff, value);
1409 return;
1410
1411 case 0x04: /* FUNC_MUX_CTRL_1 */
8da3ff18
PB		 1412 diff = s->func_mux_ctrl[addr >> 2] ^ value;
1413 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 1414 omap_pin_funcmux1_update(s, diff, value);
1415 return;
1416
1417 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 1418 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 1419 return;
1420
1421 case 0x0c: /* COMP_MODE_CTRL_0 */
1422 s->comp_mode_ctrl[0] = value;
1423 s->compat1509 = (value != 0x0000eaef);
1424 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
1425 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
1426 return;
1427
1428 case 0x10: /* FUNC_MUX_CTRL_3 */
1429 case 0x14: /* FUNC_MUX_CTRL_4 */
1430 case 0x18: /* FUNC_MUX_CTRL_5 */
1431 case 0x1c: /* FUNC_MUX_CTRL_6 */
1432 case 0x20: /* FUNC_MUX_CTRL_7 */
1433 case 0x24: /* FUNC_MUX_CTRL_8 */
1434 case 0x28: /* FUNC_MUX_CTRL_9 */
1435 case 0x2c: /* FUNC_MUX_CTRL_A */
1436 case 0x30: /* FUNC_MUX_CTRL_B */
1437 case 0x34: /* FUNC_MUX_CTRL_C */
1438 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 1439 s->func_mux_ctrl[(addr >> 2) - 1] = value;
c3d2689d
AZ		 1440 return;
1441
1442 case 0x40: /* PULL_DWN_CTRL_0 */
1443 case 0x44: /* PULL_DWN_CTRL_1 */
1444 case 0x48: /* PULL_DWN_CTRL_2 */
1445 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 1446 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
c3d2689d
AZ		 1447 return;
1448
1449 case 0x50: /* GATE_INH_CTRL_0 */
1450 s->gate_inh_ctrl[0] = value;
1451 return;
1452
1453 case 0x60: /* VOLTAGE_CTRL_0 */
1454 s->voltage_ctrl[0] = value;
1455 return;
1456
1457 case 0x70: /* TEST_DBG_CTRL_0 */
1458 s->test_dbg_ctrl[0] = value;
1459 return;
1460
1461 case 0x80: /* MOD_CONF_CTRL_0 */
1462 diff = s->mod_conf_ctrl[0] ^ value;
1463 s->mod_conf_ctrl[0] = value;
1464 omap_pin_modconf1_update(s, diff, value);
1465 return;
1466
1467 default:
1468 OMAP_BAD_REG(addr);
1469 }
1470}
1471
d60efc6b 1472static CPUReadMemoryFunc * const omap_pin_cfg_readfn[] = {
c3d2689d
AZ		 1473 omap_badwidth_read32,
1474 omap_badwidth_read32,
1475 omap_pin_cfg_read,
1476};
1477
d60efc6b 1478static CPUWriteMemoryFunc * const omap_pin_cfg_writefn[] = {
c3d2689d
AZ		 1479 omap_badwidth_write32,
1480 omap_badwidth_write32,
1481 omap_pin_cfg_write,
1482};
1483
1484static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
1485{
1486 /* Start in Compatibility Mode. */
1487 mpu->compat1509 = 1;
1488 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
1489 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
1490 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
1491 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
1492 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
1493 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
1494 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
1495 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
1496 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
1497 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
1498}
1499
c227f099 1500static void omap_pin_cfg_init(target_phys_addr_t base,
c3d2689d
AZ		 1501 struct omap_mpu_state_s *mpu)
1502{
1eed09cb 1503 int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
c3d2689d
AZ		 1504 omap_pin_cfg_writefn, mpu);
1505
8da3ff18 1506 cpu_register_physical_memory(base, 0x800, iomemtype);
c3d2689d
AZ		 1507 omap_pin_cfg_reset(mpu);
1508}
1509
1510/* Device Identification, Die Identification */
c227f099 1511static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1512{
1513 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1514
1515 switch (addr) {
1516 case 0xfffe1800: /* DIE_ID_LSB */
1517 return 0xc9581f0e;
1518 case 0xfffe1804: /* DIE_ID_MSB */
1519 return 0xa8858bfa;
1520
1521 case 0xfffe2000: /* PRODUCT_ID_LSB */
1522 return 0x00aaaafc;
1523 case 0xfffe2004: /* PRODUCT_ID_MSB */
1524 return 0xcafeb574;
1525
1526 case 0xfffed400: /* JTAG_ID_LSB */
1527 switch (s->mpu_model) {
1528 case omap310:
1529 return 0x03310315;
1530 case omap1510:
1531 return 0x03310115;
827df9f3 1532 default:
2ac71179 1533 hw_error("%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 1534 }
1535 break;
1536
1537 case 0xfffed404: /* JTAG_ID_MSB */
1538 switch (s->mpu_model) {
1539 case omap310:
1540 return 0xfb57402f;
1541 case omap1510:
1542 return 0xfb47002f;
827df9f3 1543 default:
2ac71179 1544 hw_error("%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 1545 }
1546 break;
1547 }
1548
1549 OMAP_BAD_REG(addr);
1550 return 0;
1551}
1552
c227f099 1553static void omap_id_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1554 uint32_t value)
1555{
1556 OMAP_BAD_REG(addr);
1557}
1558
d60efc6b 1559static CPUReadMemoryFunc * const omap_id_readfn[] = {
c3d2689d
AZ		 1560 omap_badwidth_read32,
1561 omap_badwidth_read32,
1562 omap_id_read,
1563};
1564
d60efc6b 1565static CPUWriteMemoryFunc * const omap_id_writefn[] = {
c3d2689d
AZ		 1566 omap_badwidth_write32,
1567 omap_badwidth_write32,
1568 omap_id_write,
1569};
1570
1571static void omap_id_init(struct omap_mpu_state_s *mpu)
1572{
1eed09cb 1573 int iomemtype = cpu_register_io_memory(omap_id_readfn,
c3d2689d 1574 omap_id_writefn, mpu);
8da3ff18
PB		 1575 cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
1576 cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
c3d2689d 1577 if (!cpu_is_omap15xx(mpu))
8da3ff18 1578 cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000);
c3d2689d
AZ		 1579}
1580
1581/* MPUI Control (Dummy) */
c227f099 1582static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1583{
1584 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1585
8da3ff18 1586 switch (addr) {
c3d2689d
AZ		 1587 case 0x00: /* CTRL */
1588 return s->mpui_ctrl;
1589 case 0x04: /* DEBUG_ADDR */
1590 return 0x01ffffff;
1591 case 0x08: /* DEBUG_DATA */
1592 return 0xffffffff;
1593 case 0x0c: /* DEBUG_FLAG */
1594 return 0x00000800;
1595 case 0x10: /* STATUS */
1596 return 0x00000000;
1597
1598 /* Not in OMAP310 */
1599 case 0x14: /* DSP_STATUS */
1600 case 0x18: /* DSP_BOOT_CONFIG */
1601 return 0x00000000;
1602 case 0x1c: /* DSP_MPUI_CONFIG */
1603 return 0x0000ffff;
1604 }
1605
1606 OMAP_BAD_REG(addr);
1607 return 0;
1608}
1609
c227f099 1610static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1611 uint32_t value)
1612{
1613 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1614
8da3ff18 1615 switch (addr) {
c3d2689d
AZ		 1616 case 0x00: /* CTRL */
1617 s->mpui_ctrl = value & 0x007fffff;
1618 break;
1619
1620 case 0x04: /* DEBUG_ADDR */
1621 case 0x08: /* DEBUG_DATA */
1622 case 0x0c: /* DEBUG_FLAG */
1623 case 0x10: /* STATUS */
1624 /* Not in OMAP310 */
1625 case 0x14: /* DSP_STATUS */
1626 OMAP_RO_REG(addr);
1627 case 0x18: /* DSP_BOOT_CONFIG */
1628 case 0x1c: /* DSP_MPUI_CONFIG */
1629 break;
1630
1631 default:
1632 OMAP_BAD_REG(addr);
1633 }
1634}
1635
d60efc6b 1636static CPUReadMemoryFunc * const omap_mpui_readfn[] = {
c3d2689d
AZ		 1637 omap_badwidth_read32,
1638 omap_badwidth_read32,
1639 omap_mpui_read,
1640};
1641
d60efc6b 1642static CPUWriteMemoryFunc * const omap_mpui_writefn[] = {
c3d2689d
AZ		 1643 omap_badwidth_write32,
1644 omap_badwidth_write32,
1645 omap_mpui_write,
1646};
1647
1648static void omap_mpui_reset(struct omap_mpu_state_s *s)
1649{
1650 s->mpui_ctrl = 0x0003ff1b;
1651}
1652
c227f099 1653static void omap_mpui_init(target_phys_addr_t base,
c3d2689d
AZ		 1654 struct omap_mpu_state_s *mpu)
1655{
1eed09cb 1656 int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
c3d2689d
AZ		 1657 omap_mpui_writefn, mpu);
1658
8da3ff18 1659 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1660
1661 omap_mpui_reset(mpu);
1662}
1663
1664/* TIPB Bridges */
1665struct omap_tipb_bridge_s {
c3d2689d
AZ		 1666 qemu_irq abort;
1667
1668 int width_intr;
1669 uint16_t control;
1670 uint16_t alloc;
1671 uint16_t buffer;
1672 uint16_t enh_control;
1673};
1674
c227f099 1675static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1676{
1677 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1678
8da3ff18 1679 switch (addr) {
c3d2689d
AZ		 1680 case 0x00: /* TIPB_CNTL */
1681 return s->control;
1682 case 0x04: /* TIPB_BUS_ALLOC */
1683 return s->alloc;
1684 case 0x08: /* MPU_TIPB_CNTL */
1685 return s->buffer;
1686 case 0x0c: /* ENHANCED_TIPB_CNTL */
1687 return s->enh_control;
1688 case 0x10: /* ADDRESS_DBG */
1689 case 0x14: /* DATA_DEBUG_LOW */
1690 case 0x18: /* DATA_DEBUG_HIGH */
1691 return 0xffff;
1692 case 0x1c: /* DEBUG_CNTR_SIG */
1693 return 0x00f8;
1694 }
1695
1696 OMAP_BAD_REG(addr);
1697 return 0;
1698}
1699
c227f099 1700static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1701 uint32_t value)
1702{
1703 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1704
8da3ff18 1705 switch (addr) {
c3d2689d
AZ		 1706 case 0x00: /* TIPB_CNTL */
1707 s->control = value & 0xffff;
1708 break;
1709
1710 case 0x04: /* TIPB_BUS_ALLOC */
1711 s->alloc = value & 0x003f;
1712 break;
1713
1714 case 0x08: /* MPU_TIPB_CNTL */
1715 s->buffer = value & 0x0003;
1716 break;
1717
1718 case 0x0c: /* ENHANCED_TIPB_CNTL */
1719 s->width_intr = !(value & 2);
1720 s->enh_control = value & 0x000f;
1721 break;
1722
1723 case 0x10: /* ADDRESS_DBG */
1724 case 0x14: /* DATA_DEBUG_LOW */
1725 case 0x18: /* DATA_DEBUG_HIGH */
1726 case 0x1c: /* DEBUG_CNTR_SIG */
1727 OMAP_RO_REG(addr);
1728 break;
1729
1730 default:
1731 OMAP_BAD_REG(addr);
1732 }
1733}
1734
d60efc6b 1735static CPUReadMemoryFunc * const omap_tipb_bridge_readfn[] = {
c3d2689d
AZ		 1736 omap_badwidth_read16,
1737 omap_tipb_bridge_read,
1738 omap_tipb_bridge_read,
1739};
1740
d60efc6b 1741static CPUWriteMemoryFunc * const omap_tipb_bridge_writefn[] = {
c3d2689d
AZ		 1742 omap_badwidth_write16,
1743 omap_tipb_bridge_write,
1744 omap_tipb_bridge_write,
1745};
1746
1747static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1748{
1749 s->control = 0xffff;
1750 s->alloc = 0x0009;
1751 s->buffer = 0x0000;
1752 s->enh_control = 0x000f;
1753}
1754
c227f099 1755struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
c3d2689d
AZ		 1756 qemu_irq abort_irq, omap_clk clk)
1757{
1758 int iomemtype;
1759 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
1760 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
1761
1762 s->abort = abort_irq;
c3d2689d
AZ		 1763 omap_tipb_bridge_reset(s);
1764
1eed09cb 1765 iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn,
c3d2689d 1766 omap_tipb_bridge_writefn, s);
8da3ff18 1767 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1768
1769 return s;
1770}
1771
1772/* Dummy Traffic Controller's Memory Interface */
c227f099 1773static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1774{
1775 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1776 uint32_t ret;
1777
8da3ff18 1778 switch (addr) {
d8f699cb
AZ		 1779 case 0x00: /* IMIF_PRIO */
1780 case 0x04: /* EMIFS_PRIO */
1781 case 0x08: /* EMIFF_PRIO */
1782 case 0x0c: /* EMIFS_CONFIG */
1783 case 0x10: /* EMIFS_CS0_CONFIG */
1784 case 0x14: /* EMIFS_CS1_CONFIG */
1785 case 0x18: /* EMIFS_CS2_CONFIG */
1786 case 0x1c: /* EMIFS_CS3_CONFIG */
1787 case 0x24: /* EMIFF_MRS */
1788 case 0x28: /* TIMEOUT1 */
1789 case 0x2c: /* TIMEOUT2 */
1790 case 0x30: /* TIMEOUT3 */
1791 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1792 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1793 return s->tcmi_regs[addr >> 2];
c3d2689d 1794
d8f699cb 1795 case 0x20: /* EMIFF_SDRAM_CONFIG */
8da3ff18
PB		 1796 ret = s->tcmi_regs[addr >> 2];
1797 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
c3d2689d
AZ		 1798 /* XXX: We can try using the VGA_DIRTY flag for this */
1799 return ret;
1800 }
1801
1802 OMAP_BAD_REG(addr);
1803 return 0;
1804}
1805
c227f099 1806static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1807 uint32_t value)
1808{
1809 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1810
8da3ff18 1811 switch (addr) {
d8f699cb
AZ		 1812 case 0x00: /* IMIF_PRIO */
1813 case 0x04: /* EMIFS_PRIO */
1814 case 0x08: /* EMIFF_PRIO */
1815 case 0x10: /* EMIFS_CS0_CONFIG */
1816 case 0x14: /* EMIFS_CS1_CONFIG */
1817 case 0x18: /* EMIFS_CS2_CONFIG */
1818 case 0x1c: /* EMIFS_CS3_CONFIG */
1819 case 0x20: /* EMIFF_SDRAM_CONFIG */
1820 case 0x24: /* EMIFF_MRS */
1821 case 0x28: /* TIMEOUT1 */
1822 case 0x2c: /* TIMEOUT2 */
1823 case 0x30: /* TIMEOUT3 */
1824 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1825 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1826 s->tcmi_regs[addr >> 2] = value;
c3d2689d 1827 break;
d8f699cb 1828 case 0x0c: /* EMIFS_CONFIG */
8da3ff18 1829 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
c3d2689d
AZ		 1830 break;
1831
1832 default:
1833 OMAP_BAD_REG(addr);
1834 }
1835}
1836
d60efc6b 1837static CPUReadMemoryFunc * const omap_tcmi_readfn[] = {
c3d2689d
AZ		 1838 omap_badwidth_read32,
1839 omap_badwidth_read32,
1840 omap_tcmi_read,
1841};
1842
d60efc6b 1843static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = {
c3d2689d
AZ		 1844 omap_badwidth_write32,
1845 omap_badwidth_write32,
1846 omap_tcmi_write,
1847};
1848
1849static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1850{
1851 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1852 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1853 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1854 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1855 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1856 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1857 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1858 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1859 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1860 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1861 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1862 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1863 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1864 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1865 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1866}
1867
c227f099 1868static void omap_tcmi_init(target_phys_addr_t base,
c3d2689d
AZ		 1869 struct omap_mpu_state_s *mpu)
1870{
1eed09cb 1871 int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
c3d2689d
AZ		 1872 omap_tcmi_writefn, mpu);
1873
8da3ff18 1874 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1875 omap_tcmi_reset(mpu);
1876}
1877
1878/* Digital phase-locked loops control */
c227f099 1879static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1880{
1881 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
c3d2689d 1882
8da3ff18 1883 if (addr == 0x00) /* CTL_REG */
c3d2689d
AZ		 1884 return s->mode;
1885
1886 OMAP_BAD_REG(addr);
1887 return 0;
1888}
1889
c227f099 1890static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1891 uint32_t value)
1892{
1893 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1894 uint16_t diff;
c3d2689d
AZ		 1895 static const int bypass_div[4] = { 1, 2, 4, 4 };
1896 int div, mult;
1897
8da3ff18 1898 if (addr == 0x00) { /* CTL_REG */
c3d2689d
AZ		 1899 /* See omap_ulpd_pm_write() too */
1900 diff = s->mode & value;
1901 s->mode = value & 0x2fff;
1902 if (diff & (0x3ff << 2)) {
1903 if (value & (1 << 4)) { /* PLL_ENABLE */
1904 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1905 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1906 } else {
1907 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1908 mult = 1;
1909 }
1910 omap_clk_setrate(s->dpll, div, mult);
1911 }
1912
1913 /* Enter the desired mode. */
1914 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1915
1916 /* Act as if the lock is restored. */
1917 s->mode |= 2;
1918 } else {
1919 OMAP_BAD_REG(addr);
1920 }
1921}
1922
d60efc6b 1923static CPUReadMemoryFunc * const omap_dpll_readfn[] = {
c3d2689d
AZ		 1924 omap_badwidth_read16,
1925 omap_dpll_read,
1926 omap_badwidth_read16,
1927};
1928
d60efc6b 1929static CPUWriteMemoryFunc * const omap_dpll_writefn[] = {
c3d2689d
AZ		 1930 omap_badwidth_write16,
1931 omap_dpll_write,
1932 omap_badwidth_write16,
1933};
1934
1935static void omap_dpll_reset(struct dpll_ctl_s *s)
1936{
1937 s->mode = 0x2002;
1938 omap_clk_setrate(s->dpll, 1, 1);
1939}
1940
c227f099 1941static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
c3d2689d
AZ		 1942 omap_clk clk)
1943{
1eed09cb 1944 int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
c3d2689d
AZ		 1945 omap_dpll_writefn, s);
1946
c3d2689d
AZ		 1947 s->dpll = clk;
1948 omap_dpll_reset(s);
1949
8da3ff18 1950 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1951}
1952
1953/* UARTs */
1954struct omap_uart_s {
c227f099 1955 target_phys_addr_t base;
c3d2689d 1956 SerialState *serial; /* TODO */
827df9f3 1957 struct omap_target_agent_s *ta;
75554a3c
AZ		 1958 omap_clk fclk;
1959 qemu_irq irq;
827df9f3
AZ		 1960
1961 uint8_t eblr;
1962 uint8_t syscontrol;
1963 uint8_t wkup;
1964 uint8_t cfps;
54585ffe
AZ		 1965 uint8_t mdr[2];
1966 uint8_t scr;
c588de3d 1967 uint8_t clksel;
c3d2689d
AZ		 1968};
1969
827df9f3 1970void omap_uart_reset(struct omap_uart_s *s)
c3d2689d 1971{
827df9f3
AZ		 1972 s->eblr = 0x00;
1973 s->syscontrol = 0;
1974 s->wkup = 0x3f;
1975 s->cfps = 0x69;
c588de3d 1976 s->clksel = 0;
c3d2689d
AZ		 1977}
1978
c227f099 1979struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
827df9f3
AZ		 1980 qemu_irq irq, omap_clk fclk, omap_clk iclk,
1981 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
c3d2689d
AZ		 1982{
1983 struct omap_uart_s *s = (struct omap_uart_s *)
1984 qemu_mallocz(sizeof(struct omap_uart_s));
827df9f3 1985
75554a3c
AZ		 1986 s->base = base;
1987 s->fclk = fclk;
1988 s->irq = irq;
2d48377a 1989#ifdef TARGET_WORDS_BIGENDIAN
b6cd0ea1 1990 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
2d48377a
BS		 1991 chr ?: qemu_chr_open("null", "null", NULL), 1,
1992 1);
1993#else
1994 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
1995 chr ?: qemu_chr_open("null", "null", NULL), 1,
1996 0);
1997#endif
827df9f3
AZ		 1998 return s;
1999}
2000
c227f099 2001static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
827df9f3
AZ		 2002{
2003 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
827df9f3 2004
8da3ff18
PB		 2005 addr &= 0xff;
2006 switch (addr) {
54585ffe
AZ		 2007 case 0x20: /* MDR1 */
2008 return s->mdr[0];
2009 case 0x24: /* MDR2 */
2010 return s->mdr[1];
2011 case 0x40: /* SCR */
2012 return s->scr;
2013 case 0x44: /* SSR */
2014 return 0x0;
c588de3d 2015 case 0x48: /* EBLR (OMAP2) */
827df9f3 2016 return s->eblr;
c588de3d
AZ		 2017 case 0x4C: /* OSC_12M_SEL (OMAP1) */
2018 return s->clksel;
827df9f3
AZ		 2019 case 0x50: /* MVR */
2020 return 0x30;
c588de3d 2021 case 0x54: /* SYSC (OMAP2) */
827df9f3 2022 return s->syscontrol;
c588de3d 2023 case 0x58: /* SYSS (OMAP2) */
827df9f3 2024 return 1;
c588de3d 2025 case 0x5c: /* WER (OMAP2) */
827df9f3 2026 return s->wkup;
c588de3d 2027 case 0x60: /* CFPS (OMAP2) */
827df9f3
AZ		 2028 return s->cfps;
2029 }
2030
2031 OMAP_BAD_REG(addr);
2032 return 0;
2033}
2034
c227f099 2035static void omap_uart_write(void *opaque, target_phys_addr_t addr,
827df9f3
AZ		 2036 uint32_t value)
2037{
2038 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
827df9f3 2039
8da3ff18
PB		 2040 addr &= 0xff;
2041 switch (addr) {
54585ffe
AZ		 2042 case 0x20: /* MDR1 */
2043 s->mdr[0] = value & 0x7f;
2044 break;
2045 case 0x24: /* MDR2 */
2046 s->mdr[1] = value & 0xff;
2047 break;
2048 case 0x40: /* SCR */
2049 s->scr = value & 0xff;
2050 break;
c588de3d 2051 case 0x48: /* EBLR (OMAP2) */
827df9f3
AZ		 2052 s->eblr = value & 0xff;
2053 break;
c588de3d
AZ		 2054 case 0x4C: /* OSC_12M_SEL (OMAP1) */
2055 s->clksel = value & 1;
2056 break;
54585ffe 2057 case 0x44: /* SSR */
827df9f3 2058 case 0x50: /* MVR */
c588de3d 2059 case 0x58: /* SYSS (OMAP2) */
827df9f3
AZ		 2060 OMAP_RO_REG(addr);
2061 break;
c588de3d 2062 case 0x54: /* SYSC (OMAP2) */
827df9f3
AZ		 2063 s->syscontrol = value & 0x1d;
2064 if (value & 2)
2065 omap_uart_reset(s);
2066 break;
c588de3d 2067 case 0x5c: /* WER (OMAP2) */
827df9f3
AZ		 2068 s->wkup = value & 0x7f;
2069 break;
c588de3d 2070 case 0x60: /* CFPS (OMAP2) */
827df9f3
AZ		 2071 s->cfps = value & 0xff;
2072 break;
2073 default:
2074 OMAP_BAD_REG(addr);
2075 }
2076}
2077
d60efc6b 2078static CPUReadMemoryFunc * const omap_uart_readfn[] = {
827df9f3
AZ		 2079 omap_uart_read,
2080 omap_uart_read,
2081 omap_badwidth_read8,
2082};
2083
d60efc6b 2084static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
827df9f3
AZ		 2085 omap_uart_write,
2086 omap_uart_write,
2087 omap_badwidth_write8,
2088};
2089
2090struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
2091 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2092 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2093{
c227f099 2094 target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
827df9f3
AZ		 2095 struct omap_uart_s *s = omap_uart_init(base, irq,
2096 fclk, iclk, txdma, rxdma, chr);
1eed09cb 2097 int iomemtype = cpu_register_io_memory(omap_uart_readfn,
827df9f3
AZ		 2098 omap_uart_writefn, s);
2099
2100 s->ta = ta;
827df9f3 2101
8da3ff18 2102 cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
827df9f3 2103
c3d2689d
AZ		 2104 return s;
2105}
2106
75554a3c
AZ		 2107void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
2108{
2109 /* TODO: Should reuse or destroy current s->serial */
2d48377a
BS		 2110#ifdef TARGET_WORDS_BIGENDIAN
2111 s->serial = serial_mm_init(s->base, 2, s->irq,
2112 omap_clk_getrate(s->fclk) / 16,
2113 chr ?: qemu_chr_open("null", "null", NULL), 1,
2114 1);
2115#else
75554a3c 2116 s->serial = serial_mm_init(s->base, 2, s->irq,
2d48377a
BS		 2117 omap_clk_getrate(s->fclk) / 16,
2118 chr ?: qemu_chr_open("null", "null", NULL), 1,
2119 0);
2120#endif
75554a3c
AZ		 2121}
2122
c3d2689d 2123/* MPU Clock/Reset/Power Mode Control */
c227f099 2124static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 2125{
2126 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 2127
8da3ff18 2128 switch (addr) {
c3d2689d
AZ		 2129 case 0x00: /* ARM_CKCTL */
2130 return s->clkm.arm_ckctl;
2131
2132 case 0x04: /* ARM_IDLECT1 */
2133 return s->clkm.arm_idlect1;
2134
2135 case 0x08: /* ARM_IDLECT2 */
2136 return s->clkm.arm_idlect2;
2137
2138 case 0x0c: /* ARM_EWUPCT */
2139 return s->clkm.arm_ewupct;
2140
2141 case 0x10: /* ARM_RSTCT1 */
2142 return s->clkm.arm_rstct1;
2143
2144 case 0x14: /* ARM_RSTCT2 */
2145 return s->clkm.arm_rstct2;
2146
2147 case 0x18: /* ARM_SYSST */
d8f699cb 2148 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
c3d2689d
AZ		 2149
2150 case 0x1c: /* ARM_CKOUT1 */
2151 return s->clkm.arm_ckout1;
2152
2153 case 0x20: /* ARM_CKOUT2 */
2154 break;
2155 }
2156
2157 OMAP_BAD_REG(addr);
2158 return 0;
2159}
2160
2161static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
2162 uint16_t diff, uint16_t value)
2163{
2164 omap_clk clk;
2165
2166 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
2167 if (value & (1 << 14))
2168 /* Reserved */;
2169 else {
2170 clk = omap_findclk(s, "arminth_ck");
2171 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2172 }
2173 }
2174 if (diff & (1 << 12)) { /* ARM_TIMXO */
2175 clk = omap_findclk(s, "armtim_ck");
2176 if (value & (1 << 12))
2177 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
2178 else
2179 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2180 }
2181 /* XXX: en_dspck */
2182 if (diff & (3 << 10)) { /* DSPMMUDIV */
2183 clk = omap_findclk(s, "dspmmu_ck");
2184 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
2185 }
2186 if (diff & (3 << 8)) { /* TCDIV */
2187 clk = omap_findclk(s, "tc_ck");
2188 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
2189 }
2190 if (diff & (3 << 6)) { /* DSPDIV */
2191 clk = omap_findclk(s, "dsp_ck");
2192 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
2193 }
2194 if (diff & (3 << 4)) { /* ARMDIV */
2195 clk = omap_findclk(s, "arm_ck");
2196 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
2197 }
2198 if (diff & (3 << 2)) { /* LCDDIV */
2199 clk = omap_findclk(s, "lcd_ck");
2200 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
2201 }
2202 if (diff & (3 << 0)) { /* PERDIV */
2203 clk = omap_findclk(s, "armper_ck");
2204 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
2205 }
2206}
2207
2208static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
2209 uint16_t diff, uint16_t value)
2210{
2211 omap_clk clk;
2212
2213 if (value & (1 << 11)) /* SETARM_IDLE */
2214 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
2215 if (!(value & (1 << 10))) /* WKUP_MODE */
2216 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2217
2218#define SET_CANIDLE(clock, bit) \
2219 if (diff & (1 << bit)) { \
2220 clk = omap_findclk(s, clock); \
2221 omap_clk_canidle(clk, (value >> bit) & 1); \
2222 }
2223 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2224 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2225 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2226 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2227 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2228 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2229 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2230 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2231 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2232 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2233 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2234 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2235 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2236 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2237}
2238
2239static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
2240 uint16_t diff, uint16_t value)
2241{
2242 omap_clk clk;
2243
2244#define SET_ONOFF(clock, bit) \
2245 if (diff & (1 << bit)) { \
2246 clk = omap_findclk(s, clock); \
2247 omap_clk_onoff(clk, (value >> bit) & 1); \
2248 }
2249 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2250 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2251 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2252 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2253 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2254 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2255 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2256 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2257 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2258 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2259 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2260}
2261
2262static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
2263 uint16_t diff, uint16_t value)
2264{
2265 omap_clk clk;
2266
2267 if (diff & (3 << 4)) { /* TCLKOUT */
2268 clk = omap_findclk(s, "tclk_out");
2269 switch ((value >> 4) & 3) {
2270 case 1:
2271 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
2272 omap_clk_onoff(clk, 1);
2273 break;
2274 case 2:
2275 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2276 omap_clk_onoff(clk, 1);
2277 break;
2278 default:
2279 omap_clk_onoff(clk, 0);
2280 }
2281 }
2282 if (diff & (3 << 2)) { /* DCLKOUT */
2283 clk = omap_findclk(s, "dclk_out");
2284 switch ((value >> 2) & 3) {
2285 case 0:
2286 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
2287 break;
2288 case 1:
2289 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
2290 break;
2291 case 2:
2292 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
2293 break;
2294 case 3:
2295 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2296 break;
2297 }
2298 }
2299 if (diff & (3 << 0)) { /* ACLKOUT */
2300 clk = omap_findclk(s, "aclk_out");
2301 switch ((value >> 0) & 3) {
2302 case 1:
2303 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2304 omap_clk_onoff(clk, 1);
2305 break;
2306 case 2:
2307 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
2308 omap_clk_onoff(clk, 1);
2309 break;
2310 case 3:
2311 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2312 omap_clk_onoff(clk, 1);
2313 break;
2314 default:
2315 omap_clk_onoff(clk, 0);
2316 }
2317 }
2318}
2319
c227f099 2320static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 2321 uint32_t value)
2322{
2323 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 2324 uint16_t diff;
2325 omap_clk clk;
2326 static const char *clkschemename[8] = {
2327 "fully synchronous", "fully asynchronous", "synchronous scalable",
2328 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2329 };
2330
8da3ff18 2331 switch (addr) {
c3d2689d
AZ		 2332 case 0x00: /* ARM_CKCTL */
2333 diff = s->clkm.arm_ckctl ^ value;
2334 s->clkm.arm_ckctl = value & 0x7fff;
2335 omap_clkm_ckctl_update(s, diff, value);
2336 return;
2337
2338 case 0x04: /* ARM_IDLECT1 */
2339 diff = s->clkm.arm_idlect1 ^ value;
2340 s->clkm.arm_idlect1 = value & 0x0fff;
2341 omap_clkm_idlect1_update(s, diff, value);
2342 return;
2343
2344 case 0x08: /* ARM_IDLECT2 */
2345 diff = s->clkm.arm_idlect2 ^ value;
2346 s->clkm.arm_idlect2 = value & 0x07ff;
2347 omap_clkm_idlect2_update(s, diff, value);
2348 return;
2349
2350 case 0x0c: /* ARM_EWUPCT */
2351 diff = s->clkm.arm_ewupct ^ value;
2352 s->clkm.arm_ewupct = value & 0x003f;
2353 return;
2354
2355 case 0x10: /* ARM_RSTCT1 */
2356 diff = s->clkm.arm_rstct1 ^ value;
2357 s->clkm.arm_rstct1 = value & 0x0007;
2358 if (value & 9) {
2359 qemu_system_reset_request();
2360 s->clkm.cold_start = 0xa;
2361 }
2362 if (diff & ~value & 4) { /* DSP_RST */
2363 omap_mpui_reset(s);
2364 omap_tipb_bridge_reset(s->private_tipb);
2365 omap_tipb_bridge_reset(s->public_tipb);
2366 }
2367 if (diff & 2) { /* DSP_EN */
2368 clk = omap_findclk(s, "dsp_ck");
2369 omap_clk_canidle(clk, (~value >> 1) & 1);
2370 }
2371 return;
2372
2373 case 0x14: /* ARM_RSTCT2 */
2374 s->clkm.arm_rstct2 = value & 0x0001;
2375 return;
2376
2377 case 0x18: /* ARM_SYSST */
2378 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
2379 s->clkm.clocking_scheme = (value >> 11) & 7;
2380 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
2381 clkschemename[s->clkm.clocking_scheme]);
2382 }
2383 s->clkm.cold_start &= value & 0x3f;
2384 return;
2385
2386 case 0x1c: /* ARM_CKOUT1 */
2387 diff = s->clkm.arm_ckout1 ^ value;
2388 s->clkm.arm_ckout1 = value & 0x003f;
2389 omap_clkm_ckout1_update(s, diff, value);
2390 return;
2391
2392 case 0x20: /* ARM_CKOUT2 */
2393 default:
2394 OMAP_BAD_REG(addr);
2395 }
2396}
2397
d60efc6b 2398static CPUReadMemoryFunc * const omap_clkm_readfn[] = {
c3d2689d
AZ		 2399 omap_badwidth_read16,
2400 omap_clkm_read,
2401 omap_badwidth_read16,
2402};
2403
d60efc6b 2404static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
c3d2689d
AZ		 2405 omap_badwidth_write16,
2406 omap_clkm_write,
2407 omap_badwidth_write16,
2408};
2409
c227f099 2410static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 2411{
2412 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 2413
8da3ff18 2414 switch (addr) {
c3d2689d
AZ		 2415 case 0x04: /* DSP_IDLECT1 */
2416 return s->clkm.dsp_idlect1;
2417
2418 case 0x08: /* DSP_IDLECT2 */
2419 return s->clkm.dsp_idlect2;
2420
2421 case 0x14: /* DSP_RSTCT2 */
2422 return s->clkm.dsp_rstct2;
2423
2424 case 0x18: /* DSP_SYSST */
d8f699cb 2425 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
c3d2689d
AZ		 2426 (s->env->halted << 6); /* Quite useless... */
2427 }
2428
2429 OMAP_BAD_REG(addr);
2430 return 0;
2431}
2432
2433static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
2434 uint16_t diff, uint16_t value)
2435{
2436 omap_clk clk;
2437
2438 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2439}
2440
2441static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
2442 uint16_t diff, uint16_t value)
2443{
2444 omap_clk clk;
2445
2446 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2447}
2448
c227f099 2449static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 2450 uint32_t value)
2451{
2452 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 2453 uint16_t diff;
2454
8da3ff18 2455 switch (addr) {
c3d2689d
AZ		 2456 case 0x04: /* DSP_IDLECT1 */
2457 diff = s->clkm.dsp_idlect1 ^ value;
2458 s->clkm.dsp_idlect1 = value & 0x01f7;
2459 omap_clkdsp_idlect1_update(s, diff, value);
2460 break;
2461
2462 case 0x08: /* DSP_IDLECT2 */
2463 s->clkm.dsp_idlect2 = value & 0x0037;
2464 diff = s->clkm.dsp_idlect1 ^ value;
2465 omap_clkdsp_idlect2_update(s, diff, value);
2466 break;
2467
2468 case 0x14: /* DSP_RSTCT2 */
2469 s->clkm.dsp_rstct2 = value & 0x0001;
2470 break;
2471
2472 case 0x18: /* DSP_SYSST */
2473 s->clkm.cold_start &= value & 0x3f;
2474 break;
2475
2476 default:
2477 OMAP_BAD_REG(addr);
2478 }
2479}
2480
d60efc6b 2481static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = {
c3d2689d
AZ		 2482 omap_badwidth_read16,
2483 omap_clkdsp_read,
2484 omap_badwidth_read16,
2485};
2486
d60efc6b 2487static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = {
c3d2689d
AZ		 2488 omap_badwidth_write16,
2489 omap_clkdsp_write,
2490 omap_badwidth_write16,
2491};
2492
2493static void omap_clkm_reset(struct omap_mpu_state_s *s)
2494{
2495 if (s->wdt && s->wdt->reset)
2496 s->clkm.cold_start = 0x6;
2497 s->clkm.clocking_scheme = 0;
2498 omap_clkm_ckctl_update(s, ~0, 0x3000);
2499 s->clkm.arm_ckctl = 0x3000;
d8f699cb 2500 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
c3d2689d 2501 s->clkm.arm_idlect1 = 0x0400;
d8f699cb 2502 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
c3d2689d
AZ		 2503 s->clkm.arm_idlect2 = 0x0100;
2504 s->clkm.arm_ewupct = 0x003f;
2505 s->clkm.arm_rstct1 = 0x0000;
2506 s->clkm.arm_rstct2 = 0x0000;
2507 s->clkm.arm_ckout1 = 0x0015;
2508 s->clkm.dpll1_mode = 0x2002;
2509 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
2510 s->clkm.dsp_idlect1 = 0x0040;
2511 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
2512 s->clkm.dsp_idlect2 = 0x0000;
2513 s->clkm.dsp_rstct2 = 0x0000;
2514}
2515
c227f099
AL		 2516static void omap_clkm_init(target_phys_addr_t mpu_base,
2517 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
c3d2689d
AZ		 2518{
2519 int iomemtype[2] = {
1eed09cb
AK		 2520 cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s),
2521 cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s),
c3d2689d
AZ		 2522 };
2523
d8f699cb
AZ		 2524 s->clkm.arm_idlect1 = 0x03ff;
2525 s->clkm.arm_idlect2 = 0x0100;
2526 s->clkm.dsp_idlect1 = 0x0002;
c3d2689d 2527 omap_clkm_reset(s);
d8f699cb 2528 s->clkm.cold_start = 0x3a;
c3d2689d 2529
8da3ff18
PB		 2530 cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]);
2531 cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]);
c3d2689d
AZ		 2532}
2533
fe71e81a
AZ		 2534/* MPU I/O */
2535struct omap_mpuio_s {
fe71e81a
AZ		 2536 qemu_irq irq;
2537 qemu_irq kbd_irq;
2538 qemu_irq *in;
2539 qemu_irq handler[16];
2540 qemu_irq wakeup;
2541
2542 uint16_t inputs;
2543 uint16_t outputs;
2544 uint16_t dir;
2545 uint16_t edge;
2546 uint16_t mask;
2547 uint16_t ints;
2548
2549 uint16_t debounce;
2550 uint16_t latch;
2551 uint8_t event;
2552
2553 uint8_t buttons[5];
2554 uint8_t row_latch;
2555 uint8_t cols;
2556 int kbd_mask;
2557 int clk;
2558};
2559
2560static void omap_mpuio_set(void *opaque, int line, int level)
2561{
2562 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2563 uint16_t prev = s->inputs;
2564
2565 if (level)
2566 s->inputs |= 1 << line;
2567 else
2568 s->inputs &= ~(1 << line);
2569
2570 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
2571 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
2572 s->ints |= 1 << line;
2573 qemu_irq_raise(s->irq);
2574 /* TODO: wakeup */
2575 }
2576 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2577 (s->event >> 1) == line) /* PIN_SELECT */
2578 s->latch = s->inputs;
2579 }
2580}
2581
2582static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
2583{
2584 int i;
2585 uint8_t *row, rows = 0, cols = ~s->cols;
2586
38a34e1d 2587 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
fe71e81a 2588 if (*row & cols)
38a34e1d 2589 rows |= i;
fe71e81a 2590
cf6d9118
AZ		 2591 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
2592 s->row_latch = ~rows;
fe71e81a
AZ		 2593}
2594
c227f099 2595static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
fe71e81a
AZ		 2596{
2597 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 2598 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 2599 uint16_t ret;
2600
2601 switch (offset) {
2602 case 0x00: /* INPUT_LATCH */
2603 return s->inputs;
2604
2605 case 0x04: /* OUTPUT_REG */
2606 return s->outputs;
2607
2608 case 0x08: /* IO_CNTL */
2609 return s->dir;
2610
2611 case 0x10: /* KBR_LATCH */
2612 return s->row_latch;
2613
2614 case 0x14: /* KBC_REG */
2615 return s->cols;
2616
2617 case 0x18: /* GPIO_EVENT_MODE_REG */
2618 return s->event;
2619
2620 case 0x1c: /* GPIO_INT_EDGE_REG */
2621 return s->edge;
2622
2623 case 0x20: /* KBD_INT */
cf6d9118 2624 return (~s->row_latch & 0x1f) && !s->kbd_mask;
fe71e81a
AZ		 2625
2626 case 0x24: /* GPIO_INT */
2627 ret = s->ints;
8e129e07
AZ		 2628 s->ints &= s->mask;
2629 if (ret)
2630 qemu_irq_lower(s->irq);
fe71e81a
AZ		 2631 return ret;
2632
2633 case 0x28: /* KBD_MASKIT */
2634 return s->kbd_mask;
2635
2636 case 0x2c: /* GPIO_MASKIT */
2637 return s->mask;
2638
2639 case 0x30: /* GPIO_DEBOUNCING_REG */
2640 return s->debounce;
2641
2642 case 0x34: /* GPIO_LATCH_REG */
2643 return s->latch;
2644 }
2645
2646 OMAP_BAD_REG(addr);
2647 return 0;
2648}
2649
c227f099 2650static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
fe71e81a
AZ		 2651 uint32_t value)
2652{
2653 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 2654 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 2655 uint16_t diff;
2656 int ln;
2657
2658 switch (offset) {
2659 case 0x04: /* OUTPUT_REG */
d8f699cb 2660 diff = (s->outputs ^ value) & ~s->dir;
fe71e81a 2661 s->outputs = value;
fe71e81a
AZ		 2662 while ((ln = ffs(diff))) {
2663 ln --;
2664 if (s->handler[ln])
2665 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2666 diff &= ~(1 << ln);
2667 }
2668 break;
2669
2670 case 0x08: /* IO_CNTL */
2671 diff = s->outputs & (s->dir ^ value);
2672 s->dir = value;
2673
2674 value = s->outputs & ~s->dir;
2675 while ((ln = ffs(diff))) {
2676 ln --;
2677 if (s->handler[ln])
2678 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2679 diff &= ~(1 << ln);
2680 }
2681 break;
2682
2683 case 0x14: /* KBC_REG */
2684 s->cols = value;
2685 omap_mpuio_kbd_update(s);
2686 break;
2687
2688 case 0x18: /* GPIO_EVENT_MODE_REG */
2689 s->event = value & 0x1f;
2690 break;
2691
2692 case 0x1c: /* GPIO_INT_EDGE_REG */
2693 s->edge = value;
2694 break;
2695
2696 case 0x28: /* KBD_MASKIT */
2697 s->kbd_mask = value & 1;
2698 omap_mpuio_kbd_update(s);
2699 break;
2700
2701 case 0x2c: /* GPIO_MASKIT */
2702 s->mask = value;
2703 break;
2704
2705 case 0x30: /* GPIO_DEBOUNCING_REG */
2706 s->debounce = value & 0x1ff;
2707 break;
2708
2709 case 0x00: /* INPUT_LATCH */
2710 case 0x10: /* KBR_LATCH */
2711 case 0x20: /* KBD_INT */
2712 case 0x24: /* GPIO_INT */
2713 case 0x34: /* GPIO_LATCH_REG */
2714 OMAP_RO_REG(addr);
2715 return;
2716
2717 default:
2718 OMAP_BAD_REG(addr);
2719 return;
2720 }
2721}
2722
d60efc6b 2723static CPUReadMemoryFunc * const omap_mpuio_readfn[] = {
fe71e81a
AZ		 2724 omap_badwidth_read16,
2725 omap_mpuio_read,
2726 omap_badwidth_read16,
2727};
2728
d60efc6b 2729static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = {
fe71e81a
AZ		 2730 omap_badwidth_write16,
2731 omap_mpuio_write,
2732 omap_badwidth_write16,
2733};
2734
9596ebb7 2735static void omap_mpuio_reset(struct omap_mpuio_s *s)
fe71e81a
AZ		 2736{
2737 s->inputs = 0;
2738 s->outputs = 0;
2739 s->dir = ~0;
2740 s->event = 0;
2741 s->edge = 0;
2742 s->kbd_mask = 0;
2743 s->mask = 0;
2744 s->debounce = 0;
2745 s->latch = 0;
2746 s->ints = 0;
2747 s->row_latch = 0x1f;
38a34e1d 2748 s->clk = 1;
fe71e81a
AZ		 2749}
2750
2751static void omap_mpuio_onoff(void *opaque, int line, int on)
2752{
2753 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2754
2755 s->clk = on;
2756 if (on)
2757 omap_mpuio_kbd_update(s);
2758}
2759
c227f099 2760struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
fe71e81a
AZ		 2761 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2762 omap_clk clk)
2763{
2764 int iomemtype;
2765 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
2766 qemu_mallocz(sizeof(struct omap_mpuio_s));
2767
fe71e81a
AZ		 2768 s->irq = gpio_int;
2769 s->kbd_irq = kbd_int;
2770 s->wakeup = wakeup;
2771 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2772 omap_mpuio_reset(s);
2773
1eed09cb 2774 iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
fe71e81a 2775 omap_mpuio_writefn, s);
8da3ff18 2776 cpu_register_physical_memory(base, 0x800, iomemtype);
fe71e81a
AZ		 2777
2778 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2779
2780 return s;
2781}
2782
2783qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2784{
2785 return s->in;
2786}
2787
2788void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2789{
2790 if (line >= 16 || line < 0)
2ac71179 2791 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
fe71e81a
AZ		 2792 s->handler[line] = handler;
2793}
2794
2795void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2796{
2797 if (row >= 5 || row < 0)
2ac71179 2798 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
fe71e81a
AZ		 2799
2800 if (down)
38a34e1d 2801 s->buttons[row] |= 1 << col;
fe71e81a 2802 else
38a34e1d 2803 s->buttons[row] &= ~(1 << col);
fe71e81a
AZ		 2804
2805 omap_mpuio_kbd_update(s);
2806}
2807
64330148
AZ		 2808/* General-Purpose I/O */
2809struct omap_gpio_s {
64330148
AZ		 2810 qemu_irq irq;
2811 qemu_irq *in;
2812 qemu_irq handler[16];
2813
2814 uint16_t inputs;
2815 uint16_t outputs;
2816 uint16_t dir;
2817 uint16_t edge;
2818 uint16_t mask;
2819 uint16_t ints;
d8f699cb 2820 uint16_t pins;
64330148
AZ		 2821};
2822
2823static void omap_gpio_set(void *opaque, int line, int level)
2824{
2825 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2826 uint16_t prev = s->inputs;
2827
2828 if (level)
2829 s->inputs |= 1 << line;
2830 else
2831 s->inputs &= ~(1 << line);
2832
2833 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
2834 (1 << line) & s->dir & ~s->mask) {
2835 s->ints |= 1 << line;
2836 qemu_irq_raise(s->irq);
2837 }
2838}
2839
c227f099 2840static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
64330148
AZ		 2841{
2842 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
cf965d24 2843 int offset = addr & OMAP_MPUI_REG_MASK;
64330148
AZ		 2844
2845 switch (offset) {
2846 case 0x00: /* DATA_INPUT */
d8f699cb 2847 return s->inputs & s->pins;
64330148
AZ		 2848
2849 case 0x04: /* DATA_OUTPUT */
2850 return s->outputs;
2851
2852 case 0x08: /* DIRECTION_CONTROL */
2853 return s->dir;
2854
2855 case 0x0c: /* INTERRUPT_CONTROL */
2856 return s->edge;
2857
2858 case 0x10: /* INTERRUPT_MASK */
2859 return s->mask;
2860
2861 case 0x14: /* INTERRUPT_STATUS */
2862 return s->ints;
d8f699cb
AZ		 2863
2864 case 0x18: /* PIN_CONTROL (not in OMAP310) */
2865 OMAP_BAD_REG(addr);
2866 return s->pins;
64330148
AZ		 2867 }
2868
2869 OMAP_BAD_REG(addr);
2870 return 0;
2871}
2872
c227f099 2873static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
64330148
AZ		 2874 uint32_t value)
2875{
2876 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
cf965d24 2877 int offset = addr & OMAP_MPUI_REG_MASK;
64330148
AZ		 2878 uint16_t diff;
2879 int ln;
2880
2881 switch (offset) {
2882 case 0x00: /* DATA_INPUT */
2883 OMAP_RO_REG(addr);
2884 return;
2885
2886 case 0x04: /* DATA_OUTPUT */
66450b15 2887 diff = (s->outputs ^ value) & ~s->dir;
64330148 2888 s->outputs = value;
64330148
AZ		 2889 while ((ln = ffs(diff))) {
2890 ln --;
2891 if (s->handler[ln])
2892 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2893 diff &= ~(1 << ln);
2894 }
2895 break;
2896
2897 case 0x08: /* DIRECTION_CONTROL */
2898 diff = s->outputs & (s->dir ^ value);
2899 s->dir = value;
2900
2901 value = s->outputs & ~s->dir;
2902 while ((ln = ffs(diff))) {
2903 ln --;
2904 if (s->handler[ln])
2905 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2906 diff &= ~(1 << ln);
2907 }
2908 break;
2909
2910 case 0x0c: /* INTERRUPT_CONTROL */
2911 s->edge = value;
2912 break;
2913
2914 case 0x10: /* INTERRUPT_MASK */
2915 s->mask = value;
2916 break;
2917
2918 case 0x14: /* INTERRUPT_STATUS */
2919 s->ints &= ~value;
2920 if (!s->ints)
2921 qemu_irq_lower(s->irq);
2922 break;
2923
d8f699cb
AZ		 2924 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
2925 OMAP_BAD_REG(addr);
2926 s->pins = value;
2927 break;
2928
64330148
AZ		 2929 default:
2930 OMAP_BAD_REG(addr);
2931 return;
2932 }
2933}
2934
3efda49d 2935/* *Some* sources say the memory region is 32-bit. */
d60efc6b 2936static CPUReadMemoryFunc * const omap_gpio_readfn[] = {
3efda49d 2937 omap_badwidth_read16,
64330148 2938 omap_gpio_read,
3efda49d 2939 omap_badwidth_read16,
64330148
AZ		 2940};
2941
d60efc6b 2942static CPUWriteMemoryFunc * const omap_gpio_writefn[] = {
3efda49d 2943 omap_badwidth_write16,
64330148 2944 omap_gpio_write,
3efda49d 2945 omap_badwidth_write16,
64330148
AZ		 2946};
2947
9596ebb7 2948static void omap_gpio_reset(struct omap_gpio_s *s)
64330148
AZ		 2949{
2950 s->inputs = 0;
2951 s->outputs = ~0;
2952 s->dir = ~0;
2953 s->edge = ~0;
2954 s->mask = ~0;
2955 s->ints = 0;
d8f699cb 2956 s->pins = ~0;
64330148
AZ		 2957}
2958
c227f099 2959struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
64330148
AZ		 2960 qemu_irq irq, omap_clk clk)
2961{
2962 int iomemtype;
2963 struct omap_gpio_s *s = (struct omap_gpio_s *)
2964 qemu_mallocz(sizeof(struct omap_gpio_s));
2965
64330148
AZ		 2966 s->irq = irq;
2967 s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
2968 omap_gpio_reset(s);
2969
1eed09cb 2970 iomemtype = cpu_register_io_memory(omap_gpio_readfn,
64330148 2971 omap_gpio_writefn, s);
8da3ff18 2972 cpu_register_physical_memory(base, 0x1000, iomemtype);
64330148
AZ		 2973
2974 return s;
2975}
2976
2977qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
2978{
2979 return s->in;
2980}
2981
2982void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
2983{
2984 if (line >= 16 || line < 0)
2ac71179 2985 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
64330148
AZ		 2986 s->handler[line] = handler;
2987}
2988
d951f6ff
AZ		 2989/* MicroWire Interface */
2990struct omap_uwire_s {
d951f6ff
AZ		 2991 qemu_irq txirq;
2992 qemu_irq rxirq;
2993 qemu_irq txdrq;
2994
2995 uint16_t txbuf;
2996 uint16_t rxbuf;
2997 uint16_t control;
2998 uint16_t setup[5];
2999
bc24a225 3000 uWireSlave *chip[4];
d951f6ff
AZ		 3001};
3002
3003static void omap_uwire_transfer_start(struct omap_uwire_s *s)
3004{
3005 int chipselect = (s->control >> 10) & 3; /* INDEX */
bc24a225 3006 uWireSlave *slave = s->chip[chipselect];
d951f6ff
AZ		 3007
3008 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
3009 if (s->control & (1 << 12)) /* CS_CMD */
3010 if (slave && slave->send)
3011 slave->send(slave->opaque,
3012 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
3013 s->control &= ~(1 << 14); /* CSRB */
3014 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3015 * a DRQ. When is the level IRQ supposed to be reset? */
3016 }
3017
3018 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
3019 if (s->control & (1 << 12)) /* CS_CMD */
3020 if (slave && slave->receive)
3021 s->rxbuf = slave->receive(slave->opaque);
3022 s->control |= 1 << 15; /* RDRB */
3023 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3024 * a DRQ. When is the level IRQ supposed to be reset? */
3025 }
3026}
3027
c227f099 3028static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
d951f6ff
AZ		 3029{
3030 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 3031 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff
AZ		 3032
3033 switch (offset) {
3034 case 0x00: /* RDR */
3035 s->control &= ~(1 << 15); /* RDRB */
3036 return s->rxbuf;
3037
3038 case 0x04: /* CSR */
3039 return s->control;
3040
3041 case 0x08: /* SR1 */
3042 return s->setup[0];
3043 case 0x0c: /* SR2 */
3044 return s->setup[1];
3045 case 0x10: /* SR3 */
3046 return s->setup[2];
3047 case 0x14: /* SR4 */
3048 return s->setup[3];
3049 case 0x18: /* SR5 */
3050 return s->setup[4];
3051 }
3052
3053 OMAP_BAD_REG(addr);
3054 return 0;
3055}
3056
c227f099 3057static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
d951f6ff
AZ		 3058 uint32_t value)
3059{
3060 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 3061 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff
AZ		 3062
3063 switch (offset) {
3064 case 0x00: /* TDR */
3065 s->txbuf = value; /* TD */
d951f6ff
AZ		 3066 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
3067 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
cf965d24
AZ		 3068 (s->control & (1 << 12)))) { /* CS_CMD */
3069 s->control |= 1 << 14; /* CSRB */
d951f6ff 3070 omap_uwire_transfer_start(s);
cf965d24 3071 }
d951f6ff
AZ		 3072 break;
3073
3074 case 0x04: /* CSR */
3075 s->control = value & 0x1fff;
3076 if (value & (1 << 13)) /* START */
3077 omap_uwire_transfer_start(s);
3078 break;
3079
3080 case 0x08: /* SR1 */
3081 s->setup[0] = value & 0x003f;
3082 break;
3083
3084 case 0x0c: /* SR2 */
3085 s->setup[1] = value & 0x0fc0;
3086 break;
3087
3088 case 0x10: /* SR3 */
3089 s->setup[2] = value & 0x0003;
3090 break;
3091
3092 case 0x14: /* SR4 */
3093 s->setup[3] = value & 0x0001;
3094 break;
3095
3096 case 0x18: /* SR5 */
3097 s->setup[4] = value & 0x000f;
3098 break;
3099
3100 default:
3101 OMAP_BAD_REG(addr);
3102 return;
3103 }
3104}
3105
d60efc6b 3106static CPUReadMemoryFunc * const omap_uwire_readfn[] = {
d951f6ff
AZ		 3107 omap_badwidth_read16,
3108 omap_uwire_read,
3109 omap_badwidth_read16,
3110};
3111
d60efc6b 3112static CPUWriteMemoryFunc * const omap_uwire_writefn[] = {
d951f6ff
AZ		 3113 omap_badwidth_write16,
3114 omap_uwire_write,
3115 omap_badwidth_write16,
3116};
3117
9596ebb7 3118static void omap_uwire_reset(struct omap_uwire_s *s)
d951f6ff 3119{
66450b15 3120 s->control = 0;
d951f6ff
AZ		 3121 s->setup[0] = 0;
3122 s->setup[1] = 0;
3123 s->setup[2] = 0;
3124 s->setup[3] = 0;
3125 s->setup[4] = 0;
3126}
3127
c227f099 3128struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
d951f6ff
AZ		 3129 qemu_irq *irq, qemu_irq dma, omap_clk clk)
3130{
3131 int iomemtype;
3132 struct omap_uwire_s *s = (struct omap_uwire_s *)
3133 qemu_mallocz(sizeof(struct omap_uwire_s));
3134
d951f6ff
AZ		 3135 s->txirq = irq[0];
3136 s->rxirq = irq[1];
3137 s->txdrq = dma;
3138 omap_uwire_reset(s);
3139
1eed09cb 3140 iomemtype = cpu_register_io_memory(omap_uwire_readfn,
d951f6ff 3141 omap_uwire_writefn, s);
8da3ff18 3142 cpu_register_physical_memory(base, 0x800, iomemtype);
d951f6ff
AZ		 3143
3144 return s;
3145}
3146
3147void omap_uwire_attach(struct omap_uwire_s *s,
bc24a225 3148 uWireSlave *slave, int chipselect)
d951f6ff 3149{
827df9f3
AZ		 3150 if (chipselect < 0 || chipselect > 3) {
3151 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
3152 exit(-1);
3153 }
d951f6ff
AZ		 3154
3155 s->chip[chipselect] = slave;
3156}
3157
66450b15 3158/* Pseudonoise Pulse-Width Light Modulator */
9596ebb7 3159static void omap_pwl_update(struct omap_mpu_state_s *s)
66450b15
AZ		 3160{
3161 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
3162
3163 if (output != s->pwl.output) {
3164 s->pwl.output = output;
3165 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
3166 }
3167}
3168
c227f099 3169static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
66450b15
AZ		 3170{
3171 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3172 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15
AZ		 3173
3174 switch (offset) {
3175 case 0x00: /* PWL_LEVEL */
3176 return s->pwl.level;
3177 case 0x04: /* PWL_CTRL */
3178 return s->pwl.enable;
3179 }
3180 OMAP_BAD_REG(addr);
3181 return 0;
3182}
3183
c227f099 3184static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
66450b15
AZ		 3185 uint32_t value)
3186{
3187 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3188 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15
AZ		 3189
3190 switch (offset) {
3191 case 0x00: /* PWL_LEVEL */
3192 s->pwl.level = value;
3193 omap_pwl_update(s);
3194 break;
3195 case 0x04: /* PWL_CTRL */
3196 s->pwl.enable = value & 1;
3197 omap_pwl_update(s);
3198 break;
3199 default:
3200 OMAP_BAD_REG(addr);
3201 return;
3202 }
3203}
3204
d60efc6b 3205static CPUReadMemoryFunc * const omap_pwl_readfn[] = {
02645926 3206 omap_pwl_read,
66450b15
AZ		 3207 omap_badwidth_read8,
3208 omap_badwidth_read8,
66450b15
AZ		 3209};
3210
d60efc6b 3211static CPUWriteMemoryFunc * const omap_pwl_writefn[] = {
02645926 3212 omap_pwl_write,
66450b15
AZ		 3213 omap_badwidth_write8,
3214 omap_badwidth_write8,
66450b15
AZ		 3215};
3216
9596ebb7 3217static void omap_pwl_reset(struct omap_mpu_state_s *s)
66450b15
AZ		 3218{
3219 s->pwl.output = 0;
3220 s->pwl.level = 0;
3221 s->pwl.enable = 0;
3222 s->pwl.clk = 1;
3223 omap_pwl_update(s);
3224}
3225
3226static void omap_pwl_clk_update(void *opaque, int line, int on)
3227{
3228 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3229
3230 s->pwl.clk = on;
3231 omap_pwl_update(s);
3232}
3233
c227f099 3234static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
66450b15
AZ		 3235 omap_clk clk)
3236{
3237 int iomemtype;
3238
66450b15
AZ		 3239 omap_pwl_reset(s);
3240
1eed09cb 3241 iomemtype = cpu_register_io_memory(omap_pwl_readfn,
66450b15 3242 omap_pwl_writefn, s);
b854bc19 3243 cpu_register_physical_memory(base, 0x800, iomemtype);
66450b15
AZ		 3244
3245 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
3246}
3247
f34c417b 3248/* Pulse-Width Tone module */
c227f099 3249static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
f34c417b
AZ		 3250{
3251 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3252 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b
AZ		 3253
3254 switch (offset) {
3255 case 0x00: /* FRC */
3256 return s->pwt.frc;
3257 case 0x04: /* VCR */
3258 return s->pwt.vrc;
3259 case 0x08: /* GCR */
3260 return s->pwt.gcr;
3261 }
3262 OMAP_BAD_REG(addr);
3263 return 0;
3264}
3265
c227f099 3266static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
f34c417b
AZ		 3267 uint32_t value)
3268{
3269 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3270 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b
AZ		 3271
3272 switch (offset) {
3273 case 0x00: /* FRC */
3274 s->pwt.frc = value & 0x3f;
3275 break;
3276 case 0x04: /* VRC */
3277 if ((value ^ s->pwt.vrc) & 1) {
3278 if (value & 1)
3279 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
3280 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3281 ((omap_clk_getrate(s->pwt.clk) >> 3) /
3282 /* Pre-multiplexer divider */
3283 ((s->pwt.gcr & 2) ? 1 : 154) /
3284 /* Octave multiplexer */
3285 (2 << (value & 3)) *
3286 /* 101/107 divider */
3287 ((value & (1 << 2)) ? 101 : 107) *
3288 /* 49/55 divider */
3289 ((value & (1 << 3)) ? 49 : 55) *
3290 /* 50/63 divider */
3291 ((value & (1 << 4)) ? 50 : 63) *
3292 /* 80/127 divider */
3293 ((value & (1 << 5)) ? 80 : 127) /
3294 (107 * 55 * 63 * 127)));
3295 else
3296 printf("%s: silence!\n", __FUNCTION__);
3297 }
3298 s->pwt.vrc = value & 0x7f;
3299 break;
3300 case 0x08: /* GCR */
3301 s->pwt.gcr = value & 3;
3302 break;
3303 default:
3304 OMAP_BAD_REG(addr);
3305 return;
3306 }
3307}
3308
d60efc6b 3309static CPUReadMemoryFunc * const omap_pwt_readfn[] = {
02645926 3310 omap_pwt_read,
f34c417b
AZ		 3311 omap_badwidth_read8,
3312 omap_badwidth_read8,
f34c417b
AZ		 3313};
3314
d60efc6b 3315static CPUWriteMemoryFunc * const omap_pwt_writefn[] = {
02645926 3316 omap_pwt_write,
f34c417b
AZ		 3317 omap_badwidth_write8,
3318 omap_badwidth_write8,
f34c417b
AZ		 3319};
3320
9596ebb7 3321static void omap_pwt_reset(struct omap_mpu_state_s *s)
f34c417b
AZ		 3322{
3323 s->pwt.frc = 0;
3324 s->pwt.vrc = 0;
3325 s->pwt.gcr = 0;
3326}
3327
c227f099 3328static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
f34c417b
AZ		 3329 omap_clk clk)
3330{
3331 int iomemtype;
3332
f34c417b
AZ		 3333 s->pwt.clk = clk;
3334 omap_pwt_reset(s);
3335
1eed09cb 3336 iomemtype = cpu_register_io_memory(omap_pwt_readfn,
f34c417b 3337 omap_pwt_writefn, s);
b854bc19 3338 cpu_register_physical_memory(base, 0x800, iomemtype);
f34c417b
AZ		 3339}
3340
5c1c390f
AZ		 3341/* Real-time Clock module */
3342struct omap_rtc_s {
5c1c390f
AZ		 3343 qemu_irq irq;
3344 qemu_irq alarm;
3345 QEMUTimer *clk;
3346
3347 uint8_t interrupts;
3348 uint8_t status;
3349 int16_t comp_reg;
3350 int running;
3351 int pm_am;
3352 int auto_comp;
3353 int round;
5c1c390f
AZ		 3354 struct tm alarm_tm;
3355 time_t alarm_ti;
3356
3357 struct tm current_tm;
3358 time_t ti;
3359 uint64_t tick;
3360};
3361
3362static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
3363{
106627d0 3364 /* s->alarm is level-triggered */
5c1c390f
AZ		 3365 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
3366}
3367
3368static void omap_rtc_alarm_update(struct omap_rtc_s *s)
3369{
0cd2df75 3370 s->alarm_ti = mktimegm(&s->alarm_tm);
5c1c390f
AZ		 3371 if (s->alarm_ti == -1)
3372 printf("%s: conversion failed\n", __FUNCTION__);
3373}
3374
c227f099 3375static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
5c1c390f
AZ		 3376{
3377 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 3378 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 3379 uint8_t i;
3380
3381 switch (offset) {
3382 case 0x00: /* SECONDS_REG */
abd0c6bd 3383 return to_bcd(s->current_tm.tm_sec);
5c1c390f
AZ		 3384
3385 case 0x04: /* MINUTES_REG */
abd0c6bd 3386 return to_bcd(s->current_tm.tm_min);
5c1c390f
AZ		 3387
3388 case 0x08: /* HOURS_REG */
3389 if (s->pm_am)
3390 return ((s->current_tm.tm_hour > 11) << 7) |
abd0c6bd 3391 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
5c1c390f 3392 else
abd0c6bd 3393 return to_bcd(s->current_tm.tm_hour);
5c1c390f
AZ		 3394
3395 case 0x0c: /* DAYS_REG */
abd0c6bd 3396 return to_bcd(s->current_tm.tm_mday);
5c1c390f
AZ		 3397
3398 case 0x10: /* MONTHS_REG */
abd0c6bd 3399 return to_bcd(s->current_tm.tm_mon + 1);
5c1c390f
AZ		 3400
3401 case 0x14: /* YEARS_REG */
abd0c6bd 3402 return to_bcd(s->current_tm.tm_year % 100);
5c1c390f
AZ		 3403
3404 case 0x18: /* WEEK_REG */
3405 return s->current_tm.tm_wday;
3406
3407 case 0x20: /* ALARM_SECONDS_REG */
abd0c6bd 3408 return to_bcd(s->alarm_tm.tm_sec);
5c1c390f
AZ		 3409
3410 case 0x24: /* ALARM_MINUTES_REG */
abd0c6bd 3411 return to_bcd(s->alarm_tm.tm_min);
5c1c390f
AZ		 3412
3413 case 0x28: /* ALARM_HOURS_REG */
3414 if (s->pm_am)
3415 return ((s->alarm_tm.tm_hour > 11) << 7) |
abd0c6bd 3416 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
5c1c390f 3417 else
abd0c6bd 3418 return to_bcd(s->alarm_tm.tm_hour);
5c1c390f
AZ		 3419
3420 case 0x2c: /* ALARM_DAYS_REG */
abd0c6bd 3421 return to_bcd(s->alarm_tm.tm_mday);
5c1c390f
AZ		 3422
3423 case 0x30: /* ALARM_MONTHS_REG */
abd0c6bd 3424 return to_bcd(s->alarm_tm.tm_mon + 1);
5c1c390f
AZ		 3425
3426 case 0x34: /* ALARM_YEARS_REG */
abd0c6bd 3427 return to_bcd(s->alarm_tm.tm_year % 100);
5c1c390f
AZ		 3428
3429 case 0x40: /* RTC_CTRL_REG */
3430 return (s->pm_am << 3) | (s->auto_comp << 2) |
3431 (s->round << 1) | s->running;
3432
3433 case 0x44: /* RTC_STATUS_REG */
3434 i = s->status;
3435 s->status &= ~0x3d;
3436 return i;
3437
3438 case 0x48: /* RTC_INTERRUPTS_REG */
3439 return s->interrupts;
3440
3441 case 0x4c: /* RTC_COMP_LSB_REG */
3442 return ((uint16_t) s->comp_reg) & 0xff;
3443
3444 case 0x50: /* RTC_COMP_MSB_REG */
3445 return ((uint16_t) s->comp_reg) >> 8;
3446 }
3447
3448 OMAP_BAD_REG(addr);
3449 return 0;
3450}
3451
c227f099 3452static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
5c1c390f
AZ		 3453 uint32_t value)
3454{
3455 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 3456 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 3457 struct tm new_tm;
3458 time_t ti[2];
3459
3460 switch (offset) {
3461 case 0x00: /* SECONDS_REG */
eb38c52c 3462#ifdef ALMDEBUG
5c1c390f
AZ		 3463 printf("RTC SEC_REG <-- %02x\n", value);
3464#endif
3465 s->ti -= s->current_tm.tm_sec;
abd0c6bd 3466 s->ti += from_bcd(value);
5c1c390f
AZ		 3467 return;
3468
3469 case 0x04: /* MINUTES_REG */
eb38c52c 3470#ifdef ALMDEBUG
5c1c390f
AZ		 3471 printf("RTC MIN_REG <-- %02x\n", value);
3472#endif
3473 s->ti -= s->current_tm.tm_min * 60;
abd0c6bd 3474 s->ti += from_bcd(value) * 60;
5c1c390f
AZ		 3475 return;
3476
3477 case 0x08: /* HOURS_REG */
eb38c52c 3478#ifdef ALMDEBUG
5c1c390f
AZ		 3479 printf("RTC HRS_REG <-- %02x\n", value);
3480#endif
3481 s->ti -= s->current_tm.tm_hour * 3600;
3482 if (s->pm_am) {
abd0c6bd 3483 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
5c1c390f
AZ		 3484 s->ti += ((value >> 7) & 1) * 43200;
3485 } else
abd0c6bd 3486 s->ti += from_bcd(value & 0x3f) * 3600;
5c1c390f
AZ		 3487 return;
3488
3489 case 0x0c: /* DAYS_REG */
eb38c52c 3490#ifdef ALMDEBUG
5c1c390f
AZ		 3491 printf("RTC DAY_REG <-- %02x\n", value);
3492#endif
3493 s->ti -= s->current_tm.tm_mday * 86400;
abd0c6bd 3494 s->ti += from_bcd(value) * 86400;
5c1c390f
AZ		 3495 return;
3496
3497 case 0x10: /* MONTHS_REG */
eb38c52c 3498#ifdef ALMDEBUG
5c1c390f
AZ		 3499 printf("RTC MTH_REG <-- %02x\n", value);
3500#endif
3501 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 3502 new_tm.tm_mon = from_bcd(value);
0cd2df75
AJ		 3503 ti[0] = mktimegm(&s->current_tm);
3504 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 3505
3506 if (ti[0] != -1 && ti[1] != -1) {
3507 s->ti -= ti[0];
3508 s->ti += ti[1];
3509 } else {
3510 /* A less accurate version */
3511 s->ti -= s->current_tm.tm_mon * 2592000;
abd0c6bd 3512 s->ti += from_bcd(value) * 2592000;
5c1c390f
AZ		 3513 }
3514 return;
3515
3516 case 0x14: /* YEARS_REG */
eb38c52c 3517#ifdef ALMDEBUG
5c1c390f
AZ		 3518 printf("RTC YRS_REG <-- %02x\n", value);
3519#endif
3520 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 3521 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
0cd2df75
AJ		 3522 ti[0] = mktimegm(&s->current_tm);
3523 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 3524
3525 if (ti[0] != -1 && ti[1] != -1) {
3526 s->ti -= ti[0];
3527 s->ti += ti[1];
3528 } else {
3529 /* A less accurate version */
3530 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
abd0c6bd 3531 s->ti += from_bcd(value) * 31536000;
5c1c390f
AZ		 3532 }
3533 return;
3534
3535 case 0x18: /* WEEK_REG */
3536 return; /* Ignored */
3537
3538 case 0x20: /* ALARM_SECONDS_REG */
eb38c52c 3539#ifdef ALMDEBUG
5c1c390f
AZ		 3540 printf("ALM SEC_REG <-- %02x\n", value);
3541#endif
abd0c6bd 3542 s->alarm_tm.tm_sec = from_bcd(value);
5c1c390f
AZ		 3543 omap_rtc_alarm_update(s);
3544 return;
3545
3546 case 0x24: /* ALARM_MINUTES_REG */
eb38c52c 3547#ifdef ALMDEBUG
5c1c390f
AZ		 3548 printf("ALM MIN_REG <-- %02x\n", value);
3549#endif
abd0c6bd 3550 s->alarm_tm.tm_min = from_bcd(value);
5c1c390f
AZ		 3551 omap_rtc_alarm_update(s);
3552 return;
3553
3554 case 0x28: /* ALARM_HOURS_REG */
eb38c52c 3555#ifdef ALMDEBUG
5c1c390f
AZ		 3556 printf("ALM HRS_REG <-- %02x\n", value);
3557#endif
3558 if (s->pm_am)
3559 s->alarm_tm.tm_hour =
abd0c6bd 3560 ((from_bcd(value & 0x3f)) % 12) +
5c1c390f
AZ		 3561 ((value >> 7) & 1) * 12;
3562 else
abd0c6bd 3563 s->alarm_tm.tm_hour = from_bcd(value);
5c1c390f
AZ		 3564 omap_rtc_alarm_update(s);
3565 return;
3566
3567 case 0x2c: /* ALARM_DAYS_REG */
eb38c52c 3568#ifdef ALMDEBUG
5c1c390f
AZ		 3569 printf("ALM DAY_REG <-- %02x\n", value);
3570#endif
abd0c6bd 3571 s->alarm_tm.tm_mday = from_bcd(value);
5c1c390f
AZ		 3572 omap_rtc_alarm_update(s);
3573 return;
3574
3575 case 0x30: /* ALARM_MONTHS_REG */
eb38c52c 3576#ifdef ALMDEBUG
5c1c390f
AZ		 3577 printf("ALM MON_REG <-- %02x\n", value);
3578#endif
abd0c6bd 3579 s->alarm_tm.tm_mon = from_bcd(value);
5c1c390f
AZ		 3580 omap_rtc_alarm_update(s);
3581 return;
3582
3583 case 0x34: /* ALARM_YEARS_REG */
eb38c52c 3584#ifdef ALMDEBUG
5c1c390f
AZ		 3585 printf("ALM YRS_REG <-- %02x\n", value);
3586#endif
abd0c6bd 3587 s->alarm_tm.tm_year = from_bcd(value);
5c1c390f
AZ		 3588 omap_rtc_alarm_update(s);
3589 return;
3590
3591 case 0x40: /* RTC_CTRL_REG */
eb38c52c 3592#ifdef ALMDEBUG
5c1c390f
AZ		 3593 printf("RTC CONTROL <-- %02x\n", value);
3594#endif
3595 s->pm_am = (value >> 3) & 1;
3596 s->auto_comp = (value >> 2) & 1;
3597 s->round = (value >> 1) & 1;
3598 s->running = value & 1;
3599 s->status &= 0xfd;
3600 s->status |= s->running << 1;
3601 return;
3602
3603 case 0x44: /* RTC_STATUS_REG */
eb38c52c 3604#ifdef ALMDEBUG
5c1c390f
AZ		 3605 printf("RTC STATUSL <-- %02x\n", value);
3606#endif
3607 s->status &= ~((value & 0xc0) ^ 0x80);
3608 omap_rtc_interrupts_update(s);
3609 return;
3610
3611 case 0x48: /* RTC_INTERRUPTS_REG */
eb38c52c 3612#ifdef ALMDEBUG
5c1c390f
AZ		 3613 printf("RTC INTRS <-- %02x\n", value);
3614#endif
3615 s->interrupts = value;
3616 return;
3617
3618 case 0x4c: /* RTC_COMP_LSB_REG */
eb38c52c 3619#ifdef ALMDEBUG
5c1c390f
AZ		 3620 printf("RTC COMPLSB <-- %02x\n", value);
3621#endif
3622 s->comp_reg &= 0xff00;
3623 s->comp_reg |= 0x00ff & value;
3624 return;
3625
3626 case 0x50: /* RTC_COMP_MSB_REG */
eb38c52c 3627#ifdef ALMDEBUG
5c1c390f
AZ		 3628 printf("RTC COMPMSB <-- %02x\n", value);
3629#endif
3630 s->comp_reg &= 0x00ff;
3631 s->comp_reg |= 0xff00 & (value << 8);
3632 return;
3633
3634 default:
3635 OMAP_BAD_REG(addr);
3636 return;
3637 }
3638}
3639
d60efc6b 3640static CPUReadMemoryFunc * const omap_rtc_readfn[] = {
5c1c390f
AZ		 3641 omap_rtc_read,
3642 omap_badwidth_read8,
3643 omap_badwidth_read8,
3644};
3645
d60efc6b 3646static CPUWriteMemoryFunc * const omap_rtc_writefn[] = {
5c1c390f
AZ		 3647 omap_rtc_write,
3648 omap_badwidth_write8,
3649 omap_badwidth_write8,
3650};
3651
3652static void omap_rtc_tick(void *opaque)
3653{
3654 struct omap_rtc_s *s = opaque;
3655
3656 if (s->round) {
3657 /* Round to nearest full minute. */
3658 if (s->current_tm.tm_sec < 30)
3659 s->ti -= s->current_tm.tm_sec;
3660 else
3661 s->ti += 60 - s->current_tm.tm_sec;
3662
3663 s->round = 0;
3664 }
3665
f6503059 3666 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
5c1c390f
AZ		 3667
3668 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
3669 s->status |= 0x40;
3670 omap_rtc_interrupts_update(s);
3671 }
3672
3673 if (s->interrupts & 0x04)
3674 switch (s->interrupts & 3) {
3675 case 0:
3676 s->status |= 0x04;
106627d0 3677 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3678 break;
3679 case 1:
3680 if (s->current_tm.tm_sec)
3681 break;
3682 s->status |= 0x08;
106627d0 3683 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3684 break;
3685 case 2:
3686 if (s->current_tm.tm_sec || s->current_tm.tm_min)
3687 break;
3688 s->status |= 0x10;
106627d0 3689 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3690 break;
3691 case 3:
3692 if (s->current_tm.tm_sec ||
3693 s->current_tm.tm_min || s->current_tm.tm_hour)
3694 break;
3695 s->status |= 0x20;
106627d0 3696 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3697 break;
3698 }
3699
3700 /* Move on */
3701 if (s->running)
3702 s->ti ++;
3703 s->tick += 1000;
3704
3705 /*
3706 * Every full hour add a rough approximation of the compensation
3707 * register to the 32kHz Timer (which drives the RTC) value.
3708 */
3709 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
3710 s->tick += s->comp_reg * 1000 / 32768;
3711
3712 qemu_mod_timer(s->clk, s->tick);
3713}
3714
9596ebb7 3715static void omap_rtc_reset(struct omap_rtc_s *s)
5c1c390f 3716{
f6503059
AZ		 3717 struct tm tm;
3718
5c1c390f
AZ		 3719 s->interrupts = 0;
3720 s->comp_reg = 0;
3721 s->running = 0;
3722 s->pm_am = 0;
3723 s->auto_comp = 0;
3724 s->round = 0;
3725 s->tick = qemu_get_clock(rt_clock);
3726 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
3727 s->alarm_tm.tm_mday = 0x01;
3728 s->status = 1 << 7;
f6503059 3729 qemu_get_timedate(&tm, 0);
0cd2df75 3730 s->ti = mktimegm(&tm);
5c1c390f
AZ		 3731
3732 omap_rtc_alarm_update(s);
3733 omap_rtc_tick(s);
3734}
3735
c227f099 3736struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
5c1c390f
AZ		 3737 qemu_irq *irq, omap_clk clk)
3738{
3739 int iomemtype;
3740 struct omap_rtc_s *s = (struct omap_rtc_s *)
3741 qemu_mallocz(sizeof(struct omap_rtc_s));
3742
5c1c390f
AZ		 3743 s->irq = irq[0];
3744 s->alarm = irq[1];
3745 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
5c1c390f
AZ		 3746
3747 omap_rtc_reset(s);
3748
1eed09cb 3749 iomemtype = cpu_register_io_memory(omap_rtc_readfn,
5c1c390f 3750 omap_rtc_writefn, s);
8da3ff18 3751 cpu_register_physical_memory(base, 0x800, iomemtype);
5c1c390f
AZ		 3752
3753 return s;
3754}
3755
d8f699cb
AZ		 3756/* Multi-channel Buffered Serial Port interfaces */
3757struct omap_mcbsp_s {
d8f699cb
AZ		 3758 qemu_irq txirq;
3759 qemu_irq rxirq;
3760 qemu_irq txdrq;
3761 qemu_irq rxdrq;
3762
3763 uint16_t spcr[2];
3764 uint16_t rcr[2];
3765 uint16_t xcr[2];
3766 uint16_t srgr[2];
3767 uint16_t mcr[2];
3768 uint16_t pcr;
3769 uint16_t rcer[8];
3770 uint16_t xcer[8];
3771 int tx_rate;
3772 int rx_rate;
3773 int tx_req;
73560bc8 3774 int rx_req;
d8f699cb 3775
bc24a225 3776 I2SCodec *codec;
73560bc8
AZ		 3777 QEMUTimer *source_timer;
3778 QEMUTimer *sink_timer;
d8f699cb
AZ		 3779};
3780
3781static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
3782{
3783 int irq;
3784
3785 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
3786 case 0:
3787 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
3788 break;
3789 case 3:
3790 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
3791 break;
3792 default:
3793 irq = 0;
3794 break;
3795 }
3796
106627d0
AZ		 3797 if (irq)
3798 qemu_irq_pulse(s->rxirq);
d8f699cb
AZ		 3799
3800 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
3801 case 0:
3802 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
3803 break;
3804 case 3:
3805 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
3806 break;
3807 default:
3808 irq = 0;
3809 break;
3810 }
3811
106627d0
AZ		 3812 if (irq)
3813 qemu_irq_pulse(s->txirq);
d8f699cb
AZ		 3814}
3815
73560bc8 3816static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
d8f699cb 3817{
73560bc8
AZ		 3818 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3819 s->spcr[0] |= 1 << 2; /* RFULL */
3820 s->spcr[0] |= 1 << 1; /* RRDY */
3821 qemu_irq_raise(s->rxdrq);
3822 omap_mcbsp_intr_update(s);
d8f699cb
AZ		 3823}
3824
73560bc8 3825static void omap_mcbsp_source_tick(void *opaque)
d8f699cb 3826{
73560bc8
AZ		 3827 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3828 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3829
3830 if (!s->rx_rate)
d8f699cb 3831 return;
73560bc8
AZ		 3832 if (s->rx_req)
3833 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
d8f699cb 3834
73560bc8 3835 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
d8f699cb 3836
73560bc8 3837 omap_mcbsp_rx_newdata(s);
6ee093c9
JQ		 3838 qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) +
3839 get_ticks_per_sec());
d8f699cb
AZ		 3840}
3841
3842static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3843{
73560bc8
AZ		 3844 if (!s->codec || !s->codec->rts)
3845 omap_mcbsp_source_tick(s);
3846 else if (s->codec->in.len) {
3847 s->rx_req = s->codec->in.len;
3848 omap_mcbsp_rx_newdata(s);
d8f699cb 3849 }
d8f699cb
AZ		 3850}
3851
3852static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
73560bc8
AZ		 3853{
3854 qemu_del_timer(s->source_timer);
3855}
3856
3857static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
d8f699cb
AZ		 3858{
3859 s->spcr[0] &= ~(1 << 1); /* RRDY */
3860 qemu_irq_lower(s->rxdrq);
3861 omap_mcbsp_intr_update(s);
3862}
3863
73560bc8
AZ		 3864static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3865{
3866 s->spcr[1] |= 1 << 1; /* XRDY */
3867 qemu_irq_raise(s->txdrq);
3868 omap_mcbsp_intr_update(s);
3869}
3870
3871static void omap_mcbsp_sink_tick(void *opaque)
d8f699cb 3872{
73560bc8
AZ		 3873 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3874 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3875
3876 if (!s->tx_rate)
d8f699cb 3877 return;
73560bc8
AZ		 3878 if (s->tx_req)
3879 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
3880
3881 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3882
3883 omap_mcbsp_tx_newdata(s);
6ee093c9
JQ		 3884 qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) +
3885 get_ticks_per_sec());
73560bc8
AZ		 3886}
3887
3888static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3889{
3890 if (!s->codec || !s->codec->cts)
3891 omap_mcbsp_sink_tick(s);
3892 else if (s->codec->out.size) {
3893 s->tx_req = s->codec->out.size;
3894 omap_mcbsp_tx_newdata(s);
3895 }
3896}
3897
3898static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3899{
3900 s->spcr[1] &= ~(1 << 1); /* XRDY */
3901 qemu_irq_lower(s->txdrq);
3902 omap_mcbsp_intr_update(s);
3903 if (s->codec && s->codec->cts)
3904 s->codec->tx_swallow(s->codec->opaque);
d8f699cb
AZ		 3905}
3906
3907static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3908{
73560bc8
AZ		 3909 s->tx_req = 0;
3910 omap_mcbsp_tx_done(s);
3911 qemu_del_timer(s->sink_timer);
3912}
3913
3914static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3915{
3916 int prev_rx_rate, prev_tx_rate;
3917 int rx_rate = 0, tx_rate = 0;
3918 int cpu_rate = 1500000; /* XXX */
3919
3920 /* TODO: check CLKSTP bit */
3921 if (s->spcr[1] & (1 << 6)) { /* GRST */
3922 if (s->spcr[0] & (1 << 0)) { /* RRST */
3923 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3924 (s->pcr & (1 << 8))) { /* CLKRM */
3925 if (~s->pcr & (1 << 7)) /* SCLKME */
3926 rx_rate = cpu_rate /
3927 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3928 } else
3929 if (s->codec)
3930 rx_rate = s->codec->rx_rate;
3931 }
3932
3933 if (s->spcr[1] & (1 << 0)) { /* XRST */
3934 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3935 (s->pcr & (1 << 9))) { /* CLKXM */
3936 if (~s->pcr & (1 << 7)) /* SCLKME */
3937 tx_rate = cpu_rate /
3938 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3939 } else
3940 if (s->codec)
3941 tx_rate = s->codec->tx_rate;
3942 }
3943 }
3944 prev_tx_rate = s->tx_rate;
3945 prev_rx_rate = s->rx_rate;
3946 s->tx_rate = tx_rate;
3947 s->rx_rate = rx_rate;
3948
3949 if (s->codec)
3950 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3951
3952 if (!prev_tx_rate && tx_rate)
3953 omap_mcbsp_tx_start(s);
3954 else if (s->tx_rate && !tx_rate)
3955 omap_mcbsp_tx_stop(s);
3956
3957 if (!prev_rx_rate && rx_rate)
3958 omap_mcbsp_rx_start(s);
3959 else if (prev_tx_rate && !tx_rate)
3960 omap_mcbsp_rx_stop(s);
d8f699cb
AZ		 3961}
3962
c227f099 3963static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
d8f699cb
AZ		 3964{
3965 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3966 int offset = addr & OMAP_MPUI_REG_MASK;
3967 uint16_t ret;
3968
3969 switch (offset) {
3970 case 0x00: /* DRR2 */
3971 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3972 return 0x0000;
3973 /* Fall through. */
3974 case 0x02: /* DRR1 */
73560bc8 3975 if (s->rx_req < 2) {
d8f699cb 3976 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
73560bc8 3977 omap_mcbsp_rx_done(s);
d8f699cb 3978 } else {
73560bc8
AZ		 3979 s->tx_req -= 2;
3980 if (s->codec && s->codec->in.len >= 2) {
3981 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3982 ret |= s->codec->in.fifo[s->codec->in.start ++];
3983 s->codec->in.len -= 2;
3984 } else
3985 ret = 0x0000;
3986 if (!s->tx_req)
3987 omap_mcbsp_rx_done(s);
d8f699cb
AZ		 3988 return ret;
3989 }
3990 return 0x0000;
3991
3992 case 0x04: /* DXR2 */
3993 case 0x06: /* DXR1 */
3994 return 0x0000;
3995
3996 case 0x08: /* SPCR2 */
3997 return s->spcr[1];
3998 case 0x0a: /* SPCR1 */
3999 return s->spcr[0];
4000 case 0x0c: /* RCR2 */
4001 return s->rcr[1];
4002 case 0x0e: /* RCR1 */
4003 return s->rcr[0];
4004 case 0x10: /* XCR2 */
4005 return s->xcr[1];
4006 case 0x12: /* XCR1 */
4007 return s->xcr[0];
4008 case 0x14: /* SRGR2 */
4009 return s->srgr[1];
4010 case 0x16: /* SRGR1 */
4011 return s->srgr[0];
4012 case 0x18: /* MCR2 */
4013 return s->mcr[1];
4014 case 0x1a: /* MCR1 */
4015 return s->mcr[0];
4016 case 0x1c: /* RCERA */
4017 return s->rcer[0];
4018 case 0x1e: /* RCERB */
4019 return s->rcer[1];
4020 case 0x20: /* XCERA */
4021 return s->xcer[0];
4022 case 0x22: /* XCERB */
4023 return s->xcer[1];
4024 case 0x24: /* PCR0 */
4025 return s->pcr;
4026 case 0x26: /* RCERC */
4027 return s->rcer[2];
4028 case 0x28: /* RCERD */
4029 return s->rcer[3];
4030 case 0x2a: /* XCERC */
4031 return s->xcer[2];
4032 case 0x2c: /* XCERD */
4033 return s->xcer[3];
4034 case 0x2e: /* RCERE */
4035 return s->rcer[4];
4036 case 0x30: /* RCERF */
4037 return s->rcer[5];
4038 case 0x32: /* XCERE */
4039 return s->xcer[4];
4040 case 0x34: /* XCERF */
4041 return s->xcer[5];
4042 case 0x36: /* RCERG */
4043 return s->rcer[6];
4044 case 0x38: /* RCERH */
4045 return s->rcer[7];
4046 case 0x3a: /* XCERG */
4047 return s->xcer[6];
4048 case 0x3c: /* XCERH */
4049 return s->xcer[7];
4050 }
4051
4052 OMAP_BAD_REG(addr);
4053 return 0;
4054}
4055
c227f099 4056static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
d8f699cb
AZ		 4057 uint32_t value)
4058{
4059 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4060 int offset = addr & OMAP_MPUI_REG_MASK;
4061
4062 switch (offset) {
4063 case 0x00: /* DRR2 */
4064 case 0x02: /* DRR1 */
4065 OMAP_RO_REG(addr);
4066 return;
4067
4068 case 0x04: /* DXR2 */
4069 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4070 return;
4071 /* Fall through. */
4072 case 0x06: /* DXR1 */
73560bc8
AZ		 4073 if (s->tx_req > 1) {
4074 s->tx_req -= 2;
4075 if (s->codec && s->codec->cts) {
d8f699cb
AZ		 4076 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
4077 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
d8f699cb 4078 }
73560bc8
AZ		 4079 if (s->tx_req < 2)
4080 omap_mcbsp_tx_done(s);
d8f699cb
AZ		 4081 } else
4082 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4083 return;
4084
4085 case 0x08: /* SPCR2 */
4086 s->spcr[1] &= 0x0002;
4087 s->spcr[1] |= 0x03f9 & value;
4088 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
73560bc8 4089 if (~value & 1) /* XRST */
d8f699cb 4090 s->spcr[1] &= ~6;
d8f699cb
AZ		 4091 omap_mcbsp_req_update(s);
4092 return;
4093 case 0x0a: /* SPCR1 */
4094 s->spcr[0] &= 0x0006;
4095 s->spcr[0] |= 0xf8f9 & value;
4096 if (value & (1 << 15)) /* DLB */
4097 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
4098 if (~value & 1) { /* RRST */
4099 s->spcr[0] &= ~6;
73560bc8
AZ		 4100 s->rx_req = 0;
4101 omap_mcbsp_rx_done(s);
d8f699cb 4102 }
d8f699cb
AZ		 4103 omap_mcbsp_req_update(s);
4104 return;
4105
4106 case 0x0c: /* RCR2 */
4107 s->rcr[1] = value & 0xffff;
4108 return;
4109 case 0x0e: /* RCR1 */
4110 s->rcr[0] = value & 0x7fe0;
4111 return;
4112 case 0x10: /* XCR2 */
4113 s->xcr[1] = value & 0xffff;
4114 return;
4115 case 0x12: /* XCR1 */
4116 s->xcr[0] = value & 0x7fe0;
4117 return;
4118 case 0x14: /* SRGR2 */
4119 s->srgr[1] = value & 0xffff;
73560bc8 4120 omap_mcbsp_req_update(s);
d8f699cb
AZ		 4121 return;
4122 case 0x16: /* SRGR1 */
4123 s->srgr[0] = value & 0xffff;
73560bc8 4124 omap_mcbsp_req_update(s);
d8f699cb
AZ		 4125 return;
4126 case 0x18: /* MCR2 */
4127 s->mcr[1] = value & 0x03e3;
4128 if (value & 3) /* XMCM */
4129 printf("%s: Tx channel selection mode enable attempt\n",
4130 __FUNCTION__);
4131 return;
4132 case 0x1a: /* MCR1 */
4133 s->mcr[0] = value & 0x03e1;
4134 if (value & 1) /* RMCM */
4135 printf("%s: Rx channel selection mode enable attempt\n",
4136 __FUNCTION__);
4137 return;
4138 case 0x1c: /* RCERA */
4139 s->rcer[0] = value & 0xffff;
4140 return;
4141 case 0x1e: /* RCERB */
4142 s->rcer[1] = value & 0xffff;
4143 return;
4144 case 0x20: /* XCERA */
4145 s->xcer[0] = value & 0xffff;
4146 return;
4147 case 0x22: /* XCERB */
4148 s->xcer[1] = value & 0xffff;
4149 return;
4150 case 0x24: /* PCR0 */
4151 s->pcr = value & 0x7faf;
4152 return;
4153 case 0x26: /* RCERC */
4154 s->rcer[2] = value & 0xffff;
4155 return;
4156 case 0x28: /* RCERD */
4157 s->rcer[3] = value & 0xffff;
4158 return;
4159 case 0x2a: /* XCERC */
4160 s->xcer[2] = value & 0xffff;
4161 return;
4162 case 0x2c: /* XCERD */
4163 s->xcer[3] = value & 0xffff;
4164 return;
4165 case 0x2e: /* RCERE */
4166 s->rcer[4] = value & 0xffff;
4167 return;
4168 case 0x30: /* RCERF */
4169 s->rcer[5] = value & 0xffff;
4170 return;
4171 case 0x32: /* XCERE */
4172 s->xcer[4] = value & 0xffff;
4173 return;
4174 case 0x34: /* XCERF */
4175 s->xcer[5] = value & 0xffff;
4176 return;
4177 case 0x36: /* RCERG */
4178 s->rcer[6] = value & 0xffff;
4179 return;
4180 case 0x38: /* RCERH */
4181 s->rcer[7] = value & 0xffff;
4182 return;
4183 case 0x3a: /* XCERG */
4184 s->xcer[6] = value & 0xffff;
4185 return;
4186 case 0x3c: /* XCERH */
4187 s->xcer[7] = value & 0xffff;
4188 return;
4189 }
4190
4191 OMAP_BAD_REG(addr);
4192}
4193
c227f099 4194static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
73560bc8
AZ		 4195 uint32_t value)
4196{
4197 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4198 int offset = addr & OMAP_MPUI_REG_MASK;
4199
4200 if (offset == 0x04) { /* DXR */
4201 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4202 return;
4203 if (s->tx_req > 3) {
4204 s->tx_req -= 4;
4205 if (s->codec && s->codec->cts) {
4206 s->codec->out.fifo[s->codec->out.len ++] =
4207 (value >> 24) & 0xff;
4208 s->codec->out.fifo[s->codec->out.len ++] =
4209 (value >> 16) & 0xff;
4210 s->codec->out.fifo[s->codec->out.len ++] =
4211 (value >> 8) & 0xff;
4212 s->codec->out.fifo[s->codec->out.len ++] =
4213 (value >> 0) & 0xff;
4214 }
4215 if (s->tx_req < 4)
4216 omap_mcbsp_tx_done(s);
4217 } else
4218 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4219 return;
4220 }
4221
4222 omap_badwidth_write16(opaque, addr, value);
4223}
4224
d60efc6b 4225static CPUReadMemoryFunc * const omap_mcbsp_readfn[] = {
d8f699cb
AZ		 4226 omap_badwidth_read16,
4227 omap_mcbsp_read,
4228 omap_badwidth_read16,
4229};
4230
d60efc6b 4231static CPUWriteMemoryFunc * const omap_mcbsp_writefn[] = {
d8f699cb 4232 omap_badwidth_write16,
73560bc8
AZ		 4233 omap_mcbsp_writeh,
4234 omap_mcbsp_writew,
d8f699cb
AZ		 4235};
4236
4237static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
4238{
4239 memset(&s->spcr, 0, sizeof(s->spcr));
4240 memset(&s->rcr, 0, sizeof(s->rcr));
4241 memset(&s->xcr, 0, sizeof(s->xcr));
4242 s->srgr[0] = 0x0001;
4243 s->srgr[1] = 0x2000;
4244 memset(&s->mcr, 0, sizeof(s->mcr));
4245 memset(&s->pcr, 0, sizeof(s->pcr));
4246 memset(&s->rcer, 0, sizeof(s->rcer));
4247 memset(&s->xcer, 0, sizeof(s->xcer));
4248 s->tx_req = 0;
73560bc8 4249 s->rx_req = 0;
d8f699cb
AZ		 4250 s->tx_rate = 0;
4251 s->rx_rate = 0;
73560bc8
AZ		 4252 qemu_del_timer(s->source_timer);
4253 qemu_del_timer(s->sink_timer);
d8f699cb
AZ		 4254}
4255
c227f099 4256struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
d8f699cb
AZ		 4257 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
4258{
4259 int iomemtype;
4260 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
4261 qemu_mallocz(sizeof(struct omap_mcbsp_s));
4262
d8f699cb
AZ		 4263 s->txirq = irq[0];
4264 s->rxirq = irq[1];
4265 s->txdrq = dma[0];
4266 s->rxdrq = dma[1];
73560bc8
AZ		 4267 s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s);
4268 s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
d8f699cb
AZ		 4269 omap_mcbsp_reset(s);
4270
1eed09cb 4271 iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
d8f699cb 4272 omap_mcbsp_writefn, s);
8da3ff18 4273 cpu_register_physical_memory(base, 0x800, iomemtype);
d8f699cb
AZ		 4274
4275 return s;
4276}
4277
9596ebb7 4278static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
d8f699cb
AZ		 4279{
4280 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4281
73560bc8
AZ		 4282 if (s->rx_rate) {
4283 s->rx_req = s->codec->in.len;
4284 omap_mcbsp_rx_newdata(s);
4285 }
d8f699cb
AZ		 4286}
4287
9596ebb7 4288static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
d8f699cb
AZ		 4289{
4290 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4291
73560bc8
AZ		 4292 if (s->tx_rate) {
4293 s->tx_req = s->codec->out.size;
4294 omap_mcbsp_tx_newdata(s);
4295 }
d8f699cb
AZ		 4296}
4297
bc24a225 4298void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
d8f699cb
AZ		 4299{
4300 s->codec = slave;
4301 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
4302 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
4303}
4304
f9d43072
AZ		 4305/* LED Pulse Generators */
4306struct omap_lpg_s {
f9d43072
AZ		 4307 QEMUTimer *tm;
4308
4309 uint8_t control;
4310 uint8_t power;
4311 int64_t on;
4312 int64_t period;
4313 int clk;
4314 int cycle;
4315};
4316
4317static void omap_lpg_tick(void *opaque)
4318{
4319 struct omap_lpg_s *s = opaque;
4320
4321 if (s->cycle)
4322 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on);
4323 else
4324 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on);
4325
4326 s->cycle = !s->cycle;
4327 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
4328}
4329
4330static void omap_lpg_update(struct omap_lpg_s *s)
4331{
4332 int64_t on, period = 1, ticks = 1000;
4333 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
4334
4335 if (~s->control & (1 << 6)) /* LPGRES */
4336 on = 0;
4337 else if (s->control & (1 << 7)) /* PERM_ON */
4338 on = period;
4339 else {
4340 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
4341 256 / 32);
4342 on = (s->clk && s->power) ? muldiv64(ticks,
4343 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
4344 }
4345
4346 qemu_del_timer(s->tm);
4347 if (on == period && s->on < s->period)
4348 printf("%s: LED is on\n", __FUNCTION__);
4349 else if (on == 0 && s->on)
4350 printf("%s: LED is off\n", __FUNCTION__);
4351 else if (on && (on != s->on || period != s->period)) {
4352 s->cycle = 0;
4353 s->on = on;
4354 s->period = period;
4355 omap_lpg_tick(s);
4356 return;
4357 }
4358
4359 s->on = on;
4360 s->period = period;
4361}
4362
4363static void omap_lpg_reset(struct omap_lpg_s *s)
4364{
4365 s->control = 0x00;
4366 s->power = 0x00;
4367 s->clk = 1;
4368 omap_lpg_update(s);
4369}
4370
c227f099 4371static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
f9d43072
AZ		 4372{
4373 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4374 int offset = addr & OMAP_MPUI_REG_MASK;
4375
4376 switch (offset) {
4377 case 0x00: /* LCR */
4378 return s->control;
4379
4380 case 0x04: /* PMR */
4381 return s->power;
4382 }
4383
4384 OMAP_BAD_REG(addr);
4385 return 0;
4386}
4387
c227f099 4388static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
f9d43072
AZ		 4389 uint32_t value)
4390{
4391 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4392 int offset = addr & OMAP_MPUI_REG_MASK;
4393
4394 switch (offset) {
4395 case 0x00: /* LCR */
4396 if (~value & (1 << 6)) /* LPGRES */
4397 omap_lpg_reset(s);
4398 s->control = value & 0xff;
4399 omap_lpg_update(s);
4400 return;
4401
4402 case 0x04: /* PMR */
4403 s->power = value & 0x01;
4404 omap_lpg_update(s);
4405 return;
4406
4407 default:
4408 OMAP_BAD_REG(addr);
4409 return;
4410 }
4411}
4412
d60efc6b 4413static CPUReadMemoryFunc * const omap_lpg_readfn[] = {
f9d43072
AZ		 4414 omap_lpg_read,
4415 omap_badwidth_read8,
4416 omap_badwidth_read8,
4417};
4418
d60efc6b 4419static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
f9d43072
AZ		 4420 omap_lpg_write,
4421 omap_badwidth_write8,
4422 omap_badwidth_write8,
4423};
4424
4425static void omap_lpg_clk_update(void *opaque, int line, int on)
4426{
4427 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4428
4429 s->clk = on;
4430 omap_lpg_update(s);
4431}
4432
c227f099 4433struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
f9d43072
AZ		 4434{
4435 int iomemtype;
4436 struct omap_lpg_s *s = (struct omap_lpg_s *)
4437 qemu_mallocz(sizeof(struct omap_lpg_s));
4438
f9d43072
AZ		 4439 s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
4440
4441 omap_lpg_reset(s);
4442
1eed09cb 4443 iomemtype = cpu_register_io_memory(omap_lpg_readfn,
f9d43072 4444 omap_lpg_writefn, s);
8da3ff18 4445 cpu_register_physical_memory(base, 0x800, iomemtype);
f9d43072
AZ		 4446
4447 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
4448
4449 return s;
4450}
4451
4452/* MPUI Peripheral Bridge configuration */
c227f099 4453static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
f9d43072
AZ		 4454{
4455 if (addr == OMAP_MPUI_BASE) /* CMR */
4456 return 0xfe4d;
4457
4458 OMAP_BAD_REG(addr);
4459 return 0;
4460}
4461
d60efc6b 4462static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = {
f9d43072
AZ		 4463 omap_badwidth_read16,
4464 omap_mpui_io_read,
4465 omap_badwidth_read16,
4466};
4467
d60efc6b 4468static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
f9d43072
AZ		 4469 omap_badwidth_write16,
4470 omap_badwidth_write16,
4471 omap_badwidth_write16,
4472};
4473
4474static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
4475{
1eed09cb 4476 int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
f9d43072
AZ		 4477 omap_mpui_io_writefn, mpu);
4478 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
4479}
4480
c3d2689d 4481/* General chip reset */
827df9f3 4482static void omap1_mpu_reset(void *opaque)
c3d2689d
AZ		 4483{
4484 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4485
c3d2689d
AZ		 4486 omap_inth_reset(mpu->ih[0]);
4487 omap_inth_reset(mpu->ih[1]);
4488 omap_dma_reset(mpu->dma);
4489 omap_mpu_timer_reset(mpu->timer[0]);
4490 omap_mpu_timer_reset(mpu->timer[1]);
4491 omap_mpu_timer_reset(mpu->timer[2]);
4492 omap_wd_timer_reset(mpu->wdt);
4493 omap_os_timer_reset(mpu->os_timer);
4494 omap_lcdc_reset(mpu->lcd);
4495 omap_ulpd_pm_reset(mpu);
4496 omap_pin_cfg_reset(mpu);
4497 omap_mpui_reset(mpu);
4498 omap_tipb_bridge_reset(mpu->private_tipb);
4499 omap_tipb_bridge_reset(mpu->public_tipb);
4500 omap_dpll_reset(&mpu->dpll[0]);
4501 omap_dpll_reset(&mpu->dpll[1]);
4502 omap_dpll_reset(&mpu->dpll[2]);
d951f6ff
AZ		 4503 omap_uart_reset(mpu->uart[0]);
4504 omap_uart_reset(mpu->uart[1]);
4505 omap_uart_reset(mpu->uart[2]);
b30bb3a2 4506 omap_mmc_reset(mpu->mmc);
fe71e81a 4507 omap_mpuio_reset(mpu->mpuio);
64330148 4508 omap_gpio_reset(mpu->gpio);
d951f6ff 4509 omap_uwire_reset(mpu->microwire);
66450b15 4510 omap_pwl_reset(mpu);
4a2c8ac2 4511 omap_pwt_reset(mpu);
827df9f3 4512 omap_i2c_reset(mpu->i2c[0]);
5c1c390f 4513 omap_rtc_reset(mpu->rtc);
d8f699cb
AZ		 4514 omap_mcbsp_reset(mpu->mcbsp1);
4515 omap_mcbsp_reset(mpu->mcbsp2);
4516 omap_mcbsp_reset(mpu->mcbsp3);
f9d43072
AZ		 4517 omap_lpg_reset(mpu->led[0]);
4518 omap_lpg_reset(mpu->led[1]);
8ef6367e 4519 omap_clkm_reset(mpu);
c3d2689d
AZ		 4520 cpu_reset(mpu->env);
4521}
4522
cf965d24 4523static const struct omap_map_s {
c227f099
AL		 4524 target_phys_addr_t phys_dsp;
4525 target_phys_addr_t phys_mpu;
cf965d24
AZ		 4526 uint32_t size;
4527 const char *name;
4528} omap15xx_dsp_mm[] = {
4529 /* Strobe 0 */
4530 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
4531 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
4532 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
4533 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
4534 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
4535 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
4536 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
4537 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
4538 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
4539 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
4540 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
4541 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
4542 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
4543 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
4544 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
4545 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
4546 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
4547 /* Strobe 1 */
4548 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
4549
4550 { 0 }
4551};
4552
4553static void omap_setup_dsp_mapping(const struct omap_map_s *map)
4554{
4555 int io;
4556
4557 for (; map->phys_dsp; map ++) {
4558 io = cpu_get_physical_page_desc(map->phys_mpu);
4559
4560 cpu_register_physical_memory(map->phys_dsp, map->size, io);
4561 }
4562}
4563
827df9f3 4564void omap_mpu_wakeup(void *opaque, int irq, int req)
c3d2689d
AZ		 4565{
4566 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4567
fe71e81a
AZ		 4568 if (mpu->env->halted)
4569 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
c3d2689d
AZ		 4570}
4571
827df9f3 4572static const struct dma_irq_map omap1_dma_irq_map[] = {
089b7c0a
AZ		 4573 { 0, OMAP_INT_DMA_CH0_6 },
4574 { 0, OMAP_INT_DMA_CH1_7 },
4575 { 0, OMAP_INT_DMA_CH2_8 },
4576 { 0, OMAP_INT_DMA_CH3 },
4577 { 0, OMAP_INT_DMA_CH4 },
4578 { 0, OMAP_INT_DMA_CH5 },
4579 { 1, OMAP_INT_1610_DMA_CH6 },
4580 { 1, OMAP_INT_1610_DMA_CH7 },
4581 { 1, OMAP_INT_1610_DMA_CH8 },
4582 { 1, OMAP_INT_1610_DMA_CH9 },
4583 { 1, OMAP_INT_1610_DMA_CH10 },
4584 { 1, OMAP_INT_1610_DMA_CH11 },
4585 { 1, OMAP_INT_1610_DMA_CH12 },
4586 { 1, OMAP_INT_1610_DMA_CH13 },
4587 { 1, OMAP_INT_1610_DMA_CH14 },
4588 { 1, OMAP_INT_1610_DMA_CH15 }
4589};
4590
b4e3104b
AZ		 4591/* DMA ports for OMAP1 */
4592static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
c227f099 4593 target_phys_addr_t addr)
b4e3104b
AZ		 4594{
4595 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
4596}
4597
4598static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
c227f099 4599 target_phys_addr_t addr)
b4e3104b
AZ		 4600{
4601 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
4602}
4603
4604static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
c227f099 4605 target_phys_addr_t addr)
b4e3104b
AZ		 4606{
4607 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
4608}
4609
4610static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
c227f099 4611 target_phys_addr_t addr)
b4e3104b
AZ		 4612{
4613 return addr >= 0xfffb0000 && addr < 0xffff0000;
4614}
4615
4616static int omap_validate_local_addr(struct omap_mpu_state_s *s,
c227f099 4617 target_phys_addr_t addr)
b4e3104b
AZ		 4618{
4619 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
4620}
4621
4622static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
c227f099 4623 target_phys_addr_t addr)
b4e3104b
AZ		 4624{
4625 return addr >= 0xe1010000 && addr < 0xe1020004;
4626}
4627
c3d2689d 4628struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
3023f332 4629 const char *core)
c3d2689d 4630{
089b7c0a 4631 int i;
c3d2689d
AZ		 4632 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4633 qemu_mallocz(sizeof(struct omap_mpu_state_s));
c227f099 4634 ram_addr_t imif_base, emiff_base;
106627d0 4635 qemu_irq *cpu_irq;
089b7c0a 4636 qemu_irq dma_irqs[6];
751c6a17 4637 DriveInfo *dinfo;
106627d0 4638
aaed909a
FB		 4639 if (!core)
4640 core = "ti925t";
c3d2689d
AZ		 4641
4642 /* Core */
4643 s->mpu_model = omap310;
aaed909a
FB		 4644 s->env = cpu_init(core);
4645 if (!s->env) {
4646 fprintf(stderr, "Unable to find CPU definition\n");
4647 exit(1);
4648 }
c3d2689d
AZ		 4649 s->sdram_size = sdram_size;
4650 s->sram_size = OMAP15XX_SRAM_SIZE;
4651
fe71e81a
AZ		 4652 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4653
c3d2689d
AZ		 4654 /* Clocks */
4655 omap_clk_init(s);
4656
4657 /* Memory-mapped stuff */
4658 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
4659 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4660 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
4661 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4662
4663 omap_clkm_init(0xfffece00, 0xe1008000, s);
4664
106627d0 4665 cpu_irq = arm_pic_init_cpu(s->env);
827df9f3 4666 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
106627d0 4667 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
c3d2689d 4668 omap_findclk(s, "arminth_ck"));
827df9f3 4669 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
106627d0 4670 s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL,
c3d2689d 4671 omap_findclk(s, "arminth_ck"));
c3d2689d 4672
089b7c0a 4673 for (i = 0; i < 6; i ++)
827df9f3
AZ		 4674 dma_irqs[i] =
4675 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
089b7c0a
AZ		 4676 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
4677 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
4678
c3d2689d
AZ		 4679 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
4680 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
4681 s->port[imif ].addr_valid = omap_validate_imif_addr;
4682 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
4683 s->port[local ].addr_valid = omap_validate_local_addr;
4684 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
4685
afbb5194
AZ		 4686 /* Register SDRAM and SRAM DMA ports for fast transfers. */
4687 soc_dma_port_add_mem_ram(s->dma,
4688 emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
4689 soc_dma_port_add_mem_ram(s->dma,
4690 imif_base, OMAP_IMIF_BASE, s->sram_size);
4691
c3d2689d
AZ		 4692 s->timer[0] = omap_mpu_timer_init(0xfffec500,
4693 s->irq[0][OMAP_INT_TIMER1],
4694 omap_findclk(s, "mputim_ck"));
4695 s->timer[1] = omap_mpu_timer_init(0xfffec600,
4696 s->irq[0][OMAP_INT_TIMER2],
4697 omap_findclk(s, "mputim_ck"));
4698 s->timer[2] = omap_mpu_timer_init(0xfffec700,
4699 s->irq[0][OMAP_INT_TIMER3],
4700 omap_findclk(s, "mputim_ck"));
4701
4702 s->wdt = omap_wd_timer_init(0xfffec800,
4703 s->irq[0][OMAP_INT_WD_TIMER],
4704 omap_findclk(s, "armwdt_ck"));
4705
4706 s->os_timer = omap_os_timer_init(0xfffb9000,
4707 s->irq[1][OMAP_INT_OS_TIMER],
4708 omap_findclk(s, "clk32-kHz"));
4709
4710 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
3023f332 4711 omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
c3d2689d
AZ		 4712 omap_findclk(s, "lcd_ck"));
4713
4714 omap_ulpd_pm_init(0xfffe0800, s);
4715 omap_pin_cfg_init(0xfffe1000, s);
4716 omap_id_init(s);
4717
4718 omap_mpui_init(0xfffec900, s);
4719
4720 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
4721 s->irq[0][OMAP_INT_BRIDGE_PRIV],
4722 omap_findclk(s, "tipb_ck"));
4723 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
4724 s->irq[0][OMAP_INT_BRIDGE_PUB],
4725 omap_findclk(s, "tipb_ck"));
4726
4727 omap_tcmi_init(0xfffecc00, s);
4728
d951f6ff 4729 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
c3d2689d 4730 omap_findclk(s, "uart1_ck"),
827df9f3
AZ		 4731 omap_findclk(s, "uart1_ck"),
4732 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
c3d2689d 4733 serial_hds[0]);
d951f6ff 4734 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
c3d2689d 4735 omap_findclk(s, "uart2_ck"),
827df9f3
AZ		 4736 omap_findclk(s, "uart2_ck"),
4737 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
b9d38e95 4738 serial_hds[0] ? serial_hds[1] : NULL);
13643323 4739 s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3],
c3d2689d 4740 omap_findclk(s, "uart3_ck"),
827df9f3
AZ		 4741 omap_findclk(s, "uart3_ck"),
4742 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
b9d38e95 4743 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
c3d2689d
AZ		 4744
4745 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
4746 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
4747 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
4748
751c6a17
GH		 4749 dinfo = drive_get(IF_SD, 0, 0);
4750 if (!dinfo) {
e4bcb14c
TS		 4751 fprintf(stderr, "qemu: missing SecureDigital device\n");
4752 exit(1);
4753 }
751c6a17 4754 s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
9d413d1d
AZ		 4755 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
4756 omap_findclk(s, "mmc_ck"));
b30bb3a2 4757
fe71e81a
AZ		 4758 s->mpuio = omap_mpuio_init(0xfffb5000,
4759 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
4760 s->wakeup, omap_findclk(s, "clk32-kHz"));
4761
3efda49d 4762 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1],
66450b15 4763 omap_findclk(s, "arm_gpio_ck"));
64330148 4764
d951f6ff
AZ		 4765 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
4766 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4767
d8f699cb
AZ		 4768 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
4769 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
66450b15 4770
827df9f3 4771 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
4a2c8ac2
AZ		 4772 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
4773
5c1c390f
AZ		 4774 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
4775 omap_findclk(s, "clk32-kHz"));
02645926 4776
d8f699cb
AZ		 4777 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
4778 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4779 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
4780 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4781 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
4782 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4783
f9d43072
AZ		 4784 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
4785 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
4786
02645926 4787 /* Register mappings not currenlty implemented:
02645926
AZ		 4788 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4789 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4790 * USB W2FC fffb4000 - fffb47ff
4791 * Camera Interface fffb6800 - fffb6fff
02645926
AZ		 4792 * USB Host fffba000 - fffba7ff
4793 * FAC fffba800 - fffbafff
4794 * HDQ/1-Wire fffbc000 - fffbc7ff
b854bc19 4795 * TIPB switches fffbc800 - fffbcfff
02645926
AZ		 4796 * Mailbox fffcf000 - fffcf7ff
4797 * Local bus IF fffec100 - fffec1ff
4798 * Local bus MMU fffec200 - fffec2ff
4799 * DSP MMU fffed200 - fffed2ff
4800 */
4801
cf965d24 4802 omap_setup_dsp_mapping(omap15xx_dsp_mm);
f9d43072 4803 omap_setup_mpui_io(s);
cf965d24 4804
a08d4367 4805 qemu_register_reset(omap1_mpu_reset, s);
c3d2689d
AZ		 4806
4807 return s;
4808}
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