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hw/omap2.c : separate tap module(Test-Chip-level)
[mirror_qemu.git] / hw / omap2.c
CommitLineData
827df9f3
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
827df9f3 19 */
666daa68
MA		 20
21#include "blockdev.h"
827df9f3
AZ		 22#include "hw.h"
23#include "arm-misc.h"
24#include "omap.h"
25#include "sysemu.h"
26#include "qemu-timer.h"
27#include "qemu-char.h"
28#include "flash.h"
afbb5194 29#include "soc_dma.h"
99570a40 30#include "audio/audio.h"
827df9f3 31
99570a40
AZ		 32/* Enhanced Audio Controller (CODEC only) */
33struct omap_eac_s {
99570a40
AZ		 34 qemu_irq irq;
35
36 uint16_t sysconfig;
37 uint8_t config[4];
38 uint8_t control;
39 uint8_t address;
40 uint16_t data;
41 uint8_t vtol;
42 uint8_t vtsl;
43 uint16_t mixer;
44 uint16_t gain[4];
45 uint8_t att;
46 uint16_t max[7];
47
48 struct {
49 qemu_irq txdrq;
50 qemu_irq rxdrq;
51 uint32_t (*txrx)(void *opaque, uint32_t, int);
52 void *opaque;
53
54#define EAC_BUF_LEN 1024
55 uint32_t rxbuf[EAC_BUF_LEN];
ab17b46d 56 int rxoff;
99570a40
AZ		 57 int rxlen;
58 int rxavail;
59 uint32_t txbuf[EAC_BUF_LEN];
60 int txlen;
61 int txavail;
62
63 int enable;
64 int rate;
65
66 uint16_t config[4];
67
68 /* These need to be moved to the actual codec */
69 QEMUSoundCard card;
70 SWVoiceIn *in_voice;
71 SWVoiceOut *out_voice;
72 int hw_enable;
73 } codec;
74
75 struct {
76 uint8_t control;
77 uint16_t config;
78 } modem, bt;
79};
80
81static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
82{
83 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
84}
85
86static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
87{
ab17b46d 88 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
99570a40
AZ		 89 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
90}
91
92static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
93{
94 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
95 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
96}
97
98static inline void omap_eac_in_refill(struct omap_eac_s *s)
99{
ab17b46d
AZ		 100 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
101 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
102 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
103 int recv = 1;
104 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
105
106 left -= leftwrap;
107 start = 0;
108 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
109 leftwrap)) > 0) { /* Be defensive */
110 start += recv;
111 leftwrap -= recv;
112 }
113 if (recv <= 0)
114 s->codec.rxavail = 0;
115 else
116 s->codec.rxavail -= start >> 2;
117 s->codec.rxlen += start >> 2;
118
119 if (recv > 0 && left > 0) {
120 start = 0;
121 while (left && (recv = AUD_read(s->codec.in_voice,
122 (uint8_t *) s->codec.rxbuf + start,
123 left)) > 0) { /* Be defensive */
124 start += recv;
125 left -= recv;
126 }
127 if (recv <= 0)
128 s->codec.rxavail = 0;
129 else
130 s->codec.rxavail -= start >> 2;
131 s->codec.rxlen += start >> 2;
132 }
99570a40
AZ		 133}
134
135static inline void omap_eac_out_empty(struct omap_eac_s *s)
136{
ab17b46d
AZ		 137 int left = s->codec.txlen << 2;
138 int start = 0;
139 int sent = 1;
140
141 while (left && (sent = AUD_write(s->codec.out_voice,
142 (uint8_t *) s->codec.txbuf + start,
143 left)) > 0) { /* Be defensive */
144 start += sent;
145 left -= sent;
146 }
99570a40 147
ab17b46d
AZ		 148 if (!sent) {
149 s->codec.txavail = 0;
150 omap_eac_out_dmarequest_update(s);
151 }
99570a40 152
ab17b46d
AZ		 153 if (start)
154 s->codec.txlen = 0;
99570a40
AZ		 155}
156
157static void omap_eac_in_cb(void *opaque, int avail_b)
158{
159 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
160
161 s->codec.rxavail = avail_b >> 2;
ab17b46d 162 omap_eac_in_refill(s);
99570a40 163 /* TODO: possibly discard current buffer if overrun */
ab17b46d 164 omap_eac_in_dmarequest_update(s);
99570a40
AZ		 165}
166
167static void omap_eac_out_cb(void *opaque, int free_b)
168{
169 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
170
171 s->codec.txavail = free_b >> 2;
ab17b46d
AZ		 172 if (s->codec.txlen)
173 omap_eac_out_empty(s);
174 else
175 omap_eac_out_dmarequest_update(s);
99570a40
AZ		 176}
177
178static void omap_eac_enable_update(struct omap_eac_s *s)
179{
180 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
181 (s->codec.config[1] & 2) && /* AUDEN */
182 s->codec.hw_enable;
183}
184
185static const int omap_eac_fsint[4] = {
186 8000,
187 11025,
188 22050,
189 44100,
190};
191
192static const int omap_eac_fsint2[8] = {
193 8000,
194 11025,
195 22050,
196 44100,
197 48000,
198 0, 0, 0,
199};
200
201static const int omap_eac_fsint3[16] = {
202 8000,
203 11025,
204 16000,
205 22050,
206 24000,
207 32000,
208 44100,
209 48000,
210 0, 0, 0, 0, 0, 0, 0, 0,
211};
212
213static void omap_eac_rate_update(struct omap_eac_s *s)
214{
215 int fsint[3];
216
217 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
218 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
219 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
220 if (fsint[2] < 0xf)
221 s->codec.rate = omap_eac_fsint3[fsint[2]];
222 else if (fsint[1] < 0x7)
223 s->codec.rate = omap_eac_fsint2[fsint[1]];
224 else
225 s->codec.rate = omap_eac_fsint[fsint[0]];
226}
227
228static void omap_eac_volume_update(struct omap_eac_s *s)
229{
230 /* TODO */
231}
232
233static void omap_eac_format_update(struct omap_eac_s *s)
234{
1ea879e5 235 struct audsettings fmt;
99570a40 236
ab17b46d
AZ		 237 /* The hardware buffers at most one sample */
238 if (s->codec.rxlen)
239 s->codec.rxlen = 1;
99570a40
AZ		 240
241 if (s->codec.in_voice) {
242 AUD_set_active_in(s->codec.in_voice, 0);
243 AUD_close_in(&s->codec.card, s->codec.in_voice);
b9d38e95 244 s->codec.in_voice = NULL;
99570a40
AZ		 245 }
246 if (s->codec.out_voice) {
ab17b46d 247 omap_eac_out_empty(s);
99570a40
AZ		 248 AUD_set_active_out(s->codec.out_voice, 0);
249 AUD_close_out(&s->codec.card, s->codec.out_voice);
b9d38e95 250 s->codec.out_voice = NULL;
ab17b46d 251 s->codec.txavail = 0;
99570a40 252 }
ab17b46d
AZ		 253 /* Discard what couldn't be written */
254 s->codec.txlen = 0;
99570a40
AZ		 255
256 omap_eac_enable_update(s);
257 if (!s->codec.enable)
258 return;
259
260 omap_eac_rate_update(s);
261 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
262 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
263 fmt.freq = s->codec.rate;
264 /* TODO: signedness possibly depends on the CODEC hardware - or
265 * does I2S specify it? */
266 /* All register writes are 16 bits so we we store 16-bit samples
267 * in the buffers regardless of AGCFR[B8_16] value. */
268 fmt.fmt = AUD_FMT_U16;
269
270 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
271 "eac.codec.in", s, omap_eac_in_cb, &fmt);
272 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
273 "eac.codec.out", s, omap_eac_out_cb, &fmt);
274
275 omap_eac_volume_update(s);
276
277 AUD_set_active_in(s->codec.in_voice, 1);
278 AUD_set_active_out(s->codec.out_voice, 1);
279}
280
281static void omap_eac_reset(struct omap_eac_s *s)
282{
283 s->sysconfig = 0;
284 s->config[0] = 0x0c;
285 s->config[1] = 0x09;
286 s->config[2] = 0xab;
287 s->config[3] = 0x03;
288 s->control = 0x00;
289 s->address = 0x00;
290 s->data = 0x0000;
291 s->vtol = 0x00;
292 s->vtsl = 0x00;
293 s->mixer = 0x0000;
294 s->gain[0] = 0xe7e7;
295 s->gain[1] = 0x6767;
296 s->gain[2] = 0x6767;
297 s->gain[3] = 0x6767;
298 s->att = 0xce;
299 s->max[0] = 0;
300 s->max[1] = 0;
301 s->max[2] = 0;
302 s->max[3] = 0;
303 s->max[4] = 0;
304 s->max[5] = 0;
305 s->max[6] = 0;
306
307 s->modem.control = 0x00;
308 s->modem.config = 0x0000;
309 s->bt.control = 0x00;
310 s->bt.config = 0x0000;
311 s->codec.config[0] = 0x0649;
312 s->codec.config[1] = 0x0000;
313 s->codec.config[2] = 0x0007;
314 s->codec.config[3] = 0x1ffc;
ab17b46d 315 s->codec.rxoff = 0;
99570a40
AZ		 316 s->codec.rxlen = 0;
317 s->codec.txlen = 0;
318 s->codec.rxavail = 0;
319 s->codec.txavail = 0;
320
321 omap_eac_format_update(s);
322 omap_eac_interrupt_update(s);
323}
324
c227f099 325static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
99570a40
AZ		 326{
327 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
ab17b46d 328 uint32_t ret;
99570a40 329
8da3ff18 330 switch (addr) {
99570a40
AZ		 331 case 0x000: /* CPCFR1 */
332 return s->config[0];
333 case 0x004: /* CPCFR2 */
334 return s->config[1];
335 case 0x008: /* CPCFR3 */
336 return s->config[2];
337 case 0x00c: /* CPCFR4 */
338 return s->config[3];
339
340 case 0x010: /* CPTCTL */
341 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
342 ((s->codec.txlen < s->codec.txavail) << 5);
343
344 case 0x014: /* CPTTADR */
345 return s->address;
346 case 0x018: /* CPTDATL */
347 return s->data & 0xff;
348 case 0x01c: /* CPTDATH */
349 return s->data >> 8;
350 case 0x020: /* CPTVSLL */
351 return s->vtol;
352 case 0x024: /* CPTVSLH */
353 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
354 case 0x040: /* MPCTR */
355 return s->modem.control;
356 case 0x044: /* MPMCCFR */
357 return s->modem.config;
358 case 0x060: /* BPCTR */
359 return s->bt.control;
360 case 0x064: /* BPMCCFR */
361 return s->bt.config;
362 case 0x080: /* AMSCFR */
363 return s->mixer;
364 case 0x084: /* AMVCTR */
365 return s->gain[0];
366 case 0x088: /* AM1VCTR */
367 return s->gain[1];
368 case 0x08c: /* AM2VCTR */
369 return s->gain[2];
370 case 0x090: /* AM3VCTR */
371 return s->gain[3];
372 case 0x094: /* ASTCTR */
373 return s->att;
374 case 0x098: /* APD1LCR */
375 return s->max[0];
376 case 0x09c: /* APD1RCR */
377 return s->max[1];
378 case 0x0a0: /* APD2LCR */
379 return s->max[2];
380 case 0x0a4: /* APD2RCR */
381 return s->max[3];
382 case 0x0a8: /* APD3LCR */
383 return s->max[4];
384 case 0x0ac: /* APD3RCR */
385 return s->max[5];
386 case 0x0b0: /* APD4R */
387 return s->max[6];
388 case 0x0b4: /* ADWR */
389 /* This should be write-only? Docs list it as read-only. */
390 return 0x0000;
391 case 0x0b8: /* ADRDR */
ab17b46d
AZ		 392 if (likely(s->codec.rxlen > 1)) {
393 ret = s->codec.rxbuf[s->codec.rxoff ++];
394 s->codec.rxlen --;
395 s->codec.rxoff &= EAC_BUF_LEN - 1;
396 return ret;
397 } else if (s->codec.rxlen) {
398 ret = s->codec.rxbuf[s->codec.rxoff ++];
399 s->codec.rxlen --;
400 s->codec.rxoff &= EAC_BUF_LEN - 1;
99570a40
AZ		 401 if (s->codec.rxavail)
402 omap_eac_in_refill(s);
ab17b46d
AZ		 403 omap_eac_in_dmarequest_update(s);
404 return ret;
99570a40
AZ		 405 }
406 return 0x0000;
407 case 0x0bc: /* AGCFR */
408 return s->codec.config[0];
409 case 0x0c0: /* AGCTR */
410 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
411 case 0x0c4: /* AGCFR2 */
412 return s->codec.config[2];
413 case 0x0c8: /* AGCFR3 */
414 return s->codec.config[3];
415 case 0x0cc: /* MBPDMACTR */
416 case 0x0d0: /* MPDDMARR */
417 case 0x0d8: /* MPUDMARR */
418 case 0x0e4: /* BPDDMARR */
419 case 0x0ec: /* BPUDMARR */
420 return 0x0000;
421
422 case 0x100: /* VERSION_NUMBER */
423 return 0x0010;
424
425 case 0x104: /* SYSCONFIG */
426 return s->sysconfig;
427
428 case 0x108: /* SYSSTATUS */
429 return 1 | 0xe; /* RESETDONE | stuff */
430 }
431
432 OMAP_BAD_REG(addr);
433 return 0;
434}
435
c227f099 436static void omap_eac_write(void *opaque, target_phys_addr_t addr,
99570a40
AZ		 437 uint32_t value)
438{
439 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
99570a40 440
8da3ff18 441 switch (addr) {
99570a40
AZ		 442 case 0x098: /* APD1LCR */
443 case 0x09c: /* APD1RCR */
444 case 0x0a0: /* APD2LCR */
445 case 0x0a4: /* APD2RCR */
446 case 0x0a8: /* APD3LCR */
447 case 0x0ac: /* APD3RCR */
448 case 0x0b0: /* APD4R */
449 case 0x0b8: /* ADRDR */
450 case 0x0d0: /* MPDDMARR */
451 case 0x0d8: /* MPUDMARR */
452 case 0x0e4: /* BPDDMARR */
453 case 0x0ec: /* BPUDMARR */
454 case 0x100: /* VERSION_NUMBER */
455 case 0x108: /* SYSSTATUS */
456 OMAP_RO_REG(addr);
457 return;
458
459 case 0x000: /* CPCFR1 */
460 s->config[0] = value & 0xff;
461 omap_eac_format_update(s);
462 break;
463 case 0x004: /* CPCFR2 */
464 s->config[1] = value & 0xff;
465 omap_eac_format_update(s);
466 break;
467 case 0x008: /* CPCFR3 */
468 s->config[2] = value & 0xff;
469 omap_eac_format_update(s);
470 break;
471 case 0x00c: /* CPCFR4 */
472 s->config[3] = value & 0xff;
473 omap_eac_format_update(s);
474 break;
475
476 case 0x010: /* CPTCTL */
477 /* Assuming TXF and TXE bits are read-only... */
478 s->control = value & 0x5f;
479 omap_eac_interrupt_update(s);
480 break;
481
482 case 0x014: /* CPTTADR */
483 s->address = value & 0xff;
484 break;
485 case 0x018: /* CPTDATL */
486 s->data &= 0xff00;
487 s->data |= value & 0xff;
488 break;
489 case 0x01c: /* CPTDATH */
490 s->data &= 0x00ff;
491 s->data |= value << 8;
492 break;
493 case 0x020: /* CPTVSLL */
494 s->vtol = value & 0xf8;
495 break;
496 case 0x024: /* CPTVSLH */
497 s->vtsl = value & 0x9f;
498 break;
499 case 0x040: /* MPCTR */
500 s->modem.control = value & 0x8f;
501 break;
502 case 0x044: /* MPMCCFR */
503 s->modem.config = value & 0x7fff;
504 break;
505 case 0x060: /* BPCTR */
506 s->bt.control = value & 0x8f;
507 break;
508 case 0x064: /* BPMCCFR */
509 s->bt.config = value & 0x7fff;
510 break;
511 case 0x080: /* AMSCFR */
512 s->mixer = value & 0x0fff;
513 break;
514 case 0x084: /* AMVCTR */
515 s->gain[0] = value & 0xffff;
516 break;
517 case 0x088: /* AM1VCTR */
518 s->gain[1] = value & 0xff7f;
519 break;
520 case 0x08c: /* AM2VCTR */
521 s->gain[2] = value & 0xff7f;
522 break;
523 case 0x090: /* AM3VCTR */
524 s->gain[3] = value & 0xff7f;
525 break;
526 case 0x094: /* ASTCTR */
527 s->att = value & 0xff;
528 break;
529
530 case 0x0b4: /* ADWR */
531 s->codec.txbuf[s->codec.txlen ++] = value;
532 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
533 s->codec.txlen == s->codec.txavail)) {
534 if (s->codec.txavail)
535 omap_eac_out_empty(s);
ab17b46d
AZ		 536 /* Discard what couldn't be written */
537 s->codec.txlen = 0;
99570a40
AZ		 538 }
539 break;
540
541 case 0x0bc: /* AGCFR */
542 s->codec.config[0] = value & 0x07ff;
543 omap_eac_format_update(s);
544 break;
545 case 0x0c0: /* AGCTR */
546 s->codec.config[1] = value & 0x780f;
547 omap_eac_format_update(s);
548 break;
549 case 0x0c4: /* AGCFR2 */
550 s->codec.config[2] = value & 0x003f;
551 omap_eac_format_update(s);
552 break;
553 case 0x0c8: /* AGCFR3 */
554 s->codec.config[3] = value & 0xffff;
555 omap_eac_format_update(s);
556 break;
557 case 0x0cc: /* MBPDMACTR */
558 case 0x0d4: /* MPDDMAWR */
559 case 0x0e0: /* MPUDMAWR */
560 case 0x0e8: /* BPDDMAWR */
561 case 0x0f0: /* BPUDMAWR */
562 break;
563
564 case 0x104: /* SYSCONFIG */
565 if (value & (1 << 1)) /* SOFTRESET */
566 omap_eac_reset(s);
567 s->sysconfig = value & 0x31d;
568 break;
569
570 default:
571 OMAP_BAD_REG(addr);
572 return;
573 }
574}
575
d60efc6b 576static CPUReadMemoryFunc * const omap_eac_readfn[] = {
99570a40
AZ		 577 omap_badwidth_read16,
578 omap_eac_read,
579 omap_badwidth_read16,
580};
581
d60efc6b 582static CPUWriteMemoryFunc * const omap_eac_writefn[] = {
99570a40
AZ		 583 omap_badwidth_write16,
584 omap_eac_write,
585 omap_badwidth_write16,
586};
587
588struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
589 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
590{
591 int iomemtype;
592 struct omap_eac_s *s = (struct omap_eac_s *)
593 qemu_mallocz(sizeof(struct omap_eac_s));
594
595 s->irq = irq;
596 s->codec.rxdrq = *drq ++;
22ed1d34 597 s->codec.txdrq = *drq;
99570a40
AZ		 598 omap_eac_reset(s);
599
1a7dafce 600 AUD_register_card("OMAP EAC", &s->codec.card);
99570a40 601
1eed09cb 602 iomemtype = cpu_register_io_memory(omap_eac_readfn,
99570a40 603 omap_eac_writefn, s);
8da3ff18 604 omap_l4_attach(ta, 0, iomemtype);
99570a40
AZ		 605
606 return s;
607}
608
54585ffe
AZ		 609/* STI/XTI (emulation interface) console - reverse engineered only */
610struct omap_sti_s {
54585ffe
AZ		 611 qemu_irq irq;
612 CharDriverState *chr;
613
614 uint32_t sysconfig;
615 uint32_t systest;
616 uint32_t irqst;
617 uint32_t irqen;
618 uint32_t clkcontrol;
619 uint32_t serial_config;
620};
621
622#define STI_TRACE_CONSOLE_CHANNEL 239
623#define STI_TRACE_CONTROL_CHANNEL 253
624
625static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
626{
627 qemu_set_irq(s->irq, s->irqst & s->irqen);
628}
629
630static void omap_sti_reset(struct omap_sti_s *s)
631{
632 s->sysconfig = 0;
633 s->irqst = 0;
634 s->irqen = 0;
635 s->clkcontrol = 0;
636 s->serial_config = 0;
637
638 omap_sti_interrupt_update(s);
639}
640
c227f099 641static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
54585ffe
AZ		 642{
643 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
54585ffe 644
8da3ff18 645 switch (addr) {
54585ffe
AZ		 646 case 0x00: /* STI_REVISION */
647 return 0x10;
648
649 case 0x10: /* STI_SYSCONFIG */
650 return s->sysconfig;
651
652 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
653 return 0x00;
654
655 case 0x18: /* STI_IRQSTATUS */
656 return s->irqst;
657
658 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
659 return s->irqen;
660
661 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
662 case 0x28: /* STI_RX_DR / XTI_RXDATA */
e927bb00
AZ		 663 /* TODO */
664 return 0;
54585ffe
AZ		 665
666 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
667 return s->clkcontrol;
668
669 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
670 return s->serial_config;
671 }
672
673 OMAP_BAD_REG(addr);
674 return 0;
675}
676
c227f099 677static void omap_sti_write(void *opaque, target_phys_addr_t addr,
54585ffe
AZ		 678 uint32_t value)
679{
680 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
54585ffe 681
8da3ff18 682 switch (addr) {
54585ffe
AZ		 683 case 0x00: /* STI_REVISION */
684 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
685 OMAP_RO_REG(addr);
686 return;
687
688 case 0x10: /* STI_SYSCONFIG */
689 if (value & (1 << 1)) /* SOFTRESET */
690 omap_sti_reset(s);
691 s->sysconfig = value & 0xfe;
692 break;
693
694 case 0x18: /* STI_IRQSTATUS */
695 s->irqst &= ~value;
696 omap_sti_interrupt_update(s);
697 break;
698
699 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
700 s->irqen = value & 0xffff;
701 omap_sti_interrupt_update(s);
702 break;
703
704 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
705 s->clkcontrol = value & 0xff;
706 break;
707
708 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
709 s->serial_config = value & 0xff;
710 break;
711
712 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
713 case 0x28: /* STI_RX_DR / XTI_RXDATA */
e927bb00
AZ		 714 /* TODO */
715 return;
716
54585ffe
AZ		 717 default:
718 OMAP_BAD_REG(addr);
719 return;
720 }
721}
722
d60efc6b 723static CPUReadMemoryFunc * const omap_sti_readfn[] = {
54585ffe
AZ		 724 omap_badwidth_read32,
725 omap_badwidth_read32,
726 omap_sti_read,
727};
728
d60efc6b 729static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
54585ffe
AZ		 730 omap_badwidth_write32,
731 omap_badwidth_write32,
732 omap_sti_write,
733};
734
c227f099 735static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
54585ffe
AZ		 736{
737 OMAP_BAD_REG(addr);
738 return 0;
739}
740
c227f099 741static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
54585ffe
AZ		 742 uint32_t value)
743{
744 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
8da3ff18 745 int ch = addr >> 6;
54585ffe
AZ		 746 uint8_t byte = value;
747
748 if (ch == STI_TRACE_CONTROL_CHANNEL) {
749 /* Flush channel <i>value</i>. */
75554a3c 750 qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
54585ffe
AZ		 751 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
752 if (value == 0xc0 || value == 0xc3) {
753 /* Open channel <i>ch</i>. */
754 } else if (value == 0x00)
75554a3c 755 qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
54585ffe
AZ		 756 else
757 qemu_chr_write(s->chr, &byte, 1);
758 }
759}
760
d60efc6b 761static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = {
54585ffe
AZ		 762 omap_sti_fifo_read,
763 omap_badwidth_read8,
764 omap_badwidth_read8,
765};
766
d60efc6b 767static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
54585ffe
AZ		 768 omap_sti_fifo_write,
769 omap_badwidth_write8,
770 omap_badwidth_write8,
771};
772
b1d8e52e 773static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
c227f099 774 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
54585ffe
AZ		 775 CharDriverState *chr)
776{
777 int iomemtype;
778 struct omap_sti_s *s = (struct omap_sti_s *)
779 qemu_mallocz(sizeof(struct omap_sti_s));
780
781 s->irq = irq;
782 omap_sti_reset(s);
783
ceecf1d1 784 s->chr = chr ?: qemu_chr_open("null", "null", NULL);
54585ffe 785
1eed09cb 786 iomemtype = l4_register_io_memory(omap_sti_readfn,
54585ffe 787 omap_sti_writefn, s);
8da3ff18 788 omap_l4_attach(ta, 0, iomemtype);
54585ffe 789
1eed09cb 790 iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
54585ffe 791 omap_sti_fifo_writefn, s);
8da3ff18 792 cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
54585ffe
AZ		 793
794 return s;
795}
796
827df9f3
AZ		 797/* L4 Interconnect */
798struct omap_target_agent_s {
799 struct omap_l4_s *bus;
800 int regions;
801 struct omap_l4_region_s *start;
c227f099 802 target_phys_addr_t base;
827df9f3
AZ		 803 uint32_t component;
804 uint32_t control;
805 uint32_t status;
806};
807
808struct omap_l4_s {
c227f099 809 target_phys_addr_t base;
827df9f3
AZ		 810 int ta_num;
811 struct omap_target_agent_s ta[0];
812};
813
c66fb5bc
AZ		 814#ifdef L4_MUX_HACK
815static int omap_l4_io_entries;
816static int omap_cpu_io_entry;
817static struct omap_l4_entry {
d60efc6b
BS		 818 CPUReadMemoryFunc * const *mem_read;
819 CPUWriteMemoryFunc * const *mem_write;
c66fb5bc
AZ		 820 void *opaque;
821} *omap_l4_io_entry;
d60efc6b
BS		 822static CPUReadMemoryFunc * const *omap_l4_io_readb_fn;
823static CPUReadMemoryFunc * const *omap_l4_io_readh_fn;
824static CPUReadMemoryFunc * const *omap_l4_io_readw_fn;
825static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn;
826static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn;
827static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn;
c66fb5bc
AZ		 828static void **omap_l4_io_opaque;
829
d60efc6b
BS		 830int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
831 CPUWriteMemoryFunc * const *mem_write, void *opaque)
c66fb5bc
AZ		 832{
833 omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
834 omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
835 omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
836
837 return omap_l4_io_entries ++;
838}
839
c227f099 840static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
c66fb5bc
AZ		 841{
842 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
843
844 return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
845}
846
c227f099 847static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
c66fb5bc
AZ		 848{
849 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
850
851 return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
852}
853
c227f099 854static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
c66fb5bc
AZ		 855{
856 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
857
858 return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
859}
860
c227f099 861static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
c66fb5bc
AZ		 862 uint32_t value)
863{
864 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
865
866 return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
867}
868
c227f099 869static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
c66fb5bc
AZ		 870 uint32_t value)
871{
872 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
873
874 return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
875}
876
c227f099 877static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
c66fb5bc
AZ		 878 uint32_t value)
879{
880 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
881
882 return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
883}
884
d60efc6b 885static CPUReadMemoryFunc * const omap_l4_io_readfn[] = {
c66fb5bc
AZ		 886 omap_l4_io_readb,
887 omap_l4_io_readh,
888 omap_l4_io_readw,
889};
890
d60efc6b 891static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
c66fb5bc
AZ		 892 omap_l4_io_writeb,
893 omap_l4_io_writeh,
894 omap_l4_io_writew,
895};
896#endif
897
c227f099 898struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
827df9f3
AZ		 899{
900 struct omap_l4_s *bus = qemu_mallocz(
901 sizeof(*bus) + ta_num * sizeof(*bus->ta));
902
903 bus->ta_num = ta_num;
904 bus->base = base;
905
c66fb5bc
AZ		 906#ifdef L4_MUX_HACK
907 omap_l4_io_entries = 1;
908 omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
909
910 omap_cpu_io_entry =
1eed09cb 911 cpu_register_io_memory(omap_l4_io_readfn,
c66fb5bc
AZ		 912 omap_l4_io_writefn, bus);
913# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
914 omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
915 omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
916 omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
917 omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
918 omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
919 omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
920 omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
921#endif
922
827df9f3
AZ		 923 return bus;
924}
925
c227f099 926static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
827df9f3
AZ		 927{
928 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
827df9f3 929
8da3ff18 930 switch (addr) {
827df9f3
AZ		 931 case 0x00: /* COMPONENT */
932 return s->component;
933
934 case 0x20: /* AGENT_CONTROL */
935 return s->control;
936
937 case 0x28: /* AGENT_STATUS */
938 return s->status;
939 }
940
941 OMAP_BAD_REG(addr);
942 return 0;
943}
944
c227f099 945static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
827df9f3
AZ		 946 uint32_t value)
947{
948 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
827df9f3 949
8da3ff18 950 switch (addr) {
827df9f3
AZ		 951 case 0x00: /* COMPONENT */
952 case 0x28: /* AGENT_STATUS */
953 OMAP_RO_REG(addr);
954 break;
955
956 case 0x20: /* AGENT_CONTROL */
957 s->control = value & 0x01000700;
958 if (value & 1) /* OCP_RESET */
959 s->status &= ~1; /* REQ_TIMEOUT */
960 break;
961
962 default:
963 OMAP_BAD_REG(addr);
964 }
965}
966
d60efc6b 967static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
827df9f3
AZ		 968 omap_badwidth_read16,
969 omap_l4ta_read,
970 omap_badwidth_read16,
971};
972
d60efc6b 973static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
827df9f3
AZ		 974 omap_badwidth_write32,
975 omap_badwidth_write32,
976 omap_l4ta_write,
977};
978
979#define L4TA(n) (n)
980#define L4TAO(n) ((n) + 39)
981
982static struct omap_l4_region_s {
c227f099 983 target_phys_addr_t offset;
827df9f3
AZ		 984 size_t size;
985 int access;
986} omap_l4_region[125] = {
987 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
988 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
989 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
990 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
991 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
992 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
993 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
994 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
995 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
996 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
997 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
998 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
999 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
1000 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
1001 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
1002 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
1003 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
1004 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
1005 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
1006 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
1007 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
1008 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
1009 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
1010 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
1011 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
1012 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
1013 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
1014 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
1015 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
1016 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
1017 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
1018 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
1019 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
1020 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
1021 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
1022 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
1023 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
1024 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
1025 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
1026 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
1027 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
1028 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
1029 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
1030 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
1031 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
1032 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
1033 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
1034 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
1035 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
1036 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
1037 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
1038 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
1039 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
1040 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
1041 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
1042 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
1043 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
1044 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
1045 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
1046 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
1047 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
1048 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
1049 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
1050 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
1051 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
1052 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
1053 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
1054 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
1055 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
1056 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
1057 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
1058 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
1059 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
1060 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
1061 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
1062 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
1063 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
1064 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
1065 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
1066 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
1067 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
1068 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
1069 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
1070 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
1071 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
1072 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
1073 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
1074 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
1075 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
1076 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
1077 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
1078 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
1079 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
1080 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
1081 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
1082 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
1083 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
1084 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
1085 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
1086 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
1087 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
1088 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
1089 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
1090 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
1091 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
1092 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
1093 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
1094 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
1095 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
1096 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
1097 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
1098 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
1099 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
1100 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
1101 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
1102 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
1103 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
1104 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
1105 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
1106 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
1107 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
1108 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
1109 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
1110 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
1111 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
1112};
1113
1114static struct omap_l4_agent_info_s {
1115 int ta;
1116 int region;
1117 int regions;
1118 int ta_region;
1119} omap_l4_agent_info[54] = {
1120 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
1121 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
1122 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
1123 { L4TAO(3), 7, 3, 2 }, /* PRCM */
1124 { L4TA(1), 10, 2, 1 }, /* BCM */
1125 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
1126 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
1127 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
1128 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
1129 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
1130 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
1131 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
1132 { L4TA(12), 38, 2, 1 }, /* sDMA */
1133 { L4TA(13), 40, 5, 4 }, /* SSI */
1134 { L4TAO(4), 45, 2, 1 }, /* USB */
1135 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
1136 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
1137 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
1138 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
1139 { L4TA(18), 55, 2, 1 }, /* XTI */
1140 { L4TA(19), 57, 2, 1 }, /* UART1 */
1141 { L4TA(20), 59, 2, 1 }, /* UART2 */
1142 { L4TA(21), 61, 2, 1 }, /* UART3 */
1143 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
1144 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
1145 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
1146 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
1147 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
1148 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
1149 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
1150 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
1151 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
1152 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
1153 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
1154 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
1155 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
1156 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
1157 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
1158 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
1159 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
1160 { L4TA(32), 97, 2, 1 }, /* EAC */
1161 { L4TA(33), 99, 2, 1 }, /* FAC */
1162 { L4TA(34), 101, 2, 1 }, /* IPC */
1163 { L4TA(35), 103, 2, 1 }, /* SPI1 */
1164 { L4TA(36), 105, 2, 1 }, /* SPI2 */
1165 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
1166 { L4TAO(10), 109, 2, 1 },
1167 { L4TAO(11), 111, 2, 1 }, /* RNG */
1168 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
1169 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
1170 { L4TA(37), 117, 2, 1 }, /* AES */
1171 { L4TA(38), 119, 2, 1 }, /* PKA */
1172 { -1, 121, 2, 1 },
1173 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
1174};
1175
1176#define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
1177#define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
1178
1179struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
1180{
1181 int i, iomemtype;
b9d38e95
BS		 1182 struct omap_target_agent_s *ta = NULL;
1183 struct omap_l4_agent_info_s *info = NULL;
827df9f3
AZ		 1184
1185 for (i = 0; i < bus->ta_num; i ++)
1186 if (omap_l4_agent_info[i].ta == cs) {
1187 ta = &bus->ta[i];
1188 info = &omap_l4_agent_info[i];
1189 break;
1190 }
1191 if (!ta) {
1192 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
1193 exit(-1);
1194 }
1195
1196 ta->bus = bus;
1197 ta->start = &omap_l4_region[info->region];
1198 ta->regions = info->regions;
827df9f3
AZ		 1199
1200 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1201 ta->status = 0x00000000;
1202 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
1203
1eed09cb 1204 iomemtype = l4_register_io_memory(omap_l4ta_readfn,
827df9f3 1205 omap_l4ta_writefn, ta);
c66fb5bc 1206 ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
827df9f3
AZ		 1207
1208 return ta;
1209}
1210
c227f099 1211target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
827df9f3
AZ		 1212 int iotype)
1213{
c227f099 1214 target_phys_addr_t base;
c66fb5bc
AZ		 1215 ssize_t size;
1216#ifdef L4_MUX_HACK
1217 int i;
1218#endif
827df9f3
AZ		 1219
1220 if (region < 0 || region >= ta->regions) {
1221 fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
1222 exit(-1);
1223 }
1224
1225 base = ta->bus->base + ta->start[region].offset;
1226 size = ta->start[region].size;
c66fb5bc
AZ		 1227 if (iotype) {
1228#ifndef L4_MUX_HACK
827df9f3 1229 cpu_register_physical_memory(base, size, iotype);
c66fb5bc
AZ		 1230#else
1231 cpu_register_physical_memory(base, size, omap_cpu_io_entry);
1232 i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
1233 for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
1234 omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
1235 omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
1236 omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
1237 omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
1238 omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
1239 omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
1240 omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
1241 }
1242#endif
1243 }
827df9f3
AZ		 1244
1245 return base;
1246}
1247
827df9f3
AZ		 1248/* Power, Reset, and Clock Management */
1249struct omap_prcm_s {
827df9f3
AZ		 1250 qemu_irq irq[3];
1251 struct omap_mpu_state_s *mpu;
1252
1253 uint32_t irqst[3];
1254 uint32_t irqen[3];
1255
1256 uint32_t sysconfig;
1257 uint32_t voltctrl;
1258 uint32_t scratch[20];
1259
1260 uint32_t clksrc[1];
1261 uint32_t clkout[1];
1262 uint32_t clkemul[1];
1263 uint32_t clkpol[1];
1264 uint32_t clksel[8];
1265 uint32_t clken[12];
1266 uint32_t clkctrl[4];
1267 uint32_t clkidle[7];
1268 uint32_t setuptime[2];
1269
1270 uint32_t wkup[3];
1271 uint32_t wken[3];
1272 uint32_t wkst[3];
1273 uint32_t rst[4];
1274 uint32_t rstctrl[1];
1275 uint32_t power[4];
1276 uint32_t rsttime_wkup;
1277
1278 uint32_t ev;
1279 uint32_t evtime[2];
51fec3cc
AZ		 1280
1281 int dpll_lock, apll_lock[2];
827df9f3
AZ		 1282};
1283
1284static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1285{
1286 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1287 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1288}
1289
c227f099 1290static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
827df9f3
AZ		 1291{
1292 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
51fec3cc 1293 uint32_t ret;
827df9f3 1294
8da3ff18 1295 switch (addr) {
827df9f3
AZ		 1296 case 0x000: /* PRCM_REVISION */
1297 return 0x10;
1298
1299 case 0x010: /* PRCM_SYSCONFIG */
1300 return s->sysconfig;
1301
1302 case 0x018: /* PRCM_IRQSTATUS_MPU */
1303 return s->irqst[0];
1304
1305 case 0x01c: /* PRCM_IRQENABLE_MPU */
1306 return s->irqen[0];
1307
1308 case 0x050: /* PRCM_VOLTCTRL */
1309 return s->voltctrl;
1310 case 0x054: /* PRCM_VOLTST */
1311 return s->voltctrl & 3;
1312
1313 case 0x060: /* PRCM_CLKSRC_CTRL */
1314 return s->clksrc[0];
1315 case 0x070: /* PRCM_CLKOUT_CTRL */
1316 return s->clkout[0];
1317 case 0x078: /* PRCM_CLKEMUL_CTRL */
1318 return s->clkemul[0];
1319 case 0x080: /* PRCM_CLKCFG_CTRL */
1320 case 0x084: /* PRCM_CLKCFG_STATUS */
1321 return 0;
1322
1323 case 0x090: /* PRCM_VOLTSETUP */
1324 return s->setuptime[0];
1325
1326 case 0x094: /* PRCM_CLKSSETUP */
1327 return s->setuptime[1];
1328
1329 case 0x098: /* PRCM_POLCTRL */
1330 return s->clkpol[0];
1331
1332 case 0x0b0: /* GENERAL_PURPOSE1 */
1333 case 0x0b4: /* GENERAL_PURPOSE2 */
1334 case 0x0b8: /* GENERAL_PURPOSE3 */
1335 case 0x0bc: /* GENERAL_PURPOSE4 */
1336 case 0x0c0: /* GENERAL_PURPOSE5 */
1337 case 0x0c4: /* GENERAL_PURPOSE6 */
1338 case 0x0c8: /* GENERAL_PURPOSE7 */
1339 case 0x0cc: /* GENERAL_PURPOSE8 */
1340 case 0x0d0: /* GENERAL_PURPOSE9 */
1341 case 0x0d4: /* GENERAL_PURPOSE10 */
1342 case 0x0d8: /* GENERAL_PURPOSE11 */
1343 case 0x0dc: /* GENERAL_PURPOSE12 */
1344 case 0x0e0: /* GENERAL_PURPOSE13 */
1345 case 0x0e4: /* GENERAL_PURPOSE14 */
1346 case 0x0e8: /* GENERAL_PURPOSE15 */
1347 case 0x0ec: /* GENERAL_PURPOSE16 */
1348 case 0x0f0: /* GENERAL_PURPOSE17 */
1349 case 0x0f4: /* GENERAL_PURPOSE18 */
1350 case 0x0f8: /* GENERAL_PURPOSE19 */
1351 case 0x0fc: /* GENERAL_PURPOSE20 */
8da3ff18 1352 return s->scratch[(addr - 0xb0) >> 2];
827df9f3
AZ		 1353
1354 case 0x140: /* CM_CLKSEL_MPU */
1355 return s->clksel[0];
1356 case 0x148: /* CM_CLKSTCTRL_MPU */
1357 return s->clkctrl[0];
1358
1359 case 0x158: /* RM_RSTST_MPU */
1360 return s->rst[0];
1361 case 0x1c8: /* PM_WKDEP_MPU */
1362 return s->wkup[0];
1363 case 0x1d4: /* PM_EVGENCTRL_MPU */
1364 return s->ev;
1365 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1366 return s->evtime[0];
1367 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1368 return s->evtime[1];
1369 case 0x1e0: /* PM_PWSTCTRL_MPU */
1370 return s->power[0];
1371 case 0x1e4: /* PM_PWSTST_MPU */
1372 return 0;
1373
1374 case 0x200: /* CM_FCLKEN1_CORE */
1375 return s->clken[0];
1376 case 0x204: /* CM_FCLKEN2_CORE */
1377 return s->clken[1];
1378 case 0x210: /* CM_ICLKEN1_CORE */
1379 return s->clken[2];
1380 case 0x214: /* CM_ICLKEN2_CORE */
1381 return s->clken[3];
1382 case 0x21c: /* CM_ICLKEN4_CORE */
1383 return s->clken[4];
1384
1385 case 0x220: /* CM_IDLEST1_CORE */
1386 /* TODO: check the actual iclk status */
1387 return 0x7ffffff9;
1388 case 0x224: /* CM_IDLEST2_CORE */
1389 /* TODO: check the actual iclk status */
1390 return 0x00000007;
1391 case 0x22c: /* CM_IDLEST4_CORE */
1392 /* TODO: check the actual iclk status */
1393 return 0x0000001f;
1394
1395 case 0x230: /* CM_AUTOIDLE1_CORE */
1396 return s->clkidle[0];
1397 case 0x234: /* CM_AUTOIDLE2_CORE */
1398 return s->clkidle[1];
1399 case 0x238: /* CM_AUTOIDLE3_CORE */
1400 return s->clkidle[2];
1401 case 0x23c: /* CM_AUTOIDLE4_CORE */
1402 return s->clkidle[3];
1403
1404 case 0x240: /* CM_CLKSEL1_CORE */
1405 return s->clksel[1];
1406 case 0x244: /* CM_CLKSEL2_CORE */
1407 return s->clksel[2];
1408
1409 case 0x248: /* CM_CLKSTCTRL_CORE */
1410 return s->clkctrl[1];
1411
1412 case 0x2a0: /* PM_WKEN1_CORE */
1413 return s->wken[0];
1414 case 0x2a4: /* PM_WKEN2_CORE */
1415 return s->wken[1];
1416
1417 case 0x2b0: /* PM_WKST1_CORE */
1418 return s->wkst[0];
1419 case 0x2b4: /* PM_WKST2_CORE */
1420 return s->wkst[1];
1421 case 0x2c8: /* PM_WKDEP_CORE */
1422 return 0x1e;
1423
1424 case 0x2e0: /* PM_PWSTCTRL_CORE */
1425 return s->power[1];
1426 case 0x2e4: /* PM_PWSTST_CORE */
1427 return 0x000030 | (s->power[1] & 0xfc00);
1428
1429 case 0x300: /* CM_FCLKEN_GFX */
1430 return s->clken[5];
1431 case 0x310: /* CM_ICLKEN_GFX */
1432 return s->clken[6];
1433 case 0x320: /* CM_IDLEST_GFX */
1434 /* TODO: check the actual iclk status */
1435 return 0x00000001;
1436 case 0x340: /* CM_CLKSEL_GFX */
1437 return s->clksel[3];
1438 case 0x348: /* CM_CLKSTCTRL_GFX */
1439 return s->clkctrl[2];
1440 case 0x350: /* RM_RSTCTRL_GFX */
1441 return s->rstctrl[0];
1442 case 0x358: /* RM_RSTST_GFX */
1443 return s->rst[1];
1444 case 0x3c8: /* PM_WKDEP_GFX */
1445 return s->wkup[1];
1446
1447 case 0x3e0: /* PM_PWSTCTRL_GFX */
1448 return s->power[2];
1449 case 0x3e4: /* PM_PWSTST_GFX */
1450 return s->power[2] & 3;
1451
1452 case 0x400: /* CM_FCLKEN_WKUP */
1453 return s->clken[7];
1454 case 0x410: /* CM_ICLKEN_WKUP */
1455 return s->clken[8];
1456 case 0x420: /* CM_IDLEST_WKUP */
1457 /* TODO: check the actual iclk status */
1458 return 0x0000003f;
1459 case 0x430: /* CM_AUTOIDLE_WKUP */
1460 return s->clkidle[4];
1461 case 0x440: /* CM_CLKSEL_WKUP */
1462 return s->clksel[4];
1463 case 0x450: /* RM_RSTCTRL_WKUP */
1464 return 0;
1465 case 0x454: /* RM_RSTTIME_WKUP */
1466 return s->rsttime_wkup;
1467 case 0x458: /* RM_RSTST_WKUP */
1468 return s->rst[2];
1469 case 0x4a0: /* PM_WKEN_WKUP */
1470 return s->wken[2];
1471 case 0x4b0: /* PM_WKST_WKUP */
1472 return s->wkst[2];
1473
1474 case 0x500: /* CM_CLKEN_PLL */
1475 return s->clken[9];
1476 case 0x520: /* CM_IDLEST_CKGEN */
51fec3cc 1477 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
827df9f3 1478 if (!(s->clksel[6] & 3))
51fec3cc
AZ		 1479 /* Core uses 32-kHz clock */
1480 ret |= 3 << 0;
1481 else if (!s->dpll_lock)
1482 /* DPLL not locked, core uses ref_clk */
1483 ret |= 1 << 0;
1484 else
1485 /* Core uses DPLL */
1486 ret |= 2 << 0;
1487 return ret;
827df9f3
AZ		 1488 case 0x530: /* CM_AUTOIDLE_PLL */
1489 return s->clkidle[5];
1490 case 0x540: /* CM_CLKSEL1_PLL */
1491 return s->clksel[5];
1492 case 0x544: /* CM_CLKSEL2_PLL */
1493 return s->clksel[6];
1494
1495 case 0x800: /* CM_FCLKEN_DSP */
1496 return s->clken[10];
1497 case 0x810: /* CM_ICLKEN_DSP */
1498 return s->clken[11];
1499 case 0x820: /* CM_IDLEST_DSP */
1500 /* TODO: check the actual iclk status */
1501 return 0x00000103;
1502 case 0x830: /* CM_AUTOIDLE_DSP */
1503 return s->clkidle[6];
1504 case 0x840: /* CM_CLKSEL_DSP */
1505 return s->clksel[7];
1506 case 0x848: /* CM_CLKSTCTRL_DSP */
1507 return s->clkctrl[3];
1508 case 0x850: /* RM_RSTCTRL_DSP */
1509 return 0;
1510 case 0x858: /* RM_RSTST_DSP */
1511 return s->rst[3];
1512 case 0x8c8: /* PM_WKDEP_DSP */
1513 return s->wkup[2];
1514 case 0x8e0: /* PM_PWSTCTRL_DSP */
1515 return s->power[3];
1516 case 0x8e4: /* PM_PWSTST_DSP */
1517 return 0x008030 | (s->power[3] & 0x3003);
1518
1519 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1520 return s->irqst[1];
1521 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1522 return s->irqen[1];
1523
1524 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1525 return s->irqst[2];
1526 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1527 return s->irqen[2];
1528 }
1529
1530 OMAP_BAD_REG(addr);
1531 return 0;
1532}
1533
51fec3cc
AZ		 1534static void omap_prcm_apll_update(struct omap_prcm_s *s)
1535{
1536 int mode[2];
1537
1538 mode[0] = (s->clken[9] >> 6) & 3;
1539 s->apll_lock[0] = (mode[0] == 3);
1540 mode[1] = (s->clken[9] >> 2) & 3;
1541 s->apll_lock[1] = (mode[1] == 3);
1542 /* TODO: update clocks */
1543
16d55035 1544 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
51fec3cc
AZ		 1545 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1546 __FUNCTION__);
1547}
1548
1549static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1550{
1551 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1552 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1553 omap_clk core = omap_findclk(s->mpu, "core_clk");
1554 int mode = (s->clken[9] >> 0) & 3;
1555 int mult, div;
1556
1557 mult = (s->clksel[5] >> 12) & 0x3ff;
1558 div = (s->clksel[5] >> 8) & 0xf;
1559 if (mult == 0 || mult == 1)
1560 mode = 1; /* Bypass */
1561
1562 s->dpll_lock = 0;
1563 switch (mode) {
1564 case 0:
1565 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
1566 break;
1567 case 1: /* Low-power bypass mode (Default) */
1568 case 2: /* Fast-relock bypass mode */
1569 omap_clk_setrate(dpll, 1, 1);
1570 omap_clk_setrate(dpll_x2, 1, 1);
1571 break;
1572 case 3: /* Lock mode */
1573 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1574
1575 omap_clk_setrate(dpll, div + 1, mult);
1576 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1577 break;
1578 }
1579
1580 switch ((s->clksel[6] >> 0) & 3) {
1581 case 0:
1582 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1583 break;
1584 case 1:
1585 omap_clk_reparent(core, dpll);
1586 break;
1587 case 2:
1588 /* Default */
1589 omap_clk_reparent(core, dpll_x2);
1590 break;
1591 case 3:
1592 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
1593 break;
1594 }
1595}
1596
c227f099 1597static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
827df9f3
AZ		 1598 uint32_t value)
1599{
1600 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
827df9f3 1601
8da3ff18 1602 switch (addr) {
827df9f3
AZ		 1603 case 0x000: /* PRCM_REVISION */
1604 case 0x054: /* PRCM_VOLTST */
1605 case 0x084: /* PRCM_CLKCFG_STATUS */
1606 case 0x1e4: /* PM_PWSTST_MPU */
1607 case 0x220: /* CM_IDLEST1_CORE */
1608 case 0x224: /* CM_IDLEST2_CORE */
1609 case 0x22c: /* CM_IDLEST4_CORE */
1610 case 0x2c8: /* PM_WKDEP_CORE */
1611 case 0x2e4: /* PM_PWSTST_CORE */
1612 case 0x320: /* CM_IDLEST_GFX */
1613 case 0x3e4: /* PM_PWSTST_GFX */
1614 case 0x420: /* CM_IDLEST_WKUP */
1615 case 0x520: /* CM_IDLEST_CKGEN */
1616 case 0x820: /* CM_IDLEST_DSP */
1617 case 0x8e4: /* PM_PWSTST_DSP */
1618 OMAP_RO_REG(addr);
1619 return;
1620
1621 case 0x010: /* PRCM_SYSCONFIG */
1622 s->sysconfig = value & 1;
1623 break;
1624
1625 case 0x018: /* PRCM_IRQSTATUS_MPU */
1626 s->irqst[0] &= ~value;
1627 omap_prcm_int_update(s, 0);
1628 break;
1629 case 0x01c: /* PRCM_IRQENABLE_MPU */
1630 s->irqen[0] = value & 0x3f;
1631 omap_prcm_int_update(s, 0);
1632 break;
1633
1634 case 0x050: /* PRCM_VOLTCTRL */
1635 s->voltctrl = value & 0xf1c3;
1636 break;
1637
1638 case 0x060: /* PRCM_CLKSRC_CTRL */
1639 s->clksrc[0] = value & 0xdb;
1640 /* TODO update clocks */
1641 break;
1642
1643 case 0x070: /* PRCM_CLKOUT_CTRL */
1644 s->clkout[0] = value & 0xbbbb;
1645 /* TODO update clocks */
1646 break;
1647
1648 case 0x078: /* PRCM_CLKEMUL_CTRL */
1649 s->clkemul[0] = value & 1;
1650 /* TODO update clocks */
1651 break;
1652
1653 case 0x080: /* PRCM_CLKCFG_CTRL */
1654 break;
1655
1656 case 0x090: /* PRCM_VOLTSETUP */
1657 s->setuptime[0] = value & 0xffff;
1658 break;
1659 case 0x094: /* PRCM_CLKSSETUP */
1660 s->setuptime[1] = value & 0xffff;
1661 break;
1662
1663 case 0x098: /* PRCM_POLCTRL */
1664 s->clkpol[0] = value & 0x701;
1665 break;
1666
1667 case 0x0b0: /* GENERAL_PURPOSE1 */
1668 case 0x0b4: /* GENERAL_PURPOSE2 */
1669 case 0x0b8: /* GENERAL_PURPOSE3 */
1670 case 0x0bc: /* GENERAL_PURPOSE4 */
1671 case 0x0c0: /* GENERAL_PURPOSE5 */
1672 case 0x0c4: /* GENERAL_PURPOSE6 */
1673 case 0x0c8: /* GENERAL_PURPOSE7 */
1674 case 0x0cc: /* GENERAL_PURPOSE8 */
1675 case 0x0d0: /* GENERAL_PURPOSE9 */
1676 case 0x0d4: /* GENERAL_PURPOSE10 */
1677 case 0x0d8: /* GENERAL_PURPOSE11 */
1678 case 0x0dc: /* GENERAL_PURPOSE12 */
1679 case 0x0e0: /* GENERAL_PURPOSE13 */
1680 case 0x0e4: /* GENERAL_PURPOSE14 */
1681 case 0x0e8: /* GENERAL_PURPOSE15 */
1682 case 0x0ec: /* GENERAL_PURPOSE16 */
1683 case 0x0f0: /* GENERAL_PURPOSE17 */
1684 case 0x0f4: /* GENERAL_PURPOSE18 */
1685 case 0x0f8: /* GENERAL_PURPOSE19 */
1686 case 0x0fc: /* GENERAL_PURPOSE20 */
8da3ff18 1687 s->scratch[(addr - 0xb0) >> 2] = value;
827df9f3
AZ		 1688 break;
1689
1690 case 0x140: /* CM_CLKSEL_MPU */
1691 s->clksel[0] = value & 0x1f;
1692 /* TODO update clocks */
1693 break;
1694 case 0x148: /* CM_CLKSTCTRL_MPU */
1695 s->clkctrl[0] = value & 0x1f;
1696 break;
1697
1698 case 0x158: /* RM_RSTST_MPU */
1699 s->rst[0] &= ~value;
1700 break;
1701 case 0x1c8: /* PM_WKDEP_MPU */
1702 s->wkup[0] = value & 0x15;
1703 break;
1704
1705 case 0x1d4: /* PM_EVGENCTRL_MPU */
1706 s->ev = value & 0x1f;
1707 break;
1708 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1709 s->evtime[0] = value;
1710 break;
1711 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1712 s->evtime[1] = value;
1713 break;
1714
1715 case 0x1e0: /* PM_PWSTCTRL_MPU */
1716 s->power[0] = value & 0xc0f;
1717 break;
1718
1719 case 0x200: /* CM_FCLKEN1_CORE */
1720 s->clken[0] = value & 0xbfffffff;
1721 /* TODO update clocks */
99570a40 1722 /* The EN_EAC bit only gets/puts func_96m_clk. */
827df9f3
AZ		 1723 break;
1724 case 0x204: /* CM_FCLKEN2_CORE */
1725 s->clken[1] = value & 0x00000007;
1726 /* TODO update clocks */
1727 break;
1728 case 0x210: /* CM_ICLKEN1_CORE */
1729 s->clken[2] = value & 0xfffffff9;
1730 /* TODO update clocks */
99570a40 1731 /* The EN_EAC bit only gets/puts core_l4_iclk. */
827df9f3
AZ		 1732 break;
1733 case 0x214: /* CM_ICLKEN2_CORE */
1734 s->clken[3] = value & 0x00000007;
1735 /* TODO update clocks */
1736 break;
1737 case 0x21c: /* CM_ICLKEN4_CORE */
1738 s->clken[4] = value & 0x0000001f;
1739 /* TODO update clocks */
1740 break;
1741
1742 case 0x230: /* CM_AUTOIDLE1_CORE */
1743 s->clkidle[0] = value & 0xfffffff9;
1744 /* TODO update clocks */
1745 break;
1746 case 0x234: /* CM_AUTOIDLE2_CORE */
1747 s->clkidle[1] = value & 0x00000007;
1748 /* TODO update clocks */
1749 break;
1750 case 0x238: /* CM_AUTOIDLE3_CORE */
1751 s->clkidle[2] = value & 0x00000007;
1752 /* TODO update clocks */
1753 break;
1754 case 0x23c: /* CM_AUTOIDLE4_CORE */
1755 s->clkidle[3] = value & 0x0000001f;
1756 /* TODO update clocks */
1757 break;
1758
1759 case 0x240: /* CM_CLKSEL1_CORE */
1760 s->clksel[1] = value & 0x0fffbf7f;
1761 /* TODO update clocks */
1762 break;
1763
1764 case 0x244: /* CM_CLKSEL2_CORE */
1765 s->clksel[2] = value & 0x00fffffc;
1766 /* TODO update clocks */
1767 break;
1768
1769 case 0x248: /* CM_CLKSTCTRL_CORE */
1770 s->clkctrl[1] = value & 0x7;
1771 break;
1772
1773 case 0x2a0: /* PM_WKEN1_CORE */
1774 s->wken[0] = value & 0x04667ff8;
1775 break;
1776 case 0x2a4: /* PM_WKEN2_CORE */
1777 s->wken[1] = value & 0x00000005;
1778 break;
1779
1780 case 0x2b0: /* PM_WKST1_CORE */
1781 s->wkst[0] &= ~value;
1782 break;
1783 case 0x2b4: /* PM_WKST2_CORE */
1784 s->wkst[1] &= ~value;
1785 break;
1786
1787 case 0x2e0: /* PM_PWSTCTRL_CORE */
1788 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1789 break;
1790
1791 case 0x300: /* CM_FCLKEN_GFX */
1792 s->clken[5] = value & 6;
1793 /* TODO update clocks */
1794 break;
1795 case 0x310: /* CM_ICLKEN_GFX */
1796 s->clken[6] = value & 1;
1797 /* TODO update clocks */
1798 break;
1799 case 0x340: /* CM_CLKSEL_GFX */
1800 s->clksel[3] = value & 7;
1801 /* TODO update clocks */
1802 break;
1803 case 0x348: /* CM_CLKSTCTRL_GFX */
1804 s->clkctrl[2] = value & 1;
1805 break;
1806 case 0x350: /* RM_RSTCTRL_GFX */
1807 s->rstctrl[0] = value & 1;
1808 /* TODO: reset */
1809 break;
1810 case 0x358: /* RM_RSTST_GFX */
1811 s->rst[1] &= ~value;
1812 break;
1813 case 0x3c8: /* PM_WKDEP_GFX */
1814 s->wkup[1] = value & 0x13;
1815 break;
1816 case 0x3e0: /* PM_PWSTCTRL_GFX */
1817 s->power[2] = (value & 0x00c0f) | (3 << 2);
1818 break;
1819
1820 case 0x400: /* CM_FCLKEN_WKUP */
1821 s->clken[7] = value & 0xd;
1822 /* TODO update clocks */
1823 break;
1824 case 0x410: /* CM_ICLKEN_WKUP */
1825 s->clken[8] = value & 0x3f;
1826 /* TODO update clocks */
1827 break;
1828 case 0x430: /* CM_AUTOIDLE_WKUP */
1829 s->clkidle[4] = value & 0x0000003f;
1830 /* TODO update clocks */
1831 break;
1832 case 0x440: /* CM_CLKSEL_WKUP */
1833 s->clksel[4] = value & 3;
1834 /* TODO update clocks */
1835 break;
1836 case 0x450: /* RM_RSTCTRL_WKUP */
1837 /* TODO: reset */
1838 if (value & 2)
1839 qemu_system_reset_request();
1840 break;
1841 case 0x454: /* RM_RSTTIME_WKUP */
1842 s->rsttime_wkup = value & 0x1fff;
1843 break;
1844 case 0x458: /* RM_RSTST_WKUP */
1845 s->rst[2] &= ~value;
1846 break;
1847 case 0x4a0: /* PM_WKEN_WKUP */
1848 s->wken[2] = value & 0x00000005;
1849 break;
1850 case 0x4b0: /* PM_WKST_WKUP */
1851 s->wkst[2] &= ~value;
1852 break;
1853
1854 case 0x500: /* CM_CLKEN_PLL */
51fec3cc
AZ		 1855 if (value & 0xffffff30)
1856 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
1857 "future compatiblity\n", __FUNCTION__);
1858 if ((s->clken[9] ^ value) & 0xcc) {
1859 s->clken[9] &= ~0xcc;
1860 s->clken[9] |= value & 0xcc;
1861 omap_prcm_apll_update(s);
1862 }
1863 if ((s->clken[9] ^ value) & 3) {
1864 s->clken[9] &= ~3;
1865 s->clken[9] |= value & 3;
1866 omap_prcm_dpll_update(s);
1867 }
827df9f3
AZ		 1868 break;
1869 case 0x530: /* CM_AUTOIDLE_PLL */
1870 s->clkidle[5] = value & 0x000000cf;
1871 /* TODO update clocks */
1872 break;
1873 case 0x540: /* CM_CLKSEL1_PLL */
51fec3cc
AZ		 1874 if (value & 0xfc4000d7)
1875 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
1876 "future compatiblity\n", __FUNCTION__);
1877 if ((s->clksel[5] ^ value) & 0x003fff00) {
1878 s->clksel[5] = value & 0x03bfff28;
1879 omap_prcm_dpll_update(s);
1880 }
1881 /* TODO update the other clocks */
1882
827df9f3 1883 s->clksel[5] = value & 0x03bfff28;
827df9f3
AZ		 1884 break;
1885 case 0x544: /* CM_CLKSEL2_PLL */
51fec3cc
AZ		 1886 if (value & ~3)
1887 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1888 "future compatiblity\n", __FUNCTION__);
1889 if (s->clksel[6] != (value & 3)) {
1890 s->clksel[6] = value & 3;
1891 omap_prcm_dpll_update(s);
1892 }
827df9f3
AZ		 1893 break;
1894
1895 case 0x800: /* CM_FCLKEN_DSP */
1896 s->clken[10] = value & 0x501;
1897 /* TODO update clocks */
1898 break;
1899 case 0x810: /* CM_ICLKEN_DSP */
1900 s->clken[11] = value & 0x2;
1901 /* TODO update clocks */
1902 break;
1903 case 0x830: /* CM_AUTOIDLE_DSP */
1904 s->clkidle[6] = value & 0x2;
1905 /* TODO update clocks */
1906 break;
1907 case 0x840: /* CM_CLKSEL_DSP */
1908 s->clksel[7] = value & 0x3fff;
1909 /* TODO update clocks */
1910 break;
1911 case 0x848: /* CM_CLKSTCTRL_DSP */
1912 s->clkctrl[3] = value & 0x101;
1913 break;
1914 case 0x850: /* RM_RSTCTRL_DSP */
1915 /* TODO: reset */
1916 break;
1917 case 0x858: /* RM_RSTST_DSP */
1918 s->rst[3] &= ~value;
1919 break;
1920 case 0x8c8: /* PM_WKDEP_DSP */
1921 s->wkup[2] = value & 0x13;
1922 break;
1923 case 0x8e0: /* PM_PWSTCTRL_DSP */
1924 s->power[3] = (value & 0x03017) | (3 << 2);
1925 break;
1926
1927 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1928 s->irqst[1] &= ~value;
1929 omap_prcm_int_update(s, 1);
1930 break;
1931 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1932 s->irqen[1] = value & 0x7;
1933 omap_prcm_int_update(s, 1);
1934 break;
1935
1936 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1937 s->irqst[2] &= ~value;
1938 omap_prcm_int_update(s, 2);
1939 break;
1940 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1941 s->irqen[2] = value & 0x7;
1942 omap_prcm_int_update(s, 2);
1943 break;
1944
1945 default:
1946 OMAP_BAD_REG(addr);
1947 return;
1948 }
1949}
1950
d60efc6b 1951static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
827df9f3
AZ		 1952 omap_badwidth_read32,
1953 omap_badwidth_read32,
1954 omap_prcm_read,
1955};
1956
d60efc6b 1957static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
827df9f3
AZ		 1958 omap_badwidth_write32,
1959 omap_badwidth_write32,
1960 omap_prcm_write,
1961};
1962
1963static void omap_prcm_reset(struct omap_prcm_s *s)
1964{
1965 s->sysconfig = 0;
1966 s->irqst[0] = 0;
1967 s->irqst[1] = 0;
1968 s->irqst[2] = 0;
1969 s->irqen[0] = 0;
1970 s->irqen[1] = 0;
1971 s->irqen[2] = 0;
1972 s->voltctrl = 0x1040;
1973 s->ev = 0x14;
1974 s->evtime[0] = 0;
1975 s->evtime[1] = 0;
1976 s->clkctrl[0] = 0;
1977 s->clkctrl[1] = 0;
1978 s->clkctrl[2] = 0;
1979 s->clkctrl[3] = 0;
1980 s->clken[1] = 7;
1981 s->clken[3] = 7;
1982 s->clken[4] = 0;
1983 s->clken[5] = 0;
1984 s->clken[6] = 0;
1985 s->clken[7] = 0xc;
1986 s->clken[8] = 0x3e;
1987 s->clken[9] = 0x0d;
1988 s->clken[10] = 0;
1989 s->clken[11] = 0;
1990 s->clkidle[0] = 0;
1991 s->clkidle[2] = 7;
1992 s->clkidle[3] = 0;
1993 s->clkidle[4] = 0;
1994 s->clkidle[5] = 0x0c;
1995 s->clkidle[6] = 0;
1996 s->clksel[0] = 0x01;
1997 s->clksel[1] = 0x02100121;
1998 s->clksel[2] = 0x00000000;
1999 s->clksel[3] = 0x01;
2000 s->clksel[4] = 0;
2001 s->clksel[7] = 0x0121;
2002 s->wkup[0] = 0x15;
2003 s->wkup[1] = 0x13;
2004 s->wkup[2] = 0x13;
2005 s->wken[0] = 0x04667ff8;
2006 s->wken[1] = 0x00000005;
2007 s->wken[2] = 5;
2008 s->wkst[0] = 0;
2009 s->wkst[1] = 0;
2010 s->wkst[2] = 0;
2011 s->power[0] = 0x00c;
2012 s->power[1] = 4;
2013 s->power[2] = 0x0000c;
2014 s->power[3] = 0x14;
2015 s->rstctrl[0] = 1;
2016 s->rst[3] = 1;
51fec3cc
AZ		 2017 omap_prcm_apll_update(s);
2018 omap_prcm_dpll_update(s);
827df9f3
AZ		 2019}
2020
2021static void omap_prcm_coldreset(struct omap_prcm_s *s)
2022{
2023 s->setuptime[0] = 0;
2024 s->setuptime[1] = 0;
2025 memset(&s->scratch, 0, sizeof(s->scratch));
2026 s->rst[0] = 0x01;
2027 s->rst[1] = 0x00;
2028 s->rst[2] = 0x01;
2029 s->clken[0] = 0;
2030 s->clken[2] = 0;
2031 s->clkidle[1] = 0;
2032 s->clksel[5] = 0;
2033 s->clksel[6] = 2;
2034 s->clksrc[0] = 0x43;
2035 s->clkout[0] = 0x0303;
2036 s->clkemul[0] = 0;
2037 s->clkpol[0] = 0x100;
2038 s->rsttime_wkup = 0x1002;
2039
2040 omap_prcm_reset(s);
2041}
2042
2043struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
2044 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
2045 struct omap_mpu_state_s *mpu)
2046{
2047 int iomemtype;
2048 struct omap_prcm_s *s = (struct omap_prcm_s *)
2049 qemu_mallocz(sizeof(struct omap_prcm_s));
2050
2051 s->irq[0] = mpu_int;
2052 s->irq[1] = dsp_int;
2053 s->irq[2] = iva_int;
2054 s->mpu = mpu;
2055 omap_prcm_coldreset(s);
2056
1eed09cb 2057 iomemtype = l4_register_io_memory(omap_prcm_readfn,
827df9f3 2058 omap_prcm_writefn, s);
8da3ff18 2059 omap_l4_attach(ta, 0, iomemtype);
827df9f3
AZ		 2060 omap_l4_attach(ta, 1, iomemtype);
2061
2062 return s;
2063}
2064
2065/* System and Pinout control */
2066struct omap_sysctl_s {
827df9f3
AZ		 2067 struct omap_mpu_state_s *mpu;
2068
2069 uint32_t sysconfig;
2070 uint32_t devconfig;
2071 uint32_t psaconfig;
2072 uint32_t padconf[0x45];
2073 uint8_t obs;
2074 uint32_t msuspendmux[5];
2075};
2076
c227f099 2077static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
f451387a
AZ		 2078{
2079
2080 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
f451387a
AZ		 2081 int pad_offset, byte_offset;
2082 int value;
2083
8da3ff18 2084 switch (addr) {
f451387a 2085 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
8da3ff18
PB		 2086 pad_offset = (addr - 0x30) >> 2;
2087 byte_offset = (addr - 0x30) & (4 - 1);
f451387a
AZ		 2088
2089 value = s->padconf[pad_offset];
2090 value = (value >> (byte_offset * 8)) & 0xff;
2091
2092 return value;
2093
2094 default:
2095 break;
2096 }
2097
2098 OMAP_BAD_REG(addr);
2099 return 0;
2100}
2101
c227f099 2102static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
827df9f3
AZ		 2103{
2104 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
827df9f3 2105
8da3ff18 2106 switch (addr) {
827df9f3
AZ		 2107 case 0x000: /* CONTROL_REVISION */
2108 return 0x20;
2109
2110 case 0x010: /* CONTROL_SYSCONFIG */
2111 return s->sysconfig;
2112
2113 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
8da3ff18 2114 return s->padconf[(addr - 0x30) >> 2];
827df9f3
AZ		 2115
2116 case 0x270: /* CONTROL_DEBOBS */
2117 return s->obs;
2118
2119 case 0x274: /* CONTROL_DEVCONF */
2120 return s->devconfig;
2121
2122 case 0x28c: /* CONTROL_EMU_SUPPORT */
2123 return 0;
2124
2125 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2126 return s->msuspendmux[0];
2127 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2128 return s->msuspendmux[1];
2129 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2130 return s->msuspendmux[2];
2131 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2132 return s->msuspendmux[3];
2133 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2134 return s->msuspendmux[4];
2135 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2136 return 0;
2137
2138 case 0x2b8: /* CONTROL_PSA_CTRL */
2139 return s->psaconfig;
2140 case 0x2bc: /* CONTROL_PSA_CMD */
2141 case 0x2c0: /* CONTROL_PSA_VALUE */
2142 return 0;
2143
2144 case 0x2b0: /* CONTROL_SEC_CTRL */
2145 return 0x800000f1;
2146 case 0x2d0: /* CONTROL_SEC_EMU */
2147 return 0x80000015;
2148 case 0x2d4: /* CONTROL_SEC_TAP */
2149 return 0x8000007f;
2150 case 0x2b4: /* CONTROL_SEC_TEST */
2151 case 0x2f0: /* CONTROL_SEC_STATUS */
2152 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2153 /* Secure mode is not present on general-pusrpose device. Outside
2154 * secure mode these values cannot be read or written. */
2155 return 0;
2156
2157 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2158 return 0xff;
2159 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2160 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2161 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2162 /* No secure mode so no Extended Secure RAM present. */
2163 return 0;
2164
2165 case 0x2f8: /* CONTROL_STATUS */
2166 /* Device Type => General-purpose */
2167 return 0x0300;
2168 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2169
2170 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2171 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2172 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2173 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2174 return 0xdecafbad;
2175
2176 case 0x310: /* CONTROL_RAND_KEY_0 */
2177 case 0x314: /* CONTROL_RAND_KEY_1 */
2178 case 0x318: /* CONTROL_RAND_KEY_2 */
2179 case 0x31c: /* CONTROL_RAND_KEY_3 */
2180 case 0x320: /* CONTROL_CUST_KEY_0 */
2181 case 0x324: /* CONTROL_CUST_KEY_1 */
2182 case 0x330: /* CONTROL_TEST_KEY_0 */
2183 case 0x334: /* CONTROL_TEST_KEY_1 */
2184 case 0x338: /* CONTROL_TEST_KEY_2 */
2185 case 0x33c: /* CONTROL_TEST_KEY_3 */
2186 case 0x340: /* CONTROL_TEST_KEY_4 */
2187 case 0x344: /* CONTROL_TEST_KEY_5 */
2188 case 0x348: /* CONTROL_TEST_KEY_6 */
2189 case 0x34c: /* CONTROL_TEST_KEY_7 */
2190 case 0x350: /* CONTROL_TEST_KEY_8 */
2191 case 0x354: /* CONTROL_TEST_KEY_9 */
2192 /* Can only be accessed in secure mode and when C_FieldAccEnable
2193 * bit is set in CONTROL_SEC_CTRL.
2194 * TODO: otherwise an interconnect access error is generated. */
2195 return 0;
2196 }
2197
2198 OMAP_BAD_REG(addr);
2199 return 0;
2200}
2201
c227f099 2202static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
f451387a
AZ		 2203 uint32_t value)
2204{
2205 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
f451387a
AZ		 2206 int pad_offset, byte_offset;
2207 int prev_value;
2208
8da3ff18 2209 switch (addr) {
f451387a 2210 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
8da3ff18
PB		 2211 pad_offset = (addr - 0x30) >> 2;
2212 byte_offset = (addr - 0x30) & (4 - 1);
f451387a
AZ		 2213
2214 prev_value = s->padconf[pad_offset];
2215 prev_value &= ~(0xff << (byte_offset * 8));
2216 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
2217 s->padconf[pad_offset] = prev_value;
2218 break;
2219
2220 default:
2221 OMAP_BAD_REG(addr);
2222 break;
2223 }
2224}
2225
c227f099 2226static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
827df9f3
AZ		 2227 uint32_t value)
2228{
2229 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
827df9f3 2230
8da3ff18 2231 switch (addr) {
827df9f3
AZ		 2232 case 0x000: /* CONTROL_REVISION */
2233 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2234 case 0x2c0: /* CONTROL_PSA_VALUE */
2235 case 0x2f8: /* CONTROL_STATUS */
2236 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2237 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2238 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2239 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2240 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2241 case 0x310: /* CONTROL_RAND_KEY_0 */
2242 case 0x314: /* CONTROL_RAND_KEY_1 */
2243 case 0x318: /* CONTROL_RAND_KEY_2 */
2244 case 0x31c: /* CONTROL_RAND_KEY_3 */
2245 case 0x320: /* CONTROL_CUST_KEY_0 */
2246 case 0x324: /* CONTROL_CUST_KEY_1 */
2247 case 0x330: /* CONTROL_TEST_KEY_0 */
2248 case 0x334: /* CONTROL_TEST_KEY_1 */
2249 case 0x338: /* CONTROL_TEST_KEY_2 */
2250 case 0x33c: /* CONTROL_TEST_KEY_3 */
2251 case 0x340: /* CONTROL_TEST_KEY_4 */
2252 case 0x344: /* CONTROL_TEST_KEY_5 */
2253 case 0x348: /* CONTROL_TEST_KEY_6 */
2254 case 0x34c: /* CONTROL_TEST_KEY_7 */
2255 case 0x350: /* CONTROL_TEST_KEY_8 */
2256 case 0x354: /* CONTROL_TEST_KEY_9 */
2257 OMAP_RO_REG(addr);
2258 return;
2259
2260 case 0x010: /* CONTROL_SYSCONFIG */
2261 s->sysconfig = value & 0x1e;
2262 break;
2263
2264 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2265 /* XXX: should check constant bits */
8da3ff18 2266 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
827df9f3
AZ		 2267 break;
2268
2269 case 0x270: /* CONTROL_DEBOBS */
2270 s->obs = value & 0xff;
2271 break;
2272
2273 case 0x274: /* CONTROL_DEVCONF */
2274 s->devconfig = value & 0xffffc7ff;
2275 break;
2276
2277 case 0x28c: /* CONTROL_EMU_SUPPORT */
2278 break;
2279
2280 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2281 s->msuspendmux[0] = value & 0x3fffffff;
2282 break;
2283 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2284 s->msuspendmux[1] = value & 0x3fffffff;
2285 break;
2286 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2287 s->msuspendmux[2] = value & 0x3fffffff;
2288 break;
2289 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2290 s->msuspendmux[3] = value & 0x3fffffff;
2291 break;
2292 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2293 s->msuspendmux[4] = value & 0x3fffffff;
2294 break;
2295
2296 case 0x2b8: /* CONTROL_PSA_CTRL */
2297 s->psaconfig = value & 0x1c;
2298 s->psaconfig |= (value & 0x20) ? 2 : 1;
2299 break;
2300 case 0x2bc: /* CONTROL_PSA_CMD */
2301 break;
2302
2303 case 0x2b0: /* CONTROL_SEC_CTRL */
2304 case 0x2b4: /* CONTROL_SEC_TEST */
2305 case 0x2d0: /* CONTROL_SEC_EMU */
2306 case 0x2d4: /* CONTROL_SEC_TAP */
2307 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2308 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2309 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2310 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2311 case 0x2f0: /* CONTROL_SEC_STATUS */
2312 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2313 break;
2314
2315 default:
2316 OMAP_BAD_REG(addr);
2317 return;
2318 }
2319}
2320
d60efc6b 2321static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
f451387a 2322 omap_sysctl_read8,
827df9f3
AZ		 2323 omap_badwidth_read32, /* TODO */
2324 omap_sysctl_read,
2325};
2326
d60efc6b 2327static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
f451387a 2328 omap_sysctl_write8,
827df9f3
AZ		 2329 omap_badwidth_write32, /* TODO */
2330 omap_sysctl_write,
2331};
2332
2333static void omap_sysctl_reset(struct omap_sysctl_s *s)
2334{
2335 /* (power-on reset) */
2336 s->sysconfig = 0;
2337 s->obs = 0;
2338 s->devconfig = 0x0c000000;
2339 s->msuspendmux[0] = 0x00000000;
2340 s->msuspendmux[1] = 0x00000000;
2341 s->msuspendmux[2] = 0x00000000;
2342 s->msuspendmux[3] = 0x00000000;
2343 s->msuspendmux[4] = 0x00000000;
2344 s->psaconfig = 1;
2345
2346 s->padconf[0x00] = 0x000f0f0f;
2347 s->padconf[0x01] = 0x00000000;
2348 s->padconf[0x02] = 0x00000000;
2349 s->padconf[0x03] = 0x00000000;
2350 s->padconf[0x04] = 0x00000000;
2351 s->padconf[0x05] = 0x00000000;
2352 s->padconf[0x06] = 0x00000000;
2353 s->padconf[0x07] = 0x00000000;
2354 s->padconf[0x08] = 0x08080800;
2355 s->padconf[0x09] = 0x08080808;
2356 s->padconf[0x0a] = 0x08080808;
2357 s->padconf[0x0b] = 0x08080808;
2358 s->padconf[0x0c] = 0x08080808;
2359 s->padconf[0x0d] = 0x08080800;
2360 s->padconf[0x0e] = 0x08080808;
2361 s->padconf[0x0f] = 0x08080808;
2362 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2363 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2364 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2365 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2366 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2367 s->padconf[0x15] = 0x18181818;
2368 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2369 s->padconf[0x17] = 0x1f001f00;
2370 s->padconf[0x18] = 0x1f1f1f1f;
2371 s->padconf[0x19] = 0x00000000;
2372 s->padconf[0x1a] = 0x1f180000;
2373 s->padconf[0x1b] = 0x00001f1f;
2374 s->padconf[0x1c] = 0x1f001f00;
2375 s->padconf[0x1d] = 0x00000000;
2376 s->padconf[0x1e] = 0x00000000;
2377 s->padconf[0x1f] = 0x08000000;
2378 s->padconf[0x20] = 0x08080808;
2379 s->padconf[0x21] = 0x08080808;
2380 s->padconf[0x22] = 0x0f080808;
2381 s->padconf[0x23] = 0x0f0f0f0f;
2382 s->padconf[0x24] = 0x000f0f0f;
2383 s->padconf[0x25] = 0x1f1f1f0f;
2384 s->padconf[0x26] = 0x080f0f1f;
2385 s->padconf[0x27] = 0x070f1808;
2386 s->padconf[0x28] = 0x0f070707;
2387 s->padconf[0x29] = 0x000f0f1f;
2388 s->padconf[0x2a] = 0x0f0f0f1f;
2389 s->padconf[0x2b] = 0x08000000;
2390 s->padconf[0x2c] = 0x0000001f;
2391 s->padconf[0x2d] = 0x0f0f1f00;
2392 s->padconf[0x2e] = 0x1f1f0f0f;
2393 s->padconf[0x2f] = 0x0f1f1f1f;
2394 s->padconf[0x30] = 0x0f0f0f0f;
2395 s->padconf[0x31] = 0x0f1f0f1f;
2396 s->padconf[0x32] = 0x0f0f0f0f;
2397 s->padconf[0x33] = 0x0f1f0f1f;
2398 s->padconf[0x34] = 0x1f1f0f0f;
2399 s->padconf[0x35] = 0x0f0f1f1f;
2400 s->padconf[0x36] = 0x0f0f1f0f;
2401 s->padconf[0x37] = 0x0f0f0f0f;
2402 s->padconf[0x38] = 0x1f18180f;
2403 s->padconf[0x39] = 0x1f1f1f1f;
2404 s->padconf[0x3a] = 0x00001f1f;
2405 s->padconf[0x3b] = 0x00000000;
2406 s->padconf[0x3c] = 0x00000000;
2407 s->padconf[0x3d] = 0x0f0f0f0f;
2408 s->padconf[0x3e] = 0x18000f0f;
2409 s->padconf[0x3f] = 0x00070000;
2410 s->padconf[0x40] = 0x00000707;
2411 s->padconf[0x41] = 0x0f1f0700;
2412 s->padconf[0x42] = 0x1f1f070f;
2413 s->padconf[0x43] = 0x0008081f;
2414 s->padconf[0x44] = 0x00000800;
2415}
2416
2417struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2418 omap_clk iclk, struct omap_mpu_state_s *mpu)
2419{
2420 int iomemtype;
2421 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
2422 qemu_mallocz(sizeof(struct omap_sysctl_s));
2423
2424 s->mpu = mpu;
2425 omap_sysctl_reset(s);
2426
1eed09cb 2427 iomemtype = l4_register_io_memory(omap_sysctl_readfn,
827df9f3 2428 omap_sysctl_writefn, s);
8da3ff18 2429 omap_l4_attach(ta, 0, iomemtype);
827df9f3
AZ		 2430
2431 return s;
2432}
2433
827df9f3
AZ		 2434/* General chip reset */
2435static void omap2_mpu_reset(void *opaque)
2436{
2437 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2438
2439 omap_inth_reset(mpu->ih[0]);
2440 omap_dma_reset(mpu->dma);
2441 omap_prcm_reset(mpu->prcm);
2442 omap_sysctl_reset(mpu->sysc);
2443 omap_gp_timer_reset(mpu->gptimer[0]);
2444 omap_gp_timer_reset(mpu->gptimer[1]);
2445 omap_gp_timer_reset(mpu->gptimer[2]);
2446 omap_gp_timer_reset(mpu->gptimer[3]);
2447 omap_gp_timer_reset(mpu->gptimer[4]);
2448 omap_gp_timer_reset(mpu->gptimer[5]);
2449 omap_gp_timer_reset(mpu->gptimer[6]);
2450 omap_gp_timer_reset(mpu->gptimer[7]);
2451 omap_gp_timer_reset(mpu->gptimer[8]);
2452 omap_gp_timer_reset(mpu->gptimer[9]);
2453 omap_gp_timer_reset(mpu->gptimer[10]);
2454 omap_gp_timer_reset(mpu->gptimer[11]);
011d87d0 2455 omap_synctimer_reset(mpu->synctimer);
827df9f3
AZ		 2456 omap_sdrc_reset(mpu->sdrc);
2457 omap_gpmc_reset(mpu->gpmc);
2458 omap_dss_reset(mpu->dss);
2459 omap_uart_reset(mpu->uart[0]);
2460 omap_uart_reset(mpu->uart[1]);
2461 omap_uart_reset(mpu->uart[2]);
2462 omap_mmc_reset(mpu->mmc);
2463 omap_gpif_reset(mpu->gpif);
2464 omap_mcspi_reset(mpu->mcspi[0]);
2465 omap_mcspi_reset(mpu->mcspi[1]);
2466 omap_i2c_reset(mpu->i2c[0]);
2467 omap_i2c_reset(mpu->i2c[1]);
2468 cpu_reset(mpu->env);
2469}
2470
2471static int omap2_validate_addr(struct omap_mpu_state_s *s,
c227f099 2472 target_phys_addr_t addr)
827df9f3
AZ		 2473{
2474 return 1;
2475}
2476
2477static const struct dma_irq_map omap2_dma_irq_map[] = {
2478 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2479 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2480 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2481 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2482};
2483
2484struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
3023f332 2485 const char *core)
827df9f3
AZ		 2486{
2487 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
2488 qemu_mallocz(sizeof(struct omap_mpu_state_s));
c227f099 2489 ram_addr_t sram_base, q2_base;
827df9f3
AZ		 2490 qemu_irq *cpu_irq;
2491 qemu_irq dma_irqs[4];
2492 omap_clk gpio_clks[4];
751c6a17 2493 DriveInfo *dinfo;
827df9f3
AZ		 2494 int i;
2495
2496 /* Core */
2497 s->mpu_model = omap2420;
2498 s->env = cpu_init(core ?: "arm1136-r2");
2499 if (!s->env) {
2500 fprintf(stderr, "Unable to find CPU definition\n");
2501 exit(1);
2502 }
2503 s->sdram_size = sdram_size;
2504 s->sram_size = OMAP242X_SRAM_SIZE;
2505
2506 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
2507
2508 /* Clocks */
2509 omap_clk_init(s);
2510
2511 /* Memory-mapped stuff */
2512 cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
7e7c5e4c 2513 (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
827df9f3
AZ		 2514 cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
2515 (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
2516
2517 s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
2518
2519 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2520 cpu_irq = arm_pic_init_cpu(s->env);
2521 s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
2522 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
2523 omap_findclk(s, "mpu_intc_fclk"),
2524 omap_findclk(s, "mpu_intc_iclk"));
2525
2526 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
2527 s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
2528
2529 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2530 omap_findclk(s, "omapctrl_iclk"), s);
2531
2532 for (i = 0; i < 4; i ++)
2533 dma_irqs[i] =
2534 s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
2535 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
2536 omap_findclk(s, "sdma_iclk"),
2537 omap_findclk(s, "sdma_fclk"));
2538 s->port->addr_valid = omap2_validate_addr;
2539
afbb5194
AZ		 2540 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2541 soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
2542 soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
2543
827df9f3
AZ		 2544 s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
2545 s->irq[0][OMAP_INT_24XX_UART1_IRQ],
2546 omap_findclk(s, "uart1_fclk"),
2547 omap_findclk(s, "uart1_iclk"),
2548 s->drq[OMAP24XX_DMA_UART1_TX],
2549 s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
2550 s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
2551 s->irq[0][OMAP_INT_24XX_UART2_IRQ],
2552 omap_findclk(s, "uart2_fclk"),
2553 omap_findclk(s, "uart2_iclk"),
2554 s->drq[OMAP24XX_DMA_UART2_TX],
2555 s->drq[OMAP24XX_DMA_UART2_RX],
b9d38e95 2556 serial_hds[0] ? serial_hds[1] : NULL);
827df9f3
AZ		 2557 s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
2558 s->irq[0][OMAP_INT_24XX_UART3_IRQ],
2559 omap_findclk(s, "uart3_fclk"),
2560 omap_findclk(s, "uart3_iclk"),
2561 s->drq[OMAP24XX_DMA_UART3_TX],
2562 s->drq[OMAP24XX_DMA_UART3_RX],
b9d38e95 2563 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
827df9f3
AZ		 2564
2565 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
2566 s->irq[0][OMAP_INT_24XX_GPTIMER1],
2567 omap_findclk(s, "wu_gpt1_clk"),
2568 omap_findclk(s, "wu_l4_iclk"));
2569 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
2570 s->irq[0][OMAP_INT_24XX_GPTIMER2],
2571 omap_findclk(s, "core_gpt2_clk"),
2572 omap_findclk(s, "core_l4_iclk"));
2573 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
2574 s->irq[0][OMAP_INT_24XX_GPTIMER3],
2575 omap_findclk(s, "core_gpt3_clk"),
2576 omap_findclk(s, "core_l4_iclk"));
2577 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
2578 s->irq[0][OMAP_INT_24XX_GPTIMER4],
2579 omap_findclk(s, "core_gpt4_clk"),
2580 omap_findclk(s, "core_l4_iclk"));
2581 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
2582 s->irq[0][OMAP_INT_24XX_GPTIMER5],
2583 omap_findclk(s, "core_gpt5_clk"),
2584 omap_findclk(s, "core_l4_iclk"));
2585 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
2586 s->irq[0][OMAP_INT_24XX_GPTIMER6],
2587 omap_findclk(s, "core_gpt6_clk"),
2588 omap_findclk(s, "core_l4_iclk"));
2589 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
2590 s->irq[0][OMAP_INT_24XX_GPTIMER7],
2591 omap_findclk(s, "core_gpt7_clk"),
2592 omap_findclk(s, "core_l4_iclk"));
2593 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
2594 s->irq[0][OMAP_INT_24XX_GPTIMER8],
2595 omap_findclk(s, "core_gpt8_clk"),
2596 omap_findclk(s, "core_l4_iclk"));
2597 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
2598 s->irq[0][OMAP_INT_24XX_GPTIMER9],
2599 omap_findclk(s, "core_gpt9_clk"),
2600 omap_findclk(s, "core_l4_iclk"));
2601 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
2602 s->irq[0][OMAP_INT_24XX_GPTIMER10],
2603 omap_findclk(s, "core_gpt10_clk"),
2604 omap_findclk(s, "core_l4_iclk"));
2605 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
2606 s->irq[0][OMAP_INT_24XX_GPTIMER11],
2607 omap_findclk(s, "core_gpt11_clk"),
2608 omap_findclk(s, "core_l4_iclk"));
2609 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
2610 s->irq[0][OMAP_INT_24XX_GPTIMER12],
2611 omap_findclk(s, "core_gpt12_clk"),
2612 omap_findclk(s, "core_l4_iclk"));
2613
2614 omap_tap_init(omap_l4ta(s->l4, 2), s);
2615
011d87d0 2616 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
827df9f3
AZ		 2617 omap_findclk(s, "clk32-kHz"),
2618 omap_findclk(s, "core_l4_iclk"));
2619
2620 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
2621 s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
2622 &s->drq[OMAP24XX_DMA_I2C1_TX],
2623 omap_findclk(s, "i2c1.fclk"),
2624 omap_findclk(s, "i2c1.iclk"));
2625 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
2626 s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
2627 &s->drq[OMAP24XX_DMA_I2C2_TX],
2628 omap_findclk(s, "i2c2.fclk"),
2629 omap_findclk(s, "i2c2.iclk"));
2630
2631 gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
2632 gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
2633 gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
2634 gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
2635 s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
2636 &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
2637 gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
2638
2639 s->sdrc = omap_sdrc_init(0x68009000);
2640 s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
2641
751c6a17
GH		 2642 dinfo = drive_get(IF_SD, 0, 0);
2643 if (!dinfo) {
827df9f3
AZ		 2644 fprintf(stderr, "qemu: missing SecureDigital device\n");
2645 exit(1);
2646 }
751c6a17 2647 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
827df9f3
AZ		 2648 s->irq[0][OMAP_INT_24XX_MMC_IRQ],
2649 &s->drq[OMAP24XX_DMA_MMC1_TX],
2650 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2651
2652 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
99570a40 2653 s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
827df9f3
AZ		 2654 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2655 omap_findclk(s, "spi1_fclk"),
2656 omap_findclk(s, "spi1_iclk"));
2657 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
99570a40 2658 s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
827df9f3
AZ		 2659 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2660 omap_findclk(s, "spi2_fclk"),
2661 omap_findclk(s, "spi2_iclk"));
2662
3023f332 2663 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
827df9f3
AZ		 2664 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2665 s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
2666 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2667 omap_findclk(s, "dss_54m_clk"),
2668 omap_findclk(s, "dss_l3_iclk"),
2669 omap_findclk(s, "dss_l4_iclk"));
2670
54585ffe
AZ		 2671 omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
2672 s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
2673 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
b9d38e95 2674 serial_hds[3] : NULL);
54585ffe 2675
99570a40
AZ		 2676 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
2677 s->irq[0][OMAP_INT_24XX_EAC_IRQ],
2678 /* Ten consecutive lines */
2679 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2680 omap_findclk(s, "func_96m_clk"),
2681 omap_findclk(s, "core_l4_iclk"));
2682
827df9f3
AZ		 2683 /* All register mappings (includin those not currenlty implemented):
2684 * SystemControlMod 48000000 - 48000fff
2685 * SystemControlL4 48001000 - 48001fff
2686 * 32kHz Timer Mod 48004000 - 48004fff
2687 * 32kHz Timer L4 48005000 - 48005fff
2688 * PRCM ModA 48008000 - 480087ff
2689 * PRCM ModB 48008800 - 48008fff
2690 * PRCM L4 48009000 - 48009fff
2691 * TEST-BCM Mod 48012000 - 48012fff
2692 * TEST-BCM L4 48013000 - 48013fff
2693 * TEST-TAP Mod 48014000 - 48014fff
2694 * TEST-TAP L4 48015000 - 48015fff
2695 * GPIO1 Mod 48018000 - 48018fff
2696 * GPIO Top 48019000 - 48019fff
2697 * GPIO2 Mod 4801a000 - 4801afff
2698 * GPIO L4 4801b000 - 4801bfff
2699 * GPIO3 Mod 4801c000 - 4801cfff
2700 * GPIO4 Mod 4801e000 - 4801efff
2701 * WDTIMER1 Mod 48020000 - 48010fff
2702 * WDTIMER Top 48021000 - 48011fff
2703 * WDTIMER2 Mod 48022000 - 48012fff
2704 * WDTIMER L4 48023000 - 48013fff
2705 * WDTIMER3 Mod 48024000 - 48014fff
2706 * WDTIMER3 L4 48025000 - 48015fff
2707 * WDTIMER4 Mod 48026000 - 48016fff
2708 * WDTIMER4 L4 48027000 - 48017fff
2709 * GPTIMER1 Mod 48028000 - 48018fff
2710 * GPTIMER1 L4 48029000 - 48019fff
2711 * GPTIMER2 Mod 4802a000 - 4801afff
2712 * GPTIMER2 L4 4802b000 - 4801bfff
2713 * L4-Config AP 48040000 - 480407ff
2714 * L4-Config IP 48040800 - 48040fff
2715 * L4-Config LA 48041000 - 48041fff
2716 * ARM11ETB Mod 48048000 - 48049fff
2717 * ARM11ETB L4 4804a000 - 4804afff
2718 * DISPLAY Top 48050000 - 480503ff
2719 * DISPLAY DISPC 48050400 - 480507ff
2720 * DISPLAY RFBI 48050800 - 48050bff
2721 * DISPLAY VENC 48050c00 - 48050fff
2722 * DISPLAY L4 48051000 - 48051fff
2723 * CAMERA Top 48052000 - 480523ff
2724 * CAMERA core 48052400 - 480527ff
2725 * CAMERA DMA 48052800 - 48052bff
2726 * CAMERA MMU 48052c00 - 48052fff
2727 * CAMERA L4 48053000 - 48053fff
2728 * SDMA Mod 48056000 - 48056fff
2729 * SDMA L4 48057000 - 48057fff
2730 * SSI Top 48058000 - 48058fff
2731 * SSI GDD 48059000 - 48059fff
2732 * SSI Port1 4805a000 - 4805afff
2733 * SSI Port2 4805b000 - 4805bfff
2734 * SSI L4 4805c000 - 4805cfff
2735 * USB Mod 4805e000 - 480fefff
2736 * USB L4 4805f000 - 480fffff
2737 * WIN_TRACER1 Mod 48060000 - 48060fff
2738 * WIN_TRACER1 L4 48061000 - 48061fff
2739 * WIN_TRACER2 Mod 48062000 - 48062fff
2740 * WIN_TRACER2 L4 48063000 - 48063fff
2741 * WIN_TRACER3 Mod 48064000 - 48064fff
2742 * WIN_TRACER3 L4 48065000 - 48065fff
2743 * WIN_TRACER4 Top 48066000 - 480660ff
2744 * WIN_TRACER4 ETT 48066100 - 480661ff
2745 * WIN_TRACER4 WT 48066200 - 480662ff
2746 * WIN_TRACER4 L4 48067000 - 48067fff
2747 * XTI Mod 48068000 - 48068fff
2748 * XTI L4 48069000 - 48069fff
2749 * UART1 Mod 4806a000 - 4806afff
2750 * UART1 L4 4806b000 - 4806bfff
2751 * UART2 Mod 4806c000 - 4806cfff
2752 * UART2 L4 4806d000 - 4806dfff
2753 * UART3 Mod 4806e000 - 4806efff
2754 * UART3 L4 4806f000 - 4806ffff
2755 * I2C1 Mod 48070000 - 48070fff
2756 * I2C1 L4 48071000 - 48071fff
2757 * I2C2 Mod 48072000 - 48072fff
2758 * I2C2 L4 48073000 - 48073fff
2759 * McBSP1 Mod 48074000 - 48074fff
2760 * McBSP1 L4 48075000 - 48075fff
2761 * McBSP2 Mod 48076000 - 48076fff
2762 * McBSP2 L4 48077000 - 48077fff
2763 * GPTIMER3 Mod 48078000 - 48078fff
2764 * GPTIMER3 L4 48079000 - 48079fff
2765 * GPTIMER4 Mod 4807a000 - 4807afff
2766 * GPTIMER4 L4 4807b000 - 4807bfff
2767 * GPTIMER5 Mod 4807c000 - 4807cfff
2768 * GPTIMER5 L4 4807d000 - 4807dfff
2769 * GPTIMER6 Mod 4807e000 - 4807efff
2770 * GPTIMER6 L4 4807f000 - 4807ffff
2771 * GPTIMER7 Mod 48080000 - 48080fff
2772 * GPTIMER7 L4 48081000 - 48081fff
2773 * GPTIMER8 Mod 48082000 - 48082fff
2774 * GPTIMER8 L4 48083000 - 48083fff
2775 * GPTIMER9 Mod 48084000 - 48084fff
2776 * GPTIMER9 L4 48085000 - 48085fff
2777 * GPTIMER10 Mod 48086000 - 48086fff
2778 * GPTIMER10 L4 48087000 - 48087fff
2779 * GPTIMER11 Mod 48088000 - 48088fff
2780 * GPTIMER11 L4 48089000 - 48089fff
2781 * GPTIMER12 Mod 4808a000 - 4808afff
2782 * GPTIMER12 L4 4808b000 - 4808bfff
2783 * EAC Mod 48090000 - 48090fff
2784 * EAC L4 48091000 - 48091fff
2785 * FAC Mod 48092000 - 48092fff
2786 * FAC L4 48093000 - 48093fff
2787 * MAILBOX Mod 48094000 - 48094fff
2788 * MAILBOX L4 48095000 - 48095fff
2789 * SPI1 Mod 48098000 - 48098fff
2790 * SPI1 L4 48099000 - 48099fff
2791 * SPI2 Mod 4809a000 - 4809afff
2792 * SPI2 L4 4809b000 - 4809bfff
2793 * MMC/SDIO Mod 4809c000 - 4809cfff
2794 * MMC/SDIO L4 4809d000 - 4809dfff
2795 * MS_PRO Mod 4809e000 - 4809efff
2796 * MS_PRO L4 4809f000 - 4809ffff
2797 * RNG Mod 480a0000 - 480a0fff
2798 * RNG L4 480a1000 - 480a1fff
2799 * DES3DES Mod 480a2000 - 480a2fff
2800 * DES3DES L4 480a3000 - 480a3fff
2801 * SHA1MD5 Mod 480a4000 - 480a4fff
2802 * SHA1MD5 L4 480a5000 - 480a5fff
2803 * AES Mod 480a6000 - 480a6fff
2804 * AES L4 480a7000 - 480a7fff
2805 * PKA Mod 480a8000 - 480a9fff
2806 * PKA L4 480aa000 - 480aafff
2807 * MG Mod 480b0000 - 480b0fff
2808 * MG L4 480b1000 - 480b1fff
2809 * HDQ/1-wire Mod 480b2000 - 480b2fff
2810 * HDQ/1-wire L4 480b3000 - 480b3fff
2811 * MPU interrupt 480fe000 - 480fefff
54585ffe 2812 * STI channel base 54000000 - 5400ffff
827df9f3
AZ		 2813 * IVA RAM 5c000000 - 5c01ffff
2814 * IVA ROM 5c020000 - 5c027fff
2815 * IMG_BUF_A 5c040000 - 5c040fff
2816 * IMG_BUF_B 5c042000 - 5c042fff
2817 * VLCDS 5c048000 - 5c0487ff
2818 * IMX_COEF 5c049000 - 5c04afff
2819 * IMX_CMD 5c051000 - 5c051fff
2820 * VLCDQ 5c053000 - 5c0533ff
2821 * VLCDH 5c054000 - 5c054fff
2822 * SEQ_CMD 5c055000 - 5c055fff
2823 * IMX_REG 5c056000 - 5c0560ff
2824 * VLCD_REG 5c056100 - 5c0561ff
2825 * SEQ_REG 5c056200 - 5c0562ff
2826 * IMG_BUF_REG 5c056300 - 5c0563ff
2827 * SEQIRQ_REG 5c056400 - 5c0564ff
2828 * OCP_REG 5c060000 - 5c060fff
2829 * SYSC_REG 5c070000 - 5c070fff
2830 * MMU_REG 5d000000 - 5d000fff
2831 * sDMA R 68000400 - 680005ff
2832 * sDMA W 68000600 - 680007ff
2833 * Display Control 68000800 - 680009ff
2834 * DSP subsystem 68000a00 - 68000bff
2835 * MPU subsystem 68000c00 - 68000dff
2836 * IVA subsystem 68001000 - 680011ff
2837 * USB 68001200 - 680013ff
2838 * Camera 68001400 - 680015ff
2839 * VLYNQ (firewall) 68001800 - 68001bff
2840 * VLYNQ 68001e00 - 68001fff
2841 * SSI 68002000 - 680021ff
2842 * L4 68002400 - 680025ff
2843 * DSP (firewall) 68002800 - 68002bff
2844 * DSP subsystem 68002e00 - 68002fff
2845 * IVA (firewall) 68003000 - 680033ff
2846 * IVA 68003600 - 680037ff
2847 * GFX 68003a00 - 68003bff
2848 * CMDWR emulation 68003c00 - 68003dff
2849 * SMS 68004000 - 680041ff
2850 * OCM 68004200 - 680043ff
2851 * GPMC 68004400 - 680045ff
2852 * RAM (firewall) 68005000 - 680053ff
2853 * RAM (err login) 68005400 - 680057ff
2854 * ROM (firewall) 68005800 - 68005bff
2855 * ROM (err login) 68005c00 - 68005fff
2856 * GPMC (firewall) 68006000 - 680063ff
2857 * GPMC (err login) 68006400 - 680067ff
2858 * SMS (err login) 68006c00 - 68006fff
2859 * SMS registers 68008000 - 68008fff
2860 * SDRC registers 68009000 - 68009fff
2861 * GPMC registers 6800a000 6800afff
2862 */
2863
a08d4367 2864 qemu_register_reset(omap2_mpu_reset, s);
827df9f3
AZ		 2865
2866 return s;
2867}
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