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dbda808a FB |
1 | /* |
2 | * OpenPIC emulation | |
5fafdf24 | 3 | * |
dbda808a | 4 | * Copyright (c) 2004 Jocelyn Mayer |
704c7e5d | 5 | * 2011 Alexander Graf |
5fafdf24 | 6 | * |
dbda808a FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | /* | |
26 | * | |
27 | * Based on OpenPic implementations: | |
67b55785 | 28 | * - Intel GW80314 I/O companion chip developer's manual |
dbda808a FB |
29 | * - Motorola MPC8245 & MPC8540 user manuals. |
30 | * - Motorola MCP750 (aka Raven) programmer manual. | |
31 | * - Motorola Harrier programmer manuel | |
32 | * | |
33 | * Serial interrupts, as implemented in Raven chipset are not supported yet. | |
5fafdf24 | 34 | * |
dbda808a | 35 | */ |
87ecb68b PB |
36 | #include "hw.h" |
37 | #include "ppc_mac.h" | |
a2cb15b0 | 38 | #include "pci/pci.h" |
b7169916 | 39 | #include "openpic.h" |
d0b72631 | 40 | #include "sysbus.h" |
6f991980 | 41 | #include "pci/msi.h" |
dbda808a | 42 | |
611493d9 | 43 | //#define DEBUG_OPENPIC |
dbda808a FB |
44 | |
45 | #ifdef DEBUG_OPENPIC | |
001faf32 | 46 | #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
dbda808a | 47 | #else |
001faf32 | 48 | #define DPRINTF(fmt, ...) do { } while (0) |
dbda808a | 49 | #endif |
dbda808a | 50 | |
cdbb912a AG |
51 | #define MAX_CPU 15 |
52 | #define MAX_SRC 256 | |
dbda808a | 53 | #define MAX_TMR 4 |
dbda808a | 54 | #define MAX_IPI 4 |
732aa6ec | 55 | #define MAX_MSI 8 |
cdbb912a | 56 | #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR) |
dbda808a | 57 | #define VID 0x03 /* MPIC version ID */ |
dbda808a | 58 | |
d0b72631 AG |
59 | /* OpenPIC capability flags */ |
60 | #define OPENPIC_FLAG_IDE_CRIT (1 << 0) | |
dbda808a | 61 | |
d0b72631 | 62 | /* OpenPIC address map */ |
780d16b7 AG |
63 | #define OPENPIC_GLB_REG_START 0x0 |
64 | #define OPENPIC_GLB_REG_SIZE 0x10F0 | |
65 | #define OPENPIC_TMR_REG_START 0x10F0 | |
66 | #define OPENPIC_TMR_REG_SIZE 0x220 | |
732aa6ec AG |
67 | #define OPENPIC_MSI_REG_START 0x1600 |
68 | #define OPENPIC_MSI_REG_SIZE 0x200 | |
780d16b7 AG |
69 | #define OPENPIC_SRC_REG_START 0x10000 |
70 | #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20) | |
71 | #define OPENPIC_CPU_REG_START 0x20000 | |
72 | #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) | |
73 | ||
d0b72631 AG |
74 | /* Raven */ |
75 | #define RAVEN_MAX_CPU 2 | |
76 | #define RAVEN_MAX_EXT 48 | |
77 | #define RAVEN_MAX_IRQ 64 | |
78 | #define RAVEN_MAX_TMR MAX_TMR | |
79 | #define RAVEN_MAX_IPI MAX_IPI | |
80 | ||
81 | /* Interrupt definitions */ | |
82 | #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ | |
83 | #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ | |
84 | #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ | |
85 | #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ | |
86 | /* First doorbell IRQ */ | |
87 | #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) | |
88 | ||
89 | /* FSL_MPIC_20 */ | |
90 | #define FSL_MPIC_20_MAX_CPU 1 | |
91 | #define FSL_MPIC_20_MAX_EXT 12 | |
92 | #define FSL_MPIC_20_MAX_INT 64 | |
93 | #define FSL_MPIC_20_MAX_IRQ MAX_IRQ | |
dbda808a FB |
94 | |
95 | /* Interrupt definitions */ | |
cdbb912a | 96 | /* IRQs, accessible through the IRQ region */ |
d0b72631 AG |
97 | #define FSL_MPIC_20_EXT_IRQ 0x00 |
98 | #define FSL_MPIC_20_INT_IRQ 0x10 | |
99 | #define FSL_MPIC_20_MSG_IRQ 0xb0 | |
100 | #define FSL_MPIC_20_MSI_IRQ 0xe0 | |
cdbb912a AG |
101 | /* These are available through separate regions, but |
102 | for simplicity's sake mapped into the same number space */ | |
d0b72631 AG |
103 | #define FSL_MPIC_20_TMR_IRQ 0x100 |
104 | #define FSL_MPIC_20_IPI_IRQ 0x104 | |
b7169916 | 105 | |
3e772232 BB |
106 | /* |
107 | * Block Revision Register1 (BRR1): QEMU does not fully emulate | |
108 | * any version on MPIC. So to start with, set the IP version to 0. | |
109 | * | |
110 | * NOTE: This is Freescale MPIC specific register. Keep it here till | |
111 | * this code is refactored for different variants of OPENPIC and MPIC. | |
112 | */ | |
113 | #define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */ | |
114 | #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */ | |
115 | #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */ | |
116 | ||
825463b3 AG |
117 | #define FREP_NIRQ_SHIFT 16 |
118 | #define FREP_NCPU_SHIFT 8 | |
119 | #define FREP_VID_SHIFT 0 | |
120 | ||
121 | #define VID_REVISION_1_2 2 | |
d0b72631 | 122 | #define VID_REVISION_1_3 3 |
825463b3 AG |
123 | |
124 | #define VENI_GENERIC 0x00000000 /* Generic Vendor ID */ | |
125 | ||
71c6cacb SW |
126 | #define GLBC_RESET 0x80000000 |
127 | ||
128 | #define TIBC_CI 0x80000000 /* count inhibit */ | |
129 | #define TICC_TOG 0x80000000 /* toggles when decrement to zero */ | |
130 | ||
1945dbc1 AG |
131 | #define IDR_EP_SHIFT 31 |
132 | #define IDR_EP_MASK (1 << IDR_EP_SHIFT) | |
133 | #define IDR_CI0_SHIFT 30 | |
134 | #define IDR_CI1_SHIFT 29 | |
135 | #define IDR_P1_SHIFT 1 | |
136 | #define IDR_P0_SHIFT 0 | |
b7169916 | 137 | |
732aa6ec AG |
138 | #define MSIIR_OFFSET 0x140 |
139 | #define MSIIR_SRS_SHIFT 29 | |
140 | #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT) | |
141 | #define MSIIR_IBS_SHIFT 24 | |
142 | #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT) | |
143 | ||
dbda808a FB |
144 | #define BF_WIDTH(_bits_) \ |
145 | (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) | |
146 | ||
dbe30e13 | 147 | static inline void set_bit(uint32_t *field, int bit) |
dbda808a FB |
148 | { |
149 | field[bit >> 5] |= 1 << (bit & 0x1F); | |
150 | } | |
151 | ||
dbe30e13 | 152 | static inline void reset_bit(uint32_t *field, int bit) |
dbda808a FB |
153 | { |
154 | field[bit >> 5] &= ~(1 << (bit & 0x1F)); | |
155 | } | |
156 | ||
dbe30e13 | 157 | static inline int test_bit(uint32_t *field, int bit) |
dbda808a FB |
158 | { |
159 | return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; | |
160 | } | |
161 | ||
704c7e5d AG |
162 | static int get_current_cpu(void) |
163 | { | |
164 | return cpu_single_env->cpu_index; | |
165 | } | |
166 | ||
a8170e5e | 167 | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
704c7e5d | 168 | int idx); |
a8170e5e | 169 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
704c7e5d AG |
170 | uint32_t val, int idx); |
171 | ||
c227f099 | 172 | typedef struct IRQ_queue_t { |
dbda808a FB |
173 | uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
174 | int next; | |
175 | int priority; | |
76aec1f8 | 176 | int pending; /* nr of pending bits in queue */ |
c227f099 | 177 | } IRQ_queue_t; |
dbda808a | 178 | |
c227f099 | 179 | typedef struct IRQ_src_t { |
dbda808a FB |
180 | uint32_t ipvp; /* IRQ vector/priority register */ |
181 | uint32_t ide; /* IRQ destination register */ | |
dbda808a | 182 | int last_cpu; |
611493d9 | 183 | int pending; /* TRUE if IRQ is pending */ |
c227f099 | 184 | } IRQ_src_t; |
dbda808a | 185 | |
1945dbc1 AG |
186 | #define IPVP_MASK_SHIFT 31 |
187 | #define IPVP_MASK_MASK (1 << IPVP_MASK_SHIFT) | |
188 | #define IPVP_ACTIVITY_SHIFT 30 | |
189 | #define IPVP_ACTIVITY_MASK (1 << IPVP_ACTIVITY_SHIFT) | |
190 | #define IPVP_MODE_SHIFT 29 | |
191 | #define IPVP_MODE_MASK (1 << IPVP_MODE_SHIFT) | |
192 | #define IPVP_POLARITY_SHIFT 23 | |
193 | #define IPVP_POLARITY_MASK (1 << IPVP_POLARITY_SHIFT) | |
194 | #define IPVP_SENSE_SHIFT 22 | |
195 | #define IPVP_SENSE_MASK (1 << IPVP_SENSE_SHIFT) | |
196 | ||
71c6cacb | 197 | #define IPVP_PRIORITY_MASK (0xF << 16) |
611493d9 | 198 | #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) |
0fe04622 | 199 | #define IPVP_VECTOR(opp, _ipvpr_) ((_ipvpr_) & (opp)->vector_mask) |
dbda808a | 200 | |
71c6cacb SW |
201 | /* IDE[EP/CI] are only for FSL MPIC prior to v4.0 */ |
202 | #define IDE_EP 0x80000000 /* external pin */ | |
203 | #define IDE_CI 0x40000000 /* critical interrupt */ | |
204 | ||
c227f099 | 205 | typedef struct IRQ_dst_t { |
dbda808a | 206 | uint32_t pctp; /* CPU current task priority */ |
c227f099 AL |
207 | IRQ_queue_t raised; |
208 | IRQ_queue_t servicing; | |
e9df014c | 209 | qemu_irq *irqs; |
c227f099 | 210 | } IRQ_dst_t; |
dbda808a | 211 | |
6d544ee8 | 212 | typedef struct OpenPICState { |
d0b72631 | 213 | SysBusDevice busdev; |
23c5e4ca | 214 | MemoryRegion mem; |
71cf9e62 | 215 | |
5861a338 | 216 | /* Behavior control */ |
d0b72631 | 217 | uint32_t model; |
5861a338 | 218 | uint32_t flags; |
825463b3 AG |
219 | uint32_t nb_irqs; |
220 | uint32_t vid; | |
221 | uint32_t veni; /* Vendor identification register */ | |
0fe04622 | 222 | uint32_t vector_mask; |
825463b3 AG |
223 | uint32_t tifr_reset; |
224 | uint32_t ipvp_reset; | |
225 | uint32_t ide_reset; | |
dbbbfd60 | 226 | uint32_t brr1; |
5861a338 | 227 | |
71cf9e62 | 228 | /* Sub-regions */ |
732aa6ec | 229 | MemoryRegion sub_io_mem[5]; |
71cf9e62 | 230 | |
dbda808a FB |
231 | /* Global registers */ |
232 | uint32_t frep; /* Feature reporting register */ | |
233 | uint32_t glbc; /* Global configuration register */ | |
e9df014c | 234 | uint32_t pint; /* Processor initialization register */ |
dbda808a FB |
235 | uint32_t spve; /* Spurious vector register */ |
236 | uint32_t tifr; /* Timer frequency reporting register */ | |
237 | /* Source registers */ | |
c227f099 | 238 | IRQ_src_t src[MAX_IRQ]; |
dbda808a | 239 | /* Local registers per output pin */ |
c227f099 | 240 | IRQ_dst_t dst[MAX_CPU]; |
d0b72631 | 241 | uint32_t nb_cpus; |
dbda808a FB |
242 | /* Timer registers */ |
243 | struct { | |
060fbfe1 AJ |
244 | uint32_t ticc; /* Global timer current count register */ |
245 | uint32_t tibc; /* Global timer base count register */ | |
dbda808a | 246 | } timers[MAX_TMR]; |
732aa6ec AG |
247 | /* Shared MSI registers */ |
248 | struct { | |
249 | uint32_t msir; /* Shared Message Signaled Interrupt Register */ | |
250 | } msi[MAX_MSI]; | |
d0b72631 AG |
251 | uint32_t max_irq; |
252 | uint32_t irq_ipi0; | |
253 | uint32_t irq_tim0; | |
732aa6ec | 254 | uint32_t irq_msi; |
6d544ee8 | 255 | } OpenPICState; |
dbda808a | 256 | |
6d544ee8 | 257 | static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src); |
5861a338 | 258 | |
dbe30e13 | 259 | static inline void IRQ_setbit(IRQ_queue_t *q, int n_IRQ) |
dbda808a | 260 | { |
76aec1f8 | 261 | q->pending++; |
dbda808a FB |
262 | set_bit(q->queue, n_IRQ); |
263 | } | |
264 | ||
dbe30e13 | 265 | static inline void IRQ_resetbit(IRQ_queue_t *q, int n_IRQ) |
dbda808a | 266 | { |
76aec1f8 | 267 | q->pending--; |
dbda808a FB |
268 | reset_bit(q->queue, n_IRQ); |
269 | } | |
270 | ||
dbe30e13 | 271 | static inline int IRQ_testbit(IRQ_queue_t *q, int n_IRQ) |
dbda808a FB |
272 | { |
273 | return test_bit(q->queue, n_IRQ); | |
274 | } | |
275 | ||
6d544ee8 | 276 | static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q) |
dbda808a FB |
277 | { |
278 | int next, i; | |
279 | int priority; | |
280 | ||
281 | next = -1; | |
282 | priority = -1; | |
76aec1f8 AG |
283 | |
284 | if (!q->pending) { | |
285 | /* IRQ bitmap is empty */ | |
286 | goto out; | |
287 | } | |
288 | ||
b7169916 | 289 | for (i = 0; i < opp->max_irq; i++) { |
060fbfe1 | 290 | if (IRQ_testbit(q, i)) { |
5fafdf24 | 291 | DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n", |
611493d9 | 292 | i, IPVP_PRIORITY(opp->src[i].ipvp), priority); |
060fbfe1 AJ |
293 | if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) { |
294 | next = i; | |
295 | priority = IPVP_PRIORITY(opp->src[i].ipvp); | |
296 | } | |
297 | } | |
dbda808a | 298 | } |
76aec1f8 AG |
299 | |
300 | out: | |
dbda808a FB |
301 | q->next = next; |
302 | q->priority = priority; | |
303 | } | |
304 | ||
6d544ee8 | 305 | static int IRQ_get_next(OpenPICState *opp, IRQ_queue_t *q) |
dbda808a FB |
306 | { |
307 | if (q->next == -1) { | |
611493d9 | 308 | /* XXX: optimize */ |
060fbfe1 | 309 | IRQ_check(opp, q); |
dbda808a FB |
310 | } |
311 | ||
312 | return q->next; | |
313 | } | |
314 | ||
6d544ee8 | 315 | static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ) |
dbda808a | 316 | { |
c227f099 AL |
317 | IRQ_dst_t *dst; |
318 | IRQ_src_t *src; | |
dbda808a FB |
319 | int priority; |
320 | ||
321 | dst = &opp->dst[n_CPU]; | |
322 | src = &opp->src[n_IRQ]; | |
323 | priority = IPVP_PRIORITY(src->ipvp); | |
324 | if (priority <= dst->pctp) { | |
060fbfe1 | 325 | /* Too low priority */ |
e9df014c JM |
326 | DPRINTF("%s: IRQ %d has too low priority on CPU %d\n", |
327 | __func__, n_IRQ, n_CPU); | |
060fbfe1 | 328 | return; |
dbda808a FB |
329 | } |
330 | if (IRQ_testbit(&dst->raised, n_IRQ)) { | |
060fbfe1 | 331 | /* Interrupt miss */ |
e9df014c JM |
332 | DPRINTF("%s: IRQ %d was missed on CPU %d\n", |
333 | __func__, n_IRQ, n_CPU); | |
060fbfe1 | 334 | return; |
dbda808a | 335 | } |
1945dbc1 | 336 | src->ipvp |= IPVP_ACTIVITY_MASK; |
dbda808a | 337 | IRQ_setbit(&dst->raised, n_IRQ); |
e9df014c JM |
338 | if (priority < dst->raised.priority) { |
339 | /* An higher priority IRQ is already raised */ | |
340 | DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n", | |
341 | __func__, n_IRQ, dst->raised.next, n_CPU); | |
342 | return; | |
343 | } | |
344 | IRQ_get_next(opp, &dst->raised); | |
345 | if (IRQ_get_next(opp, &dst->servicing) != -1 && | |
24865167 | 346 | priority <= dst->servicing.priority) { |
e9df014c JM |
347 | DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", |
348 | __func__, n_IRQ, dst->servicing.next, n_CPU); | |
349 | /* Already servicing a higher priority IRQ */ | |
350 | return; | |
dbda808a | 351 | } |
e9df014c | 352 | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ); |
5861a338 | 353 | openpic_irq_raise(opp, n_CPU, src); |
dbda808a FB |
354 | } |
355 | ||
611493d9 | 356 | /* update pic state because registers for n_IRQ have changed value */ |
6d544ee8 | 357 | static void openpic_update_irq(OpenPICState *opp, int n_IRQ) |
dbda808a | 358 | { |
c227f099 | 359 | IRQ_src_t *src; |
dbda808a FB |
360 | int i; |
361 | ||
362 | src = &opp->src[n_IRQ]; | |
611493d9 FB |
363 | |
364 | if (!src->pending) { | |
365 | /* no irq pending */ | |
e9df014c | 366 | DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ); |
611493d9 FB |
367 | return; |
368 | } | |
1945dbc1 | 369 | if (src->ipvp & IPVP_MASK_MASK) { |
060fbfe1 | 370 | /* Interrupt source is disabled */ |
e9df014c | 371 | DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); |
060fbfe1 | 372 | return; |
dbda808a FB |
373 | } |
374 | if (IPVP_PRIORITY(src->ipvp) == 0) { | |
060fbfe1 | 375 | /* Priority set to zero */ |
e9df014c | 376 | DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ); |
060fbfe1 | 377 | return; |
dbda808a | 378 | } |
1945dbc1 | 379 | if (src->ipvp & IPVP_ACTIVITY_MASK) { |
611493d9 | 380 | /* IRQ already active */ |
e9df014c | 381 | DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ); |
611493d9 FB |
382 | return; |
383 | } | |
71c6cacb | 384 | if (src->ide == 0) { |
060fbfe1 | 385 | /* No target */ |
e9df014c | 386 | DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); |
060fbfe1 | 387 | return; |
dbda808a | 388 | } |
611493d9 | 389 | |
e9df014c JM |
390 | if (src->ide == (1 << src->last_cpu)) { |
391 | /* Only one CPU is allowed to receive this IRQ */ | |
392 | IRQ_local_pipe(opp, src->last_cpu, n_IRQ); | |
1945dbc1 | 393 | } else if (!(src->ipvp & IPVP_MODE_MASK)) { |
611493d9 FB |
394 | /* Directed delivery mode */ |
395 | for (i = 0; i < opp->nb_cpus; i++) { | |
1945dbc1 | 396 | if (src->ide & (1 << i)) { |
611493d9 | 397 | IRQ_local_pipe(opp, i, n_IRQ); |
1945dbc1 | 398 | } |
611493d9 | 399 | } |
dbda808a | 400 | } else { |
611493d9 | 401 | /* Distributed delivery mode */ |
e9df014c JM |
402 | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
403 | if (i == opp->nb_cpus) | |
611493d9 | 404 | i = 0; |
1945dbc1 | 405 | if (src->ide & (1 << i)) { |
611493d9 FB |
406 | IRQ_local_pipe(opp, i, n_IRQ); |
407 | src->last_cpu = i; | |
408 | break; | |
409 | } | |
410 | } | |
411 | } | |
412 | } | |
413 | ||
d537cf6c | 414 | static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
611493d9 | 415 | { |
6d544ee8 | 416 | OpenPICState *opp = opaque; |
c227f099 | 417 | IRQ_src_t *src; |
611493d9 FB |
418 | |
419 | src = &opp->src[n_IRQ]; | |
5fafdf24 | 420 | DPRINTF("openpic: set irq %d = %d ipvp=%08x\n", |
611493d9 | 421 | n_IRQ, level, src->ipvp); |
1945dbc1 | 422 | if (src->ipvp & IPVP_SENSE_MASK) { |
611493d9 FB |
423 | /* level-sensitive irq */ |
424 | src->pending = level; | |
1945dbc1 AG |
425 | if (!level) { |
426 | src->ipvp &= ~IPVP_ACTIVITY_MASK; | |
427 | } | |
611493d9 FB |
428 | } else { |
429 | /* edge-sensitive irq */ | |
430 | if (level) | |
431 | src->pending = 1; | |
dbda808a | 432 | } |
611493d9 | 433 | openpic_update_irq(opp, n_IRQ); |
dbda808a FB |
434 | } |
435 | ||
d0b72631 | 436 | static void openpic_reset(DeviceState *d) |
dbda808a | 437 | { |
d0b72631 | 438 | OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d)); |
dbda808a FB |
439 | int i; |
440 | ||
71c6cacb | 441 | opp->glbc = GLBC_RESET; |
f8407028 | 442 | /* Initialise controller registers */ |
a26a7b38 SW |
443 | opp->frep = ((opp->nb_irqs - 1) << FREP_NIRQ_SHIFT) | |
444 | ((opp->nb_cpus - 1) << FREP_NCPU_SHIFT) | | |
825463b3 AG |
445 | (opp->vid << FREP_VID_SHIFT); |
446 | ||
71c6cacb | 447 | opp->pint = 0; |
0fe04622 | 448 | opp->spve = -1 & opp->vector_mask; |
825463b3 | 449 | opp->tifr = opp->tifr_reset; |
dbda808a | 450 | /* Initialise IRQ sources */ |
b7169916 | 451 | for (i = 0; i < opp->max_irq; i++) { |
825463b3 AG |
452 | opp->src[i].ipvp = opp->ipvp_reset; |
453 | opp->src[i].ide = opp->ide_reset; | |
dbda808a FB |
454 | } |
455 | /* Initialise IRQ destinations */ | |
e9df014c | 456 | for (i = 0; i < MAX_CPU; i++) { |
71c6cacb | 457 | opp->dst[i].pctp = 15; |
060fbfe1 | 458 | memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
d14ed254 | 459 | opp->dst[i].raised.next = -1; |
060fbfe1 | 460 | memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
d14ed254 | 461 | opp->dst[i].servicing.next = -1; |
dbda808a FB |
462 | } |
463 | /* Initialise timers */ | |
464 | for (i = 0; i < MAX_TMR; i++) { | |
71c6cacb SW |
465 | opp->timers[i].ticc = 0; |
466 | opp->timers[i].tibc = TIBC_CI; | |
dbda808a | 467 | } |
dbda808a | 468 | /* Go out of RESET state */ |
71c6cacb | 469 | opp->glbc = 0; |
dbda808a FB |
470 | } |
471 | ||
6d544ee8 | 472 | static inline uint32_t read_IRQreg_ide(OpenPICState *opp, int n_IRQ) |
dbda808a | 473 | { |
8d3a8c1e AG |
474 | return opp->src[n_IRQ].ide; |
475 | } | |
dbda808a | 476 | |
6d544ee8 | 477 | static inline uint32_t read_IRQreg_ipvp(OpenPICState *opp, int n_IRQ) |
8d3a8c1e AG |
478 | { |
479 | return opp->src[n_IRQ].ipvp; | |
dbda808a FB |
480 | } |
481 | ||
6d544ee8 | 482 | static inline void write_IRQreg_ide(OpenPICState *opp, int n_IRQ, uint32_t val) |
dbda808a FB |
483 | { |
484 | uint32_t tmp; | |
485 | ||
71c6cacb | 486 | tmp = val & (IDE_EP | IDE_CI); |
11de8b71 AG |
487 | tmp |= val & ((1ULL << MAX_CPU) - 1); |
488 | opp->src[n_IRQ].ide = tmp; | |
489 | DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide); | |
490 | } | |
491 | ||
6d544ee8 | 492 | static inline void write_IRQreg_ipvp(OpenPICState *opp, int n_IRQ, uint32_t val) |
11de8b71 AG |
493 | { |
494 | /* NOTE: not fully accurate for special IRQs, but simple and sufficient */ | |
495 | /* ACTIVITY bit is read-only */ | |
71c6cacb | 496 | opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & IPVP_ACTIVITY_MASK) | |
0fe04622 | 497 | (val & (IPVP_MASK_MASK | IPVP_PRIORITY_MASK | opp->vector_mask)); |
11de8b71 AG |
498 | openpic_update_irq(opp, n_IRQ); |
499 | DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val, | |
500 | opp->src[n_IRQ].ipvp); | |
dbda808a FB |
501 | } |
502 | ||
b9b2aaa3 AG |
503 | static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, |
504 | unsigned len) | |
dbda808a | 505 | { |
6d544ee8 | 506 | OpenPICState *opp = opaque; |
c227f099 | 507 | IRQ_dst_t *dst; |
e9df014c | 508 | int idx; |
dbda808a | 509 | |
0bf9e31a | 510 | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
dbda808a FB |
511 | if (addr & 0xF) |
512 | return; | |
dbda808a | 513 | switch (addr) { |
3e772232 BB |
514 | case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ |
515 | break; | |
704c7e5d AG |
516 | case 0x40: |
517 | case 0x50: | |
518 | case 0x60: | |
519 | case 0x70: | |
520 | case 0x80: | |
521 | case 0x90: | |
522 | case 0xA0: | |
523 | case 0xB0: | |
524 | openpic_cpu_write_internal(opp, addr, val, get_current_cpu()); | |
dbda808a | 525 | break; |
704c7e5d | 526 | case 0x1000: /* FREP */ |
dbda808a | 527 | break; |
704c7e5d | 528 | case 0x1020: /* GLBC */ |
71c6cacb | 529 | if (val & GLBC_RESET) { |
d0b72631 | 530 | openpic_reset(&opp->busdev.qdev); |
825463b3 | 531 | } |
060fbfe1 | 532 | break; |
704c7e5d | 533 | case 0x1080: /* VENI */ |
060fbfe1 | 534 | break; |
704c7e5d | 535 | case 0x1090: /* PINT */ |
e9df014c JM |
536 | for (idx = 0; idx < opp->nb_cpus; idx++) { |
537 | if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) { | |
538 | DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx); | |
539 | dst = &opp->dst[idx]; | |
540 | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); | |
541 | } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) { | |
542 | DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx); | |
543 | dst = &opp->dst[idx]; | |
544 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); | |
545 | } | |
dbda808a | 546 | } |
e9df014c | 547 | opp->pint = val; |
060fbfe1 | 548 | break; |
704c7e5d AG |
549 | case 0x10A0: /* IPI_IPVP */ |
550 | case 0x10B0: | |
551 | case 0x10C0: | |
552 | case 0x10D0: | |
dbda808a FB |
553 | { |
554 | int idx; | |
704c7e5d | 555 | idx = (addr - 0x10A0) >> 4; |
11de8b71 | 556 | write_IRQreg_ipvp(opp, opp->irq_ipi0 + idx, val); |
dbda808a FB |
557 | } |
558 | break; | |
704c7e5d | 559 | case 0x10E0: /* SPVE */ |
0fe04622 | 560 | opp->spve = val & opp->vector_mask; |
dbda808a | 561 | break; |
dbda808a FB |
562 | default: |
563 | break; | |
564 | } | |
565 | } | |
566 | ||
b9b2aaa3 | 567 | static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 568 | { |
6d544ee8 | 569 | OpenPICState *opp = opaque; |
dbda808a FB |
570 | uint32_t retval; |
571 | ||
0bf9e31a | 572 | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
dbda808a FB |
573 | retval = 0xFFFFFFFF; |
574 | if (addr & 0xF) | |
575 | return retval; | |
dbda808a | 576 | switch (addr) { |
704c7e5d | 577 | case 0x1000: /* FREP */ |
dbda808a FB |
578 | retval = opp->frep; |
579 | break; | |
704c7e5d | 580 | case 0x1020: /* GLBC */ |
dbda808a | 581 | retval = opp->glbc; |
060fbfe1 | 582 | break; |
704c7e5d | 583 | case 0x1080: /* VENI */ |
dbda808a | 584 | retval = opp->veni; |
060fbfe1 | 585 | break; |
704c7e5d | 586 | case 0x1090: /* PINT */ |
dbda808a | 587 | retval = 0x00000000; |
060fbfe1 | 588 | break; |
3e772232 | 589 | case 0x00: /* Block Revision Register1 (BRR1) */ |
0d404683 SW |
590 | retval = opp->brr1; |
591 | break; | |
704c7e5d AG |
592 | case 0x40: |
593 | case 0x50: | |
594 | case 0x60: | |
595 | case 0x70: | |
596 | case 0x80: | |
597 | case 0x90: | |
598 | case 0xA0: | |
dbda808a | 599 | case 0xB0: |
704c7e5d AG |
600 | retval = openpic_cpu_read_internal(opp, addr, get_current_cpu()); |
601 | break; | |
602 | case 0x10A0: /* IPI_IPVP */ | |
603 | case 0x10B0: | |
604 | case 0x10C0: | |
605 | case 0x10D0: | |
dbda808a FB |
606 | { |
607 | int idx; | |
704c7e5d | 608 | idx = (addr - 0x10A0) >> 4; |
8d3a8c1e | 609 | retval = read_IRQreg_ipvp(opp, opp->irq_ipi0 + idx); |
dbda808a | 610 | } |
060fbfe1 | 611 | break; |
704c7e5d | 612 | case 0x10E0: /* SPVE */ |
dbda808a FB |
613 | retval = opp->spve; |
614 | break; | |
dbda808a FB |
615 | default: |
616 | break; | |
617 | } | |
618 | DPRINTF("%s: => %08x\n", __func__, retval); | |
dbda808a FB |
619 | |
620 | return retval; | |
621 | } | |
622 | ||
6d544ee8 | 623 | static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, |
b9b2aaa3 | 624 | unsigned len) |
dbda808a | 625 | { |
6d544ee8 | 626 | OpenPICState *opp = opaque; |
dbda808a FB |
627 | int idx; |
628 | ||
629 | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); | |
630 | if (addr & 0xF) | |
631 | return; | |
c38c0b8a | 632 | idx = (addr >> 6) & 0x3; |
dbda808a | 633 | addr = addr & 0x30; |
c38c0b8a AG |
634 | |
635 | if (addr == 0x0) { | |
636 | /* TIFR (TFRR) */ | |
637 | opp->tifr = val; | |
638 | return; | |
639 | } | |
640 | switch (addr & 0x30) { | |
641 | case 0x00: /* TICC (GTCCR) */ | |
dbda808a | 642 | break; |
c38c0b8a | 643 | case 0x10: /* TIBC (GTBCR) */ |
71c6cacb SW |
644 | if ((opp->timers[idx].ticc & TICC_TOG) != 0 && |
645 | (val & TIBC_CI) == 0 && | |
646 | (opp->timers[idx].tibc & TIBC_CI) != 0) { | |
647 | opp->timers[idx].ticc &= ~TICC_TOG; | |
648 | } | |
060fbfe1 AJ |
649 | opp->timers[idx].tibc = val; |
650 | break; | |
c38c0b8a | 651 | case 0x20: /* TIVP (GTIVPR) */ |
11de8b71 | 652 | write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val); |
060fbfe1 | 653 | break; |
c38c0b8a | 654 | case 0x30: /* TIDE (GTIDR) */ |
11de8b71 | 655 | write_IRQreg_ide(opp, opp->irq_tim0 + idx, val); |
060fbfe1 | 656 | break; |
dbda808a FB |
657 | } |
658 | } | |
659 | ||
6d544ee8 | 660 | static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 661 | { |
6d544ee8 | 662 | OpenPICState *opp = opaque; |
c38c0b8a | 663 | uint32_t retval = -1; |
dbda808a FB |
664 | int idx; |
665 | ||
666 | DPRINTF("%s: addr %08x\n", __func__, addr); | |
c38c0b8a AG |
667 | if (addr & 0xF) { |
668 | goto out; | |
669 | } | |
670 | idx = (addr >> 6) & 0x3; | |
671 | if (addr == 0x0) { | |
672 | /* TIFR (TFRR) */ | |
673 | retval = opp->tifr; | |
674 | goto out; | |
675 | } | |
676 | switch (addr & 0x30) { | |
677 | case 0x00: /* TICC (GTCCR) */ | |
060fbfe1 | 678 | retval = opp->timers[idx].ticc; |
dbda808a | 679 | break; |
c38c0b8a | 680 | case 0x10: /* TIBC (GTBCR) */ |
060fbfe1 AJ |
681 | retval = opp->timers[idx].tibc; |
682 | break; | |
c38c0b8a | 683 | case 0x20: /* TIPV (TIPV) */ |
8d3a8c1e | 684 | retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx); |
060fbfe1 | 685 | break; |
c38c0b8a | 686 | case 0x30: /* TIDE (TIDR) */ |
8d3a8c1e | 687 | retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx); |
060fbfe1 | 688 | break; |
dbda808a | 689 | } |
c38c0b8a AG |
690 | |
691 | out: | |
dbda808a | 692 | DPRINTF("%s: => %08x\n", __func__, retval); |
dbda808a FB |
693 | |
694 | return retval; | |
695 | } | |
696 | ||
b9b2aaa3 AG |
697 | static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, |
698 | unsigned len) | |
dbda808a | 699 | { |
6d544ee8 | 700 | OpenPICState *opp = opaque; |
dbda808a FB |
701 | int idx; |
702 | ||
703 | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); | |
704 | if (addr & 0xF) | |
705 | return; | |
dbda808a FB |
706 | addr = addr & 0xFFF0; |
707 | idx = addr >> 5; | |
708 | if (addr & 0x10) { | |
709 | /* EXDE / IFEDE / IEEDE */ | |
11de8b71 | 710 | write_IRQreg_ide(opp, idx, val); |
dbda808a FB |
711 | } else { |
712 | /* EXVP / IFEVP / IEEVP */ | |
11de8b71 | 713 | write_IRQreg_ipvp(opp, idx, val); |
dbda808a FB |
714 | } |
715 | } | |
716 | ||
b9b2aaa3 | 717 | static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) |
dbda808a | 718 | { |
6d544ee8 | 719 | OpenPICState *opp = opaque; |
dbda808a FB |
720 | uint32_t retval; |
721 | int idx; | |
722 | ||
723 | DPRINTF("%s: addr %08x\n", __func__, addr); | |
724 | retval = 0xFFFFFFFF; | |
725 | if (addr & 0xF) | |
726 | return retval; | |
727 | addr = addr & 0xFFF0; | |
728 | idx = addr >> 5; | |
729 | if (addr & 0x10) { | |
730 | /* EXDE / IFEDE / IEEDE */ | |
8d3a8c1e | 731 | retval = read_IRQreg_ide(opp, idx); |
dbda808a FB |
732 | } else { |
733 | /* EXVP / IFEVP / IEEVP */ | |
8d3a8c1e | 734 | retval = read_IRQreg_ipvp(opp, idx); |
dbda808a FB |
735 | } |
736 | DPRINTF("%s: => %08x\n", __func__, retval); | |
dbda808a FB |
737 | |
738 | return retval; | |
739 | } | |
740 | ||
732aa6ec AG |
741 | static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val, |
742 | unsigned size) | |
743 | { | |
744 | OpenPICState *opp = opaque; | |
745 | int idx = opp->irq_msi; | |
746 | int srs, ibs; | |
747 | ||
748 | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); | |
749 | if (addr & 0xF) { | |
750 | return; | |
751 | } | |
752 | ||
753 | switch (addr) { | |
754 | case MSIIR_OFFSET: | |
755 | srs = val >> MSIIR_SRS_SHIFT; | |
756 | idx += srs; | |
757 | ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT; | |
758 | opp->msi[srs].msir |= 1 << ibs; | |
759 | openpic_set_irq(opp, idx, 1); | |
760 | break; | |
761 | default: | |
762 | /* most registers are read-only, thus ignored */ | |
763 | break; | |
764 | } | |
765 | } | |
766 | ||
767 | static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) | |
768 | { | |
769 | OpenPICState *opp = opaque; | |
770 | uint64_t r = 0; | |
771 | int i, srs; | |
772 | ||
773 | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
774 | if (addr & 0xF) { | |
775 | return -1; | |
776 | } | |
777 | ||
778 | srs = addr >> 4; | |
779 | ||
780 | switch (addr) { | |
781 | case 0x00: | |
782 | case 0x10: | |
783 | case 0x20: | |
784 | case 0x30: | |
785 | case 0x40: | |
786 | case 0x50: | |
787 | case 0x60: | |
788 | case 0x70: /* MSIRs */ | |
789 | r = opp->msi[srs].msir; | |
790 | /* Clear on read */ | |
791 | opp->msi[srs].msir = 0; | |
792 | break; | |
793 | case 0x120: /* MSISR */ | |
794 | for (i = 0; i < MAX_MSI; i++) { | |
795 | r |= (opp->msi[i].msir ? 1 : 0) << i; | |
796 | } | |
797 | break; | |
798 | } | |
799 | ||
800 | return r; | |
801 | } | |
802 | ||
a8170e5e | 803 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
704c7e5d | 804 | uint32_t val, int idx) |
dbda808a | 805 | { |
6d544ee8 | 806 | OpenPICState *opp = opaque; |
c227f099 AL |
807 | IRQ_src_t *src; |
808 | IRQ_dst_t *dst; | |
704c7e5d | 809 | int s_IRQ, n_IRQ; |
dbda808a | 810 | |
704c7e5d AG |
811 | DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx, |
812 | addr, val); | |
dbda808a FB |
813 | if (addr & 0xF) |
814 | return; | |
dbda808a FB |
815 | dst = &opp->dst[idx]; |
816 | addr &= 0xFF0; | |
817 | switch (addr) { | |
704c7e5d | 818 | case 0x40: /* IPIDR */ |
dbda808a FB |
819 | case 0x50: |
820 | case 0x60: | |
821 | case 0x70: | |
822 | idx = (addr - 0x40) >> 4; | |
a675155e | 823 | /* we use IDE as mask which CPUs to deliver the IPI to still. */ |
11de8b71 AG |
824 | write_IRQreg_ide(opp, opp->irq_ipi0 + idx, |
825 | opp->src[opp->irq_ipi0 + idx].ide | val); | |
b7169916 AJ |
826 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 1); |
827 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); | |
dbda808a | 828 | break; |
dbda808a | 829 | case 0x80: /* PCTP */ |
060fbfe1 AJ |
830 | dst->pctp = val & 0x0000000F; |
831 | break; | |
dbda808a | 832 | case 0x90: /* WHOAMI */ |
060fbfe1 AJ |
833 | /* Read-only register */ |
834 | break; | |
dbda808a | 835 | case 0xA0: /* PIAC */ |
060fbfe1 AJ |
836 | /* Read-only register */ |
837 | break; | |
dbda808a FB |
838 | case 0xB0: /* PEOI */ |
839 | DPRINTF("PEOI\n"); | |
060fbfe1 AJ |
840 | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
841 | IRQ_resetbit(&dst->servicing, s_IRQ); | |
842 | dst->servicing.next = -1; | |
843 | /* Set up next servicing IRQ */ | |
844 | s_IRQ = IRQ_get_next(opp, &dst->servicing); | |
e9df014c JM |
845 | /* Check queued interrupts. */ |
846 | n_IRQ = IRQ_get_next(opp, &dst->raised); | |
847 | src = &opp->src[n_IRQ]; | |
848 | if (n_IRQ != -1 && | |
849 | (s_IRQ == -1 || | |
850 | IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) { | |
851 | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", | |
852 | idx, n_IRQ); | |
5861a338 | 853 | openpic_irq_raise(opp, idx, src); |
e9df014c | 854 | } |
060fbfe1 | 855 | break; |
dbda808a FB |
856 | default: |
857 | break; | |
858 | } | |
859 | } | |
860 | ||
b9b2aaa3 AG |
861 | static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val, |
862 | unsigned len) | |
704c7e5d AG |
863 | { |
864 | openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); | |
865 | } | |
866 | ||
a8170e5e | 867 | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
704c7e5d | 868 | int idx) |
dbda808a | 869 | { |
6d544ee8 | 870 | OpenPICState *opp = opaque; |
c227f099 AL |
871 | IRQ_src_t *src; |
872 | IRQ_dst_t *dst; | |
dbda808a | 873 | uint32_t retval; |
704c7e5d | 874 | int n_IRQ; |
3b46e624 | 875 | |
704c7e5d | 876 | DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr); |
dbda808a FB |
877 | retval = 0xFFFFFFFF; |
878 | if (addr & 0xF) | |
879 | return retval; | |
dbda808a FB |
880 | dst = &opp->dst[idx]; |
881 | addr &= 0xFF0; | |
882 | switch (addr) { | |
883 | case 0x80: /* PCTP */ | |
060fbfe1 AJ |
884 | retval = dst->pctp; |
885 | break; | |
dbda808a | 886 | case 0x90: /* WHOAMI */ |
060fbfe1 AJ |
887 | retval = idx; |
888 | break; | |
dbda808a | 889 | case 0xA0: /* PIAC */ |
e9df014c JM |
890 | DPRINTF("Lower OpenPIC INT output\n"); |
891 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); | |
060fbfe1 | 892 | n_IRQ = IRQ_get_next(opp, &dst->raised); |
dbda808a | 893 | DPRINTF("PIAC: irq=%d\n", n_IRQ); |
060fbfe1 AJ |
894 | if (n_IRQ == -1) { |
895 | /* No more interrupt pending */ | |
0fe04622 | 896 | retval = opp->spve; |
060fbfe1 AJ |
897 | } else { |
898 | src = &opp->src[n_IRQ]; | |
1945dbc1 | 899 | if (!(src->ipvp & IPVP_ACTIVITY_MASK) || |
060fbfe1 AJ |
900 | !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) { |
901 | /* - Spurious level-sensitive IRQ | |
902 | * - Priorities has been changed | |
903 | * and the pending IRQ isn't allowed anymore | |
904 | */ | |
1945dbc1 | 905 | src->ipvp &= ~IPVP_ACTIVITY_MASK; |
0fe04622 | 906 | retval = opp->spve; |
060fbfe1 AJ |
907 | } else { |
908 | /* IRQ enter servicing state */ | |
909 | IRQ_setbit(&dst->servicing, n_IRQ); | |
0fe04622 | 910 | retval = IPVP_VECTOR(opp, src->ipvp); |
060fbfe1 AJ |
911 | } |
912 | IRQ_resetbit(&dst->raised, n_IRQ); | |
913 | dst->raised.next = -1; | |
1945dbc1 | 914 | if (!(src->ipvp & IPVP_SENSE_MASK)) { |
611493d9 | 915 | /* edge-sensitive IRQ */ |
1945dbc1 | 916 | src->ipvp &= ~IPVP_ACTIVITY_MASK; |
611493d9 FB |
917 | src->pending = 0; |
918 | } | |
a675155e AG |
919 | |
920 | if ((n_IRQ >= opp->irq_ipi0) && (n_IRQ < (opp->irq_ipi0 + MAX_IPI))) { | |
921 | src->ide &= ~(1 << idx); | |
1945dbc1 | 922 | if (src->ide && !(src->ipvp & IPVP_SENSE_MASK)) { |
a675155e AG |
923 | /* trigger on CPUs that didn't know about it yet */ |
924 | openpic_set_irq(opp, n_IRQ, 1); | |
925 | openpic_set_irq(opp, n_IRQ, 0); | |
926 | /* if all CPUs knew about it, set active bit again */ | |
1945dbc1 | 927 | src->ipvp |= IPVP_ACTIVITY_MASK; |
a675155e AG |
928 | } |
929 | } | |
060fbfe1 AJ |
930 | } |
931 | break; | |
dbda808a | 932 | case 0xB0: /* PEOI */ |
060fbfe1 AJ |
933 | retval = 0; |
934 | break; | |
dbda808a FB |
935 | default: |
936 | break; | |
937 | } | |
938 | DPRINTF("%s: => %08x\n", __func__, retval); | |
dbda808a FB |
939 | |
940 | return retval; | |
941 | } | |
942 | ||
b9b2aaa3 | 943 | static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) |
704c7e5d AG |
944 | { |
945 | return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); | |
946 | } | |
947 | ||
35732cb4 | 948 | static const MemoryRegionOps openpic_glb_ops_le = { |
780d16b7 AG |
949 | .write = openpic_gbl_write, |
950 | .read = openpic_gbl_read, | |
951 | .endianness = DEVICE_LITTLE_ENDIAN, | |
952 | .impl = { | |
953 | .min_access_size = 4, | |
954 | .max_access_size = 4, | |
955 | }, | |
956 | }; | |
dbda808a | 957 | |
35732cb4 AG |
958 | static const MemoryRegionOps openpic_glb_ops_be = { |
959 | .write = openpic_gbl_write, | |
960 | .read = openpic_gbl_read, | |
961 | .endianness = DEVICE_BIG_ENDIAN, | |
962 | .impl = { | |
963 | .min_access_size = 4, | |
964 | .max_access_size = 4, | |
965 | }, | |
966 | }; | |
967 | ||
968 | static const MemoryRegionOps openpic_tmr_ops_le = { | |
6d544ee8 AG |
969 | .write = openpic_tmr_write, |
970 | .read = openpic_tmr_read, | |
780d16b7 AG |
971 | .endianness = DEVICE_LITTLE_ENDIAN, |
972 | .impl = { | |
973 | .min_access_size = 4, | |
974 | .max_access_size = 4, | |
975 | }, | |
976 | }; | |
dbda808a | 977 | |
35732cb4 | 978 | static const MemoryRegionOps openpic_tmr_ops_be = { |
6d544ee8 AG |
979 | .write = openpic_tmr_write, |
980 | .read = openpic_tmr_read, | |
35732cb4 AG |
981 | .endianness = DEVICE_BIG_ENDIAN, |
982 | .impl = { | |
983 | .min_access_size = 4, | |
984 | .max_access_size = 4, | |
985 | }, | |
986 | }; | |
987 | ||
988 | static const MemoryRegionOps openpic_cpu_ops_le = { | |
780d16b7 AG |
989 | .write = openpic_cpu_write, |
990 | .read = openpic_cpu_read, | |
991 | .endianness = DEVICE_LITTLE_ENDIAN, | |
992 | .impl = { | |
993 | .min_access_size = 4, | |
994 | .max_access_size = 4, | |
995 | }, | |
996 | }; | |
dbda808a | 997 | |
35732cb4 AG |
998 | static const MemoryRegionOps openpic_cpu_ops_be = { |
999 | .write = openpic_cpu_write, | |
1000 | .read = openpic_cpu_read, | |
1001 | .endianness = DEVICE_BIG_ENDIAN, | |
1002 | .impl = { | |
1003 | .min_access_size = 4, | |
1004 | .max_access_size = 4, | |
1005 | }, | |
1006 | }; | |
1007 | ||
1008 | static const MemoryRegionOps openpic_src_ops_le = { | |
780d16b7 AG |
1009 | .write = openpic_src_write, |
1010 | .read = openpic_src_read, | |
23c5e4ca | 1011 | .endianness = DEVICE_LITTLE_ENDIAN, |
b9b2aaa3 AG |
1012 | .impl = { |
1013 | .min_access_size = 4, | |
1014 | .max_access_size = 4, | |
1015 | }, | |
23c5e4ca AK |
1016 | }; |
1017 | ||
35732cb4 AG |
1018 | static const MemoryRegionOps openpic_src_ops_be = { |
1019 | .write = openpic_src_write, | |
1020 | .read = openpic_src_read, | |
1021 | .endianness = DEVICE_BIG_ENDIAN, | |
1022 | .impl = { | |
1023 | .min_access_size = 4, | |
1024 | .max_access_size = 4, | |
1025 | }, | |
1026 | }; | |
1027 | ||
732aa6ec AG |
1028 | static const MemoryRegionOps openpic_msi_ops_le = { |
1029 | .read = openpic_msi_read, | |
1030 | .write = openpic_msi_write, | |
1031 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1032 | .impl = { | |
1033 | .min_access_size = 4, | |
1034 | .max_access_size = 4, | |
1035 | }, | |
1036 | }; | |
1037 | ||
1038 | static const MemoryRegionOps openpic_msi_ops_be = { | |
1039 | .read = openpic_msi_read, | |
1040 | .write = openpic_msi_write, | |
1041 | .endianness = DEVICE_BIG_ENDIAN, | |
1042 | .impl = { | |
1043 | .min_access_size = 4, | |
1044 | .max_access_size = 4, | |
1045 | }, | |
1046 | }; | |
1047 | ||
c227f099 | 1048 | static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
67b55785 BS |
1049 | { |
1050 | unsigned int i; | |
1051 | ||
1052 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) | |
1053 | qemu_put_be32s(f, &q->queue[i]); | |
1054 | ||
1055 | qemu_put_sbe32s(f, &q->next); | |
1056 | qemu_put_sbe32s(f, &q->priority); | |
1057 | } | |
1058 | ||
1059 | static void openpic_save(QEMUFile* f, void *opaque) | |
1060 | { | |
6d544ee8 | 1061 | OpenPICState *opp = (OpenPICState *)opaque; |
67b55785 BS |
1062 | unsigned int i; |
1063 | ||
67b55785 | 1064 | qemu_put_be32s(f, &opp->glbc); |
67b55785 BS |
1065 | qemu_put_be32s(f, &opp->veni); |
1066 | qemu_put_be32s(f, &opp->pint); | |
1067 | qemu_put_be32s(f, &opp->spve); | |
1068 | qemu_put_be32s(f, &opp->tifr); | |
1069 | ||
b7169916 | 1070 | for (i = 0; i < opp->max_irq; i++) { |
67b55785 BS |
1071 | qemu_put_be32s(f, &opp->src[i].ipvp); |
1072 | qemu_put_be32s(f, &opp->src[i].ide); | |
67b55785 BS |
1073 | qemu_put_sbe32s(f, &opp->src[i].last_cpu); |
1074 | qemu_put_sbe32s(f, &opp->src[i].pending); | |
1075 | } | |
1076 | ||
d0b72631 | 1077 | qemu_put_be32s(f, &opp->nb_cpus); |
b7169916 AJ |
1078 | |
1079 | for (i = 0; i < opp->nb_cpus; i++) { | |
67b55785 | 1080 | qemu_put_be32s(f, &opp->dst[i].pctp); |
67b55785 BS |
1081 | openpic_save_IRQ_queue(f, &opp->dst[i].raised); |
1082 | openpic_save_IRQ_queue(f, &opp->dst[i].servicing); | |
1083 | } | |
1084 | ||
67b55785 BS |
1085 | for (i = 0; i < MAX_TMR; i++) { |
1086 | qemu_put_be32s(f, &opp->timers[i].ticc); | |
1087 | qemu_put_be32s(f, &opp->timers[i].tibc); | |
1088 | } | |
67b55785 BS |
1089 | } |
1090 | ||
c227f099 | 1091 | static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
67b55785 BS |
1092 | { |
1093 | unsigned int i; | |
1094 | ||
1095 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) | |
1096 | qemu_get_be32s(f, &q->queue[i]); | |
1097 | ||
1098 | qemu_get_sbe32s(f, &q->next); | |
1099 | qemu_get_sbe32s(f, &q->priority); | |
1100 | } | |
1101 | ||
1102 | static int openpic_load(QEMUFile* f, void *opaque, int version_id) | |
1103 | { | |
6d544ee8 | 1104 | OpenPICState *opp = (OpenPICState *)opaque; |
67b55785 BS |
1105 | unsigned int i; |
1106 | ||
1107 | if (version_id != 1) | |
1108 | return -EINVAL; | |
1109 | ||
67b55785 | 1110 | qemu_get_be32s(f, &opp->glbc); |
67b55785 BS |
1111 | qemu_get_be32s(f, &opp->veni); |
1112 | qemu_get_be32s(f, &opp->pint); | |
1113 | qemu_get_be32s(f, &opp->spve); | |
1114 | qemu_get_be32s(f, &opp->tifr); | |
1115 | ||
b7169916 | 1116 | for (i = 0; i < opp->max_irq; i++) { |
67b55785 BS |
1117 | qemu_get_be32s(f, &opp->src[i].ipvp); |
1118 | qemu_get_be32s(f, &opp->src[i].ide); | |
67b55785 BS |
1119 | qemu_get_sbe32s(f, &opp->src[i].last_cpu); |
1120 | qemu_get_sbe32s(f, &opp->src[i].pending); | |
1121 | } | |
1122 | ||
d0b72631 | 1123 | qemu_get_be32s(f, &opp->nb_cpus); |
b7169916 AJ |
1124 | |
1125 | for (i = 0; i < opp->nb_cpus; i++) { | |
67b55785 | 1126 | qemu_get_be32s(f, &opp->dst[i].pctp); |
67b55785 BS |
1127 | openpic_load_IRQ_queue(f, &opp->dst[i].raised); |
1128 | openpic_load_IRQ_queue(f, &opp->dst[i].servicing); | |
1129 | } | |
1130 | ||
67b55785 BS |
1131 | for (i = 0; i < MAX_TMR; i++) { |
1132 | qemu_get_be32s(f, &opp->timers[i].ticc); | |
1133 | qemu_get_be32s(f, &opp->timers[i].tibc); | |
1134 | } | |
1135 | ||
d0b72631 | 1136 | return 0; |
67b55785 BS |
1137 | } |
1138 | ||
6d544ee8 | 1139 | static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src) |
b7169916 | 1140 | { |
1945dbc1 | 1141 | int n_ci = IDR_CI0_SHIFT - n_CPU; |
5861a338 | 1142 | |
1945dbc1 | 1143 | if ((opp->flags & OPENPIC_FLAG_IDE_CRIT) && (src->ide & (1 << n_ci))) { |
5861a338 AG |
1144 | qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]); |
1145 | } else { | |
1146 | qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); | |
1147 | } | |
b7169916 AJ |
1148 | } |
1149 | ||
d0b72631 AG |
1150 | struct memreg { |
1151 | const char *name; | |
1152 | MemoryRegionOps const *ops; | |
732aa6ec | 1153 | bool map; |
d0b72631 AG |
1154 | hwaddr start_addr; |
1155 | ram_addr_t size; | |
1156 | }; | |
1157 | ||
1158 | static int openpic_init(SysBusDevice *dev) | |
dbda808a | 1159 | { |
d0b72631 AG |
1160 | OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev); |
1161 | int i, j; | |
732aa6ec AG |
1162 | struct memreg list_le[] = { |
1163 | {"glb", &openpic_glb_ops_le, true, | |
1164 | OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, | |
1165 | {"tmr", &openpic_tmr_ops_le, true, | |
1166 | OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, | |
1167 | {"msi", &openpic_msi_ops_le, true, | |
1168 | OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE}, | |
1169 | {"src", &openpic_src_ops_le, true, | |
1170 | OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, | |
1171 | {"cpu", &openpic_cpu_ops_le, true, | |
1172 | OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, | |
780d16b7 | 1173 | }; |
732aa6ec AG |
1174 | struct memreg list_be[] = { |
1175 | {"glb", &openpic_glb_ops_be, true, | |
1176 | OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, | |
1177 | {"tmr", &openpic_tmr_ops_be, true, | |
1178 | OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, | |
1179 | {"msi", &openpic_msi_ops_be, true, | |
1180 | OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE}, | |
1181 | {"src", &openpic_src_ops_be, true, | |
1182 | OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, | |
1183 | {"cpu", &openpic_cpu_ops_be, true, | |
1184 | OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, | |
d0b72631 | 1185 | }; |
732aa6ec | 1186 | struct memreg *list; |
3b46e624 | 1187 | |
d0b72631 AG |
1188 | switch (opp->model) { |
1189 | case OPENPIC_MODEL_FSL_MPIC_20: | |
1190 | default: | |
1191 | opp->flags |= OPENPIC_FLAG_IDE_CRIT; | |
1192 | opp->nb_irqs = 80; | |
1193 | opp->vid = VID_REVISION_1_2; | |
1194 | opp->veni = VENI_GENERIC; | |
0fe04622 | 1195 | opp->vector_mask = 0xFFFF; |
71c6cacb SW |
1196 | opp->tifr_reset = 0; |
1197 | opp->ipvp_reset = IPVP_MASK_MASK; | |
1198 | opp->ide_reset = 1 << 0; | |
d0b72631 AG |
1199 | opp->max_irq = FSL_MPIC_20_MAX_IRQ; |
1200 | opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ; | |
1201 | opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ; | |
732aa6ec | 1202 | opp->irq_msi = FSL_MPIC_20_MSI_IRQ; |
dbbbfd60 | 1203 | opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN; |
732aa6ec | 1204 | msi_supported = true; |
d0b72631 AG |
1205 | list = list_be; |
1206 | break; | |
1207 | case OPENPIC_MODEL_RAVEN: | |
1208 | opp->nb_irqs = RAVEN_MAX_EXT; | |
1209 | opp->vid = VID_REVISION_1_3; | |
1210 | opp->veni = VENI_GENERIC; | |
0fe04622 | 1211 | opp->vector_mask = 0xFF; |
71c6cacb SW |
1212 | opp->tifr_reset = 4160000; |
1213 | opp->ipvp_reset = IPVP_MASK_MASK | IPVP_MODE_MASK; | |
1214 | opp->ide_reset = 0; | |
d0b72631 AG |
1215 | opp->max_irq = RAVEN_MAX_IRQ; |
1216 | opp->irq_ipi0 = RAVEN_IPI_IRQ; | |
1217 | opp->irq_tim0 = RAVEN_TMR_IRQ; | |
dbbbfd60 | 1218 | opp->brr1 = -1; |
d0b72631 | 1219 | list = list_le; |
732aa6ec AG |
1220 | /* Don't map MSI region */ |
1221 | list[2].map = false; | |
d0b72631 AG |
1222 | |
1223 | /* Only UP supported today */ | |
1224 | if (opp->nb_cpus != 1) { | |
1225 | return -EINVAL; | |
1226 | } | |
1227 | break; | |
1228 | } | |
780d16b7 AG |
1229 | |
1230 | memory_region_init(&opp->mem, "openpic", 0x40000); | |
1231 | ||
d0b72631 | 1232 | for (i = 0; i < ARRAY_SIZE(list_le); i++) { |
732aa6ec AG |
1233 | if (!list[i].map) { |
1234 | continue; | |
1235 | } | |
1236 | ||
780d16b7 AG |
1237 | memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp, |
1238 | list[i].name, list[i].size); | |
1239 | ||
1240 | memory_region_add_subregion(&opp->mem, list[i].start_addr, | |
1241 | &opp->sub_io_mem[i]); | |
1242 | } | |
3b46e624 | 1243 | |
d0b72631 AG |
1244 | for (i = 0; i < opp->nb_cpus; i++) { |
1245 | opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB); | |
1246 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { | |
1247 | sysbus_init_irq(dev, &opp->dst[i].irqs[j]); | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | register_savevm(&opp->busdev.qdev, "openpic", 0, 2, | |
0be71e32 | 1252 | openpic_save, openpic_load, opp); |
b7169916 | 1253 | |
d0b72631 AG |
1254 | sysbus_init_mmio(dev, &opp->mem); |
1255 | qdev_init_gpio_in(&dev->qdev, openpic_set_irq, opp->max_irq); | |
e9df014c | 1256 | |
d0b72631 | 1257 | return 0; |
b7169916 AJ |
1258 | } |
1259 | ||
d0b72631 AG |
1260 | static Property openpic_properties[] = { |
1261 | DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20), | |
1262 | DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1), | |
1263 | DEFINE_PROP_END_OF_LIST(), | |
1264 | }; | |
71cf9e62 | 1265 | |
d0b72631 AG |
1266 | static void openpic_class_init(ObjectClass *klass, void *data) |
1267 | { | |
1268 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1269 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
b7169916 | 1270 | |
d0b72631 AG |
1271 | k->init = openpic_init; |
1272 | dc->props = openpic_properties; | |
1273 | dc->reset = openpic_reset; | |
1274 | } | |
71cf9e62 | 1275 | |
d0b72631 AG |
1276 | static TypeInfo openpic_info = { |
1277 | .name = "openpic", | |
1278 | .parent = TYPE_SYS_BUS_DEVICE, | |
1279 | .instance_size = sizeof(OpenPICState), | |
1280 | .class_init = openpic_class_init, | |
1281 | }; | |
b7169916 | 1282 | |
d0b72631 AG |
1283 | static void openpic_register_types(void) |
1284 | { | |
1285 | type_register_static(&openpic_info); | |
dbda808a | 1286 | } |
d0b72631 AG |
1287 | |
1288 | type_init(openpic_register_types) |