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PCI: make duplicate devfn allocation fatal
[mirror_qemu.git] / hw / openpic.c
CommitLineData
dbda808a
FB		 1/*
2 * OpenPIC emulation
5fafdf24 3 *
dbda808a 4 * Copyright (c) 2004 Jocelyn Mayer
5fafdf24 5 *
dbda808a
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24/*
25 *
26 * Based on OpenPic implementations:
67b55785 27 * - Intel GW80314 I/O companion chip developer's manual
dbda808a
FB		 28 * - Motorola MPC8245 & MPC8540 user manuals.
29 * - Motorola MCP750 (aka Raven) programmer manual.
30 * - Motorola Harrier programmer manuel
31 *
32 * Serial interrupts, as implemented in Raven chipset are not supported yet.
5fafdf24 33 *
dbda808a 34 */
87ecb68b
PB		 35#include "hw.h"
36#include "ppc_mac.h"
37#include "pci.h"
b7169916 38#include "openpic.h"
dbda808a 39
611493d9 40//#define DEBUG_OPENPIC
dbda808a
FB		 41
42#ifdef DEBUG_OPENPIC
001faf32 43#define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
dbda808a 44#else
001faf32 45#define DPRINTF(fmt, ...) do { } while (0)
dbda808a 46#endif
dbda808a
FB		 47
48#define USE_MPCxxx /* Intel model is broken, for now */
49
50#if defined (USE_INTEL_GW80314)
51/* Intel GW80314 I/O Companion chip */
52
53#define MAX_CPU 4
54#define MAX_IRQ 32
55#define MAX_DBL 4
56#define MAX_MBX 4
57#define MAX_TMR 4
58#define VECTOR_BITS 8
59#define MAX_IPI 0
60
61#define VID (0x00000000)
62
dbda808a
FB		 63#elif defined(USE_MPCxxx)
64
65#define MAX_CPU 2
b7169916 66#define MAX_IRQ 128
dbda808a
FB		 67#define MAX_DBL 0
68#define MAX_MBX 0
69#define MAX_TMR 4
70#define VECTOR_BITS 8
71#define MAX_IPI 4
72#define VID 0x03 /* MPIC version ID */
73#define VENI 0x00000000 /* Vendor ID */
74
75enum {
76 IRQ_IPVP = 0,
77 IRQ_IDE,
78};
79
b7169916
AJ		 80/* OpenPIC */
81#define OPENPIC_MAX_CPU 2
82#define OPENPIC_MAX_IRQ 64
83#define OPENPIC_EXT_IRQ 48
84#define OPENPIC_MAX_TMR MAX_TMR
85#define OPENPIC_MAX_IPI MAX_IPI
dbda808a 86
b7169916
AJ		 87/* Interrupt definitions */
88#define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
89#define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
90#define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
91#if OPENPIC_MAX_IPI > 0
92#define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
93#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
dbda808a 94#else
b7169916
AJ		 95#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
96#define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
dbda808a
FB		 97#endif
98
b7169916
AJ		 99/* MPIC */
100#define MPIC_MAX_CPU 1
101#define MPIC_MAX_EXT 12
102#define MPIC_MAX_INT 64
103#define MPIC_MAX_MSG 4
104#define MPIC_MAX_MSI 8
105#define MPIC_MAX_TMR MAX_TMR
106#define MPIC_MAX_IPI MAX_IPI
107#define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
dbda808a
FB		 108
109/* Interrupt definitions */
b7169916
AJ		 110#define MPIC_EXT_IRQ 0
111#define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
112#define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
113#define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
114#define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
115#define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
116
117#define MPIC_GLB_REG_START 0x0
118#define MPIC_GLB_REG_SIZE 0x10F0
119#define MPIC_TMR_REG_START 0x10F0
120#define MPIC_TMR_REG_SIZE 0x220
121#define MPIC_EXT_REG_START 0x10000
122#define MPIC_EXT_REG_SIZE 0x180
123#define MPIC_INT_REG_START 0x10200
124#define MPIC_INT_REG_SIZE 0x800
125#define MPIC_MSG_REG_START 0x11600
126#define MPIC_MSG_REG_SIZE 0x100
127#define MPIC_MSI_REG_START 0x11C00
128#define MPIC_MSI_REG_SIZE 0x100
129#define MPIC_CPU_REG_START 0x20000
130#define MPIC_CPU_REG_SIZE 0x100
131
132enum mpic_ide_bits {
133 IDR_EP = 0,
134 IDR_CI0 = 1,
135 IDR_CI1 = 2,
136 IDR_P1 = 30,
137 IDR_P0 = 31,
138};
139
dbda808a 140#else
b7169916 141#error "Please select which OpenPic implementation is to be emulated"
dbda808a
FB		 142#endif
143
144#define BF_WIDTH(_bits_) \
145(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
146
147static inline void set_bit (uint32_t *field, int bit)
148{
149 field[bit >> 5] |= 1 << (bit & 0x1F);
150}
151
152static inline void reset_bit (uint32_t *field, int bit)
153{
154 field[bit >> 5] &= ~(1 << (bit & 0x1F));
155}
156
157static inline int test_bit (uint32_t *field, int bit)
158{
159 return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
160}
161
162enum {
163 IRQ_EXTERNAL = 0x01,
164 IRQ_INTERNAL = 0x02,
165 IRQ_TIMER = 0x04,
166 IRQ_SPECIAL = 0x08,
b1d8e52e 167};
dbda808a 168
c227f099 169typedef struct IRQ_queue_t {
dbda808a
FB		 170 uint32_t queue[BF_WIDTH(MAX_IRQ)];
171 int next;
172 int priority;
c227f099 173} IRQ_queue_t;
dbda808a 174
c227f099 175typedef struct IRQ_src_t {
dbda808a
FB		 176 uint32_t ipvp; /* IRQ vector/priority register */
177 uint32_t ide; /* IRQ destination register */
178 int type;
179 int last_cpu;
611493d9 180 int pending; /* TRUE if IRQ is pending */
c227f099 181} IRQ_src_t;
dbda808a
FB		 182
183enum IPVP_bits {
184 IPVP_MASK = 31,
185 IPVP_ACTIVITY = 30,
186 IPVP_MODE = 29,
187 IPVP_POLARITY = 23,
188 IPVP_SENSE = 22,
189};
190#define IPVP_PRIORITY_MASK (0x1F << 16)
611493d9 191#define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
dbda808a
FB		 192#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
193#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
194
c227f099 195typedef struct IRQ_dst_t {
b7169916 196 uint32_t tfrr;
dbda808a
FB		 197 uint32_t pctp; /* CPU current task priority */
198 uint32_t pcsr; /* CPU sensitivity register */
c227f099
AL		 199 IRQ_queue_t raised;
200 IRQ_queue_t servicing;
e9df014c 201 qemu_irq *irqs;
c227f099 202} IRQ_dst_t;
dbda808a 203
c227f099 204typedef struct openpic_t {
dbda808a 205 PCIDevice pci_dev;
91d848eb 206 int mem_index;
dbda808a
FB		 207 /* Global registers */
208 uint32_t frep; /* Feature reporting register */
209 uint32_t glbc; /* Global configuration register */
210 uint32_t micr; /* MPIC interrupt configuration register */
211 uint32_t veni; /* Vendor identification register */
e9df014c 212 uint32_t pint; /* Processor initialization register */
dbda808a
FB		 213 uint32_t spve; /* Spurious vector register */
214 uint32_t tifr; /* Timer frequency reporting register */
215 /* Source registers */
c227f099 216 IRQ_src_t src[MAX_IRQ];
dbda808a 217 /* Local registers per output pin */
c227f099 218 IRQ_dst_t dst[MAX_CPU];
dbda808a
FB		 219 int nb_cpus;
220 /* Timer registers */
221 struct {
222 uint32_t ticc; /* Global timer current count register */
223 uint32_t tibc; /* Global timer base count register */
224 } timers[MAX_TMR];
225#if MAX_DBL > 0
226 /* Doorbell registers */
227 uint32_t dar; /* Doorbell activate register */
228 struct {
229 uint32_t dmr; /* Doorbell messaging register */
230 } doorbells[MAX_DBL];
231#endif
232#if MAX_MBX > 0
233 /* Mailbox registers */
234 struct {
235 uint32_t mbr; /* Mailbox register */
236 } mailboxes[MAX_MAILBOXES];
237#endif
e9df014c
JM		 238 /* IRQ out is used when in bypass mode (not implemented) */
239 qemu_irq irq_out;
b7169916
AJ		 240 int max_irq;
241 int irq_ipi0;
242 int irq_tim0;
243 int need_swap;
244 void (*reset) (void *);
c227f099
AL		 245 void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
246} openpic_t;
dbda808a 247
c227f099 248static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
b7169916
AJ		 249{
250 if (opp->need_swap)
251 return bswap32(val);
252
253 return val;
254}
255
c227f099 256static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
dbda808a
FB		 257{
258 set_bit(q->queue, n_IRQ);
259}
260
c227f099 261static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
dbda808a
FB		 262{
263 reset_bit(q->queue, n_IRQ);
264}
265
c227f099 266static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
dbda808a
FB		 267{
268 return test_bit(q->queue, n_IRQ);
269}
270
c227f099 271static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
dbda808a
FB		 272{
273 int next, i;
274 int priority;
275
276 next = -1;
277 priority = -1;
b7169916 278 for (i = 0; i < opp->max_irq; i++) {
dbda808a 279 if (IRQ_testbit(q, i)) {
5fafdf24 280 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
611493d9 281 i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
dbda808a
FB		 282 if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
283 next = i;
284 priority = IPVP_PRIORITY(opp->src[i].ipvp);
285 }
286 }
287 }
288 q->next = next;
289 q->priority = priority;
290}
291
c227f099 292static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
dbda808a
FB		 293{
294 if (q->next == -1) {
611493d9 295 /* XXX: optimize */
dbda808a
FB		 296 IRQ_check(opp, q);
297 }
298
299 return q->next;
300}
301
c227f099 302static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
dbda808a 303{
c227f099
AL		 304 IRQ_dst_t *dst;
305 IRQ_src_t *src;
dbda808a
FB		 306 int priority;
307
308 dst = &opp->dst[n_CPU];
309 src = &opp->src[n_IRQ];
310 priority = IPVP_PRIORITY(src->ipvp);
311 if (priority <= dst->pctp) {
312 /* Too low priority */
e9df014c
JM		 313 DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
314 __func__, n_IRQ, n_CPU);
dbda808a
FB		 315 return;
316 }
317 if (IRQ_testbit(&dst->raised, n_IRQ)) {
318 /* Interrupt miss */
e9df014c
JM		 319 DPRINTF("%s: IRQ %d was missed on CPU %d\n",
320 __func__, n_IRQ, n_CPU);
dbda808a
FB		 321 return;
322 }
323 set_bit(&src->ipvp, IPVP_ACTIVITY);
324 IRQ_setbit(&dst->raised, n_IRQ);
e9df014c
JM		 325 if (priority < dst->raised.priority) {
326 /* An higher priority IRQ is already raised */
327 DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
328 __func__, n_IRQ, dst->raised.next, n_CPU);
329 return;
330 }
331 IRQ_get_next(opp, &dst->raised);
332 if (IRQ_get_next(opp, &dst->servicing) != -1 &&
24865167 333 priority <= dst->servicing.priority) {
e9df014c
JM		 334 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
335 __func__, n_IRQ, dst->servicing.next, n_CPU);
336 /* Already servicing a higher priority IRQ */
337 return;
dbda808a 338 }
e9df014c 339 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
b7169916 340 opp->irq_raise(opp, n_CPU, src);
dbda808a
FB		 341}
342
611493d9 343/* update pic state because registers for n_IRQ have changed value */
c227f099 344static void openpic_update_irq(openpic_t *opp, int n_IRQ)
dbda808a 345{
c227f099 346 IRQ_src_t *src;
dbda808a
FB		 347 int i;
348
349 src = &opp->src[n_IRQ];
611493d9
FB		 350
351 if (!src->pending) {
352 /* no irq pending */
e9df014c 353 DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
611493d9
FB		 354 return;
355 }
356 if (test_bit(&src->ipvp, IPVP_MASK)) {
dbda808a 357 /* Interrupt source is disabled */
e9df014c 358 DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
dbda808a
FB		 359 return;
360 }
361 if (IPVP_PRIORITY(src->ipvp) == 0) {
362 /* Priority set to zero */
e9df014c 363 DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
dbda808a
FB		 364 return;
365 }
611493d9
FB		 366 if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
367 /* IRQ already active */
e9df014c 368 DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
611493d9
FB		 369 return;
370 }
dbda808a
FB		 371 if (src->ide == 0x00000000) {
372 /* No target */
e9df014c 373 DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
dbda808a
FB		 374 return;
375 }
611493d9 376
e9df014c
JM		 377 if (src->ide == (1 << src->last_cpu)) {
378 /* Only one CPU is allowed to receive this IRQ */
379 IRQ_local_pipe(opp, src->last_cpu, n_IRQ);
380 } else if (!test_bit(&src->ipvp, IPVP_MODE)) {
611493d9
FB		 381 /* Directed delivery mode */
382 for (i = 0; i < opp->nb_cpus; i++) {
383 if (test_bit(&src->ide, i))
384 IRQ_local_pipe(opp, i, n_IRQ);
385 }
dbda808a 386 } else {
611493d9 387 /* Distributed delivery mode */
e9df014c
JM		 388 for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
389 if (i == opp->nb_cpus)
611493d9
FB		 390 i = 0;
391 if (test_bit(&src->ide, i)) {
392 IRQ_local_pipe(opp, i, n_IRQ);
393 src->last_cpu = i;
394 break;
395 }
396 }
397 }
398}
399
d537cf6c 400static void openpic_set_irq(void *opaque, int n_IRQ, int level)
611493d9 401{
c227f099
AL		 402 openpic_t *opp = opaque;
403 IRQ_src_t *src;
611493d9
FB		 404
405 src = &opp->src[n_IRQ];
5fafdf24 406 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
611493d9
FB		 407 n_IRQ, level, src->ipvp);
408 if (test_bit(&src->ipvp, IPVP_SENSE)) {
409 /* level-sensitive irq */
410 src->pending = level;
411 if (!level)
412 reset_bit(&src->ipvp, IPVP_ACTIVITY);
413 } else {
414 /* edge-sensitive irq */
415 if (level)
416 src->pending = 1;
dbda808a 417 }
611493d9 418 openpic_update_irq(opp, n_IRQ);
dbda808a
FB		 419}
420
67b55785 421static void openpic_reset (void *opaque)
dbda808a 422{
c227f099 423 openpic_t *opp = (openpic_t *)opaque;
dbda808a
FB		 424 int i;
425
426 opp->glbc = 0x80000000;
f8407028 427 /* Initialise controller registers */
b7169916 428 opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID;
dbda808a 429 opp->veni = VENI;
e9df014c 430 opp->pint = 0x00000000;
dbda808a
FB		 431 opp->spve = 0x000000FF;
432 opp->tifr = 0x003F7A00;
433 /* ? */
434 opp->micr = 0x00000000;
435 /* Initialise IRQ sources */
b7169916 436 for (i = 0; i < opp->max_irq; i++) {
dbda808a
FB		 437 opp->src[i].ipvp = 0xA0000000;
438 opp->src[i].ide = 0x00000000;
439 }
440 /* Initialise IRQ destinations */
e9df014c 441 for (i = 0; i < MAX_CPU; i++) {
dbda808a
FB		 442 opp->dst[i].pctp = 0x0000000F;
443 opp->dst[i].pcsr = 0x00000000;
c227f099
AL		 444 memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
445 memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
dbda808a
FB		 446 }
447 /* Initialise timers */
448 for (i = 0; i < MAX_TMR; i++) {
449 opp->timers[i].ticc = 0x00000000;
450 opp->timers[i].tibc = 0x80000000;
451 }
452 /* Initialise doorbells */
453#if MAX_DBL > 0
454 opp->dar = 0x00000000;
455 for (i = 0; i < MAX_DBL; i++) {
456 opp->doorbells[i].dmr = 0x00000000;
457 }
458#endif
459 /* Initialise mailboxes */
460#if MAX_MBX > 0
461 for (i = 0; i < MAX_MBX; i++) { /* ? */
462 opp->mailboxes[i].mbr = 0x00000000;
463 }
464#endif
465 /* Go out of RESET state */
466 opp->glbc = 0x00000000;
467}
468
c227f099 469static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
dbda808a
FB		 470{
471 uint32_t retval;
472
473 switch (reg) {
474 case IRQ_IPVP:
475 retval = opp->src[n_IRQ].ipvp;
476 break;
477 case IRQ_IDE:
478 retval = opp->src[n_IRQ].ide;
479 break;
480 }
481
482 return retval;
483}
484
c227f099 485static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
dbda808a
FB		 486 uint32_t reg, uint32_t val)
487{
488 uint32_t tmp;
489
490 switch (reg) {
491 case IRQ_IPVP:
611493d9
FB		 492 /* NOTE: not fully accurate for special IRQs, but simple and
493 sufficient */
494 /* ACTIVITY bit is read-only */
5fafdf24 495 opp->src[n_IRQ].ipvp =
611493d9
FB		 496 (opp->src[n_IRQ].ipvp & 0x40000000) |
497 (val & 0x800F00FF);
498 openpic_update_irq(opp, n_IRQ);
5fafdf24 499 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
611493d9 500 n_IRQ, val, opp->src[n_IRQ].ipvp);
dbda808a
FB		 501 break;
502 case IRQ_IDE:
503 tmp = val & 0xC0000000;
504 tmp |= val & ((1 << MAX_CPU) - 1);
505 opp->src[n_IRQ].ide = tmp;
506 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
507 break;
508 }
509}
510
511#if 0 // Code provision for Intel model
512#if MAX_DBL > 0
c227f099 513static uint32_t read_doorbell_register (openpic_t *opp,
dbda808a
FB		 514 int n_dbl, uint32_t offset)
515{
516 uint32_t retval;
517
518 switch (offset) {
519 case DBL_IPVP_OFFSET:
520 retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
521 break;
522 case DBL_IDE_OFFSET:
523 retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
524 break;
525 case DBL_DMR_OFFSET:
526 retval = opp->doorbells[n_dbl].dmr;
527 break;
528 }
529
530 return retval;
531}
3b46e624 532
dbda808a
FB		 533static void write_doorbell_register (penpic_t *opp, int n_dbl,
534 uint32_t offset, uint32_t value)
535{
536 switch (offset) {
537 case DBL_IVPR_OFFSET:
538 write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
539 break;
540 case DBL_IDE_OFFSET:
541 write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
542 break;
543 case DBL_DMR_OFFSET:
544 opp->doorbells[n_dbl].dmr = value;
545 break;
546 }
547}
548#endif
549
550#if MAX_MBX > 0
c227f099 551static uint32_t read_mailbox_register (openpic_t *opp,
dbda808a
FB		 552 int n_mbx, uint32_t offset)
553{
554 uint32_t retval;
555
556 switch (offset) {
557 case MBX_MBR_OFFSET:
558 retval = opp->mailboxes[n_mbx].mbr;
559 break;
560 case MBX_IVPR_OFFSET:
561 retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
562 break;
563 case MBX_DMR_OFFSET:
564 retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
565 break;
566 }
567
568 return retval;
569}
570
c227f099 571static void write_mailbox_register (openpic_t *opp, int n_mbx,
dbda808a
FB		 572 uint32_t address, uint32_t value)
573{
574 switch (offset) {
575 case MBX_MBR_OFFSET:
576 opp->mailboxes[n_mbx].mbr = value;
577 break;
578 case MBX_IVPR_OFFSET:
579 write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
580 break;
581 case MBX_DMR_OFFSET:
582 write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
583 break;
584 }
585}
586#endif
587#endif /* 0 : Code provision for Intel model */
588
c227f099 589static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
dbda808a 590{
c227f099
AL		 591 openpic_t *opp = opaque;
592 IRQ_dst_t *dst;
e9df014c 593 int idx;
dbda808a 594
0bf9e31a 595 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
dbda808a
FB		 596 if (addr & 0xF)
597 return;
b7169916
AJ		 598#if defined TARGET_WORDS_BIGENDIAN
599 val = openpic_swap32(opp, val);
dbda808a
FB		 600#endif
601 addr &= 0xFF;
602 switch (addr) {
603 case 0x00: /* FREP */
604 break;
605 case 0x20: /* GLBC */
b7169916
AJ		 606 if (val & 0x80000000 && opp->reset)
607 opp->reset(opp);
dbda808a
FB		 608 opp->glbc = val & ~0x80000000;
609 break;
610 case 0x80: /* VENI */
611 break;
612 case 0x90: /* PINT */
e9df014c
JM		 613 for (idx = 0; idx < opp->nb_cpus; idx++) {
614 if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
615 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
616 dst = &opp->dst[idx];
617 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
618 } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) {
619 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
620 dst = &opp->dst[idx];
621 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
622 }
dbda808a 623 }
e9df014c 624 opp->pint = val;
dbda808a
FB		 625 break;
626#if MAX_IPI > 0
627 case 0xA0: /* IPI_IPVP */
628 case 0xB0:
629 case 0xC0:
630 case 0xD0:
631 {
632 int idx;
633 idx = (addr - 0xA0) >> 4;
b7169916 634 write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP, val);
dbda808a
FB		 635 }
636 break;
637#endif
638 case 0xE0: /* SPVE */
639 opp->spve = val & 0x000000FF;
640 break;
641 case 0xF0: /* TIFR */
642 opp->tifr = val;
643 break;
644 default:
645 break;
646 }
647}
648
c227f099 649static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
dbda808a 650{
c227f099 651 openpic_t *opp = opaque;
dbda808a
FB		 652 uint32_t retval;
653
0bf9e31a 654 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
dbda808a
FB		 655 retval = 0xFFFFFFFF;
656 if (addr & 0xF)
657 return retval;
658 addr &= 0xFF;
659 switch (addr) {
660 case 0x00: /* FREP */
661 retval = opp->frep;
662 break;
663 case 0x20: /* GLBC */
664 retval = opp->glbc;
665 break;
666 case 0x80: /* VENI */
667 retval = opp->veni;
668 break;
669 case 0x90: /* PINT */
670 retval = 0x00000000;
671 break;
672#if MAX_IPI > 0
673 case 0xA0: /* IPI_IPVP */
674 case 0xB0:
675 case 0xC0:
676 case 0xD0:
677 {
678 int idx;
679 idx = (addr - 0xA0) >> 4;
b7169916 680 retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP);
dbda808a
FB		 681 }
682 break;
683#endif
684 case 0xE0: /* SPVE */
685 retval = opp->spve;
686 break;
687 case 0xF0: /* TIFR */
688 retval = opp->tifr;
689 break;
690 default:
691 break;
692 }
693 DPRINTF("%s: => %08x\n", __func__, retval);
b7169916
AJ		 694#if defined TARGET_WORDS_BIGENDIAN
695 retval = openpic_swap32(opp, retval);
dbda808a
FB		 696#endif
697
698 return retval;
699}
700
701static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
702{
c227f099 703 openpic_t *opp = opaque;
dbda808a
FB		 704 int idx;
705
706 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
707 if (addr & 0xF)
708 return;
b7169916
AJ		 709#if defined TARGET_WORDS_BIGENDIAN
710 val = openpic_swap32(opp, val);
dbda808a
FB		 711#endif
712 addr -= 0x1100;
713 addr &= 0xFFFF;
714 idx = (addr & 0xFFF0) >> 6;
715 addr = addr & 0x30;
716 switch (addr) {
717 case 0x00: /* TICC */
718 break;
719 case 0x10: /* TIBC */
720 if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
8adbc566 721 (val & 0x80000000) == 0 &&
dbda808a
FB		 722 (opp->timers[idx].tibc & 0x80000000) != 0)
723 opp->timers[idx].ticc &= ~0x80000000;
724 opp->timers[idx].tibc = val;
725 break;
726 case 0x20: /* TIVP */
b7169916 727 write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP, val);
dbda808a
FB		 728 break;
729 case 0x30: /* TIDE */
b7169916 730 write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE, val);
dbda808a
FB		 731 break;
732 }
733}
734
735static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
736{
c227f099 737 openpic_t *opp = opaque;
dbda808a
FB		 738 uint32_t retval;
739 int idx;
740
741 DPRINTF("%s: addr %08x\n", __func__, addr);
742 retval = 0xFFFFFFFF;
743 if (addr & 0xF)
744 return retval;
745 addr -= 0x1100;
746 addr &= 0xFFFF;
747 idx = (addr & 0xFFF0) >> 6;
748 addr = addr & 0x30;
749 switch (addr) {
750 case 0x00: /* TICC */
751 retval = opp->timers[idx].ticc;
752 break;
753 case 0x10: /* TIBC */
754 retval = opp->timers[idx].tibc;
755 break;
756 case 0x20: /* TIPV */
b7169916 757 retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP);
dbda808a
FB		 758 break;
759 case 0x30: /* TIDE */
b7169916 760 retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE);
dbda808a
FB		 761 break;
762 }
763 DPRINTF("%s: => %08x\n", __func__, retval);
b7169916
AJ		 764#if defined TARGET_WORDS_BIGENDIAN
765 retval = openpic_swap32(opp, retval);
dbda808a
FB		 766#endif
767
768 return retval;
769}
770
771static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
772{
c227f099 773 openpic_t *opp = opaque;
dbda808a
FB		 774 int idx;
775
776 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
777 if (addr & 0xF)
778 return;
b7169916
AJ		 779#if defined TARGET_WORDS_BIGENDIAN
780 val = openpic_swap32(opp, val);
dbda808a
FB		 781#endif
782 addr = addr & 0xFFF0;
783 idx = addr >> 5;
784 if (addr & 0x10) {
785 /* EXDE / IFEDE / IEEDE */
786 write_IRQreg(opp, idx, IRQ_IDE, val);
787 } else {
788 /* EXVP / IFEVP / IEEVP */
789 write_IRQreg(opp, idx, IRQ_IPVP, val);
790 }
791}
792
793static uint32_t openpic_src_read (void *opaque, uint32_t addr)
794{
c227f099 795 openpic_t *opp = opaque;
dbda808a
FB		 796 uint32_t retval;
797 int idx;
798
799 DPRINTF("%s: addr %08x\n", __func__, addr);
800 retval = 0xFFFFFFFF;
801 if (addr & 0xF)
802 return retval;
803 addr = addr & 0xFFF0;
804 idx = addr >> 5;
805 if (addr & 0x10) {
806 /* EXDE / IFEDE / IEEDE */
807 retval = read_IRQreg(opp, idx, IRQ_IDE);
808 } else {
809 /* EXVP / IFEVP / IEEVP */
810 retval = read_IRQreg(opp, idx, IRQ_IPVP);
811 }
812 DPRINTF("%s: => %08x\n", __func__, retval);
b7169916
AJ		 813#if defined TARGET_WORDS_BIGENDIAN
814 retval = openpic_swap32(opp, retval);
dbda808a
FB		 815#endif
816
817 return retval;
818}
819
c227f099 820static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val)
dbda808a 821{
c227f099
AL		 822 openpic_t *opp = opaque;
823 IRQ_src_t *src;
824 IRQ_dst_t *dst;
e9df014c 825 int idx, s_IRQ, n_IRQ;
dbda808a 826
0bf9e31a 827 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
dbda808a
FB		 828 if (addr & 0xF)
829 return;
b7169916
AJ		 830#if defined TARGET_WORDS_BIGENDIAN
831 val = openpic_swap32(opp, val);
dbda808a
FB		 832#endif
833 addr &= 0x1FFF0;
834 idx = addr / 0x1000;
835 dst = &opp->dst[idx];
836 addr &= 0xFF0;
837 switch (addr) {
838#if MAX_IPI > 0
839 case 0x40: /* PIPD */
840 case 0x50:
841 case 0x60:
842 case 0x70:
843 idx = (addr - 0x40) >> 4;
b7169916
AJ		 844 write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE, val);
845 openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
846 openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
dbda808a
FB		 847 break;
848#endif
849 case 0x80: /* PCTP */
850 dst->pctp = val & 0x0000000F;
851 break;
852 case 0x90: /* WHOAMI */
853 /* Read-only register */
854 break;
855 case 0xA0: /* PIAC */
856 /* Read-only register */
857 break;
858 case 0xB0: /* PEOI */
859 DPRINTF("PEOI\n");
e9df014c
JM		 860 s_IRQ = IRQ_get_next(opp, &dst->servicing);
861 IRQ_resetbit(&dst->servicing, s_IRQ);
dbda808a 862 dst->servicing.next = -1;
dbda808a 863 /* Set up next servicing IRQ */
e9df014c
JM		 864 s_IRQ = IRQ_get_next(opp, &dst->servicing);
865 /* Check queued interrupts. */
866 n_IRQ = IRQ_get_next(opp, &dst->raised);
867 src = &opp->src[n_IRQ];
868 if (n_IRQ != -1 &&
869 (s_IRQ == -1 ||
870 IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) {
871 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
872 idx, n_IRQ);
b7169916 873 opp->irq_raise(opp, idx, src);
e9df014c 874 }
dbda808a
FB		 875 break;
876 default:
877 break;
878 }
879}
880
c227f099 881static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
dbda808a 882{
c227f099
AL		 883 openpic_t *opp = opaque;
884 IRQ_src_t *src;
885 IRQ_dst_t *dst;
dbda808a
FB		 886 uint32_t retval;
887 int idx, n_IRQ;
3b46e624 888
0bf9e31a 889 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
dbda808a
FB		 890 retval = 0xFFFFFFFF;
891 if (addr & 0xF)
892 return retval;
893 addr &= 0x1FFF0;
894 idx = addr / 0x1000;
895 dst = &opp->dst[idx];
896 addr &= 0xFF0;
897 switch (addr) {
898 case 0x80: /* PCTP */
899 retval = dst->pctp;
900 break;
901 case 0x90: /* WHOAMI */
902 retval = idx;
903 break;
904 case 0xA0: /* PIAC */
e9df014c
JM		 905 DPRINTF("Lower OpenPIC INT output\n");
906 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
dbda808a
FB		 907 n_IRQ = IRQ_get_next(opp, &dst->raised);
908 DPRINTF("PIAC: irq=%d\n", n_IRQ);
909 if (n_IRQ == -1) {
910 /* No more interrupt pending */
e9df014c 911 retval = IPVP_VECTOR(opp->spve);
dbda808a
FB		 912 } else {
913 src = &opp->src[n_IRQ];
914 if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
915 !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
916 /* - Spurious level-sensitive IRQ
917 * - Priorities has been changed
918 * and the pending IRQ isn't allowed anymore
919 */
920 reset_bit(&src->ipvp, IPVP_ACTIVITY);
921 retval = IPVP_VECTOR(opp->spve);
922 } else {
923 /* IRQ enter servicing state */
924 IRQ_setbit(&dst->servicing, n_IRQ);
925 retval = IPVP_VECTOR(src->ipvp);
926 }
927 IRQ_resetbit(&dst->raised, n_IRQ);
928 dst->raised.next = -1;
611493d9
FB		 929 if (!test_bit(&src->ipvp, IPVP_SENSE)) {
930 /* edge-sensitive IRQ */
dbda808a 931 reset_bit(&src->ipvp, IPVP_ACTIVITY);
611493d9
FB		 932 src->pending = 0;
933 }
dbda808a
FB		 934 }
935 break;
936 case 0xB0: /* PEOI */
937 retval = 0;
938 break;
939#if MAX_IPI > 0
940 case 0x40: /* IDE */
941 case 0x50:
942 idx = (addr - 0x40) >> 4;
b7169916 943 retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE);
dbda808a
FB		 944 break;
945#endif
946 default:
947 break;
948 }
949 DPRINTF("%s: => %08x\n", __func__, retval);
b7169916
AJ		 950#if defined TARGET_WORDS_BIGENDIAN
951 retval = openpic_swap32(opp, retval);
dbda808a
FB		 952#endif
953
954 return retval;
955}
956
957static void openpic_buggy_write (void *opaque,
c227f099 958 target_phys_addr_t addr, uint32_t val)
dbda808a
FB		 959{
960 printf("Invalid OPENPIC write access !\n");
961}
962
c227f099 963static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
dbda808a
FB		 964{
965 printf("Invalid OPENPIC read access !\n");
966
967 return -1;
968}
969
970static void openpic_writel (void *opaque,
c227f099 971 target_phys_addr_t addr, uint32_t val)
dbda808a 972{
c227f099 973 openpic_t *opp = opaque;
dbda808a
FB		 974
975 addr &= 0x3FFFF;
611493d9 976 DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
dbda808a
FB		 977 if (addr < 0x1100) {
978 /* Global registers */
979 openpic_gbl_write(opp, addr, val);
980 } else if (addr < 0x10000) {
981 /* Timers registers */
982 openpic_timer_write(opp, addr, val);
983 } else if (addr < 0x20000) {
984 /* Source registers */
985 openpic_src_write(opp, addr, val);
986 } else {
987 /* CPU registers */
988 openpic_cpu_write(opp, addr, val);
989 }
990}
991
c227f099 992static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
dbda808a 993{
c227f099 994 openpic_t *opp = opaque;
dbda808a
FB		 995 uint32_t retval;
996
997 addr &= 0x3FFFF;
611493d9 998 DPRINTF("%s: offset %08x\n", __func__, (int)addr);
dbda808a
FB		 999 if (addr < 0x1100) {
1000 /* Global registers */
1001 retval = openpic_gbl_read(opp, addr);
1002 } else if (addr < 0x10000) {
1003 /* Timers registers */
1004 retval = openpic_timer_read(opp, addr);
1005 } else if (addr < 0x20000) {
1006 /* Source registers */
1007 retval = openpic_src_read(opp, addr);
1008 } else {
1009 /* CPU registers */
1010 retval = openpic_cpu_read(opp, addr);
1011 }
1012
1013 return retval;
1014}
1015
d60efc6b 1016static CPUWriteMemoryFunc * const openpic_write[] = {
dbda808a
FB		 1017 &openpic_buggy_write,
1018 &openpic_buggy_write,
1019 &openpic_writel,
1020};
1021
d60efc6b 1022static CPUReadMemoryFunc * const openpic_read[] = {
dbda808a
FB		 1023 &openpic_buggy_read,
1024 &openpic_buggy_read,
1025 &openpic_readl,
1026};
1027
5fafdf24 1028static void openpic_map(PCIDevice *pci_dev, int region_num,
6e355d90 1029 pcibus_t addr, pcibus_t size, int type)
dbda808a 1030{
c227f099 1031 openpic_t *opp;
dbda808a
FB		 1032
1033 DPRINTF("Map OpenPIC\n");
c227f099 1034 opp = (openpic_t *)pci_dev;
dbda808a
FB		 1035 /* Global registers */
1036 DPRINTF("Register OPENPIC gbl %08x => %08x\n",
1037 addr + 0x1000, addr + 0x1000 + 0x100);
1038 /* Timer registers */
1039 DPRINTF("Register OPENPIC timer %08x => %08x\n",
1040 addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR);
1041 /* Interrupt source registers */
1042 DPRINTF("Register OPENPIC src %08x => %08x\n",
b7169916 1043 addr + 0x10000, addr + 0x10000 + 0x20 * (OPENPIC_EXT_IRQ + 2));
dbda808a
FB		 1044 /* Per CPU registers */
1045 DPRINTF("Register OPENPIC dst %08x => %08x\n",
1046 addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
91d848eb 1047 cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
dbda808a 1048#if 0 // Don't implement ISU for now
1eed09cb 1049 opp_io_memory = cpu_register_io_memory(openpic_src_read,
dbda808a
FB		 1050 openpic_src_write);
1051 cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
1052 opp_io_memory);
1053#endif
1054}
1055
c227f099 1056static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
67b55785
BS		 1057{
1058 unsigned int i;
1059
1060 for (i = 0; i < BF_WIDTH(MAX_IRQ); i++)
1061 qemu_put_be32s(f, &q->queue[i]);
1062
1063 qemu_put_sbe32s(f, &q->next);
1064 qemu_put_sbe32s(f, &q->priority);
1065}
1066
1067static void openpic_save(QEMUFile* f, void *opaque)
1068{
c227f099 1069 openpic_t *opp = (openpic_t *)opaque;
67b55785
BS		 1070 unsigned int i;
1071
1072 qemu_put_be32s(f, &opp->frep);
1073 qemu_put_be32s(f, &opp->glbc);
1074 qemu_put_be32s(f, &opp->micr);
1075 qemu_put_be32s(f, &opp->veni);
1076 qemu_put_be32s(f, &opp->pint);
1077 qemu_put_be32s(f, &opp->spve);
1078 qemu_put_be32s(f, &opp->tifr);
1079
b7169916 1080 for (i = 0; i < opp->max_irq; i++) {
67b55785
BS		 1081 qemu_put_be32s(f, &opp->src[i].ipvp);
1082 qemu_put_be32s(f, &opp->src[i].ide);
1083 qemu_put_sbe32s(f, &opp->src[i].type);
1084 qemu_put_sbe32s(f, &opp->src[i].last_cpu);
1085 qemu_put_sbe32s(f, &opp->src[i].pending);
1086 }
1087
b7169916
AJ		 1088 qemu_put_sbe32s(f, &opp->nb_cpus);
1089
1090 for (i = 0; i < opp->nb_cpus; i++) {
1091 qemu_put_be32s(f, &opp->dst[i].tfrr);
67b55785
BS		 1092 qemu_put_be32s(f, &opp->dst[i].pctp);
1093 qemu_put_be32s(f, &opp->dst[i].pcsr);
1094 openpic_save_IRQ_queue(f, &opp->dst[i].raised);
1095 openpic_save_IRQ_queue(f, &opp->dst[i].servicing);
1096 }
1097
67b55785
BS		 1098 for (i = 0; i < MAX_TMR; i++) {
1099 qemu_put_be32s(f, &opp->timers[i].ticc);
1100 qemu_put_be32s(f, &opp->timers[i].tibc);
1101 }
1102
1103#if MAX_DBL > 0
1104 qemu_put_be32s(f, &opp->dar);
1105
1106 for (i = 0; i < MAX_DBL; i++) {
1107 qemu_put_be32s(f, &opp->doorbells[i].dmr);
1108 }
1109#endif
1110
1111#if MAX_MBX > 0
1112 for (i = 0; i < MAX_MAILBOXES; i++) {
1113 qemu_put_be32s(f, &opp->mailboxes[i].mbr);
1114 }
1115#endif
1116
1117 pci_device_save(&opp->pci_dev, f);
1118}
1119
c227f099 1120static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
67b55785
BS		 1121{
1122 unsigned int i;
1123
1124 for (i = 0; i < BF_WIDTH(MAX_IRQ); i++)
1125 qemu_get_be32s(f, &q->queue[i]);
1126
1127 qemu_get_sbe32s(f, &q->next);
1128 qemu_get_sbe32s(f, &q->priority);
1129}
1130
1131static int openpic_load(QEMUFile* f, void *opaque, int version_id)
1132{
c227f099 1133 openpic_t *opp = (openpic_t *)opaque;
67b55785
BS		 1134 unsigned int i;
1135
1136 if (version_id != 1)
1137 return -EINVAL;
1138
1139 qemu_get_be32s(f, &opp->frep);
1140 qemu_get_be32s(f, &opp->glbc);
1141 qemu_get_be32s(f, &opp->micr);
1142 qemu_get_be32s(f, &opp->veni);
1143 qemu_get_be32s(f, &opp->pint);
1144 qemu_get_be32s(f, &opp->spve);
1145 qemu_get_be32s(f, &opp->tifr);
1146
b7169916 1147 for (i = 0; i < opp->max_irq; i++) {
67b55785
BS		 1148 qemu_get_be32s(f, &opp->src[i].ipvp);
1149 qemu_get_be32s(f, &opp->src[i].ide);
1150 qemu_get_sbe32s(f, &opp->src[i].type);
1151 qemu_get_sbe32s(f, &opp->src[i].last_cpu);
1152 qemu_get_sbe32s(f, &opp->src[i].pending);
1153 }
1154
b7169916
AJ		 1155 qemu_get_sbe32s(f, &opp->nb_cpus);
1156
1157 for (i = 0; i < opp->nb_cpus; i++) {
1158 qemu_get_be32s(f, &opp->dst[i].tfrr);
67b55785
BS		 1159 qemu_get_be32s(f, &opp->dst[i].pctp);
1160 qemu_get_be32s(f, &opp->dst[i].pcsr);
1161 openpic_load_IRQ_queue(f, &opp->dst[i].raised);
1162 openpic_load_IRQ_queue(f, &opp->dst[i].servicing);
1163 }
1164
67b55785
BS		 1165 for (i = 0; i < MAX_TMR; i++) {
1166 qemu_get_be32s(f, &opp->timers[i].ticc);
1167 qemu_get_be32s(f, &opp->timers[i].tibc);
1168 }
1169
1170#if MAX_DBL > 0
1171 qemu_get_be32s(f, &opp->dar);
1172
1173 for (i = 0; i < MAX_DBL; i++) {
1174 qemu_get_be32s(f, &opp->doorbells[i].dmr);
1175 }
1176#endif
1177
1178#if MAX_MBX > 0
1179 for (i = 0; i < MAX_MAILBOXES; i++) {
1180 qemu_get_be32s(f, &opp->mailboxes[i].mbr);
1181 }
1182#endif
1183
1184 return pci_device_load(&opp->pci_dev, f);
1185}
1186
c227f099 1187static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
b7169916
AJ		 1188{
1189 qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
1190}
1191
e9df014c
JM		 1192qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
1193 qemu_irq **irqs, qemu_irq irq_out)
dbda808a 1194{
c227f099 1195 openpic_t *opp;
dbda808a
FB		 1196 uint8_t *pci_conf;
1197 int i, m;
3b46e624 1198
dbda808a
FB		 1199 /* XXX: for now, only one CPU is supported */
1200 if (nb_cpus != 1)
1201 return NULL;
91d848eb 1202 if (bus) {
c227f099 1203 opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
91d848eb 1204 -1, NULL, NULL);
91d848eb 1205 pci_conf = opp->pci_dev.config;
deb54399 1206 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
4ebcf884 1207 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2);
173a543b 1208 pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
6407f373 1209 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
91d848eb 1210 pci_conf[0x3d] = 0x00; // no interrupt pin
3b46e624 1211
91d848eb 1212 /* Register I/O spaces */
28c2c264 1213 pci_register_bar((PCIDevice *)opp, 0, 0x40000,
0392a017 1214 PCI_BASE_ADDRESS_SPACE_MEMORY, &openpic_map);
91d848eb 1215 } else {
c227f099 1216 opp = qemu_mallocz(sizeof(openpic_t));
91d848eb 1217 }
1eed09cb 1218 opp->mem_index = cpu_register_io_memory(openpic_read,
91d848eb 1219 openpic_write, opp);
3b46e624 1220
91d848eb 1221 // isu_base &= 0xFFFC0000;
dbda808a 1222 opp->nb_cpus = nb_cpus;
b7169916
AJ		 1223 opp->max_irq = OPENPIC_MAX_IRQ;
1224 opp->irq_ipi0 = OPENPIC_IRQ_IPI0;
1225 opp->irq_tim0 = OPENPIC_IRQ_TIM0;
dbda808a 1226 /* Set IRQ types */
b7169916 1227 for (i = 0; i < OPENPIC_EXT_IRQ; i++) {
dbda808a
FB		 1228 opp->src[i].type = IRQ_EXTERNAL;
1229 }
b7169916 1230 for (; i < OPENPIC_IRQ_TIM0; i++) {
dbda808a
FB		 1231 opp->src[i].type = IRQ_SPECIAL;
1232 }
1233#if MAX_IPI > 0
b7169916 1234 m = OPENPIC_IRQ_IPI0;
dbda808a 1235#else
b7169916 1236 m = OPENPIC_IRQ_DBL0;
dbda808a
FB		 1237#endif
1238 for (; i < m; i++) {
1239 opp->src[i].type = IRQ_TIMER;
1240 }
b7169916 1241 for (; i < OPENPIC_MAX_IRQ; i++) {
dbda808a
FB		 1242 opp->src[i].type = IRQ_INTERNAL;
1243 }
7668a27f 1244 for (i = 0; i < nb_cpus; i++)
e9df014c
JM		 1245 opp->dst[i].irqs = irqs[i];
1246 opp->irq_out = irq_out;
b7169916 1247 opp->need_swap = 1;
67b55785 1248
b7169916 1249 register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp);
a08d4367 1250 qemu_register_reset(openpic_reset, opp);
b7169916
AJ		 1251
1252 opp->irq_raise = openpic_irq_raise;
1253 opp->reset = openpic_reset;
1254
91d848eb
FB		 1255 if (pmem_index)
1256 *pmem_index = opp->mem_index;
e9df014c 1257
b7169916
AJ		 1258 return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
1259}
1260
c227f099 1261static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
b7169916
AJ		 1262{
1263 int n_ci = IDR_CI0 - n_CPU;
0bf9e31a 1264
b7169916
AJ		 1265 if(test_bit(&src->ide, n_ci)) {
1266 qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
1267 }
1268 else {
1269 qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
1270 }
1271}
1272
1273static void mpic_reset (void *opaque)
1274{
c227f099 1275 openpic_t *mpp = (openpic_t *)opaque;
b7169916
AJ		 1276 int i;
1277
1278 mpp->glbc = 0x80000000;
1279 /* Initialise controller registers */
1280 mpp->frep = 0x004f0002;
1281 mpp->veni = VENI;
1282 mpp->pint = 0x00000000;
1283 mpp->spve = 0x0000FFFF;
1284 /* Initialise IRQ sources */
1285 for (i = 0; i < mpp->max_irq; i++) {
1286 mpp->src[i].ipvp = 0x80800000;
1287 mpp->src[i].ide = 0x00000001;
1288 }
1289 /* Initialise IRQ destinations */
1290 for (i = 0; i < MAX_CPU; i++) {
1291 mpp->dst[i].pctp = 0x0000000F;
1292 mpp->dst[i].tfrr = 0x00000000;
c227f099 1293 memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
b7169916 1294 mpp->dst[i].raised.next = -1;
c227f099 1295 memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
b7169916
AJ		 1296 mpp->dst[i].servicing.next = -1;
1297 }
1298 /* Initialise timers */
1299 for (i = 0; i < MAX_TMR; i++) {
1300 mpp->timers[i].ticc = 0x00000000;
1301 mpp->timers[i].tibc = 0x80000000;
1302 }
1303 /* Go out of RESET state */
1304 mpp->glbc = 0x00000000;
1305}
1306
c227f099 1307static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
b7169916 1308{
c227f099 1309 openpic_t *mpp = opaque;
b7169916
AJ		 1310 int idx, cpu;
1311
0bf9e31a 1312 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
b7169916
AJ		 1313 if (addr & 0xF)
1314 return;
1315 addr &= 0xFFFF;
1316 cpu = addr >> 12;
1317 idx = (addr >> 6) & 0x3;
1318 switch (addr & 0x30) {
1319 case 0x00: /* gtccr */
1320 break;
1321 case 0x10: /* gtbcr */
1322 if ((mpp->timers[idx].ticc & 0x80000000) != 0 &&
1323 (val & 0x80000000) == 0 &&
1324 (mpp->timers[idx].tibc & 0x80000000) != 0)
1325 mpp->timers[idx].ticc &= ~0x80000000;
1326 mpp->timers[idx].tibc = val;
1327 break;
1328 case 0x20: /* GTIVPR */
1329 write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP, val);
1330 break;
1331 case 0x30: /* GTIDR & TFRR */
1332 if ((addr & 0xF0) == 0xF0)
1333 mpp->dst[cpu].tfrr = val;
1334 else
1335 write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE, val);
1336 break;
1337 }
1338}
1339
c227f099 1340static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
b7169916 1341{
c227f099 1342 openpic_t *mpp = opaque;
b7169916
AJ		 1343 uint32_t retval;
1344 int idx, cpu;
1345
0bf9e31a 1346 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
b7169916
AJ		 1347 retval = 0xFFFFFFFF;
1348 if (addr & 0xF)
1349 return retval;
1350 addr &= 0xFFFF;
1351 cpu = addr >> 12;
1352 idx = (addr >> 6) & 0x3;
1353 switch (addr & 0x30) {
1354 case 0x00: /* gtccr */
1355 retval = mpp->timers[idx].ticc;
1356 break;
1357 case 0x10: /* gtbcr */
1358 retval = mpp->timers[idx].tibc;
1359 break;
1360 case 0x20: /* TIPV */
1361 retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP);
1362 break;
1363 case 0x30: /* TIDR */
1364 if ((addr &0xF0) == 0XF0)
1365 retval = mpp->dst[cpu].tfrr;
1366 else
1367 retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE);
1368 break;
1369 }
1370 DPRINTF("%s: => %08x\n", __func__, retval);
1371
1372 return retval;
1373}
1374
c227f099 1375static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
b7169916
AJ		 1376 uint32_t val)
1377{
c227f099 1378 openpic_t *mpp = opaque;
b7169916
AJ		 1379 int idx = MPIC_EXT_IRQ;
1380
0bf9e31a 1381 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
b7169916
AJ		 1382 if (addr & 0xF)
1383 return;
1384
1385 addr -= MPIC_EXT_REG_START & (TARGET_PAGE_SIZE - 1);
1386 if (addr < MPIC_EXT_REG_SIZE) {
1387 idx += (addr & 0xFFF0) >> 5;
1388 if (addr & 0x10) {
1389 /* EXDE / IFEDE / IEEDE */
1390 write_IRQreg(mpp, idx, IRQ_IDE, val);
1391 } else {
1392 /* EXVP / IFEVP / IEEVP */
1393 write_IRQreg(mpp, idx, IRQ_IPVP, val);
1394 }
1395 }
1396}
1397
c227f099 1398static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
b7169916 1399{
c227f099 1400 openpic_t *mpp = opaque;
b7169916
AJ		 1401 uint32_t retval;
1402 int idx = MPIC_EXT_IRQ;
1403
0bf9e31a 1404 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
b7169916
AJ		 1405 retval = 0xFFFFFFFF;
1406 if (addr & 0xF)
1407 return retval;
1408
1409 addr -= MPIC_EXT_REG_START & (TARGET_PAGE_SIZE - 1);
1410 if (addr < MPIC_EXT_REG_SIZE) {
1411 idx += (addr & 0xFFF0) >> 5;
1412 if (addr & 0x10) {
1413 /* EXDE / IFEDE / IEEDE */
1414 retval = read_IRQreg(mpp, idx, IRQ_IDE);
1415 } else {
1416 /* EXVP / IFEVP / IEEVP */
1417 retval = read_IRQreg(mpp, idx, IRQ_IPVP);
1418 }
1419 DPRINTF("%s: => %08x\n", __func__, retval);
1420 }
1421
1422 return retval;
1423}
1424
c227f099 1425static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
b7169916
AJ		 1426 uint32_t val)
1427{
c227f099 1428 openpic_t *mpp = opaque;
b7169916
AJ		 1429 int idx = MPIC_INT_IRQ;
1430
0bf9e31a 1431 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
b7169916
AJ		 1432 if (addr & 0xF)
1433 return;
1434
1435 addr -= MPIC_INT_REG_START & (TARGET_PAGE_SIZE - 1);
1436 if (addr < MPIC_INT_REG_SIZE) {
1437 idx += (addr & 0xFFF0) >> 5;
1438 if (addr & 0x10) {
1439 /* EXDE / IFEDE / IEEDE */
1440 write_IRQreg(mpp, idx, IRQ_IDE, val);
1441 } else {
1442 /* EXVP / IFEVP / IEEVP */
1443 write_IRQreg(mpp, idx, IRQ_IPVP, val);
1444 }
1445 }
1446}
1447
c227f099 1448static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
b7169916 1449{
c227f099 1450 openpic_t *mpp = opaque;
b7169916
AJ		 1451 uint32_t retval;
1452 int idx = MPIC_INT_IRQ;
1453
0bf9e31a 1454 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
b7169916
AJ		 1455 retval = 0xFFFFFFFF;
1456 if (addr & 0xF)
1457 return retval;
1458
1459 addr -= MPIC_INT_REG_START & (TARGET_PAGE_SIZE - 1);
1460 if (addr < MPIC_INT_REG_SIZE) {
1461 idx += (addr & 0xFFF0) >> 5;
1462 if (addr & 0x10) {
1463 /* EXDE / IFEDE / IEEDE */
1464 retval = read_IRQreg(mpp, idx, IRQ_IDE);
1465 } else {
1466 /* EXVP / IFEVP / IEEVP */
1467 retval = read_IRQreg(mpp, idx, IRQ_IPVP);
1468 }
1469 DPRINTF("%s: => %08x\n", __func__, retval);
1470 }
1471
1472 return retval;
1473}
1474
c227f099 1475static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
b7169916
AJ		 1476 uint32_t val)
1477{
c227f099 1478 openpic_t *mpp = opaque;
b7169916
AJ		 1479 int idx = MPIC_MSG_IRQ;
1480
0bf9e31a 1481 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
b7169916
AJ		 1482 if (addr & 0xF)
1483 return;
1484
1485 addr -= MPIC_MSG_REG_START & (TARGET_PAGE_SIZE - 1);
1486 if (addr < MPIC_MSG_REG_SIZE) {
1487 idx += (addr & 0xFFF0) >> 5;
1488 if (addr & 0x10) {
1489 /* EXDE / IFEDE / IEEDE */
1490 write_IRQreg(mpp, idx, IRQ_IDE, val);
1491 } else {
1492 /* EXVP / IFEVP / IEEVP */
1493 write_IRQreg(mpp, idx, IRQ_IPVP, val);
1494 }
1495 }
1496}
1497
c227f099 1498static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
b7169916 1499{
c227f099 1500 openpic_t *mpp = opaque;
b7169916
AJ		 1501 uint32_t retval;
1502 int idx = MPIC_MSG_IRQ;
1503
0bf9e31a 1504 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
b7169916
AJ		 1505 retval = 0xFFFFFFFF;
1506 if (addr & 0xF)
1507 return retval;
1508
1509 addr -= MPIC_MSG_REG_START & (TARGET_PAGE_SIZE - 1);
1510 if (addr < MPIC_MSG_REG_SIZE) {
1511 idx += (addr & 0xFFF0) >> 5;
1512 if (addr & 0x10) {
1513 /* EXDE / IFEDE / IEEDE */
1514 retval = read_IRQreg(mpp, idx, IRQ_IDE);
1515 } else {
1516 /* EXVP / IFEVP / IEEVP */
1517 retval = read_IRQreg(mpp, idx, IRQ_IPVP);
1518 }
1519 DPRINTF("%s: => %08x\n", __func__, retval);
1520 }
1521
1522 return retval;
1523}
1524
c227f099 1525static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
b7169916
AJ		 1526 uint32_t val)
1527{
c227f099 1528 openpic_t *mpp = opaque;
b7169916
AJ		 1529 int idx = MPIC_MSI_IRQ;
1530
0bf9e31a 1531 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
b7169916
AJ		 1532 if (addr & 0xF)
1533 return;
1534
1535 addr -= MPIC_MSI_REG_START & (TARGET_PAGE_SIZE - 1);
1536 if (addr < MPIC_MSI_REG_SIZE) {
1537 idx += (addr & 0xFFF0) >> 5;
1538 if (addr & 0x10) {
1539 /* EXDE / IFEDE / IEEDE */
1540 write_IRQreg(mpp, idx, IRQ_IDE, val);
1541 } else {
1542 /* EXVP / IFEVP / IEEVP */
1543 write_IRQreg(mpp, idx, IRQ_IPVP, val);
1544 }
1545 }
1546}
c227f099 1547static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
b7169916 1548{
c227f099 1549 openpic_t *mpp = opaque;
b7169916
AJ		 1550 uint32_t retval;
1551 int idx = MPIC_MSI_IRQ;
1552
0bf9e31a 1553 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
b7169916
AJ		 1554 retval = 0xFFFFFFFF;
1555 if (addr & 0xF)
1556 return retval;
1557
1558 addr -= MPIC_MSI_REG_START & (TARGET_PAGE_SIZE - 1);
1559 if (addr < MPIC_MSI_REG_SIZE) {
1560 idx += (addr & 0xFFF0) >> 5;
1561 if (addr & 0x10) {
1562 /* EXDE / IFEDE / IEEDE */
1563 retval = read_IRQreg(mpp, idx, IRQ_IDE);
1564 } else {
1565 /* EXVP / IFEVP / IEEVP */
1566 retval = read_IRQreg(mpp, idx, IRQ_IPVP);
1567 }
1568 DPRINTF("%s: => %08x\n", __func__, retval);
1569 }
1570
1571 return retval;
1572}
1573
d60efc6b 1574static CPUWriteMemoryFunc * const mpic_glb_write[] = {
b7169916
AJ		 1575 &openpic_buggy_write,
1576 &openpic_buggy_write,
1577 &openpic_gbl_write,
1578};
1579
d60efc6b 1580static CPUReadMemoryFunc * const mpic_glb_read[] = {
b7169916
AJ		 1581 &openpic_buggy_read,
1582 &openpic_buggy_read,
1583 &openpic_gbl_read,
1584};
1585
d60efc6b 1586static CPUWriteMemoryFunc * const mpic_tmr_write[] = {
b7169916
AJ		 1587 &openpic_buggy_write,
1588 &openpic_buggy_write,
1589 &mpic_timer_write,
1590};
1591
d60efc6b 1592static CPUReadMemoryFunc * const mpic_tmr_read[] = {
b7169916
AJ		 1593 &openpic_buggy_read,
1594 &openpic_buggy_read,
1595 &mpic_timer_read,
1596};
1597
d60efc6b 1598static CPUWriteMemoryFunc * const mpic_cpu_write[] = {
b7169916
AJ		 1599 &openpic_buggy_write,
1600 &openpic_buggy_write,
1601 &openpic_cpu_write,
1602};
1603
d60efc6b 1604static CPUReadMemoryFunc * const mpic_cpu_read[] = {
b7169916
AJ		 1605 &openpic_buggy_read,
1606 &openpic_buggy_read,
1607 &openpic_cpu_read,
1608};
1609
d60efc6b 1610static CPUWriteMemoryFunc * const mpic_ext_write[] = {
b7169916
AJ		 1611 &openpic_buggy_write,
1612 &openpic_buggy_write,
1613 &mpic_src_ext_write,
1614};
1615
d60efc6b 1616static CPUReadMemoryFunc * const mpic_ext_read[] = {
b7169916
AJ		 1617 &openpic_buggy_read,
1618 &openpic_buggy_read,
1619 &mpic_src_ext_read,
1620};
1621
d60efc6b 1622static CPUWriteMemoryFunc * const mpic_int_write[] = {
b7169916
AJ		 1623 &openpic_buggy_write,
1624 &openpic_buggy_write,
1625 &mpic_src_int_write,
1626};
1627
d60efc6b 1628static CPUReadMemoryFunc * const mpic_int_read[] = {
b7169916
AJ		 1629 &openpic_buggy_read,
1630 &openpic_buggy_read,
1631 &mpic_src_int_read,
1632};
1633
d60efc6b 1634static CPUWriteMemoryFunc * const mpic_msg_write[] = {
b7169916
AJ		 1635 &openpic_buggy_write,
1636 &openpic_buggy_write,
1637 &mpic_src_msg_write,
1638};
1639
d60efc6b 1640static CPUReadMemoryFunc * const mpic_msg_read[] = {
b7169916
AJ		 1641 &openpic_buggy_read,
1642 &openpic_buggy_read,
1643 &mpic_src_msg_read,
1644};
d60efc6b 1645static CPUWriteMemoryFunc * const mpic_msi_write[] = {
b7169916
AJ		 1646 &openpic_buggy_write,
1647 &openpic_buggy_write,
1648 &mpic_src_msi_write,
1649};
1650
d60efc6b 1651static CPUReadMemoryFunc * const mpic_msi_read[] = {
b7169916
AJ		 1652 &openpic_buggy_read,
1653 &openpic_buggy_read,
1654 &mpic_src_msi_read,
1655};
1656
c227f099 1657qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
b7169916
AJ		 1658 qemu_irq **irqs, qemu_irq irq_out)
1659{
c227f099 1660 openpic_t *mpp;
b7169916
AJ		 1661 int i;
1662 struct {
d60efc6b
BS		 1663 CPUReadMemoryFunc * const *read;
1664 CPUWriteMemoryFunc * const *write;
c227f099
AL		 1665 target_phys_addr_t start_addr;
1666 ram_addr_t size;
dfebf62b 1667 } const list[] = {
b7169916
AJ		 1668 {mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
1669 {mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
1670 {mpic_ext_read, mpic_ext_write, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
1671 {mpic_int_read, mpic_int_write, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
1672 {mpic_msg_read, mpic_msg_write, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
1673 {mpic_msi_read, mpic_msi_write, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
1674 {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
1675 };
1676
1677 /* XXX: for now, only one CPU is supported */
1678 if (nb_cpus != 1)
1679 return NULL;
1680
c227f099 1681 mpp = qemu_mallocz(sizeof(openpic_t));
b7169916
AJ		 1682
1683 for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
1684 int mem_index;
1685
1eed09cb 1686 mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp);
b7169916
AJ		 1687 if (mem_index < 0) {
1688 goto free;
1689 }
1690 cpu_register_physical_memory(base + list[i].start_addr,
1691 list[i].size, mem_index);
1692 }
1693
1694 mpp->nb_cpus = nb_cpus;
1695 mpp->max_irq = MPIC_MAX_IRQ;
1696 mpp->irq_ipi0 = MPIC_IPI_IRQ;
1697 mpp->irq_tim0 = MPIC_TMR_IRQ;
1698
1699 for (i = 0; i < nb_cpus; i++)
1700 mpp->dst[i].irqs = irqs[i];
1701 mpp->irq_out = irq_out;
1702 mpp->need_swap = 0; /* MPIC has the same endian as target */
1703
1704 mpp->irq_raise = mpic_irq_raise;
1705 mpp->reset = mpic_reset;
1706
1707 register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
a08d4367 1708 qemu_register_reset(mpic_reset, mpp);
b7169916
AJ		 1709
1710 return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
1711
1712free:
1713 qemu_free(mpp);
1714 return NULL;
dbda808a 1715}
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