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dbda808a FB |
1 | /* |
2 | * OpenPIC emulation | |
5fafdf24 | 3 | * |
dbda808a | 4 | * Copyright (c) 2004 Jocelyn Mayer |
704c7e5d | 5 | * 2011 Alexander Graf |
5fafdf24 | 6 | * |
dbda808a FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | /* | |
26 | * | |
27 | * Based on OpenPic implementations: | |
67b55785 | 28 | * - Intel GW80314 I/O companion chip developer's manual |
dbda808a FB |
29 | * - Motorola MPC8245 & MPC8540 user manuals. |
30 | * - Motorola MCP750 (aka Raven) programmer manual. | |
31 | * - Motorola Harrier programmer manuel | |
32 | * | |
33 | * Serial interrupts, as implemented in Raven chipset are not supported yet. | |
5fafdf24 | 34 | * |
dbda808a | 35 | */ |
87ecb68b PB |
36 | #include "hw.h" |
37 | #include "ppc_mac.h" | |
a2cb15b0 | 38 | #include "pci/pci.h" |
b7169916 | 39 | #include "openpic.h" |
d0b72631 | 40 | #include "sysbus.h" |
6f991980 | 41 | #include "pci/msi.h" |
e69a17f6 | 42 | #include "qemu/bitops.h" |
dbda808a | 43 | |
611493d9 | 44 | //#define DEBUG_OPENPIC |
dbda808a FB |
45 | |
46 | #ifdef DEBUG_OPENPIC | |
4c4f0e48 | 47 | static const int debug_openpic = 1; |
dbda808a | 48 | #else |
4c4f0e48 | 49 | static const int debug_openpic = 0; |
dbda808a | 50 | #endif |
dbda808a | 51 | |
4c4f0e48 SW |
52 | #define DPRINTF(fmt, ...) do { \ |
53 | if (debug_openpic) { \ | |
54 | printf(fmt , ## __VA_ARGS__); \ | |
55 | } \ | |
56 | } while (0) | |
57 | ||
cdbb912a AG |
58 | #define MAX_CPU 15 |
59 | #define MAX_SRC 256 | |
dbda808a | 60 | #define MAX_TMR 4 |
dbda808a | 61 | #define MAX_IPI 4 |
732aa6ec | 62 | #define MAX_MSI 8 |
cdbb912a | 63 | #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR) |
dbda808a | 64 | #define VID 0x03 /* MPIC version ID */ |
dbda808a | 65 | |
d0b72631 | 66 | /* OpenPIC capability flags */ |
be7c236f | 67 | #define OPENPIC_FLAG_IDR_CRIT (1 << 0) |
dbda808a | 68 | |
d0b72631 | 69 | /* OpenPIC address map */ |
780d16b7 AG |
70 | #define OPENPIC_GLB_REG_START 0x0 |
71 | #define OPENPIC_GLB_REG_SIZE 0x10F0 | |
72 | #define OPENPIC_TMR_REG_START 0x10F0 | |
73 | #define OPENPIC_TMR_REG_SIZE 0x220 | |
732aa6ec AG |
74 | #define OPENPIC_MSI_REG_START 0x1600 |
75 | #define OPENPIC_MSI_REG_SIZE 0x200 | |
780d16b7 AG |
76 | #define OPENPIC_SRC_REG_START 0x10000 |
77 | #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20) | |
78 | #define OPENPIC_CPU_REG_START 0x20000 | |
79 | #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) | |
80 | ||
d0b72631 AG |
81 | /* Raven */ |
82 | #define RAVEN_MAX_CPU 2 | |
83 | #define RAVEN_MAX_EXT 48 | |
84 | #define RAVEN_MAX_IRQ 64 | |
85 | #define RAVEN_MAX_TMR MAX_TMR | |
86 | #define RAVEN_MAX_IPI MAX_IPI | |
87 | ||
88 | /* Interrupt definitions */ | |
89 | #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ | |
90 | #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ | |
91 | #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ | |
92 | #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ | |
93 | /* First doorbell IRQ */ | |
94 | #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) | |
95 | ||
96 | /* FSL_MPIC_20 */ | |
97 | #define FSL_MPIC_20_MAX_CPU 1 | |
98 | #define FSL_MPIC_20_MAX_EXT 12 | |
99 | #define FSL_MPIC_20_MAX_INT 64 | |
100 | #define FSL_MPIC_20_MAX_IRQ MAX_IRQ | |
dbda808a FB |
101 | |
102 | /* Interrupt definitions */ | |
cdbb912a | 103 | /* IRQs, accessible through the IRQ region */ |
d0b72631 AG |
104 | #define FSL_MPIC_20_EXT_IRQ 0x00 |
105 | #define FSL_MPIC_20_INT_IRQ 0x10 | |
106 | #define FSL_MPIC_20_MSG_IRQ 0xb0 | |
107 | #define FSL_MPIC_20_MSI_IRQ 0xe0 | |
cdbb912a AG |
108 | /* These are available through separate regions, but |
109 | for simplicity's sake mapped into the same number space */ | |
d0b72631 AG |
110 | #define FSL_MPIC_20_TMR_IRQ 0x100 |
111 | #define FSL_MPIC_20_IPI_IRQ 0x104 | |
b7169916 | 112 | |
3e772232 BB |
113 | /* |
114 | * Block Revision Register1 (BRR1): QEMU does not fully emulate | |
115 | * any version on MPIC. So to start with, set the IP version to 0. | |
116 | * | |
117 | * NOTE: This is Freescale MPIC specific register. Keep it here till | |
118 | * this code is refactored for different variants of OPENPIC and MPIC. | |
119 | */ | |
120 | #define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */ | |
121 | #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */ | |
122 | #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */ | |
123 | ||
be7c236f SW |
124 | #define FRR_NIRQ_SHIFT 16 |
125 | #define FRR_NCPU_SHIFT 8 | |
126 | #define FRR_VID_SHIFT 0 | |
825463b3 AG |
127 | |
128 | #define VID_REVISION_1_2 2 | |
d0b72631 | 129 | #define VID_REVISION_1_3 3 |
825463b3 | 130 | |
be7c236f | 131 | #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */ |
825463b3 | 132 | |
be7c236f | 133 | #define GCR_RESET 0x80000000 |
68c2dd70 AG |
134 | #define GCR_MODE_PASS 0x00000000 |
135 | #define GCR_MODE_MIXED 0x20000000 | |
136 | #define GCR_MODE_PROXY 0x60000000 | |
71c6cacb | 137 | |
be7c236f SW |
138 | #define TBCR_CI 0x80000000 /* count inhibit */ |
139 | #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */ | |
825463b3 | 140 | |
1945dbc1 AG |
141 | #define IDR_EP_SHIFT 31 |
142 | #define IDR_EP_MASK (1 << IDR_EP_SHIFT) | |
143 | #define IDR_CI0_SHIFT 30 | |
144 | #define IDR_CI1_SHIFT 29 | |
145 | #define IDR_P1_SHIFT 1 | |
146 | #define IDR_P0_SHIFT 0 | |
b7169916 | 147 | |
732aa6ec AG |
148 | #define MSIIR_OFFSET 0x140 |
149 | #define MSIIR_SRS_SHIFT 29 | |
150 | #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT) | |
151 | #define MSIIR_IBS_SHIFT 24 | |
152 | #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT) | |
153 | ||
704c7e5d AG |
154 | static int get_current_cpu(void) |
155 | { | |
55e5c285 AF |
156 | CPUState *cpu_single_cpu; |
157 | ||
c3203fa5 SW |
158 | if (!cpu_single_env) { |
159 | return -1; | |
160 | } | |
161 | ||
55e5c285 AF |
162 | cpu_single_cpu = ENV_GET_CPU(cpu_single_env); |
163 | return cpu_single_cpu->cpu_index; | |
704c7e5d AG |
164 | } |
165 | ||
a8170e5e | 166 | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
704c7e5d | 167 | int idx); |
a8170e5e | 168 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
704c7e5d AG |
169 | uint32_t val, int idx); |
170 | ||
6c5e84c2 SW |
171 | typedef enum IRQType { |
172 | IRQ_TYPE_NORMAL = 0, | |
173 | IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ | |
174 | IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ | |
175 | } IRQType; | |
176 | ||
af7e9e74 | 177 | typedef struct IRQQueue { |
e69a17f6 SW |
178 | /* Round up to the nearest 64 IRQs so that the queue length |
179 | * won't change when moving between 32 and 64 bit hosts. | |
180 | */ | |
181 | unsigned long queue[BITS_TO_LONGS((MAX_IRQ + 63) & ~63)]; | |
dbda808a FB |
182 | int next; |
183 | int priority; | |
af7e9e74 | 184 | } IRQQueue; |
dbda808a | 185 | |
af7e9e74 | 186 | typedef struct IRQSource { |
be7c236f SW |
187 | uint32_t ivpr; /* IRQ vector/priority register */ |
188 | uint32_t idr; /* IRQ destination register */ | |
5e22c276 | 189 | uint32_t destmask; /* bitmap of CPU destinations */ |
dbda808a | 190 | int last_cpu; |
5e22c276 | 191 | int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ |
611493d9 | 192 | int pending; /* TRUE if IRQ is pending */ |
6c5e84c2 SW |
193 | IRQType type; |
194 | bool level:1; /* level-triggered */ | |
72c1da2c | 195 | bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ |
af7e9e74 | 196 | } IRQSource; |
dbda808a | 197 | |
be7c236f SW |
198 | #define IVPR_MASK_SHIFT 31 |
199 | #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT) | |
200 | #define IVPR_ACTIVITY_SHIFT 30 | |
201 | #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT) | |
202 | #define IVPR_MODE_SHIFT 29 | |
203 | #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT) | |
204 | #define IVPR_POLARITY_SHIFT 23 | |
205 | #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT) | |
206 | #define IVPR_SENSE_SHIFT 22 | |
207 | #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT) | |
208 | ||
209 | #define IVPR_PRIORITY_MASK (0xF << 16) | |
210 | #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) | |
211 | #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) | |
212 | ||
213 | /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ | |
214 | #define IDR_EP 0x80000000 /* external pin */ | |
215 | #define IDR_CI 0x40000000 /* critical interrupt */ | |
71c6cacb | 216 | |
af7e9e74 | 217 | typedef struct IRQDest { |
eb438427 | 218 | int32_t ctpr; /* CPU current task priority */ |
af7e9e74 AG |
219 | IRQQueue raised; |
220 | IRQQueue servicing; | |
e9df014c | 221 | qemu_irq *irqs; |
9f1d4b1d SW |
222 | |
223 | /* Count of IRQ sources asserting on non-INT outputs */ | |
224 | uint32_t outputs_active[OPENPIC_OUTPUT_NB]; | |
af7e9e74 | 225 | } IRQDest; |
dbda808a | 226 | |
6d544ee8 | 227 | typedef struct OpenPICState { |
d0b72631 | 228 | SysBusDevice busdev; |
23c5e4ca | 229 | MemoryRegion mem; |
71cf9e62 | 230 | |
5861a338 | 231 | /* Behavior control */ |
d0b72631 | 232 | uint32_t model; |
5861a338 | 233 | uint32_t flags; |
825463b3 AG |
234 | uint32_t nb_irqs; |
235 | uint32_t vid; | |
be7c236f | 236 | uint32_t vir; /* Vendor identification register */ |
0fe04622 | 237 | uint32_t vector_mask; |
be7c236f SW |
238 | uint32_t tfrr_reset; |
239 | uint32_t ivpr_reset; | |
240 | uint32_t idr_reset; | |
dbbbfd60 | 241 | uint32_t brr1; |
68c2dd70 | 242 | uint32_t mpic_mode_mask; |
5861a338 | 243 | |
71cf9e62 | 244 | /* Sub-regions */ |
732aa6ec | 245 | MemoryRegion sub_io_mem[5]; |
71cf9e62 | 246 | |
dbda808a | 247 | /* Global registers */ |
be7c236f SW |
248 | uint32_t frr; /* Feature reporting register */ |
249 | uint32_t gcr; /* Global configuration register */ | |
250 | uint32_t pir; /* Processor initialization register */ | |
dbda808a | 251 | uint32_t spve; /* Spurious vector register */ |
be7c236f | 252 | uint32_t tfrr; /* Timer frequency reporting register */ |
dbda808a | 253 | /* Source registers */ |
af7e9e74 | 254 | IRQSource src[MAX_IRQ]; |
dbda808a | 255 | /* Local registers per output pin */ |
af7e9e74 | 256 | IRQDest dst[MAX_CPU]; |
d0b72631 | 257 | uint32_t nb_cpus; |
dbda808a FB |
258 | /* Timer registers */ |
259 | struct { | |
be7c236f SW |
260 | uint32_t tccr; /* Global timer current count register */ |
261 | uint32_t tbcr; /* Global timer base count register */ | |
dbda808a | 262 | } timers[MAX_TMR]; |
732aa6ec AG |
263 | /* Shared MSI registers */ |
264 | struct { | |
265 | uint32_t msir; /* Shared Message Signaled Interrupt Register */ | |
266 | } msi[MAX_MSI]; | |
d0b72631 AG |
267 | uint32_t max_irq; |
268 | uint32_t irq_ipi0; | |
269 | uint32_t irq_tim0; | |
732aa6ec | 270 | uint32_t irq_msi; |
6d544ee8 | 271 | } OpenPICState; |
dbda808a | 272 | |
af7e9e74 | 273 | static inline void IRQ_setbit(IRQQueue *q, int n_IRQ) |
dbda808a | 274 | { |
e69a17f6 | 275 | set_bit(n_IRQ, q->queue); |
dbda808a FB |
276 | } |
277 | ||
af7e9e74 | 278 | static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ) |
dbda808a | 279 | { |
e69a17f6 | 280 | clear_bit(n_IRQ, q->queue); |
dbda808a FB |
281 | } |
282 | ||
af7e9e74 | 283 | static inline int IRQ_testbit(IRQQueue *q, int n_IRQ) |
dbda808a | 284 | { |
e69a17f6 | 285 | return test_bit(n_IRQ, q->queue); |
dbda808a FB |
286 | } |
287 | ||
af7e9e74 | 288 | static void IRQ_check(OpenPICState *opp, IRQQueue *q) |
dbda808a | 289 | { |
4417c733 SW |
290 | int irq = -1; |
291 | int next = -1; | |
292 | int priority = -1; | |
293 | ||
294 | for (;;) { | |
295 | irq = find_next_bit(q->queue, opp->max_irq, irq + 1); | |
296 | if (irq == opp->max_irq) { | |
297 | break; | |
298 | } | |
76aec1f8 | 299 | |
4417c733 SW |
300 | DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n", |
301 | irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); | |
76aec1f8 | 302 | |
4417c733 SW |
303 | if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { |
304 | next = irq; | |
305 | priority = IVPR_PRIORITY(opp->src[irq].ivpr); | |
060fbfe1 | 306 | } |
dbda808a | 307 | } |
76aec1f8 | 308 | |
dbda808a FB |
309 | q->next = next; |
310 | q->priority = priority; | |
311 | } | |
312 | ||
af7e9e74 | 313 | static int IRQ_get_next(OpenPICState *opp, IRQQueue *q) |
dbda808a | 314 | { |
3c94378e SW |
315 | /* XXX: optimize */ |
316 | IRQ_check(opp, q); | |
dbda808a FB |
317 | |
318 | return q->next; | |
319 | } | |
320 | ||
9f1d4b1d SW |
321 | static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, |
322 | bool active, bool was_active) | |
dbda808a | 323 | { |
af7e9e74 AG |
324 | IRQDest *dst; |
325 | IRQSource *src; | |
dbda808a FB |
326 | int priority; |
327 | ||
328 | dst = &opp->dst[n_CPU]; | |
329 | src = &opp->src[n_IRQ]; | |
5e22c276 | 330 | |
9f1d4b1d SW |
331 | DPRINTF("%s: IRQ %d active %d was %d\n", |
332 | __func__, n_IRQ, active, was_active); | |
333 | ||
5e22c276 | 334 | if (src->output != OPENPIC_OUTPUT_INT) { |
9f1d4b1d SW |
335 | DPRINTF("%s: output %d irq %d active %d was %d count %d\n", |
336 | __func__, src->output, n_IRQ, active, was_active, | |
337 | dst->outputs_active[src->output]); | |
338 | ||
5e22c276 SW |
339 | /* On Freescale MPIC, critical interrupts ignore priority, |
340 | * IACK, EOI, etc. Before MPIC v4.1 they also ignore | |
341 | * masking. | |
342 | */ | |
9f1d4b1d SW |
343 | if (active) { |
344 | if (!was_active && dst->outputs_active[src->output]++ == 0) { | |
345 | DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n", | |
346 | __func__, src->output, n_CPU, n_IRQ); | |
347 | qemu_irq_raise(dst->irqs[src->output]); | |
348 | } | |
349 | } else { | |
350 | if (was_active && --dst->outputs_active[src->output] == 0) { | |
351 | DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n", | |
352 | __func__, src->output, n_CPU, n_IRQ); | |
353 | qemu_irq_lower(dst->irqs[src->output]); | |
354 | } | |
355 | } | |
356 | ||
060fbfe1 | 357 | return; |
dbda808a | 358 | } |
5e22c276 | 359 | |
be7c236f | 360 | priority = IVPR_PRIORITY(src->ivpr); |
9f1d4b1d SW |
361 | |
362 | /* Even if the interrupt doesn't have enough priority, | |
363 | * it is still raised, in case ctpr is lowered later. | |
364 | */ | |
365 | if (active) { | |
366 | IRQ_setbit(&dst->raised, n_IRQ); | |
367 | } else { | |
368 | IRQ_resetbit(&dst->raised, n_IRQ); | |
dbda808a | 369 | } |
9f1d4b1d | 370 | |
3c94378e | 371 | IRQ_check(opp, &dst->raised); |
9f1d4b1d SW |
372 | |
373 | if (active && priority <= dst->ctpr) { | |
374 | DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n", | |
375 | __func__, n_IRQ, priority, dst->ctpr, n_CPU); | |
376 | active = 0; | |
e9df014c | 377 | } |
9f1d4b1d SW |
378 | |
379 | if (active) { | |
380 | if (IRQ_get_next(opp, &dst->servicing) >= 0 && | |
381 | priority <= dst->servicing.priority) { | |
382 | DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", | |
383 | __func__, n_IRQ, dst->servicing.next, n_CPU); | |
384 | } else { | |
385 | DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n", | |
386 | __func__, n_CPU, n_IRQ, dst->raised.next); | |
387 | qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); | |
388 | } | |
389 | } else { | |
390 | IRQ_get_next(opp, &dst->servicing); | |
391 | if (dst->raised.priority > dst->ctpr && | |
392 | dst->raised.priority > dst->servicing.priority) { | |
393 | DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n", | |
394 | __func__, n_IRQ, dst->raised.next, dst->raised.priority, | |
395 | dst->ctpr, dst->servicing.priority, n_CPU); | |
396 | /* IRQ line stays asserted */ | |
397 | } else { | |
398 | DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n", | |
399 | __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU); | |
400 | qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); | |
401 | } | |
dbda808a FB |
402 | } |
403 | } | |
404 | ||
611493d9 | 405 | /* update pic state because registers for n_IRQ have changed value */ |
6d544ee8 | 406 | static void openpic_update_irq(OpenPICState *opp, int n_IRQ) |
dbda808a | 407 | { |
af7e9e74 | 408 | IRQSource *src; |
9f1d4b1d | 409 | bool active, was_active; |
dbda808a FB |
410 | int i; |
411 | ||
412 | src = &opp->src[n_IRQ]; | |
9f1d4b1d | 413 | active = src->pending; |
611493d9 | 414 | |
72c1da2c | 415 | if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { |
060fbfe1 | 416 | /* Interrupt source is disabled */ |
e9df014c | 417 | DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); |
9f1d4b1d | 418 | active = false; |
dbda808a | 419 | } |
9f1d4b1d SW |
420 | |
421 | was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); | |
422 | ||
423 | /* | |
424 | * We don't have a similar check for already-active because | |
425 | * ctpr may have changed and we need to withdraw the interrupt. | |
426 | */ | |
427 | if (!active && !was_active) { | |
428 | DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ); | |
060fbfe1 | 429 | return; |
dbda808a | 430 | } |
9f1d4b1d SW |
431 | |
432 | if (active) { | |
433 | src->ivpr |= IVPR_ACTIVITY_MASK; | |
434 | } else { | |
435 | src->ivpr &= ~IVPR_ACTIVITY_MASK; | |
611493d9 | 436 | } |
9f1d4b1d | 437 | |
be7c236f | 438 | if (src->idr == 0) { |
060fbfe1 | 439 | /* No target */ |
e9df014c | 440 | DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); |
060fbfe1 | 441 | return; |
dbda808a | 442 | } |
611493d9 | 443 | |
be7c236f | 444 | if (src->idr == (1 << src->last_cpu)) { |
e9df014c | 445 | /* Only one CPU is allowed to receive this IRQ */ |
9f1d4b1d | 446 | IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); |
be7c236f | 447 | } else if (!(src->ivpr & IVPR_MODE_MASK)) { |
611493d9 FB |
448 | /* Directed delivery mode */ |
449 | for (i = 0; i < opp->nb_cpus; i++) { | |
5e22c276 | 450 | if (src->destmask & (1 << i)) { |
9f1d4b1d | 451 | IRQ_local_pipe(opp, i, n_IRQ, active, was_active); |
1945dbc1 | 452 | } |
611493d9 | 453 | } |
dbda808a | 454 | } else { |
611493d9 | 455 | /* Distributed delivery mode */ |
e9df014c | 456 | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
af7e9e74 | 457 | if (i == opp->nb_cpus) { |
611493d9 | 458 | i = 0; |
af7e9e74 | 459 | } |
5e22c276 | 460 | if (src->destmask & (1 << i)) { |
9f1d4b1d | 461 | IRQ_local_pipe(opp, i, n_IRQ, active, was_active); |
611493d9 FB |
462 | src->last_cpu = i; |
463 | break; | |
464 | } | |
465 | } | |
466 | } | |
467 | } | |
468 | ||
d537cf6c | 469 | static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
611493d9 | 470 | { |
6d544ee8 | 471 | OpenPICState *opp = opaque; |
af7e9e74 | 472 | IRQSource *src; |
611493d9 | 473 | |
65b9d0d5 SW |
474 | if (n_IRQ >= MAX_IRQ) { |
475 | fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ); | |
476 | abort(); | |
477 | } | |
611493d9 FB |
478 | |
479 | src = &opp->src[n_IRQ]; | |
be7c236f SW |
480 | DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n", |
481 | n_IRQ, level, src->ivpr); | |
6c5e84c2 | 482 | if (src->level) { |
611493d9 FB |
483 | /* level-sensitive irq */ |
484 | src->pending = level; | |
9f1d4b1d | 485 | openpic_update_irq(opp, n_IRQ); |
611493d9 FB |
486 | } else { |
487 | /* edge-sensitive irq */ | |
af7e9e74 | 488 | if (level) { |
611493d9 | 489 | src->pending = 1; |
9f1d4b1d SW |
490 | openpic_update_irq(opp, n_IRQ); |
491 | } | |
492 | ||
493 | if (src->output != OPENPIC_OUTPUT_INT) { | |
494 | /* Edge-triggered interrupts shouldn't be used | |
495 | * with non-INT delivery, but just in case, | |
496 | * try to make it do something sane rather than | |
497 | * cause an interrupt storm. This is close to | |
498 | * what you'd probably see happen in real hardware. | |
499 | */ | |
500 | src->pending = 0; | |
501 | openpic_update_irq(opp, n_IRQ); | |
af7e9e74 | 502 | } |
dbda808a FB |
503 | } |
504 | } | |
505 | ||
d0b72631 | 506 | static void openpic_reset(DeviceState *d) |
dbda808a | 507 | { |
d0b72631 | 508 | OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d)); |
dbda808a FB |
509 | int i; |
510 | ||
be7c236f | 511 | opp->gcr = GCR_RESET; |
f8407028 | 512 | /* Initialise controller registers */ |
be7c236f SW |
513 | opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) | |
514 | ((opp->nb_cpus - 1) << FRR_NCPU_SHIFT) | | |
515 | (opp->vid << FRR_VID_SHIFT); | |
825463b3 | 516 | |
be7c236f | 517 | opp->pir = 0; |
0fe04622 | 518 | opp->spve = -1 & opp->vector_mask; |
be7c236f | 519 | opp->tfrr = opp->tfrr_reset; |
dbda808a | 520 | /* Initialise IRQ sources */ |
b7169916 | 521 | for (i = 0; i < opp->max_irq; i++) { |
be7c236f SW |
522 | opp->src[i].ivpr = opp->ivpr_reset; |
523 | opp->src[i].idr = opp->idr_reset; | |
6c5e84c2 SW |
524 | |
525 | switch (opp->src[i].type) { | |
526 | case IRQ_TYPE_NORMAL: | |
527 | opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK); | |
528 | break; | |
529 | ||
530 | case IRQ_TYPE_FSLINT: | |
531 | opp->src[i].ivpr |= IVPR_POLARITY_MASK; | |
532 | break; | |
533 | ||
534 | case IRQ_TYPE_FSLSPECIAL: | |
535 | break; | |
536 | } | |
dbda808a FB |
537 | } |
538 | /* Initialise IRQ destinations */ | |
e9df014c | 539 | for (i = 0; i < MAX_CPU; i++) { |
be7c236f | 540 | opp->dst[i].ctpr = 15; |
af7e9e74 | 541 | memset(&opp->dst[i].raised, 0, sizeof(IRQQueue)); |
d14ed254 | 542 | opp->dst[i].raised.next = -1; |
af7e9e74 | 543 | memset(&opp->dst[i].servicing, 0, sizeof(IRQQueue)); |
d14ed254 | 544 | opp->dst[i].servicing.next = -1; |
dbda808a FB |
545 | } |
546 | /* Initialise timers */ | |
547 | for (i = 0; i < MAX_TMR; i++) { | |
be7c236f SW |
548 | opp->timers[i].tccr = 0; |
549 | opp->timers[i].tbcr = TBCR_CI; | |
dbda808a | 550 | } |
dbda808a | 551 | /* Go out of RESET state */ |
be7c236f | 552 | opp->gcr = 0; |
dbda808a FB |
553 | } |
554 | ||
be7c236f | 555 | static inline uint32_t read_IRQreg_idr(OpenPICState *opp, int n_IRQ) |
dbda808a | 556 | { |
be7c236f | 557 | return opp->src[n_IRQ].idr; |
8d3a8c1e | 558 | } |
dbda808a | 559 | |
be7c236f | 560 | static inline uint32_t read_IRQreg_ivpr(OpenPICState *opp, int n_IRQ) |
8d3a8c1e | 561 | { |
be7c236f | 562 | return opp->src[n_IRQ].ivpr; |
dbda808a FB |
563 | } |
564 | ||
be7c236f | 565 | static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val) |
dbda808a | 566 | { |
5e22c276 SW |
567 | IRQSource *src = &opp->src[n_IRQ]; |
568 | uint32_t normal_mask = (1UL << opp->nb_cpus) - 1; | |
569 | uint32_t crit_mask = 0; | |
570 | uint32_t mask = normal_mask; | |
571 | int crit_shift = IDR_EP_SHIFT - opp->nb_cpus; | |
572 | int i; | |
573 | ||
574 | if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { | |
575 | crit_mask = mask << crit_shift; | |
576 | mask |= crit_mask | IDR_EP; | |
577 | } | |
578 | ||
579 | src->idr = val & mask; | |
580 | DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); | |
581 | ||
582 | if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { | |
583 | if (src->idr & crit_mask) { | |
584 | if (src->idr & normal_mask) { | |
585 | DPRINTF("%s: IRQ configured for multiple output types, using " | |
586 | "critical\n", __func__); | |
587 | } | |
dbda808a | 588 | |
5e22c276 | 589 | src->output = OPENPIC_OUTPUT_CINT; |
72c1da2c | 590 | src->nomask = true; |
5e22c276 SW |
591 | src->destmask = 0; |
592 | ||
593 | for (i = 0; i < opp->nb_cpus; i++) { | |
594 | int n_ci = IDR_CI0_SHIFT - i; | |
dbda808a | 595 | |
5e22c276 SW |
596 | if (src->idr & (1UL << n_ci)) { |
597 | src->destmask |= 1UL << i; | |
598 | } | |
599 | } | |
600 | } else { | |
601 | src->output = OPENPIC_OUTPUT_INT; | |
72c1da2c | 602 | src->nomask = false; |
5e22c276 SW |
603 | src->destmask = src->idr & normal_mask; |
604 | } | |
605 | } else { | |
606 | src->destmask = src->idr; | |
607 | } | |
11de8b71 AG |
608 | } |
609 | ||
be7c236f | 610 | static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val) |
11de8b71 | 611 | { |
6c5e84c2 SW |
612 | uint32_t mask; |
613 | ||
614 | /* NOTE when implementing newer FSL MPIC models: starting with v4.0, | |
615 | * the polarity bit is read-only on internal interrupts. | |
616 | */ | |
617 | mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK | | |
618 | IVPR_POLARITY_MASK | opp->vector_mask; | |
619 | ||
11de8b71 | 620 | /* ACTIVITY bit is read-only */ |
6c5e84c2 SW |
621 | opp->src[n_IRQ].ivpr = |
622 | (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); | |
623 | ||
624 | /* For FSL internal interrupts, The sense bit is reserved and zero, | |
625 | * and the interrupt is always level-triggered. Timers and IPIs | |
626 | * have no sense or polarity bits, and are edge-triggered. | |
627 | */ | |
628 | switch (opp->src[n_IRQ].type) { | |
629 | case IRQ_TYPE_NORMAL: | |
630 | opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); | |
631 | break; | |
632 | ||
633 | case IRQ_TYPE_FSLINT: | |
634 | opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK; | |
635 | break; | |
636 | ||
637 | case IRQ_TYPE_FSLSPECIAL: | |
638 | opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK); | |
639 | break; | |
640 | } | |
641 | ||
11de8b71 | 642 | openpic_update_irq(opp, n_IRQ); |
be7c236f SW |
643 | DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, |
644 | opp->src[n_IRQ].ivpr); | |
dbda808a FB |
645 | } |
646 | ||
b9b2aaa3 AG |
647 | static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, |
648 | unsigned len) | |
dbda808a | 649 | { |
6d544ee8 | 650 | OpenPICState *opp = opaque; |
af7e9e74 | 651 | IRQDest *dst; |
e9df014c | 652 | int idx; |
dbda808a | 653 | |
4c4f0e48 SW |
654 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
655 | __func__, addr, val); | |
af7e9e74 | 656 | if (addr & 0xF) { |
dbda808a | 657 | return; |
af7e9e74 | 658 | } |
dbda808a | 659 | switch (addr) { |
3e772232 BB |
660 | case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ |
661 | break; | |
704c7e5d AG |
662 | case 0x40: |
663 | case 0x50: | |
664 | case 0x60: | |
665 | case 0x70: | |
666 | case 0x80: | |
667 | case 0x90: | |
668 | case 0xA0: | |
669 | case 0xB0: | |
670 | openpic_cpu_write_internal(opp, addr, val, get_current_cpu()); | |
dbda808a | 671 | break; |
be7c236f | 672 | case 0x1000: /* FRR */ |
dbda808a | 673 | break; |
be7c236f SW |
674 | case 0x1020: /* GCR */ |
675 | if (val & GCR_RESET) { | |
d0b72631 | 676 | openpic_reset(&opp->busdev.qdev); |
68c2dd70 AG |
677 | } else if (opp->mpic_mode_mask) { |
678 | CPUArchState *env; | |
679 | int mpic_proxy = 0; | |
680 | ||
681 | opp->gcr &= ~opp->mpic_mode_mask; | |
682 | opp->gcr |= val & opp->mpic_mode_mask; | |
683 | ||
684 | /* Set external proxy mode */ | |
685 | if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { | |
686 | mpic_proxy = 1; | |
687 | } | |
688 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
689 | env->mpic_proxy = mpic_proxy; | |
690 | } | |
825463b3 | 691 | } |
060fbfe1 | 692 | break; |
be7c236f | 693 | case 0x1080: /* VIR */ |
060fbfe1 | 694 | break; |
be7c236f | 695 | case 0x1090: /* PIR */ |
e9df014c | 696 | for (idx = 0; idx < opp->nb_cpus; idx++) { |
be7c236f | 697 | if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { |
e9df014c JM |
698 | DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx); |
699 | dst = &opp->dst[idx]; | |
700 | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); | |
be7c236f | 701 | } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) { |
e9df014c JM |
702 | DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx); |
703 | dst = &opp->dst[idx]; | |
704 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); | |
705 | } | |
dbda808a | 706 | } |
be7c236f | 707 | opp->pir = val; |
060fbfe1 | 708 | break; |
be7c236f | 709 | case 0x10A0: /* IPI_IVPR */ |
704c7e5d AG |
710 | case 0x10B0: |
711 | case 0x10C0: | |
712 | case 0x10D0: | |
dbda808a FB |
713 | { |
714 | int idx; | |
704c7e5d | 715 | idx = (addr - 0x10A0) >> 4; |
be7c236f | 716 | write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); |
dbda808a FB |
717 | } |
718 | break; | |
704c7e5d | 719 | case 0x10E0: /* SPVE */ |
0fe04622 | 720 | opp->spve = val & opp->vector_mask; |
dbda808a | 721 | break; |
dbda808a FB |
722 | default: |
723 | break; | |
724 | } | |
725 | } | |
726 | ||
b9b2aaa3 | 727 | static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 728 | { |
6d544ee8 | 729 | OpenPICState *opp = opaque; |
dbda808a FB |
730 | uint32_t retval; |
731 | ||
4c4f0e48 | 732 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
dbda808a | 733 | retval = 0xFFFFFFFF; |
af7e9e74 | 734 | if (addr & 0xF) { |
dbda808a | 735 | return retval; |
af7e9e74 | 736 | } |
dbda808a | 737 | switch (addr) { |
be7c236f SW |
738 | case 0x1000: /* FRR */ |
739 | retval = opp->frr; | |
dbda808a | 740 | break; |
be7c236f SW |
741 | case 0x1020: /* GCR */ |
742 | retval = opp->gcr; | |
060fbfe1 | 743 | break; |
be7c236f SW |
744 | case 0x1080: /* VIR */ |
745 | retval = opp->vir; | |
060fbfe1 | 746 | break; |
be7c236f | 747 | case 0x1090: /* PIR */ |
dbda808a | 748 | retval = 0x00000000; |
060fbfe1 | 749 | break; |
3e772232 | 750 | case 0x00: /* Block Revision Register1 (BRR1) */ |
0d404683 SW |
751 | retval = opp->brr1; |
752 | break; | |
704c7e5d AG |
753 | case 0x40: |
754 | case 0x50: | |
755 | case 0x60: | |
756 | case 0x70: | |
757 | case 0x80: | |
758 | case 0x90: | |
759 | case 0xA0: | |
dbda808a | 760 | case 0xB0: |
704c7e5d AG |
761 | retval = openpic_cpu_read_internal(opp, addr, get_current_cpu()); |
762 | break; | |
be7c236f | 763 | case 0x10A0: /* IPI_IVPR */ |
704c7e5d AG |
764 | case 0x10B0: |
765 | case 0x10C0: | |
766 | case 0x10D0: | |
dbda808a FB |
767 | { |
768 | int idx; | |
704c7e5d | 769 | idx = (addr - 0x10A0) >> 4; |
be7c236f | 770 | retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx); |
dbda808a | 771 | } |
060fbfe1 | 772 | break; |
704c7e5d | 773 | case 0x10E0: /* SPVE */ |
dbda808a FB |
774 | retval = opp->spve; |
775 | break; | |
dbda808a FB |
776 | default: |
777 | break; | |
778 | } | |
4c4f0e48 | 779 | DPRINTF("%s: => 0x%08x\n", __func__, retval); |
dbda808a FB |
780 | |
781 | return retval; | |
782 | } | |
783 | ||
6d544ee8 | 784 | static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, |
b9b2aaa3 | 785 | unsigned len) |
dbda808a | 786 | { |
6d544ee8 | 787 | OpenPICState *opp = opaque; |
dbda808a FB |
788 | int idx; |
789 | ||
4c4f0e48 SW |
790 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
791 | __func__, addr, val); | |
af7e9e74 | 792 | if (addr & 0xF) { |
dbda808a | 793 | return; |
af7e9e74 | 794 | } |
c38c0b8a | 795 | idx = (addr >> 6) & 0x3; |
dbda808a | 796 | addr = addr & 0x30; |
c38c0b8a AG |
797 | |
798 | if (addr == 0x0) { | |
be7c236f SW |
799 | /* TFRR */ |
800 | opp->tfrr = val; | |
c38c0b8a AG |
801 | return; |
802 | } | |
803 | switch (addr & 0x30) { | |
be7c236f | 804 | case 0x00: /* TCCR */ |
dbda808a | 805 | break; |
be7c236f SW |
806 | case 0x10: /* TBCR */ |
807 | if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && | |
808 | (val & TBCR_CI) == 0 && | |
809 | (opp->timers[idx].tbcr & TBCR_CI) != 0) { | |
810 | opp->timers[idx].tccr &= ~TCCR_TOG; | |
71c6cacb | 811 | } |
be7c236f | 812 | opp->timers[idx].tbcr = val; |
060fbfe1 | 813 | break; |
be7c236f SW |
814 | case 0x20: /* TVPR */ |
815 | write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val); | |
060fbfe1 | 816 | break; |
be7c236f SW |
817 | case 0x30: /* TDR */ |
818 | write_IRQreg_idr(opp, opp->irq_tim0 + idx, val); | |
060fbfe1 | 819 | break; |
dbda808a FB |
820 | } |
821 | } | |
822 | ||
6d544ee8 | 823 | static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 824 | { |
6d544ee8 | 825 | OpenPICState *opp = opaque; |
c38c0b8a | 826 | uint32_t retval = -1; |
dbda808a FB |
827 | int idx; |
828 | ||
4c4f0e48 | 829 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
c38c0b8a AG |
830 | if (addr & 0xF) { |
831 | goto out; | |
832 | } | |
833 | idx = (addr >> 6) & 0x3; | |
834 | if (addr == 0x0) { | |
be7c236f SW |
835 | /* TFRR */ |
836 | retval = opp->tfrr; | |
c38c0b8a AG |
837 | goto out; |
838 | } | |
839 | switch (addr & 0x30) { | |
be7c236f SW |
840 | case 0x00: /* TCCR */ |
841 | retval = opp->timers[idx].tccr; | |
dbda808a | 842 | break; |
be7c236f SW |
843 | case 0x10: /* TBCR */ |
844 | retval = opp->timers[idx].tbcr; | |
060fbfe1 | 845 | break; |
be7c236f SW |
846 | case 0x20: /* TIPV */ |
847 | retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); | |
060fbfe1 | 848 | break; |
c38c0b8a | 849 | case 0x30: /* TIDE (TIDR) */ |
be7c236f | 850 | retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx); |
060fbfe1 | 851 | break; |
dbda808a | 852 | } |
c38c0b8a AG |
853 | |
854 | out: | |
4c4f0e48 | 855 | DPRINTF("%s: => 0x%08x\n", __func__, retval); |
dbda808a FB |
856 | |
857 | return retval; | |
858 | } | |
859 | ||
b9b2aaa3 AG |
860 | static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, |
861 | unsigned len) | |
dbda808a | 862 | { |
6d544ee8 | 863 | OpenPICState *opp = opaque; |
dbda808a FB |
864 | int idx; |
865 | ||
4c4f0e48 SW |
866 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
867 | __func__, addr, val); | |
af7e9e74 | 868 | if (addr & 0xF) { |
dbda808a | 869 | return; |
af7e9e74 | 870 | } |
dbda808a FB |
871 | addr = addr & 0xFFF0; |
872 | idx = addr >> 5; | |
873 | if (addr & 0x10) { | |
874 | /* EXDE / IFEDE / IEEDE */ | |
be7c236f | 875 | write_IRQreg_idr(opp, idx, val); |
dbda808a FB |
876 | } else { |
877 | /* EXVP / IFEVP / IEEVP */ | |
be7c236f | 878 | write_IRQreg_ivpr(opp, idx, val); |
dbda808a FB |
879 | } |
880 | } | |
881 | ||
b9b2aaa3 | 882 | static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) |
dbda808a | 883 | { |
6d544ee8 | 884 | OpenPICState *opp = opaque; |
dbda808a FB |
885 | uint32_t retval; |
886 | int idx; | |
887 | ||
4c4f0e48 | 888 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
dbda808a | 889 | retval = 0xFFFFFFFF; |
af7e9e74 | 890 | if (addr & 0xF) { |
dbda808a | 891 | return retval; |
af7e9e74 | 892 | } |
dbda808a FB |
893 | addr = addr & 0xFFF0; |
894 | idx = addr >> 5; | |
895 | if (addr & 0x10) { | |
896 | /* EXDE / IFEDE / IEEDE */ | |
be7c236f | 897 | retval = read_IRQreg_idr(opp, idx); |
dbda808a FB |
898 | } else { |
899 | /* EXVP / IFEVP / IEEVP */ | |
be7c236f | 900 | retval = read_IRQreg_ivpr(opp, idx); |
dbda808a | 901 | } |
4c4f0e48 | 902 | DPRINTF("%s: => 0x%08x\n", __func__, retval); |
dbda808a FB |
903 | |
904 | return retval; | |
905 | } | |
906 | ||
732aa6ec AG |
907 | static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val, |
908 | unsigned size) | |
909 | { | |
910 | OpenPICState *opp = opaque; | |
911 | int idx = opp->irq_msi; | |
912 | int srs, ibs; | |
913 | ||
4c4f0e48 SW |
914 | DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", |
915 | __func__, addr, val); | |
732aa6ec AG |
916 | if (addr & 0xF) { |
917 | return; | |
918 | } | |
919 | ||
920 | switch (addr) { | |
921 | case MSIIR_OFFSET: | |
922 | srs = val >> MSIIR_SRS_SHIFT; | |
923 | idx += srs; | |
924 | ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT; | |
925 | opp->msi[srs].msir |= 1 << ibs; | |
926 | openpic_set_irq(opp, idx, 1); | |
927 | break; | |
928 | default: | |
929 | /* most registers are read-only, thus ignored */ | |
930 | break; | |
931 | } | |
932 | } | |
933 | ||
934 | static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) | |
935 | { | |
936 | OpenPICState *opp = opaque; | |
937 | uint64_t r = 0; | |
938 | int i, srs; | |
939 | ||
4c4f0e48 | 940 | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
732aa6ec AG |
941 | if (addr & 0xF) { |
942 | return -1; | |
943 | } | |
944 | ||
945 | srs = addr >> 4; | |
946 | ||
947 | switch (addr) { | |
948 | case 0x00: | |
949 | case 0x10: | |
950 | case 0x20: | |
951 | case 0x30: | |
952 | case 0x40: | |
953 | case 0x50: | |
954 | case 0x60: | |
955 | case 0x70: /* MSIRs */ | |
956 | r = opp->msi[srs].msir; | |
957 | /* Clear on read */ | |
958 | opp->msi[srs].msir = 0; | |
e99fd8af | 959 | openpic_set_irq(opp, opp->irq_msi + srs, 0); |
732aa6ec AG |
960 | break; |
961 | case 0x120: /* MSISR */ | |
962 | for (i = 0; i < MAX_MSI; i++) { | |
963 | r |= (opp->msi[i].msir ? 1 : 0) << i; | |
964 | } | |
965 | break; | |
966 | } | |
967 | ||
968 | return r; | |
969 | } | |
970 | ||
a8170e5e | 971 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
704c7e5d | 972 | uint32_t val, int idx) |
dbda808a | 973 | { |
6d544ee8 | 974 | OpenPICState *opp = opaque; |
af7e9e74 AG |
975 | IRQSource *src; |
976 | IRQDest *dst; | |
704c7e5d | 977 | int s_IRQ, n_IRQ; |
dbda808a | 978 | |
4c4f0e48 | 979 | DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx, |
704c7e5d | 980 | addr, val); |
c3203fa5 SW |
981 | |
982 | if (idx < 0) { | |
dbda808a | 983 | return; |
c3203fa5 SW |
984 | } |
985 | ||
af7e9e74 | 986 | if (addr & 0xF) { |
dbda808a | 987 | return; |
af7e9e74 | 988 | } |
dbda808a FB |
989 | dst = &opp->dst[idx]; |
990 | addr &= 0xFF0; | |
991 | switch (addr) { | |
704c7e5d | 992 | case 0x40: /* IPIDR */ |
dbda808a FB |
993 | case 0x50: |
994 | case 0x60: | |
995 | case 0x70: | |
996 | idx = (addr - 0x40) >> 4; | |
a675155e | 997 | /* we use IDE as mask which CPUs to deliver the IPI to still. */ |
be7c236f SW |
998 | write_IRQreg_idr(opp, opp->irq_ipi0 + idx, |
999 | opp->src[opp->irq_ipi0 + idx].idr | val); | |
b7169916 AJ |
1000 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 1); |
1001 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); | |
dbda808a | 1002 | break; |
be7c236f SW |
1003 | case 0x80: /* CTPR */ |
1004 | dst->ctpr = val & 0x0000000F; | |
9f1d4b1d SW |
1005 | |
1006 | DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n", | |
1007 | __func__, idx, dst->ctpr, dst->raised.priority, | |
1008 | dst->servicing.priority); | |
1009 | ||
1010 | if (dst->raised.priority <= dst->ctpr) { | |
1011 | DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n", | |
1012 | __func__, idx); | |
1013 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); | |
1014 | } else if (dst->raised.priority > dst->servicing.priority) { | |
1015 | DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n", | |
1016 | __func__, idx, dst->raised.next); | |
1017 | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); | |
1018 | } | |
1019 | ||
060fbfe1 | 1020 | break; |
dbda808a | 1021 | case 0x90: /* WHOAMI */ |
060fbfe1 AJ |
1022 | /* Read-only register */ |
1023 | break; | |
be7c236f | 1024 | case 0xA0: /* IACK */ |
060fbfe1 AJ |
1025 | /* Read-only register */ |
1026 | break; | |
be7c236f SW |
1027 | case 0xB0: /* EOI */ |
1028 | DPRINTF("EOI\n"); | |
060fbfe1 | 1029 | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
65b9d0d5 SW |
1030 | |
1031 | if (s_IRQ < 0) { | |
1032 | DPRINTF("%s: EOI with no interrupt in service\n", __func__); | |
1033 | break; | |
1034 | } | |
1035 | ||
060fbfe1 | 1036 | IRQ_resetbit(&dst->servicing, s_IRQ); |
060fbfe1 AJ |
1037 | /* Set up next servicing IRQ */ |
1038 | s_IRQ = IRQ_get_next(opp, &dst->servicing); | |
e9df014c JM |
1039 | /* Check queued interrupts. */ |
1040 | n_IRQ = IRQ_get_next(opp, &dst->raised); | |
1041 | src = &opp->src[n_IRQ]; | |
1042 | if (n_IRQ != -1 && | |
1043 | (s_IRQ == -1 || | |
be7c236f | 1044 | IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { |
e9df014c JM |
1045 | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", |
1046 | idx, n_IRQ); | |
5e22c276 | 1047 | qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]); |
e9df014c | 1048 | } |
060fbfe1 | 1049 | break; |
dbda808a FB |
1050 | default: |
1051 | break; | |
1052 | } | |
1053 | } | |
1054 | ||
b9b2aaa3 AG |
1055 | static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val, |
1056 | unsigned len) | |
704c7e5d AG |
1057 | { |
1058 | openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); | |
1059 | } | |
1060 | ||
a898a8fc SW |
1061 | |
1062 | static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu) | |
1063 | { | |
1064 | IRQSource *src; | |
1065 | int retval, irq; | |
1066 | ||
1067 | DPRINTF("Lower OpenPIC INT output\n"); | |
1068 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); | |
1069 | ||
1070 | irq = IRQ_get_next(opp, &dst->raised); | |
1071 | DPRINTF("IACK: irq=%d\n", irq); | |
1072 | ||
1073 | if (irq == -1) { | |
1074 | /* No more interrupt pending */ | |
1075 | return opp->spve; | |
1076 | } | |
1077 | ||
1078 | src = &opp->src[irq]; | |
1079 | if (!(src->ivpr & IVPR_ACTIVITY_MASK) || | |
1080 | !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { | |
9f1d4b1d SW |
1081 | fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", |
1082 | __func__, irq, dst->ctpr, src->ivpr); | |
1083 | openpic_update_irq(opp, irq); | |
a898a8fc SW |
1084 | retval = opp->spve; |
1085 | } else { | |
1086 | /* IRQ enter servicing state */ | |
1087 | IRQ_setbit(&dst->servicing, irq); | |
1088 | retval = IVPR_VECTOR(opp, src->ivpr); | |
1089 | } | |
9f1d4b1d | 1090 | |
a898a8fc SW |
1091 | if (!src->level) { |
1092 | /* edge-sensitive IRQ */ | |
1093 | src->ivpr &= ~IVPR_ACTIVITY_MASK; | |
1094 | src->pending = 0; | |
9f1d4b1d | 1095 | IRQ_resetbit(&dst->raised, irq); |
a898a8fc SW |
1096 | } |
1097 | ||
1098 | if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + MAX_IPI))) { | |
1099 | src->idr &= ~(1 << cpu); | |
1100 | if (src->idr && !src->level) { | |
1101 | /* trigger on CPUs that didn't know about it yet */ | |
1102 | openpic_set_irq(opp, irq, 1); | |
1103 | openpic_set_irq(opp, irq, 0); | |
1104 | /* if all CPUs knew about it, set active bit again */ | |
1105 | src->ivpr |= IVPR_ACTIVITY_MASK; | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | return retval; | |
1110 | } | |
1111 | ||
a8170e5e | 1112 | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
704c7e5d | 1113 | int idx) |
dbda808a | 1114 | { |
6d544ee8 | 1115 | OpenPICState *opp = opaque; |
af7e9e74 | 1116 | IRQDest *dst; |
dbda808a | 1117 | uint32_t retval; |
3b46e624 | 1118 | |
4c4f0e48 | 1119 | DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr); |
dbda808a | 1120 | retval = 0xFFFFFFFF; |
c3203fa5 SW |
1121 | |
1122 | if (idx < 0) { | |
1123 | return retval; | |
1124 | } | |
1125 | ||
af7e9e74 | 1126 | if (addr & 0xF) { |
dbda808a | 1127 | return retval; |
af7e9e74 | 1128 | } |
dbda808a FB |
1129 | dst = &opp->dst[idx]; |
1130 | addr &= 0xFF0; | |
1131 | switch (addr) { | |
be7c236f SW |
1132 | case 0x80: /* CTPR */ |
1133 | retval = dst->ctpr; | |
060fbfe1 | 1134 | break; |
dbda808a | 1135 | case 0x90: /* WHOAMI */ |
060fbfe1 AJ |
1136 | retval = idx; |
1137 | break; | |
be7c236f | 1138 | case 0xA0: /* IACK */ |
a898a8fc | 1139 | retval = openpic_iack(opp, dst, idx); |
060fbfe1 | 1140 | break; |
be7c236f | 1141 | case 0xB0: /* EOI */ |
060fbfe1 AJ |
1142 | retval = 0; |
1143 | break; | |
dbda808a FB |
1144 | default: |
1145 | break; | |
1146 | } | |
4c4f0e48 | 1147 | DPRINTF("%s: => 0x%08x\n", __func__, retval); |
dbda808a FB |
1148 | |
1149 | return retval; | |
1150 | } | |
1151 | ||
b9b2aaa3 | 1152 | static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) |
704c7e5d AG |
1153 | { |
1154 | return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); | |
1155 | } | |
1156 | ||
35732cb4 | 1157 | static const MemoryRegionOps openpic_glb_ops_le = { |
780d16b7 AG |
1158 | .write = openpic_gbl_write, |
1159 | .read = openpic_gbl_read, | |
1160 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1161 | .impl = { | |
1162 | .min_access_size = 4, | |
1163 | .max_access_size = 4, | |
1164 | }, | |
1165 | }; | |
dbda808a | 1166 | |
35732cb4 AG |
1167 | static const MemoryRegionOps openpic_glb_ops_be = { |
1168 | .write = openpic_gbl_write, | |
1169 | .read = openpic_gbl_read, | |
1170 | .endianness = DEVICE_BIG_ENDIAN, | |
1171 | .impl = { | |
1172 | .min_access_size = 4, | |
1173 | .max_access_size = 4, | |
1174 | }, | |
1175 | }; | |
1176 | ||
1177 | static const MemoryRegionOps openpic_tmr_ops_le = { | |
6d544ee8 AG |
1178 | .write = openpic_tmr_write, |
1179 | .read = openpic_tmr_read, | |
780d16b7 AG |
1180 | .endianness = DEVICE_LITTLE_ENDIAN, |
1181 | .impl = { | |
1182 | .min_access_size = 4, | |
1183 | .max_access_size = 4, | |
1184 | }, | |
1185 | }; | |
dbda808a | 1186 | |
35732cb4 | 1187 | static const MemoryRegionOps openpic_tmr_ops_be = { |
6d544ee8 AG |
1188 | .write = openpic_tmr_write, |
1189 | .read = openpic_tmr_read, | |
35732cb4 AG |
1190 | .endianness = DEVICE_BIG_ENDIAN, |
1191 | .impl = { | |
1192 | .min_access_size = 4, | |
1193 | .max_access_size = 4, | |
1194 | }, | |
1195 | }; | |
1196 | ||
1197 | static const MemoryRegionOps openpic_cpu_ops_le = { | |
780d16b7 AG |
1198 | .write = openpic_cpu_write, |
1199 | .read = openpic_cpu_read, | |
1200 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1201 | .impl = { | |
1202 | .min_access_size = 4, | |
1203 | .max_access_size = 4, | |
1204 | }, | |
1205 | }; | |
dbda808a | 1206 | |
35732cb4 AG |
1207 | static const MemoryRegionOps openpic_cpu_ops_be = { |
1208 | .write = openpic_cpu_write, | |
1209 | .read = openpic_cpu_read, | |
1210 | .endianness = DEVICE_BIG_ENDIAN, | |
1211 | .impl = { | |
1212 | .min_access_size = 4, | |
1213 | .max_access_size = 4, | |
1214 | }, | |
1215 | }; | |
1216 | ||
1217 | static const MemoryRegionOps openpic_src_ops_le = { | |
780d16b7 AG |
1218 | .write = openpic_src_write, |
1219 | .read = openpic_src_read, | |
23c5e4ca | 1220 | .endianness = DEVICE_LITTLE_ENDIAN, |
b9b2aaa3 AG |
1221 | .impl = { |
1222 | .min_access_size = 4, | |
1223 | .max_access_size = 4, | |
1224 | }, | |
23c5e4ca AK |
1225 | }; |
1226 | ||
35732cb4 AG |
1227 | static const MemoryRegionOps openpic_src_ops_be = { |
1228 | .write = openpic_src_write, | |
1229 | .read = openpic_src_read, | |
1230 | .endianness = DEVICE_BIG_ENDIAN, | |
1231 | .impl = { | |
1232 | .min_access_size = 4, | |
1233 | .max_access_size = 4, | |
1234 | }, | |
1235 | }; | |
1236 | ||
732aa6ec AG |
1237 | static const MemoryRegionOps openpic_msi_ops_le = { |
1238 | .read = openpic_msi_read, | |
1239 | .write = openpic_msi_write, | |
1240 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1241 | .impl = { | |
1242 | .min_access_size = 4, | |
1243 | .max_access_size = 4, | |
1244 | }, | |
1245 | }; | |
1246 | ||
1247 | static const MemoryRegionOps openpic_msi_ops_be = { | |
1248 | .read = openpic_msi_read, | |
1249 | .write = openpic_msi_write, | |
1250 | .endianness = DEVICE_BIG_ENDIAN, | |
1251 | .impl = { | |
1252 | .min_access_size = 4, | |
1253 | .max_access_size = 4, | |
1254 | }, | |
1255 | }; | |
1256 | ||
af7e9e74 | 1257 | static void openpic_save_IRQ_queue(QEMUFile* f, IRQQueue *q) |
67b55785 BS |
1258 | { |
1259 | unsigned int i; | |
1260 | ||
e69a17f6 SW |
1261 | for (i = 0; i < ARRAY_SIZE(q->queue); i++) { |
1262 | /* Always put the lower half of a 64-bit long first, in case we | |
1263 | * restore on a 32-bit host. The least significant bits correspond | |
1264 | * to lower IRQ numbers in the bitmap. | |
1265 | */ | |
1266 | qemu_put_be32(f, (uint32_t)q->queue[i]); | |
1267 | #if LONG_MAX > 0x7FFFFFFF | |
1268 | qemu_put_be32(f, (uint32_t)(q->queue[i] >> 32)); | |
1269 | #endif | |
1270 | } | |
67b55785 BS |
1271 | |
1272 | qemu_put_sbe32s(f, &q->next); | |
1273 | qemu_put_sbe32s(f, &q->priority); | |
1274 | } | |
1275 | ||
1276 | static void openpic_save(QEMUFile* f, void *opaque) | |
1277 | { | |
6d544ee8 | 1278 | OpenPICState *opp = (OpenPICState *)opaque; |
67b55785 BS |
1279 | unsigned int i; |
1280 | ||
be7c236f SW |
1281 | qemu_put_be32s(f, &opp->gcr); |
1282 | qemu_put_be32s(f, &opp->vir); | |
1283 | qemu_put_be32s(f, &opp->pir); | |
67b55785 | 1284 | qemu_put_be32s(f, &opp->spve); |
be7c236f | 1285 | qemu_put_be32s(f, &opp->tfrr); |
67b55785 | 1286 | |
d0b72631 | 1287 | qemu_put_be32s(f, &opp->nb_cpus); |
b7169916 AJ |
1288 | |
1289 | for (i = 0; i < opp->nb_cpus; i++) { | |
eb438427 | 1290 | qemu_put_sbe32s(f, &opp->dst[i].ctpr); |
67b55785 BS |
1291 | openpic_save_IRQ_queue(f, &opp->dst[i].raised); |
1292 | openpic_save_IRQ_queue(f, &opp->dst[i].servicing); | |
9f1d4b1d SW |
1293 | qemu_put_buffer(f, (uint8_t *)&opp->dst[i].outputs_active, |
1294 | sizeof(opp->dst[i].outputs_active)); | |
67b55785 BS |
1295 | } |
1296 | ||
67b55785 | 1297 | for (i = 0; i < MAX_TMR; i++) { |
be7c236f SW |
1298 | qemu_put_be32s(f, &opp->timers[i].tccr); |
1299 | qemu_put_be32s(f, &opp->timers[i].tbcr); | |
67b55785 | 1300 | } |
5e22c276 SW |
1301 | |
1302 | for (i = 0; i < opp->max_irq; i++) { | |
1303 | qemu_put_be32s(f, &opp->src[i].ivpr); | |
1304 | qemu_put_be32s(f, &opp->src[i].idr); | |
1305 | qemu_put_sbe32s(f, &opp->src[i].last_cpu); | |
1306 | qemu_put_sbe32s(f, &opp->src[i].pending); | |
67b55785 | 1307 | } |
67b55785 BS |
1308 | } |
1309 | ||
af7e9e74 | 1310 | static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q) |
67b55785 BS |
1311 | { |
1312 | unsigned int i; | |
1313 | ||
e69a17f6 SW |
1314 | for (i = 0; i < ARRAY_SIZE(q->queue); i++) { |
1315 | unsigned long val; | |
1316 | ||
1317 | val = qemu_get_be32(f); | |
1318 | #if LONG_MAX > 0x7FFFFFFF | |
1319 | val <<= 32; | |
1320 | val |= qemu_get_be32(f); | |
1321 | #endif | |
1322 | ||
1323 | q->queue[i] = val; | |
1324 | } | |
67b55785 BS |
1325 | |
1326 | qemu_get_sbe32s(f, &q->next); | |
1327 | qemu_get_sbe32s(f, &q->priority); | |
1328 | } | |
1329 | ||
1330 | static int openpic_load(QEMUFile* f, void *opaque, int version_id) | |
1331 | { | |
6d544ee8 | 1332 | OpenPICState *opp = (OpenPICState *)opaque; |
67b55785 BS |
1333 | unsigned int i; |
1334 | ||
af7e9e74 | 1335 | if (version_id != 1) { |
67b55785 | 1336 | return -EINVAL; |
af7e9e74 | 1337 | } |
67b55785 | 1338 | |
be7c236f SW |
1339 | qemu_get_be32s(f, &opp->gcr); |
1340 | qemu_get_be32s(f, &opp->vir); | |
1341 | qemu_get_be32s(f, &opp->pir); | |
67b55785 | 1342 | qemu_get_be32s(f, &opp->spve); |
be7c236f | 1343 | qemu_get_be32s(f, &opp->tfrr); |
67b55785 | 1344 | |
d0b72631 | 1345 | qemu_get_be32s(f, &opp->nb_cpus); |
b7169916 AJ |
1346 | |
1347 | for (i = 0; i < opp->nb_cpus; i++) { | |
eb438427 | 1348 | qemu_get_sbe32s(f, &opp->dst[i].ctpr); |
67b55785 BS |
1349 | openpic_load_IRQ_queue(f, &opp->dst[i].raised); |
1350 | openpic_load_IRQ_queue(f, &opp->dst[i].servicing); | |
9f1d4b1d SW |
1351 | qemu_get_buffer(f, (uint8_t *)&opp->dst[i].outputs_active, |
1352 | sizeof(opp->dst[i].outputs_active)); | |
67b55785 BS |
1353 | } |
1354 | ||
67b55785 | 1355 | for (i = 0; i < MAX_TMR; i++) { |
be7c236f SW |
1356 | qemu_get_be32s(f, &opp->timers[i].tccr); |
1357 | qemu_get_be32s(f, &opp->timers[i].tbcr); | |
67b55785 BS |
1358 | } |
1359 | ||
5e22c276 SW |
1360 | for (i = 0; i < opp->max_irq; i++) { |
1361 | uint32_t val; | |
67b55785 | 1362 | |
5e22c276 SW |
1363 | val = qemu_get_be32(f); |
1364 | write_IRQreg_idr(opp, i, val); | |
1365 | val = qemu_get_be32(f); | |
1366 | write_IRQreg_ivpr(opp, i, val); | |
5861a338 | 1367 | |
5e22c276 SW |
1368 | qemu_get_be32s(f, &opp->src[i].ivpr); |
1369 | qemu_get_be32s(f, &opp->src[i].idr); | |
1370 | qemu_get_sbe32s(f, &opp->src[i].last_cpu); | |
1371 | qemu_get_sbe32s(f, &opp->src[i].pending); | |
5861a338 | 1372 | } |
5e22c276 SW |
1373 | |
1374 | return 0; | |
b7169916 AJ |
1375 | } |
1376 | ||
af7e9e74 | 1377 | typedef struct MemReg { |
d0b72631 AG |
1378 | const char *name; |
1379 | MemoryRegionOps const *ops; | |
732aa6ec | 1380 | bool map; |
d0b72631 AG |
1381 | hwaddr start_addr; |
1382 | ram_addr_t size; | |
af7e9e74 | 1383 | } MemReg; |
d0b72631 AG |
1384 | |
1385 | static int openpic_init(SysBusDevice *dev) | |
dbda808a | 1386 | { |
d0b72631 AG |
1387 | OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev); |
1388 | int i, j; | |
af7e9e74 | 1389 | MemReg list_le[] = { |
732aa6ec AG |
1390 | {"glb", &openpic_glb_ops_le, true, |
1391 | OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, | |
1392 | {"tmr", &openpic_tmr_ops_le, true, | |
1393 | OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, | |
1394 | {"msi", &openpic_msi_ops_le, true, | |
1395 | OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE}, | |
1396 | {"src", &openpic_src_ops_le, true, | |
1397 | OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, | |
1398 | {"cpu", &openpic_cpu_ops_le, true, | |
1399 | OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, | |
780d16b7 | 1400 | }; |
af7e9e74 | 1401 | MemReg list_be[] = { |
732aa6ec AG |
1402 | {"glb", &openpic_glb_ops_be, true, |
1403 | OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, | |
1404 | {"tmr", &openpic_tmr_ops_be, true, | |
1405 | OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, | |
1406 | {"msi", &openpic_msi_ops_be, true, | |
1407 | OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE}, | |
1408 | {"src", &openpic_src_ops_be, true, | |
1409 | OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, | |
1410 | {"cpu", &openpic_cpu_ops_be, true, | |
1411 | OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, | |
d0b72631 | 1412 | }; |
af7e9e74 | 1413 | MemReg *list; |
3b46e624 | 1414 | |
d0b72631 AG |
1415 | switch (opp->model) { |
1416 | case OPENPIC_MODEL_FSL_MPIC_20: | |
1417 | default: | |
be7c236f | 1418 | opp->flags |= OPENPIC_FLAG_IDR_CRIT; |
d0b72631 AG |
1419 | opp->nb_irqs = 80; |
1420 | opp->vid = VID_REVISION_1_2; | |
be7c236f | 1421 | opp->vir = VIR_GENERIC; |
0fe04622 | 1422 | opp->vector_mask = 0xFFFF; |
be7c236f SW |
1423 | opp->tfrr_reset = 0; |
1424 | opp->ivpr_reset = IVPR_MASK_MASK; | |
1425 | opp->idr_reset = 1 << 0; | |
d0b72631 AG |
1426 | opp->max_irq = FSL_MPIC_20_MAX_IRQ; |
1427 | opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ; | |
1428 | opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ; | |
732aa6ec | 1429 | opp->irq_msi = FSL_MPIC_20_MSI_IRQ; |
dbbbfd60 | 1430 | opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN; |
68c2dd70 AG |
1431 | /* XXX really only available as of MPIC 4.0 */ |
1432 | opp->mpic_mode_mask = GCR_MODE_PROXY; | |
1433 | ||
732aa6ec | 1434 | msi_supported = true; |
d0b72631 | 1435 | list = list_be; |
6c5e84c2 SW |
1436 | |
1437 | for (i = 0; i < FSL_MPIC_20_MAX_EXT; i++) { | |
1438 | opp->src[i].level = false; | |
1439 | } | |
1440 | ||
1441 | /* Internal interrupts, including message and MSI */ | |
1442 | for (i = 16; i < MAX_SRC; i++) { | |
1443 | opp->src[i].type = IRQ_TYPE_FSLINT; | |
1444 | opp->src[i].level = true; | |
1445 | } | |
1446 | ||
1447 | /* timers and IPIs */ | |
1448 | for (i = MAX_SRC; i < MAX_IRQ; i++) { | |
1449 | opp->src[i].type = IRQ_TYPE_FSLSPECIAL; | |
1450 | opp->src[i].level = false; | |
1451 | } | |
1452 | ||
d0b72631 | 1453 | break; |
6c5e84c2 | 1454 | |
d0b72631 AG |
1455 | case OPENPIC_MODEL_RAVEN: |
1456 | opp->nb_irqs = RAVEN_MAX_EXT; | |
1457 | opp->vid = VID_REVISION_1_3; | |
be7c236f | 1458 | opp->vir = VIR_GENERIC; |
0fe04622 | 1459 | opp->vector_mask = 0xFF; |
be7c236f SW |
1460 | opp->tfrr_reset = 4160000; |
1461 | opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK; | |
1462 | opp->idr_reset = 0; | |
d0b72631 AG |
1463 | opp->max_irq = RAVEN_MAX_IRQ; |
1464 | opp->irq_ipi0 = RAVEN_IPI_IRQ; | |
1465 | opp->irq_tim0 = RAVEN_TMR_IRQ; | |
dbbbfd60 | 1466 | opp->brr1 = -1; |
d0b72631 | 1467 | list = list_le; |
732aa6ec AG |
1468 | /* Don't map MSI region */ |
1469 | list[2].map = false; | |
d0b72631 AG |
1470 | |
1471 | /* Only UP supported today */ | |
1472 | if (opp->nb_cpus != 1) { | |
1473 | return -EINVAL; | |
1474 | } | |
1475 | break; | |
1476 | } | |
780d16b7 AG |
1477 | |
1478 | memory_region_init(&opp->mem, "openpic", 0x40000); | |
1479 | ||
d0b72631 | 1480 | for (i = 0; i < ARRAY_SIZE(list_le); i++) { |
732aa6ec AG |
1481 | if (!list[i].map) { |
1482 | continue; | |
1483 | } | |
1484 | ||
780d16b7 AG |
1485 | memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp, |
1486 | list[i].name, list[i].size); | |
1487 | ||
1488 | memory_region_add_subregion(&opp->mem, list[i].start_addr, | |
1489 | &opp->sub_io_mem[i]); | |
1490 | } | |
3b46e624 | 1491 | |
d0b72631 AG |
1492 | for (i = 0; i < opp->nb_cpus; i++) { |
1493 | opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB); | |
1494 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { | |
1495 | sysbus_init_irq(dev, &opp->dst[i].irqs[j]); | |
1496 | } | |
1497 | } | |
1498 | ||
1499 | register_savevm(&opp->busdev.qdev, "openpic", 0, 2, | |
0be71e32 | 1500 | openpic_save, openpic_load, opp); |
b7169916 | 1501 | |
d0b72631 AG |
1502 | sysbus_init_mmio(dev, &opp->mem); |
1503 | qdev_init_gpio_in(&dev->qdev, openpic_set_irq, opp->max_irq); | |
e9df014c | 1504 | |
d0b72631 | 1505 | return 0; |
b7169916 AJ |
1506 | } |
1507 | ||
d0b72631 AG |
1508 | static Property openpic_properties[] = { |
1509 | DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20), | |
1510 | DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1), | |
1511 | DEFINE_PROP_END_OF_LIST(), | |
1512 | }; | |
71cf9e62 | 1513 | |
d0b72631 AG |
1514 | static void openpic_class_init(ObjectClass *klass, void *data) |
1515 | { | |
1516 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1517 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
b7169916 | 1518 | |
d0b72631 AG |
1519 | k->init = openpic_init; |
1520 | dc->props = openpic_properties; | |
1521 | dc->reset = openpic_reset; | |
1522 | } | |
71cf9e62 | 1523 | |
8c43a6f0 | 1524 | static const TypeInfo openpic_info = { |
d0b72631 AG |
1525 | .name = "openpic", |
1526 | .parent = TYPE_SYS_BUS_DEVICE, | |
1527 | .instance_size = sizeof(OpenPICState), | |
1528 | .class_init = openpic_class_init, | |
1529 | }; | |
b7169916 | 1530 | |
d0b72631 AG |
1531 | static void openpic_register_types(void) |
1532 | { | |
1533 | type_register_static(&openpic_info); | |
dbda808a | 1534 | } |
d0b72631 AG |
1535 | |
1536 | type_init(openpic_register_types) |