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99f575ed JL |
1 | /* |
2 | * QEMU OpenRISC timer support | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * Zhizhou Zhang <etouzh@gmail.com> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
198a2d21 | 10 | * version 2.1 of the License, or (at your option) any later version. |
99f575ed JL |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
99f575ed | 22 | #include "cpu.h" |
d6454270 | 23 | #include "migration/vmstate.h" |
1de7afc9 | 24 | #include "qemu/timer.h" |
557e3707 | 25 | #include "sysemu/reset.h" |
99f575ed | 26 | |
ccaf1749 | 27 | #define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */ |
99f575ed | 28 | |
6b4bbd6a SH |
29 | /* Tick Timer global state to allow all cores to be in sync */ |
30 | typedef struct OR1KTimerState { | |
31 | uint32_t ttcr; | |
32 | uint64_t last_clk; | |
33 | } OR1KTimerState; | |
99f575ed | 34 | |
6b4bbd6a SH |
35 | static OR1KTimerState *or1k_timer; |
36 | ||
37 | void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) | |
38 | { | |
39 | or1k_timer->ttcr = val; | |
40 | } | |
41 | ||
42 | uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) | |
43 | { | |
44 | return or1k_timer->ttcr; | |
45 | } | |
46 | ||
47 | /* Add elapsed ticks to ttcr */ | |
99f575ed JL |
48 | void cpu_openrisc_count_update(OpenRISCCPU *cpu) |
49 | { | |
d5155217 | 50 | uint64_t now; |
99f575ed | 51 | |
6b4bbd6a | 52 | if (!cpu->env.is_counting) { |
99f575ed JL |
53 | return; |
54 | } | |
d5155217 | 55 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
6b4bbd6a SH |
56 | or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk) |
57 | / TIMER_PERIOD); | |
58 | or1k_timer->last_clk = now; | |
d5155217 SM |
59 | } |
60 | ||
6b4bbd6a | 61 | /* Update the next timeout time as difference between ttmr and ttcr */ |
d5155217 SM |
62 | void cpu_openrisc_timer_update(OpenRISCCPU *cpu) |
63 | { | |
64 | uint32_t wait; | |
65 | uint64_t now, next; | |
66 | ||
6b4bbd6a | 67 | if (!cpu->env.is_counting) { |
d5155217 SM |
68 | return; |
69 | } | |
70 | ||
71 | cpu_openrisc_count_update(cpu); | |
6b4bbd6a | 72 | now = or1k_timer->last_clk; |
99f575ed | 73 | |
6b4bbd6a SH |
74 | if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) { |
75 | wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; | |
99f575ed JL |
76 | wait += cpu->env.ttmr & TTMR_TP; |
77 | } else { | |
6b4bbd6a | 78 | wait = (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP); |
99f575ed | 79 | } |
ccaf1749 | 80 | next = now + (uint64_t)wait * TIMER_PERIOD; |
bc72ad67 | 81 | timer_mod(cpu->env.timer, next); |
99f575ed JL |
82 | } |
83 | ||
84 | void cpu_openrisc_count_start(OpenRISCCPU *cpu) | |
85 | { | |
6b4bbd6a | 86 | cpu->env.is_counting = 1; |
99f575ed JL |
87 | cpu_openrisc_count_update(cpu); |
88 | } | |
89 | ||
90 | void cpu_openrisc_count_stop(OpenRISCCPU *cpu) | |
91 | { | |
d5155217 | 92 | timer_del(cpu->env.timer); |
99f575ed | 93 | cpu_openrisc_count_update(cpu); |
6b4bbd6a | 94 | cpu->env.is_counting = 0; |
99f575ed JL |
95 | } |
96 | ||
97 | static void openrisc_timer_cb(void *opaque) | |
98 | { | |
99 | OpenRISCCPU *cpu = opaque; | |
100 | ||
101 | if ((cpu->env.ttmr & TTMR_IE) && | |
bc72ad67 | 102 | timer_expired(cpu->env.timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL))) { |
259186a7 AF |
103 | CPUState *cs = CPU(cpu); |
104 | ||
99f575ed | 105 | cpu->env.ttmr |= TTMR_IP; |
259186a7 | 106 | cs->interrupt_request |= CPU_INTERRUPT_TIMER; |
99f575ed JL |
107 | } |
108 | ||
109 | switch (cpu->env.ttmr & TTMR_M) { | |
110 | case TIMER_NONE: | |
111 | break; | |
112 | case TIMER_INTR: | |
6b4bbd6a | 113 | or1k_timer->ttcr = 0; |
99f575ed JL |
114 | break; |
115 | case TIMER_SHOT: | |
116 | cpu_openrisc_count_stop(cpu); | |
117 | break; | |
118 | case TIMER_CONT: | |
99f575ed JL |
119 | break; |
120 | } | |
d5155217 SM |
121 | |
122 | cpu_openrisc_timer_update(cpu); | |
373b259b | 123 | qemu_cpu_kick(CPU(cpu)); |
99f575ed JL |
124 | } |
125 | ||
557e3707 SH |
126 | /* Reset the per CPU counter state. */ |
127 | static void openrisc_count_reset(void *opaque) | |
128 | { | |
129 | OpenRISCCPU *cpu = opaque; | |
130 | ||
131 | if (cpu->env.is_counting) { | |
132 | cpu_openrisc_count_stop(cpu); | |
133 | } | |
134 | cpu->env.ttmr = 0x00000000; | |
135 | } | |
136 | ||
137 | /* Reset the global timer state. */ | |
138 | static void openrisc_timer_reset(void *opaque) | |
139 | { | |
140 | or1k_timer->ttcr = 0x00000000; | |
141 | or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
142 | } | |
143 | ||
6b4bbd6a SH |
144 | static const VMStateDescription vmstate_or1k_timer = { |
145 | .name = "or1k_timer", | |
146 | .version_id = 1, | |
147 | .minimum_version_id = 1, | |
be555ec4 | 148 | .fields = (const VMStateField[]) { |
6b4bbd6a SH |
149 | VMSTATE_UINT32(ttcr, OR1KTimerState), |
150 | VMSTATE_UINT64(last_clk, OR1KTimerState), | |
151 | VMSTATE_END_OF_LIST() | |
152 | } | |
153 | }; | |
154 | ||
99f575ed JL |
155 | void cpu_openrisc_clock_init(OpenRISCCPU *cpu) |
156 | { | |
bc72ad67 | 157 | cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu); |
6b4bbd6a | 158 | |
557e3707 | 159 | qemu_register_reset(openrisc_count_reset, cpu); |
6b4bbd6a SH |
160 | if (or1k_timer == NULL) { |
161 | or1k_timer = g_new0(OR1KTimerState, 1); | |
557e3707 | 162 | qemu_register_reset(openrisc_timer_reset, cpu); |
6b4bbd6a SH |
163 | vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer); |
164 | } | |
99f575ed | 165 | } |