]>
Commit | Line | Data |
---|---|---|
ce6e1e9e JL |
1 | /* |
2 | * OpenRISC simulator for use as an IIS. | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * Feng Gao <gf91597@gmail.com> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
4771d756 PB |
23 | #include "qemu-common.h" |
24 | #include "cpu.h" | |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/boards.h" | |
ce6e1e9e | 27 | #include "elf.h" |
0d09e41a | 28 | #include "hw/char/serial.h" |
1422e32d | 29 | #include "net/net.h" |
83c9f4ca | 30 | #include "hw/loader.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
9c17d615 | 34 | #include "sysemu/qtest.h" |
ce6e1e9e JL |
35 | |
36 | #define KERNEL_LOAD_ADDR 0x100 | |
37 | ||
38 | static void main_cpu_reset(void *opaque) | |
39 | { | |
40 | OpenRISCCPU *cpu = opaque; | |
41 | ||
42 | cpu_reset(CPU(cpu)); | |
43 | } | |
44 | ||
45 | static void openrisc_sim_net_init(MemoryRegion *address_space, | |
a8170e5e AK |
46 | hwaddr base, |
47 | hwaddr descriptors, | |
ce6e1e9e JL |
48 | qemu_irq irq, NICInfo *nd) |
49 | { | |
50 | DeviceState *dev; | |
51 | SysBusDevice *s; | |
52 | ||
53 | dev = qdev_create(NULL, "open_eth"); | |
54 | qdev_set_nic_properties(dev, nd); | |
55 | qdev_init_nofail(dev); | |
56 | ||
1356b98d | 57 | s = SYS_BUS_DEVICE(dev); |
ce6e1e9e JL |
58 | sysbus_connect_irq(s, 0, irq); |
59 | memory_region_add_subregion(address_space, base, | |
60 | sysbus_mmio_get_region(s, 0)); | |
61 | memory_region_add_subregion(address_space, descriptors, | |
62 | sysbus_mmio_get_region(s, 1)); | |
63 | } | |
64 | ||
65 | static void cpu_openrisc_load_kernel(ram_addr_t ram_size, | |
66 | const char *kernel_filename, | |
67 | OpenRISCCPU *cpu) | |
68 | { | |
69 | long kernel_size; | |
70 | uint64_t elf_entry; | |
a8170e5e | 71 | hwaddr entry; |
ce6e1e9e JL |
72 | |
73 | if (kernel_filename && !qtest_enabled()) { | |
74 | kernel_size = load_elf(kernel_filename, NULL, NULL, | |
7ef295ea PC |
75 | &elf_entry, NULL, NULL, 1, EM_OPENRISC, |
76 | 1, 0); | |
ce6e1e9e JL |
77 | entry = elf_entry; |
78 | if (kernel_size < 0) { | |
79 | kernel_size = load_uimage(kernel_filename, | |
25bda50a | 80 | &entry, NULL, NULL, NULL, NULL); |
ce6e1e9e JL |
81 | } |
82 | if (kernel_size < 0) { | |
83 | kernel_size = load_image_targphys(kernel_filename, | |
84 | KERNEL_LOAD_ADDR, | |
85 | ram_size - KERNEL_LOAD_ADDR); | |
86 | entry = KERNEL_LOAD_ADDR; | |
87 | } | |
88 | ||
89 | if (kernel_size < 0) { | |
4284c051 | 90 | fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n", |
ce6e1e9e JL |
91 | kernel_filename); |
92 | exit(1); | |
93 | } | |
b6d9766d | 94 | cpu->env.pc = entry; |
ce6e1e9e | 95 | } |
ce6e1e9e JL |
96 | } |
97 | ||
3ef96221 | 98 | static void openrisc_sim_init(MachineState *machine) |
ce6e1e9e | 99 | { |
3ef96221 MA |
100 | ram_addr_t ram_size = machine->ram_size; |
101 | const char *cpu_model = machine->cpu_model; | |
102 | const char *kernel_filename = machine->kernel_filename; | |
68f12828 | 103 | OpenRISCCPU *cpu = NULL; |
ce6e1e9e JL |
104 | MemoryRegion *ram; |
105 | int n; | |
106 | ||
107 | if (!cpu_model) { | |
108 | cpu_model = "or1200"; | |
109 | } | |
110 | ||
111 | for (n = 0; n < smp_cpus; n++) { | |
112 | cpu = cpu_openrisc_init(cpu_model); | |
113 | if (cpu == NULL) { | |
4284c051 | 114 | fprintf(stderr, "Unable to find CPU definition!\n"); |
ce6e1e9e JL |
115 | exit(1); |
116 | } | |
117 | qemu_register_reset(main_cpu_reset, cpu); | |
118 | main_cpu_reset(cpu); | |
119 | } | |
120 | ||
121 | ram = g_malloc(sizeof(*ram)); | |
f8ed85ac | 122 | memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); |
ce6e1e9e JL |
123 | vmstate_register_ram_global(ram); |
124 | memory_region_add_subregion(get_system_memory(), 0, ram); | |
125 | ||
126 | cpu_openrisc_pic_init(cpu); | |
127 | cpu_openrisc_clock_init(cpu); | |
128 | ||
129 | serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2], | |
130 | 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); | |
131 | ||
a005d073 | 132 | if (nd_table[0].used) { |
ce6e1e9e JL |
133 | openrisc_sim_net_init(get_system_memory(), 0x92000000, |
134 | 0x92000400, cpu->env.irq[4], nd_table); | |
135 | } | |
136 | ||
137 | cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu); | |
138 | } | |
139 | ||
e264d29d | 140 | static void openrisc_sim_machine_init(MachineClass *mc) |
ce6e1e9e | 141 | { |
4a09d0bb | 142 | mc->desc = "or1k simulation"; |
e264d29d EH |
143 | mc->init = openrisc_sim_init; |
144 | mc->max_cpus = 1; | |
145 | mc->is_default = 1; | |
ce6e1e9e JL |
146 | } |
147 | ||
4a09d0bb | 148 | DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init) |