[mirror_qemu.git] / hw / parallel.c

/*
 * QEMU Parallel PORT emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2007 Marko Kohtala
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-char.h"
#include "isa.h"
#include "pc.h"
#include "sysemu.h"

//#define DEBUG_PARALLEL

#ifdef DEBUG_PARALLEL
#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
#else
#define pdebug(fmt, ...) ((void)0)
#endif

#define PARA_REG_DATA 0
#define PARA_REG_STS 1
#define PARA_REG_CTR 2
#define PARA_REG_EPP_ADDR 3
#define PARA_REG_EPP_DATA 4

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */
#define PARA_STS_TMOUT	0x01	/* EPP timeout */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_DIR	0x20	/* Direction (1=read, 0=write) */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)

typedef struct ParallelState {
    MemoryRegion iomem;
    uint8_t dataw;
    uint8_t datar;
    uint8_t status;
    uint8_t control;
    qemu_irq irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
    int epp_timeout;
    uint32_t last_read_offset; /* For debugging */
    /* Memory-mapped interface */
    int it_shift;
} ParallelState;

typedef struct ISAParallelState {
    ISADevice dev;
    uint32_t index;
    uint32_t iobase;
    uint32_t isairq;
    ParallelState state;
} ISAParallelState;

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;

    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        s->dataw = val;
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if ((val & PARA_CTR_INIT) == 0 ) {
            s->status = PARA_STS_BUSY;
            s->status |= PARA_STS_ACK;
            s->status |= PARA_STS_ONLINE;
            s->status |= PARA_STS_ERROR;
        }
        else if (val & PARA_CTR_SELECT) {
            if (val & PARA_CTR_STROBE) {
                s->status &= ~PARA_STS_BUSY;
                if ((s->control & PARA_CTR_STROBE) == 0)
                    qemu_chr_fe_write(s->chr, &s->dataw, 1);
            } else {
                if (s->control & PARA_CTR_INTEN) {
                    s->irq_pending = 1;
                }
            }
        }
        parallel_update_irq(s);
        s->control = val;
        break;
    }
}

static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint8_t parm = val;
    int dir;

    /* Sometimes programs do several writes for timing purposes on old
       HW. Take care not to waste time on writes that do nothing. */

    s->last_read_offset = ~0U;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->dataw == val)
            return;
        pdebug("wd%02x\n", val);
        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
        s->dataw = val;
        break;
    case PARA_REG_STS:
        pdebug("ws%02x\n", val);
        if (val & PARA_STS_TMOUT)
            s->epp_timeout = 0;
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if (s->control == val)
            return;
        pdebug("wc%02x\n", val);

        if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
            if (val & PARA_CTR_DIR) {
                dir = 1;
            } else {
                dir = 0;
            }
            qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
            parm &= ~PARA_CTR_DIR;
        }

        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
        s->control = val;
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP address cycle, so do nothing */
            pdebug("wa%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("wa%02x t\n", val);
            }
            else
                pdebug("wa%02x\n", val);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("we%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("we%02x t\n", val);
            }
            else
                pdebug("we%02x\n", val);
        }
        break;
    }
}

static void
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint16_t eppdata = cpu_to_le16(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%04x s\n", val);
        return;
    }
    err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%04x t\n", val);
    }
    else
        pdebug("we%04x\n", val);
}

static void
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint32_t eppdata = cpu_to_le32(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%08x s\n", val);
        return;
    }
    err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%08x t\n", val);
    }
    else
        pdebug("we%08x\n", val);
}

static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->control & PARA_CTR_DIR)
            ret = s->datar;
        else
            ret = s->dataw;
        break;
    case PARA_REG_STS:
        ret = s->status;
        s->irq_pending = 0;
        if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
            /* XXX Fixme: wait 5 microseconds */
            if (s->status & PARA_STS_ACK)
                s->status &= ~PARA_STS_ACK;
            else {
                /* XXX Fixme: wait 5 microseconds */
                s->status |= PARA_STS_ACK;
                s->status |= PARA_STS_BUSY;
            }
        }
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        ret = s->control;
        break;
    }
    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint8_t ret = 0xff;
    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
        if (s->last_read_offset != addr || s->datar != ret)
            pdebug("rd%02x\n", ret);
        s->datar = ret;
        break;
    case PARA_REG_STS:
        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
        ret &= ~PARA_STS_TMOUT;
        if (s->epp_timeout)
            ret |= PARA_STS_TMOUT;
        if (s->last_read_offset != addr || s->status != ret)
            pdebug("rs%02x\n", ret);
        s->status = ret;
        break;
    case PARA_REG_CTR:
        /* s->control has some bits fixed to 1. It is zero only when
           it has not been yet written to.  */
        if (s->control == 0) {
            qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
            s->control = ret;
        }
        else {
            ret = s->control;
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP addr cycle, so do nothing */
            pdebug("ra%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("ra%02x t\n", ret);
            }
            else
                pdebug("ra%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("re%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("re%02x t\n", ret);
            }
            else
                pdebug("re%02x\n", ret);
        }
        break;
    }
    s->last_read_offset = addr;
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint16_t eppdata = ~0;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%04x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le16_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%04x t\n", ret);
    }
    else
        pdebug("re%04x\n", ret);
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint32_t eppdata = ~0U;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%08x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le32_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%08x t\n", ret);
    }
    else
        pdebug("re%08x\n", ret);
    return ret;
}

static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
    pdebug("wecp%d=%02x\n", addr & 7, val);
}

static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
    uint8_t ret = 0xff;

    pdebug("recp%d:%02x\n", addr & 7, ret);
    return ret;
}

static void parallel_reset(void *opaque)
{
    ParallelState *s = opaque;

    s->datar = ~0;
    s->dataw = ~0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->status |= PARA_STS_TMOUT;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;
    s->control |= 0xc0;
    s->irq_pending = 0;
    s->hw_driver = 0;
    s->epp_timeout = 0;
    s->last_read_offset = ~0U;
}

static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };

static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
    { 0, 8, 1,
      .read = parallel_ioport_read_hw,
      .write = parallel_ioport_write_hw },
    { 4, 1, 2,
      .read = parallel_ioport_eppdata_read_hw2,
      .write = parallel_ioport_eppdata_write_hw2 },
    { 4, 1, 4,
      .read = parallel_ioport_eppdata_read_hw4,
      .write = parallel_ioport_eppdata_write_hw4 },
    { 0x400, 8, 1,
      .read = parallel_ioport_ecp_read,
      .write = parallel_ioport_ecp_write },
    PORTIO_END_OF_LIST(),
};

static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
    { 0, 8, 1,
      .read = parallel_ioport_read_sw,
      .write = parallel_ioport_write_sw },
    PORTIO_END_OF_LIST(),
};

static int parallel_isa_initfn(ISADevice *dev)
{
    static int index;
    ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
    ParallelState *s = &isa->state;
    int base;
    uint8_t dummy;

    if (!s->chr) {
        fprintf(stderr, "Can't create parallel device, empty char device\n");
        exit(1);
    }

    if (isa->index == -1)
        isa->index = index;
    if (isa->index >= MAX_PARALLEL_PORTS)
        return -1;
    if (isa->iobase == -1)
        isa->iobase = isa_parallel_io[isa->index];
    index++;

    base = isa->iobase;
    isa_init_irq(dev, &s->irq, isa->isairq);
    qemu_register_reset(parallel_reset, s);

    if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
        s->hw_driver = 1;
        s->status = dummy;
    }

    isa_register_portio_list(dev, base,
                             (s->hw_driver
                              ? &isa_parallel_portio_hw_list[0]
                              : &isa_parallel_portio_sw_list[0]),
                             s, "parallel");
    return 0;
}

/* Memory mapped interface */
static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
}

static void parallel_mm_writeb (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}

static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
}

static void parallel_mm_writew (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}

static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift);
}

static void parallel_mm_writel (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value);
}

static const MemoryRegionOps parallel_mm_ops = {
    .old_mmio = {
        .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
        .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

/* If fd is zero, it means that the parallel device uses the console */
bool parallel_mm_init(MemoryRegion *address_space,
                      target_phys_addr_t base, int it_shift, qemu_irq irq,
                      CharDriverState *chr)
{
    ParallelState *s;

    s = g_malloc0(sizeof(ParallelState));
    s->irq = irq;
    s->chr = chr;
    s->it_shift = it_shift;
    qemu_register_reset(parallel_reset, s);

    memory_region_init_io(&s->iomem, &parallel_mm_ops, s,
                          "parallel", 8 << it_shift);
    memory_region_add_subregion(address_space, base, &s->iomem);
    return true;
}

static ISADeviceInfo parallel_isa_info = {
    .qdev.name  = "isa-parallel",
    .qdev.size  = sizeof(ISAParallelState),
    .init       = parallel_isa_initfn,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("index", ISAParallelState, index,   -1),
        DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase,  -1),
        DEFINE_PROP_UINT32("irq",   ISAParallelState, isairq,  7),
        DEFINE_PROP_CHR("chardev",  ISAParallelState, state.chr),
        DEFINE_PROP_END_OF_LIST(),
    },
};

static void parallel_register_devices(void)
{
    isa_qdev_register(&parallel_isa_info);
}

device_init(parallel_register_devices)
Commit	Line	Data
6508fe59 FB	1	/*
6508fe59 FB	2	* QEMU Parallel PORT emulation
5fafdf24	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
5867c88a	5	* Copyright (c) 2007 Marko Kohtala
5fafdf24	6	*
6508fe59 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
87ecb68b PB	25	#include "hw.h"
	26	#include "qemu-char.h"
	27	#include "isa.h"
	28	#include "pc.h"
666daa68	29	#include "sysemu.h"
6508fe59 FB	30
	31	//#define DEBUG_PARALLEL
	32
5867c88a	33	#ifdef DEBUG_PARALLEL
001faf32	34	#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
5867c88a	35	#else
001faf32	36	#define pdebug(fmt, ...) ((void)0)
5867c88a TS	37	#endif
	38
	39	#define PARA_REG_DATA 0
	40	#define PARA_REG_STS 1
	41	#define PARA_REG_CTR 2
	42	#define PARA_REG_EPP_ADDR 3
	43	#define PARA_REG_EPP_DATA 4
	44
6508fe59 FB	45	/*
	46	* These are the definitions for the Printer Status Register
	47	*/
	48	#define PARA_STS_BUSY 0x80 /* Busy complement */
	49	#define PARA_STS_ACK 0x40 /* Acknowledge */
	50	#define PARA_STS_PAPER 0x20 /* Out of paper */
	51	#define PARA_STS_ONLINE 0x10 /* Online */
	52	#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a	53	#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59 FB	54
	55	/*
	56	* These are the definitions for the Printer Control Register
	57	*/
5867c88a	58	#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59 FB	59	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	60	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	61	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	62	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	63	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	64
5867c88a TS	65	#define PARA_CTR_SIGNAL (PARA_CTR_SELECT\|PARA_CTR_INIT\|PARA_CTR_AUTOLF\|PARA_CTR_STROBE)
5867c88a TS	66
defdb20e	67	typedef struct ParallelState {
63858cd9	68	MemoryRegion iomem;
5867c88a TS	69	uint8_t dataw;
	70	uint8_t datar;
	71	uint8_t status;
6508fe59	72	uint8_t control;
d537cf6c	73	qemu_irq irq;
6508fe59 FB	74	int irq_pending;
6508fe59 FB	75	CharDriverState *chr;
e57a8c0e	76	int hw_driver;
5867c88a TS	77	int epp_timeout;
5867c88a TS	78	uint32_t last_read_offset; /* For debugging */
d60532ca	79	/* Memory-mapped interface */
d60532ca	80	int it_shift;
defdb20e	81	} ParallelState;
6508fe59	82
021f0674 GH	83	typedef struct ISAParallelState {
021f0674 GH	84	ISADevice dev;
e8ee28fb	85	uint32_t index;
021f0674 GH	86	uint32_t iobase;
	87	uint32_t isairq;
	88	ParallelState state;
	89	} ISAParallelState;
	90
6508fe59 FB	91	static void parallel_update_irq(ParallelState *s)
	92	{
	93	if (s->irq_pending)
d537cf6c	94	qemu_irq_raise(s->irq);
6508fe59	95	else
d537cf6c	96	qemu_irq_lower(s->irq);
6508fe59 FB	97	}
6508fe59 FB	98
5867c88a TS	99	static void
5867c88a TS	100	parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59 FB	101	{
6508fe59 FB	102	ParallelState *s = opaque;
3b46e624	103
5867c88a TS	104	pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
	105
	106	addr &= 7;
	107	switch(addr) {
	108	case PARA_REG_DATA:
0fa7f157 TS	109	s->dataw = val;
0fa7f157 TS	110	parallel_update_irq(s);
5867c88a TS	111	break;
5867c88a TS	112	case PARA_REG_CTR:
52ccc5e0	113	val \|= 0xc0;
0fa7f157 TS	114	if ((val & PARA_CTR_INIT) == 0 ) {
	115	s->status = PARA_STS_BUSY;
	116	s->status \|= PARA_STS_ACK;
	117	s->status \|= PARA_STS_ONLINE;
	118	s->status \|= PARA_STS_ERROR;
	119	}
	120	else if (val & PARA_CTR_SELECT) {
	121	if (val & PARA_CTR_STROBE) {
	122	s->status &= ~PARA_STS_BUSY;
	123	if ((s->control & PARA_CTR_STROBE) == 0)
2cc6e0a1	124	qemu_chr_fe_write(s->chr, &s->dataw, 1);
0fa7f157 TS	125	} else {
	126	if (s->control & PARA_CTR_INTEN) {
	127	s->irq_pending = 1;
	128	}
	129	}
	130	}
	131	parallel_update_irq(s);
	132	s->control = val;
5867c88a TS	133	break;
	134	}
	135	}
	136
	137	static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
	138	{
	139	ParallelState *s = opaque;
	140	uint8_t parm = val;
563e3c6e	141	int dir;
5867c88a TS	142
	143	/* Sometimes programs do several writes for timing purposes on old
	144	HW. Take care not to waste time on writes that do nothing. */
	145
	146	s->last_read_offset = ~0U;
	147
6508fe59	148	addr &= 7;
6508fe59	149	switch(addr) {
5867c88a TS	150	case PARA_REG_DATA:
5867c88a TS	151	if (s->dataw == val)
0fa7f157 TS	152	return;
0fa7f157 TS	153	pdebug("wd%02x\n", val);
41084f1b	154	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
0fa7f157	155	s->dataw = val;
6508fe59	156	break;
5867c88a	157	case PARA_REG_STS:
0fa7f157 TS	158	pdebug("ws%02x\n", val);
	159	if (val & PARA_STS_TMOUT)
	160	s->epp_timeout = 0;
	161	break;
5867c88a TS	162	case PARA_REG_CTR:
	163	val \|= 0xc0;
	164	if (s->control == val)
0fa7f157 TS	165	return;
0fa7f157 TS	166	pdebug("wc%02x\n", val);
563e3c6e AJ	167
	168	if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
	169	if (val & PARA_CTR_DIR) {
	170	dir = 1;
	171	} else {
	172	dir = 0;
	173	}
41084f1b	174	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
563e3c6e AJ	175	parm &= ~PARA_CTR_DIR;
	176	}
	177
41084f1b	178	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
0fa7f157	179	s->control = val;
6508fe59	180	break;
5867c88a	181	case PARA_REG_EPP_ADDR:
0fa7f157 TS	182	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	183	/* Controls not correct for EPP address cycle, so do nothing */
	184	pdebug("wa%02x s\n", val);
	185	else {
	186	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
41084f1b	187	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
0fa7f157 TS	188	s->epp_timeout = 1;
	189	pdebug("wa%02x t\n", val);
	190	}
	191	else
	192	pdebug("wa%02x\n", val);
	193	}
	194	break;
5867c88a	195	case PARA_REG_EPP_DATA:
0fa7f157 TS	196	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	197	/* Controls not correct for EPP data cycle, so do nothing */
	198	pdebug("we%02x s\n", val);
	199	else {
	200	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
41084f1b	201	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
0fa7f157 TS	202	s->epp_timeout = 1;
	203	pdebug("we%02x t\n", val);
	204	}
	205	else
	206	pdebug("we%02x\n", val);
	207	}
	208	break;
5867c88a TS	209	}
	210	}
	211
	212	static void
	213	parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
	214	{
	215	ParallelState *s = opaque;
	216	uint16_t eppdata = cpu_to_le16(val);
	217	int err;
	218	struct ParallelIOArg ioarg = {
0fa7f157	219	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	220	};
5867c88a TS	221	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	222	/* Controls not correct for EPP data cycle, so do nothing */
	223	pdebug("we%04x s\n", val);
	224	return;
5867c88a	225	}
41084f1b	226	err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
5867c88a	227	if (err) {
0fa7f157 TS	228	s->epp_timeout = 1;
0fa7f157 TS	229	pdebug("we%04x t\n", val);
5867c88a TS	230	}
5867c88a TS	231	else
0fa7f157	232	pdebug("we%04x\n", val);
5867c88a TS	233	}
	234
	235	static void
	236	parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
	237	{
	238	ParallelState *s = opaque;
	239	uint32_t eppdata = cpu_to_le32(val);
	240	int err;
	241	struct ParallelIOArg ioarg = {
0fa7f157	242	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	243	};
5867c88a TS	244	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	245	/* Controls not correct for EPP data cycle, so do nothing */
	246	pdebug("we%08x s\n", val);
	247	return;
5867c88a	248	}
41084f1b	249	err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
5867c88a	250	if (err) {
0fa7f157 TS	251	s->epp_timeout = 1;
0fa7f157 TS	252	pdebug("we%08x t\n", val);
6508fe59	253	}
5867c88a	254	else
0fa7f157	255	pdebug("we%08x\n", val);
6508fe59 FB	256	}
6508fe59 FB	257
5867c88a	258	static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59 FB	259	{
	260	ParallelState *s = opaque;
	261	uint32_t ret = 0xff;
	262
	263	addr &= 7;
	264	switch(addr) {
5867c88a	265	case PARA_REG_DATA:
0fa7f157 TS	266	if (s->control & PARA_CTR_DIR)
	267	ret = s->datar;
	268	else
	269	ret = s->dataw;
6508fe59	270	break;
5867c88a	271	case PARA_REG_STS:
0fa7f157 TS	272	ret = s->status;
	273	s->irq_pending = 0;
	274	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	275	/* XXX Fixme: wait 5 microseconds */
	276	if (s->status & PARA_STS_ACK)
	277	s->status &= ~PARA_STS_ACK;
	278	else {
	279	/* XXX Fixme: wait 5 microseconds */
	280	s->status \|= PARA_STS_ACK;
	281	s->status \|= PARA_STS_BUSY;
	282	}
	283	}
	284	parallel_update_irq(s);
6508fe59	285	break;
5867c88a	286	case PARA_REG_CTR:
6508fe59 FB	287	ret = s->control;
	288	break;
	289	}
5867c88a TS	290	pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
	291	return ret;
	292	}
	293
	294	static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
	295	{
	296	ParallelState *s = opaque;
	297	uint8_t ret = 0xff;
	298	addr &= 7;
	299	switch(addr) {
	300	case PARA_REG_DATA:
41084f1b	301	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
0fa7f157 TS	302	if (s->last_read_offset != addr \|\| s->datar != ret)
0fa7f157 TS	303	pdebug("rd%02x\n", ret);
5867c88a TS	304	s->datar = ret;
	305	break;
	306	case PARA_REG_STS:
41084f1b	307	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
0fa7f157 TS	308	ret &= ~PARA_STS_TMOUT;
	309	if (s->epp_timeout)
	310	ret \|= PARA_STS_TMOUT;
	311	if (s->last_read_offset != addr \|\| s->status != ret)
	312	pdebug("rs%02x\n", ret);
	313	s->status = ret;
5867c88a TS	314	break;
	315	case PARA_REG_CTR:
	316	/* s->control has some bits fixed to 1. It is zero only when
0fa7f157 TS	317	it has not been yet written to. */
0fa7f157 TS	318	if (s->control == 0) {
41084f1b	319	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
0fa7f157 TS	320	if (s->last_read_offset != addr)
	321	pdebug("rc%02x\n", ret);
	322	s->control = ret;
	323	}
	324	else {
	325	ret = s->control;
	326	if (s->last_read_offset != addr)
	327	pdebug("rc%02x\n", ret);
	328	}
5867c88a TS	329	break;
5867c88a TS	330	case PARA_REG_EPP_ADDR:
0fa7f157 TS	331	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	332	/* Controls not correct for EPP addr cycle, so do nothing */
	333	pdebug("ra%02x s\n", ret);
	334	else {
	335	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
41084f1b	336	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
0fa7f157 TS	337	s->epp_timeout = 1;
	338	pdebug("ra%02x t\n", ret);
	339	}
	340	else
	341	pdebug("ra%02x\n", ret);
	342	}
	343	break;
5867c88a	344	case PARA_REG_EPP_DATA:
0fa7f157 TS	345	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	346	/* Controls not correct for EPP data cycle, so do nothing */
	347	pdebug("re%02x s\n", ret);
	348	else {
	349	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
41084f1b	350	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
0fa7f157 TS	351	s->epp_timeout = 1;
	352	pdebug("re%02x t\n", ret);
	353	}
	354	else
	355	pdebug("re%02x\n", ret);
	356	}
	357	break;
5867c88a TS	358	}
	359	s->last_read_offset = addr;
	360	return ret;
	361	}
	362
	363	static uint32_t
	364	parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
	365	{
	366	ParallelState *s = opaque;
	367	uint32_t ret;
	368	uint16_t eppdata = ~0;
	369	int err;
	370	struct ParallelIOArg ioarg = {
0fa7f157	371	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	372	};
5867c88a TS	373	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	374	/* Controls not correct for EPP data cycle, so do nothing */
	375	pdebug("re%04x s\n", eppdata);
	376	return eppdata;
5867c88a	377	}
41084f1b	378	err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
5867c88a TS	379	ret = le16_to_cpu(eppdata);
	380
	381	if (err) {
0fa7f157 TS	382	s->epp_timeout = 1;
0fa7f157 TS	383	pdebug("re%04x t\n", ret);
5867c88a TS	384	}
5867c88a TS	385	else
0fa7f157	386	pdebug("re%04x\n", ret);
5867c88a TS	387	return ret;
	388	}
	389
	390	static uint32_t
	391	parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
	392	{
	393	ParallelState *s = opaque;
	394	uint32_t ret;
	395	uint32_t eppdata = ~0U;
	396	int err;
	397	struct ParallelIOArg ioarg = {
0fa7f157	398	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	399	};
5867c88a TS	400	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	401	/* Controls not correct for EPP data cycle, so do nothing */
	402	pdebug("re%08x s\n", eppdata);
	403	return eppdata;
5867c88a	404	}
41084f1b	405	err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
5867c88a TS	406	ret = le32_to_cpu(eppdata);
	407
	408	if (err) {
0fa7f157 TS	409	s->epp_timeout = 1;
0fa7f157 TS	410	pdebug("re%08x t\n", ret);
5867c88a TS	411	}
5867c88a TS	412	else
0fa7f157	413	pdebug("re%08x\n", ret);
5867c88a TS	414	return ret;
	415	}
	416
	417	static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
	418	{
7f5b7d3e	419	pdebug("wecp%d=%02x\n", addr & 7, val);
5867c88a TS	420	}
	421
	422	static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
	423	{
	424	uint8_t ret = 0xff;
7f5b7d3e BS	425
7f5b7d3e BS	426	pdebug("recp%d:%02x\n", addr & 7, ret);
6508fe59 FB	427	return ret;
	428	}
	429
33093a0a	430	static void parallel_reset(void *opaque)
6508fe59	431	{
33093a0a AJ	432	ParallelState *s = opaque;
33093a0a AJ	433
5867c88a TS	434	s->datar = ~0;
5867c88a TS	435	s->dataw = ~0;
6508fe59 FB	436	s->status = PARA_STS_BUSY;
	437	s->status \|= PARA_STS_ACK;
	438	s->status \|= PARA_STS_ONLINE;
	439	s->status \|= PARA_STS_ERROR;
52ccc5e0	440	s->status \|= PARA_STS_TMOUT;
6508fe59 FB	441	s->control = PARA_CTR_SELECT;
6508fe59 FB	442	s->control \|= PARA_CTR_INIT;
52ccc5e0	443	s->control \|= 0xc0;
5867c88a	444	s->irq_pending = 0;
5867c88a TS	445	s->hw_driver = 0;
	446	s->epp_timeout = 0;
	447	s->last_read_offset = ~0U;
d60532ca TS	448	}
d60532ca TS	449
e8ee28fb GH	450	static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
e8ee28fb GH	451
1922abd0 RH	452	static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
	453	{ 0, 8, 1,
	454	.read = parallel_ioport_read_hw,
	455	.write = parallel_ioport_write_hw },
	456	{ 4, 1, 2,
	457	.read = parallel_ioport_eppdata_read_hw2,
	458	.write = parallel_ioport_eppdata_write_hw2 },
	459	{ 4, 1, 4,
	460	.read = parallel_ioport_eppdata_read_hw4,
	461	.write = parallel_ioport_eppdata_write_hw4 },
	462	{ 0x400, 8, 1,
	463	.read = parallel_ioport_ecp_read,
	464	.write = parallel_ioport_ecp_write },
	465	PORTIO_END_OF_LIST(),
	466	};
	467
	468	static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
	469	{ 0, 8, 1,
	470	.read = parallel_ioport_read_sw,
	471	.write = parallel_ioport_write_sw },
	472	PORTIO_END_OF_LIST(),
	473	};
	474
021f0674	475	static int parallel_isa_initfn(ISADevice *dev)
d60532ca	476	{
e8ee28fb	477	static int index;
021f0674 GH	478	ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
021f0674 GH	479	ParallelState *s = &isa->state;
e8ee28fb	480	int base;
d60532ca TS	481	uint8_t dummy;
d60532ca TS	482
021f0674 GH	483	if (!s->chr) {
	484	fprintf(stderr, "Can't create parallel device, empty char device\n");
	485	exit(1);
	486	}
	487
e8ee28fb GH	488	if (isa->index == -1)
	489	isa->index = index;
	490	if (isa->index >= MAX_PARALLEL_PORTS)
	491	return -1;
	492	if (isa->iobase == -1)
	493	isa->iobase = isa_parallel_io[isa->index];
	494	index++;
	495
	496	base = isa->iobase;
021f0674	497	isa_init_irq(dev, &s->irq, isa->isairq);
a08d4367	498	qemu_register_reset(parallel_reset, s);
6508fe59	499
41084f1b	500	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
5867c88a	501	s->hw_driver = 1;
0fa7f157	502	s->status = dummy;
5867c88a TS	503	}
5867c88a TS	504
1922abd0 RH	505	isa_register_portio_list(dev, base,
	506	(s->hw_driver
	507	? &isa_parallel_portio_hw_list[0]
	508	: &isa_parallel_portio_sw_list[0]),
	509	s, "parallel");
021f0674 GH	510	return 0;
	511	}
	512
d60532ca	513	/* Memory mapped interface */
c227f099	514	static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
d60532ca TS	515	{
	516	ParallelState *s = opaque;
	517
8da3ff18	518	return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
d60532ca TS	519	}
d60532ca TS	520
9596ebb7	521	static void parallel_mm_writeb (void *opaque,
c227f099	522	target_phys_addr_t addr, uint32_t value)
d60532ca TS	523	{
	524	ParallelState *s = opaque;
	525
8da3ff18	526	parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
d60532ca TS	527	}
d60532ca TS	528
c227f099	529	static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
d60532ca TS	530	{
	531	ParallelState *s = opaque;
	532
8da3ff18	533	return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
d60532ca TS	534	}
d60532ca TS	535
9596ebb7	536	static void parallel_mm_writew (void *opaque,
c227f099	537	target_phys_addr_t addr, uint32_t value)
d60532ca TS	538	{
	539	ParallelState *s = opaque;
	540
8da3ff18	541	parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
d60532ca TS	542	}
d60532ca TS	543
c227f099	544	static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
d60532ca TS	545	{
	546	ParallelState *s = opaque;
	547
8da3ff18	548	return parallel_ioport_read_sw(s, addr >> s->it_shift);
d60532ca TS	549	}
d60532ca TS	550
9596ebb7	551	static void parallel_mm_writel (void *opaque,
c227f099	552	target_phys_addr_t addr, uint32_t value)
d60532ca TS	553	{
	554	ParallelState *s = opaque;
	555
8da3ff18	556	parallel_ioport_write_sw(s, addr >> s->it_shift, value);
d60532ca TS	557	}
d60532ca TS	558
63858cd9 AK	559	static const MemoryRegionOps parallel_mm_ops = {
	560	.old_mmio = {
	561	.read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
	562	.write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
	563	},
	564	.endianness = DEVICE_NATIVE_ENDIAN,
d60532ca TS	565	};
	566
	567	/* If fd is zero, it means that the parallel device uses the console */
63858cd9 AK	568	bool parallel_mm_init(MemoryRegion *address_space,
63858cd9 AK	569	target_phys_addr_t base, int it_shift, qemu_irq irq,
defdb20e	570	CharDriverState *chr)
d60532ca TS	571	{
d60532ca TS	572	ParallelState *s;
d60532ca	573
7267c094	574	s = g_malloc0(sizeof(ParallelState));
33093a0a AJ	575	s->irq = irq;
33093a0a AJ	576	s->chr = chr;
d60532ca	577	s->it_shift = it_shift;
a08d4367	578	qemu_register_reset(parallel_reset, s);
d60532ca	579
63858cd9 AK	580	memory_region_init_io(&s->iomem, &parallel_mm_ops, s,
	581	"parallel", 8 << it_shift);
	582	memory_region_add_subregion(address_space, base, &s->iomem);
defdb20e	583	return true;
d60532ca	584	}
021f0674 GH	585
	586	static ISADeviceInfo parallel_isa_info = {
	587	.qdev.name = "isa-parallel",
	588	.qdev.size = sizeof(ISAParallelState),
	589	.init = parallel_isa_initfn,
	590	.qdev.props = (Property[]) {
51954d56	591	DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
e8ee28fb	592	DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase, -1),
021f0674 GH	593	DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
	594	DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
	595	DEFINE_PROP_END_OF_LIST(),
	596	},
	597	};
	598
	599	static void parallel_register_devices(void)
	600	{
	601	isa_qdev_register(&parallel_isa_info);
	602	}
	603
	604	device_init(parallel_register_devices)