[mirror_qemu.git] / hw / parallel.c

/*
 * QEMU Parallel PORT emulation
 * 
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_PARALLEL

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

struct ParallelState {
    uint8_t data;
    uint8_t status; /* read only register */
    uint8_t control;
    int irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
};

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        pic_set_irq(s->irq, 1);
    else
        pic_set_irq(s->irq, 0);
}

static void parallel_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    
    addr &= 7;
#ifdef DEBUG_PARALLEL
    printf("parallel: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    case 0:
        if (s->hw_driver) {
            s->data = val;
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &s->data);
        } else {
            s->data = val;
            parallel_update_irq(s);
        }
        break;
    case 2:
        if (s->hw_driver) {
            s->control = val;
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &s->control);
        } else {
            if ((val & PARA_CTR_INIT) == 0 ) {
                s->status = PARA_STS_BUSY;
                s->status |= PARA_STS_ACK;
                s->status |= PARA_STS_ONLINE;
                s->status |= PARA_STS_ERROR;
            }
            else if (val & PARA_CTR_SELECT) {
                if (val & PARA_CTR_STROBE) {
                    s->status &= ~PARA_STS_BUSY;
                    if ((s->control & PARA_CTR_STROBE) == 0)
                        qemu_chr_write(s->chr, &s->data, 1);
                } else {
                    if (s->control & PARA_CTR_INTEN) {
                        s->irq_pending = 1;
                    }
                }
            }
            parallel_update_irq(s);
            s->control = val;
        }
        break;
    }
}

static uint32_t parallel_ioport_read(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case 0:
        if (s->hw_driver) {
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &s->data);
        } 
        ret = s->data; 
        break;
    case 1:
        if (s->hw_driver) {
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &s->status);
            ret = s->status; 
        } else {
            ret = s->status;
            s->irq_pending = 0;
            if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
                /* XXX Fixme: wait 5 microseconds */
                if (s->status & PARA_STS_ACK)
                    s->status &= ~PARA_STS_ACK;
                else {
                    /* XXX Fixme: wait 5 microseconds */
                    s->status |= PARA_STS_ACK;
                    s->status |= PARA_STS_BUSY;
                }
            }
            parallel_update_irq(s);
        }
        break;
    case 2:
        if (s->hw_driver) {
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &s->control);
        }
        ret = s->control;
        break;
    }
#ifdef DEBUG_PARALLEL
    printf("parallel: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static int parallel_can_receive(ParallelState *s)
{
    return 0;
}

static void parallel_receive_byte(ParallelState *s, int ch)
{
}

static int parallel_can_receive1(void *opaque)
{
    ParallelState *s = opaque;
    return parallel_can_receive(s);
}

static void parallel_receive1(void *opaque, const uint8_t *buf, int size)
{
    ParallelState *s = opaque;
    parallel_receive_byte(s, buf[0]);
}

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_init(int base, int irq, CharDriverState *chr)
{
    ParallelState *s;
    uint8_t dummy;

    s = qemu_mallocz(sizeof(ParallelState));
    if (!s)
        return NULL;
    s->chr = chr;
    s->hw_driver = 0;
    if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0)
        s->hw_driver = 1;

    s->irq = irq;
    s->data = 0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;

    register_ioport_write(base, 8, 1, parallel_ioport_write, s);
    register_ioport_read(base, 8, 1, parallel_ioport_read, s);
    qemu_chr_add_read_handler(chr, parallel_can_receive1, parallel_receive1, s);
    return s;
}
Commit	Line	Data
6508fe59 FB	1	/*
	2	* QEMU Parallel PORT emulation
	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
6508fe59 FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	//#define DEBUG_PARALLEL
	27
	28	/*
	29	* These are the definitions for the Printer Status Register
	30	*/
	31	#define PARA_STS_BUSY 0x80 /* Busy complement */
	32	#define PARA_STS_ACK 0x40 /* Acknowledge */
	33	#define PARA_STS_PAPER 0x20 /* Out of paper */
	34	#define PARA_STS_ONLINE 0x10 /* Online */
	35	#define PARA_STS_ERROR 0x08 /* Error complement */
	36
	37	/*
	38	* These are the definitions for the Printer Control Register
	39	*/
	40	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	41	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	42	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	43	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	44	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	45
	46	struct ParallelState {
	47	uint8_t data;
	48	uint8_t status; /* read only register */
	49	uint8_t control;
	50	int irq;
	51	int irq_pending;
	52	CharDriverState *chr;
e57a8c0e	53	int hw_driver;
6508fe59 FB	54	};
	55
	56	static void parallel_update_irq(ParallelState *s)
	57	{
	58	if (s->irq_pending)
	59	pic_set_irq(s->irq, 1);
	60	else
	61	pic_set_irq(s->irq, 0);
	62	}
	63
	64	static void parallel_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	65	{
	66	ParallelState *s = opaque;
	67
	68	addr &= 7;
	69	#ifdef DEBUG_PARALLEL
	70	printf("parallel: write addr=0x%02x val=0x%02x\n", addr, val);
	71	#endif
	72	switch(addr) {
	73	case 0:
e57a8c0e FB	74	if (s->hw_driver) {
	75	s->data = val;
	76	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &s->data);
	77	} else {
	78	s->data = val;
	79	parallel_update_irq(s);
	80	}
6508fe59 FB	81	break;
6508fe59 FB	82	case 2:
e57a8c0e FB	83	if (s->hw_driver) {
	84	s->control = val;
	85	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &s->control);
	86	} else {
	87	if ((val & PARA_CTR_INIT) == 0 ) {
	88	s->status = PARA_STS_BUSY;
	89	s->status \|= PARA_STS_ACK;
	90	s->status \|= PARA_STS_ONLINE;
	91	s->status \|= PARA_STS_ERROR;
	92	}
	93	else if (val & PARA_CTR_SELECT) {
	94	if (val & PARA_CTR_STROBE) {
	95	s->status &= ~PARA_STS_BUSY;
	96	if ((s->control & PARA_CTR_STROBE) == 0)
	97	qemu_chr_write(s->chr, &s->data, 1);
	98	} else {
	99	if (s->control & PARA_CTR_INTEN) {
	100	s->irq_pending = 1;
	101	}
6508fe59 FB	102	}
6508fe59 FB	103	}
e57a8c0e FB	104	parallel_update_irq(s);
e57a8c0e FB	105	s->control = val;
6508fe59	106	}
6508fe59 FB	107	break;
	108	}
	109	}
	110
	111	static uint32_t parallel_ioport_read(void *opaque, uint32_t addr)
	112	{
	113	ParallelState *s = opaque;
	114	uint32_t ret = 0xff;
	115
	116	addr &= 7;
	117	switch(addr) {
	118	case 0:
e57a8c0e FB	119	if (s->hw_driver) {
	120	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &s->data);
	121	}
6508fe59 FB	122	ret = s->data;
	123	break;
	124	case 1:
e57a8c0e FB	125	if (s->hw_driver) {
	126	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &s->status);
	127	ret = s->status;
	128	} else {
	129	ret = s->status;
	130	s->irq_pending = 0;
	131	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	132	/* XXX Fixme: wait 5 microseconds */
	133	if (s->status & PARA_STS_ACK)
	134	s->status &= ~PARA_STS_ACK;
	135	else {
	136	/* XXX Fixme: wait 5 microseconds */
	137	s->status \|= PARA_STS_ACK;
	138	s->status \|= PARA_STS_BUSY;
	139	}
6508fe59	140	}
e57a8c0e	141	parallel_update_irq(s);
6508fe59	142	}
6508fe59 FB	143	break;
6508fe59 FB	144	case 2:
e57a8c0e FB	145	if (s->hw_driver) {
	146	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &s->control);
	147	}
6508fe59 FB	148	ret = s->control;
	149	break;
	150	}
	151	#ifdef DEBUG_PARALLEL
	152	printf("parallel: read addr=0x%02x val=0x%02x\n", addr, ret);
	153	#endif
	154	return ret;
	155	}
	156
	157	static int parallel_can_receive(ParallelState *s)
	158	{
	159	return 0;
	160	}
	161
	162	static void parallel_receive_byte(ParallelState *s, int ch)
	163	{
	164	}
	165
6508fe59 FB	166	static int parallel_can_receive1(void *opaque)
	167	{
	168	ParallelState *s = opaque;
	169	return parallel_can_receive(s);
	170	}
	171
	172	static void parallel_receive1(void opaque, const uint8_t buf, int size)
	173	{
	174	ParallelState *s = opaque;
	175	parallel_receive_byte(s, buf[0]);
	176	}
	177
6508fe59 FB	178	/* If fd is zero, it means that the parallel device uses the console */
	179	ParallelState parallel_init(int base, int irq, CharDriverState chr)
	180	{
	181	ParallelState *s;
e57a8c0e	182	uint8_t dummy;
6508fe59 FB	183
	184	s = qemu_mallocz(sizeof(ParallelState));
	185	if (!s)
	186	return NULL;
e57a8c0e FB	187	s->chr = chr;
	188	s->hw_driver = 0;
	189	if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0)
	190	s->hw_driver = 1;
	191
6508fe59 FB	192	s->irq = irq;
	193	s->data = 0;
	194	s->status = PARA_STS_BUSY;
	195	s->status \|= PARA_STS_ACK;
	196	s->status \|= PARA_STS_ONLINE;
	197	s->status \|= PARA_STS_ERROR;
	198	s->control = PARA_CTR_SELECT;
	199	s->control \|= PARA_CTR_INIT;
	200
	201	register_ioport_write(base, 8, 1, parallel_ioport_write, s);
	202	register_ioport_read(base, 8, 1, parallel_ioport_read, s);
6508fe59	203	qemu_chr_add_read_handler(chr, parallel_can_receive1, parallel_receive1, s);
6508fe59 FB	204	return s;
6508fe59 FB	205	}