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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
aa28b9bf | 26 | #include "apic.h" |
87ecb68b PB |
27 | #include "fdc.h" |
28 | #include "pci.h" | |
18e08a55 MT |
29 | #include "vmware_vga.h" |
30 | #include "usb-uhci.h" | |
31 | #include "usb-ohci.h" | |
32 | #include "prep_pci.h" | |
33 | #include "apb_pci.h" | |
87ecb68b PB |
34 | #include "block.h" |
35 | #include "sysemu.h" | |
36 | #include "audio/audio.h" | |
37 | #include "net.h" | |
38 | #include "smbus.h" | |
39 | #include "boards.h" | |
376253ec | 40 | #include "monitor.h" |
3cce6243 | 41 | #include "fw_cfg.h" |
16b29ae1 | 42 | #include "hpet_emul.h" |
9dd986cc | 43 | #include "watchdog.h" |
b6f6e3d3 | 44 | #include "smbios.h" |
ec82026c | 45 | #include "ide.h" |
ca20cf32 BS |
46 | #include "loader.h" |
47 | #include "elf.h" | |
52001445 | 48 | #include "multiboot.h" |
53b67b30 | 49 | #include "kvm.h" |
80cabfad | 50 | |
b41a2cd1 FB |
51 | /* output Bochs bios info messages */ |
52 | //#define DEBUG_BIOS | |
53 | ||
80cabfad | 54 | #define BIOS_FILENAME "bios.bin" |
80cabfad | 55 | |
7fb4fdcf AZ |
56 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
57 | ||
a80274c3 PB |
58 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
59 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 60 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 61 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 62 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 63 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 64 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
80cabfad | 65 | |
e4bcb14c TS |
66 | #define MAX_IDE_BUS 2 |
67 | ||
b0a21b53 | 68 | static RTCState *rtc_state; |
80cabfad | 69 | |
4c5b10b7 JS |
70 | #define E820_NR_ENTRIES 16 |
71 | ||
72 | struct e820_entry { | |
73 | uint64_t address; | |
74 | uint64_t length; | |
75 | uint32_t type; | |
76 | }; | |
77 | ||
78 | struct e820_table { | |
79 | uint32_t count; | |
80 | struct e820_entry entry[E820_NR_ENTRIES]; | |
81 | }; | |
82 | ||
83 | static struct e820_table e820_table; | |
84 | ||
1452411b AK |
85 | typedef struct isa_irq_state { |
86 | qemu_irq *i8259; | |
1632dc6a | 87 | qemu_irq *ioapic; |
1452411b AK |
88 | } IsaIrqState; |
89 | ||
90 | static void isa_irq_handler(void *opaque, int n, int level) | |
91 | { | |
92 | IsaIrqState *isa = (IsaIrqState *)opaque; | |
93 | ||
1632dc6a AK |
94 | if (n < 16) { |
95 | qemu_set_irq(isa->i8259[n], level); | |
96 | } | |
2c8d9340 GH |
97 | if (isa->ioapic) |
98 | qemu_set_irq(isa->ioapic[n], level); | |
1632dc6a | 99 | }; |
1452411b | 100 | |
b41a2cd1 | 101 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
102 | { |
103 | } | |
104 | ||
f929aad6 | 105 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 106 | static qemu_irq ferr_irq; |
f929aad6 FB |
107 | /* XXX: add IGNNE support */ |
108 | void cpu_set_ferr(CPUX86State *s) | |
109 | { | |
d537cf6c | 110 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
111 | } |
112 | ||
113 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
114 | { | |
d537cf6c | 115 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
116 | } |
117 | ||
28ab0e2e | 118 | /* TSC handling */ |
28ab0e2e FB |
119 | uint64_t cpu_get_tsc(CPUX86State *env) |
120 | { | |
4a1418e0 | 121 | return cpu_get_ticks(); |
28ab0e2e FB |
122 | } |
123 | ||
a5954d5c | 124 | /* SMM support */ |
f885f1ea IY |
125 | |
126 | static cpu_set_smm_t smm_set; | |
127 | static void *smm_arg; | |
128 | ||
129 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
130 | { | |
131 | assert(smm_set == NULL); | |
132 | assert(smm_arg == NULL); | |
133 | smm_set = callback; | |
134 | smm_arg = arg; | |
135 | } | |
136 | ||
a5954d5c FB |
137 | void cpu_smm_update(CPUState *env) |
138 | { | |
f885f1ea IY |
139 | if (smm_set && smm_arg && env == first_cpu) |
140 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
a5954d5c FB |
141 | } |
142 | ||
143 | ||
3de388f6 FB |
144 | /* IRQ handling */ |
145 | int cpu_get_pic_interrupt(CPUState *env) | |
146 | { | |
147 | int intno; | |
148 | ||
3de388f6 FB |
149 | intno = apic_get_interrupt(env); |
150 | if (intno >= 0) { | |
151 | /* set irq request if a PIC irq is still pending */ | |
152 | /* XXX: improve that */ | |
5fafdf24 | 153 | pic_update_irq(isa_pic); |
3de388f6 FB |
154 | return intno; |
155 | } | |
3de388f6 | 156 | /* read the irq from the PIC */ |
0e21e12b TS |
157 | if (!apic_accept_pic_intr(env)) |
158 | return -1; | |
159 | ||
3de388f6 FB |
160 | intno = pic_read_irq(isa_pic); |
161 | return intno; | |
162 | } | |
163 | ||
d537cf6c | 164 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 165 | { |
a5b38b51 AJ |
166 | CPUState *env = first_cpu; |
167 | ||
d5529471 AJ |
168 | if (env->apic_state) { |
169 | while (env) { | |
170 | if (apic_accept_pic_intr(env)) | |
1a7de94a | 171 | apic_deliver_pic_intr(env, level); |
d5529471 AJ |
172 | env = env->next_cpu; |
173 | } | |
174 | } else { | |
b614106a AJ |
175 | if (level) |
176 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
177 | else | |
178 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 179 | } |
3de388f6 FB |
180 | } |
181 | ||
b0a21b53 FB |
182 | /* PC cmos mappings */ |
183 | ||
80cabfad FB |
184 | #define REG_EQUIPMENT_BYTE 0x14 |
185 | ||
777428f2 FB |
186 | static int cmos_get_fd_drive_type(int fd0) |
187 | { | |
188 | int val; | |
189 | ||
190 | switch (fd0) { | |
191 | case 0: | |
192 | /* 1.44 Mb 3"5 drive */ | |
193 | val = 4; | |
194 | break; | |
195 | case 1: | |
196 | /* 2.88 Mb 3"5 drive */ | |
197 | val = 5; | |
198 | break; | |
199 | case 2: | |
200 | /* 1.2 Mb 5"5 drive */ | |
201 | val = 2; | |
202 | break; | |
203 | default: | |
204 | val = 0; | |
205 | break; | |
206 | } | |
207 | return val; | |
208 | } | |
209 | ||
5fafdf24 | 210 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
ba6c2377 FB |
211 | { |
212 | RTCState *s = rtc_state; | |
213 | int cylinders, heads, sectors; | |
214 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
215 | rtc_set_memory(s, type_ofs, 47); | |
216 | rtc_set_memory(s, info_ofs, cylinders); | |
217 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
218 | rtc_set_memory(s, info_ofs + 2, heads); | |
219 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
220 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
221 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
222 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
223 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
224 | rtc_set_memory(s, info_ofs + 8, sectors); | |
225 | } | |
226 | ||
6ac0e82d AZ |
227 | /* convert boot_device letter to something recognizable by the bios */ |
228 | static int boot_device2nibble(char boot_device) | |
229 | { | |
230 | switch(boot_device) { | |
231 | case 'a': | |
232 | case 'b': | |
233 | return 0x01; /* floppy boot */ | |
234 | case 'c': | |
235 | return 0x02; /* hard drive boot */ | |
236 | case 'd': | |
237 | return 0x03; /* CD-ROM boot */ | |
238 | case 'n': | |
239 | return 0x04; /* Network boot */ | |
240 | } | |
241 | return 0; | |
242 | } | |
243 | ||
d9346e81 | 244 | static int set_boot_dev(RTCState *s, const char *boot_device, int fd_bootchk) |
0ecdffbb AJ |
245 | { |
246 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
247 | int nbds, bds[3] = { 0, }; |
248 | int i; | |
249 | ||
250 | nbds = strlen(boot_device); | |
251 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 252 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
253 | return(1); |
254 | } | |
255 | for (i = 0; i < nbds; i++) { | |
256 | bds[i] = boot_device2nibble(boot_device[i]); | |
257 | if (bds[i] == 0) { | |
1ecda02b MA |
258 | error_report("Invalid boot device for PC: '%c'", |
259 | boot_device[i]); | |
0ecdffbb AJ |
260 | return(1); |
261 | } | |
262 | } | |
263 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 264 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
265 | return(0); |
266 | } | |
267 | ||
d9346e81 MA |
268 | static int pc_boot_set(void *opaque, const char *boot_device) |
269 | { | |
270 | return set_boot_dev(opaque, boot_device, 0); | |
271 | } | |
272 | ||
ba6c2377 | 273 | /* hd_table must contain 4 block drivers */ |
c227f099 | 274 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
01b9e8c1 IY |
275 | const char *boot_device, DriveInfo **hd_table, |
276 | FDCtrl *floppy_controller) | |
80cabfad | 277 | { |
b0a21b53 | 278 | RTCState *s = rtc_state; |
80cabfad | 279 | int val; |
b41a2cd1 | 280 | int fd0, fd1, nb; |
ba6c2377 | 281 | int i; |
b0a21b53 | 282 | |
b0a21b53 | 283 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
284 | |
285 | /* memory size */ | |
333190eb FB |
286 | val = 640; /* base memory in K */ |
287 | rtc_set_memory(s, 0x15, val); | |
288 | rtc_set_memory(s, 0x16, val >> 8); | |
289 | ||
80cabfad FB |
290 | val = (ram_size / 1024) - 1024; |
291 | if (val > 65535) | |
292 | val = 65535; | |
b0a21b53 FB |
293 | rtc_set_memory(s, 0x17, val); |
294 | rtc_set_memory(s, 0x18, val >> 8); | |
295 | rtc_set_memory(s, 0x30, val); | |
296 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 297 | |
00f82b8a AJ |
298 | if (above_4g_mem_size) { |
299 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
300 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
301 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
302 | } | |
303 | ||
9da98861 FB |
304 | if (ram_size > (16 * 1024 * 1024)) |
305 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
306 | else | |
307 | val = 0; | |
80cabfad FB |
308 | if (val > 65535) |
309 | val = 65535; | |
b0a21b53 FB |
310 | rtc_set_memory(s, 0x34, val); |
311 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 312 | |
298e01b6 AJ |
313 | /* set the number of CPU */ |
314 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
315 | ||
6ac0e82d | 316 | /* set boot devices, and disable floppy signature check if requested */ |
d9346e81 | 317 | if (set_boot_dev(s, boot_device, fd_bootchk)) { |
28c5af54 JM |
318 | exit(1); |
319 | } | |
80cabfad | 320 | |
b41a2cd1 FB |
321 | /* floppy type */ |
322 | ||
baca51fa FB |
323 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); |
324 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
80cabfad | 325 | |
777428f2 | 326 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); |
b0a21b53 | 327 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 328 | |
b0a21b53 | 329 | val = 0; |
b41a2cd1 | 330 | nb = 0; |
80cabfad FB |
331 | if (fd0 < 3) |
332 | nb++; | |
333 | if (fd1 < 3) | |
334 | nb++; | |
335 | switch (nb) { | |
336 | case 0: | |
337 | break; | |
338 | case 1: | |
b0a21b53 | 339 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
340 | break; |
341 | case 2: | |
b0a21b53 | 342 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
343 | break; |
344 | } | |
b0a21b53 FB |
345 | val |= 0x02; /* FPU is there */ |
346 | val |= 0x04; /* PS/2 mouse installed */ | |
347 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
348 | ||
ba6c2377 FB |
349 | /* hard drives */ |
350 | ||
351 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
352 | if (hd_table[0]) | |
f455e98c | 353 | cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv); |
5fafdf24 | 354 | if (hd_table[1]) |
f455e98c | 355 | cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv); |
ba6c2377 FB |
356 | |
357 | val = 0; | |
40b6ecc6 | 358 | for (i = 0; i < 4; i++) { |
ba6c2377 | 359 | if (hd_table[i]) { |
46d4767d FB |
360 | int cylinders, heads, sectors, translation; |
361 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
362 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
363 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
364 | geometry can be different if a translation is done. */ | |
f455e98c | 365 | translation = bdrv_get_translation_hint(hd_table[i]->bdrv); |
46d4767d | 366 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { |
f455e98c | 367 | bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, §ors); |
46d4767d FB |
368 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
369 | /* No translation. */ | |
370 | translation = 0; | |
371 | } else { | |
372 | /* LBA translation. */ | |
373 | translation = 1; | |
374 | } | |
40b6ecc6 | 375 | } else { |
46d4767d | 376 | translation--; |
ba6c2377 | 377 | } |
ba6c2377 FB |
378 | val |= translation << (i * 2); |
379 | } | |
40b6ecc6 | 380 | } |
ba6c2377 | 381 | rtc_set_memory(s, 0x39, val); |
80cabfad FB |
382 | } |
383 | ||
59b8ad81 FB |
384 | void ioport_set_a20(int enable) |
385 | { | |
386 | /* XXX: send to all CPUs ? */ | |
387 | cpu_x86_set_a20(first_cpu, enable); | |
388 | } | |
389 | ||
390 | int ioport_get_a20(void) | |
391 | { | |
392 | return ((first_cpu->a20_mask >> 20) & 1); | |
393 | } | |
394 | ||
e1a23744 FB |
395 | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
396 | { | |
59b8ad81 | 397 | ioport_set_a20((val >> 1) & 1); |
e1a23744 FB |
398 | /* XXX: bit 0 is fast reset */ |
399 | } | |
400 | ||
401 | static uint32_t ioport92_read(void *opaque, uint32_t addr) | |
402 | { | |
59b8ad81 | 403 | return ioport_get_a20() << 1; |
e1a23744 FB |
404 | } |
405 | ||
80cabfad FB |
406 | /***********************************************************/ |
407 | /* Bochs BIOS debug ports */ | |
408 | ||
9596ebb7 | 409 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 410 | { |
a2f659ee FB |
411 | static const char shutdown_str[8] = "Shutdown"; |
412 | static int shutdown_index = 0; | |
3b46e624 | 413 | |
80cabfad FB |
414 | switch(addr) { |
415 | /* Bochs BIOS messages */ | |
416 | case 0x400: | |
417 | case 0x401: | |
418 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
419 | exit(1); | |
420 | case 0x402: | |
421 | case 0x403: | |
422 | #ifdef DEBUG_BIOS | |
423 | fprintf(stderr, "%c", val); | |
424 | #endif | |
425 | break; | |
a2f659ee FB |
426 | case 0x8900: |
427 | /* same as Bochs power off */ | |
428 | if (val == shutdown_str[shutdown_index]) { | |
429 | shutdown_index++; | |
430 | if (shutdown_index == 8) { | |
431 | shutdown_index = 0; | |
432 | qemu_system_shutdown_request(); | |
433 | } | |
434 | } else { | |
435 | shutdown_index = 0; | |
436 | } | |
437 | break; | |
80cabfad FB |
438 | |
439 | /* LGPL'ed VGA BIOS messages */ | |
440 | case 0x501: | |
441 | case 0x502: | |
442 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
443 | exit(1); | |
444 | case 0x500: | |
445 | case 0x503: | |
446 | #ifdef DEBUG_BIOS | |
447 | fprintf(stderr, "%c", val); | |
448 | #endif | |
449 | break; | |
450 | } | |
451 | } | |
452 | ||
4c5b10b7 JS |
453 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
454 | { | |
455 | int index = e820_table.count; | |
456 | struct e820_entry *entry; | |
457 | ||
458 | if (index >= E820_NR_ENTRIES) | |
459 | return -EBUSY; | |
460 | entry = &e820_table.entry[index]; | |
461 | ||
462 | entry->address = address; | |
463 | entry->length = length; | |
464 | entry->type = type; | |
465 | ||
466 | e820_table.count++; | |
467 | return e820_table.count; | |
468 | } | |
469 | ||
bf483392 | 470 | static void *bochs_bios_init(void) |
80cabfad | 471 | { |
3cce6243 | 472 | void *fw_cfg; |
b6f6e3d3 AL |
473 | uint8_t *smbios_table; |
474 | size_t smbios_len; | |
11c2fd3e AL |
475 | uint64_t *numa_fw_cfg; |
476 | int i, j; | |
3cce6243 | 477 | |
b41a2cd1 FB |
478 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
479 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
480 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
481 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 482 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
483 | |
484 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
485 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
486 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
487 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
3cce6243 BS |
488 | |
489 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
bf483392 | 490 | |
3cce6243 | 491 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 492 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80deece2 BS |
493 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
494 | acpi_tables_len); | |
6b35e7bf | 495 | fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1); |
b6f6e3d3 AL |
496 | |
497 | smbios_table = smbios_get_table(&smbios_len); | |
498 | if (smbios_table) | |
499 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
500 | smbios_table, smbios_len); | |
4c5b10b7 JS |
501 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
502 | sizeof(struct e820_table)); | |
11c2fd3e AL |
503 | |
504 | /* allocate memory for the NUMA channel: one (64bit) word for the number | |
505 | * of nodes, one word for each VCPU->node and one word for each node to | |
506 | * hold the amount of memory. | |
507 | */ | |
508 | numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); | |
509 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); | |
510 | for (i = 0; i < smp_cpus; i++) { | |
511 | for (j = 0; j < nb_numa_nodes; j++) { | |
512 | if (node_cpumask[j] & (1 << i)) { | |
513 | numa_fw_cfg[i + 1] = cpu_to_le64(j); | |
514 | break; | |
515 | } | |
516 | } | |
517 | } | |
518 | for (i = 0; i < nb_numa_nodes; i++) { | |
519 | numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]); | |
520 | } | |
521 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
522 | (1 + smp_cpus + nb_numa_nodes) * 8); | |
bf483392 AG |
523 | |
524 | return fw_cfg; | |
80cabfad FB |
525 | } |
526 | ||
642a4f96 TS |
527 | static long get_file_size(FILE *f) |
528 | { | |
529 | long where, size; | |
530 | ||
531 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
532 | ||
533 | where = ftell(f); | |
534 | fseek(f, 0, SEEK_END); | |
535 | size = ftell(f); | |
536 | fseek(f, where, SEEK_SET); | |
537 | ||
538 | return size; | |
539 | } | |
540 | ||
f16408df | 541 | static void load_linux(void *fw_cfg, |
4fc9af53 | 542 | const char *kernel_filename, |
642a4f96 | 543 | const char *initrd_filename, |
e6ade764 | 544 | const char *kernel_cmdline, |
45a50b16 | 545 | target_phys_addr_t max_ram_size) |
642a4f96 TS |
546 | { |
547 | uint16_t protocol; | |
5cea8590 | 548 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 549 | uint32_t initrd_max; |
57a46d05 | 550 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
c227f099 | 551 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 552 | FILE *f; |
bf4e5d92 | 553 | char *vmode; |
642a4f96 TS |
554 | |
555 | /* Align to 16 bytes as a paranoia measure */ | |
556 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
557 | ||
558 | /* load the kernel header */ | |
559 | f = fopen(kernel_filename, "rb"); | |
560 | if (!f || !(kernel_size = get_file_size(f)) || | |
f16408df AG |
561 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
562 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
850810d0 JF |
563 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", |
564 | kernel_filename, strerror(errno)); | |
642a4f96 TS |
565 | exit(1); |
566 | } | |
567 | ||
568 | /* kernel protocol version */ | |
bc4edd79 | 569 | #if 0 |
642a4f96 | 570 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 571 | #endif |
642a4f96 TS |
572 | if (ldl_p(header+0x202) == 0x53726448) |
573 | protocol = lduw_p(header+0x206); | |
f16408df AG |
574 | else { |
575 | /* This looks like a multiboot kernel. If it is, let's stop | |
576 | treating it like a Linux kernel. */ | |
52001445 AL |
577 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
578 | kernel_cmdline, kernel_size, header)) | |
82663ee2 | 579 | return; |
642a4f96 | 580 | protocol = 0; |
f16408df | 581 | } |
642a4f96 TS |
582 | |
583 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
584 | /* Low kernel */ | |
a37af289 BS |
585 | real_addr = 0x90000; |
586 | cmdline_addr = 0x9a000 - cmdline_size; | |
587 | prot_addr = 0x10000; | |
642a4f96 TS |
588 | } else if (protocol < 0x202) { |
589 | /* High but ancient kernel */ | |
a37af289 BS |
590 | real_addr = 0x90000; |
591 | cmdline_addr = 0x9a000 - cmdline_size; | |
592 | prot_addr = 0x100000; | |
642a4f96 TS |
593 | } else { |
594 | /* High and recent kernel */ | |
a37af289 BS |
595 | real_addr = 0x10000; |
596 | cmdline_addr = 0x20000; | |
597 | prot_addr = 0x100000; | |
642a4f96 TS |
598 | } |
599 | ||
bc4edd79 | 600 | #if 0 |
642a4f96 | 601 | fprintf(stderr, |
526ccb7a AZ |
602 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
603 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
604 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
605 | real_addr, |
606 | cmdline_addr, | |
607 | prot_addr); | |
bc4edd79 | 608 | #endif |
642a4f96 TS |
609 | |
610 | /* highest address for loading the initrd */ | |
611 | if (protocol >= 0x203) | |
612 | initrd_max = ldl_p(header+0x22c); | |
613 | else | |
614 | initrd_max = 0x37ffffff; | |
615 | ||
e6ade764 GC |
616 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) |
617 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
642a4f96 | 618 | |
57a46d05 AG |
619 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
620 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
621 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, | |
622 | (uint8_t*)strdup(kernel_cmdline), | |
623 | strlen(kernel_cmdline)+1); | |
642a4f96 TS |
624 | |
625 | if (protocol >= 0x202) { | |
a37af289 | 626 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
627 | } else { |
628 | stw_p(header+0x20, 0xA33F); | |
629 | stw_p(header+0x22, cmdline_addr-real_addr); | |
630 | } | |
631 | ||
bf4e5d92 PT |
632 | /* handle vga= parameter */ |
633 | vmode = strstr(kernel_cmdline, "vga="); | |
634 | if (vmode) { | |
635 | unsigned int video_mode; | |
636 | /* skip "vga=" */ | |
637 | vmode += 4; | |
638 | if (!strncmp(vmode, "normal", 6)) { | |
639 | video_mode = 0xffff; | |
640 | } else if (!strncmp(vmode, "ext", 3)) { | |
641 | video_mode = 0xfffe; | |
642 | } else if (!strncmp(vmode, "ask", 3)) { | |
643 | video_mode = 0xfffd; | |
644 | } else { | |
645 | video_mode = strtol(vmode, NULL, 0); | |
646 | } | |
647 | stw_p(header+0x1fa, video_mode); | |
648 | } | |
649 | ||
642a4f96 TS |
650 | /* loader type */ |
651 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
652 | If this code is substantially changed, you may want to consider | |
653 | incrementing the revision. */ | |
654 | if (protocol >= 0x200) | |
655 | header[0x210] = 0xB0; | |
656 | ||
657 | /* heap */ | |
658 | if (protocol >= 0x201) { | |
659 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
660 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
661 | } | |
662 | ||
663 | /* load initrd */ | |
664 | if (initrd_filename) { | |
665 | if (protocol < 0x200) { | |
666 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
667 | exit(1); | |
668 | } | |
669 | ||
45a50b16 | 670 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 MK |
671 | if (initrd_size < 0) { |
672 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
673 | initrd_filename); | |
674 | exit(1); | |
675 | } | |
676 | ||
45a50b16 | 677 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 AG |
678 | |
679 | initrd_data = qemu_malloc(initrd_size); | |
680 | load_image(initrd_filename, initrd_data); | |
681 | ||
682 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
683 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
684 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 685 | |
a37af289 | 686 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
687 | stl_p(header+0x21c, initrd_size); |
688 | } | |
689 | ||
45a50b16 | 690 | /* load kernel and setup */ |
642a4f96 TS |
691 | setup_size = header[0x1f1]; |
692 | if (setup_size == 0) | |
693 | setup_size = 4; | |
642a4f96 | 694 | setup_size = (setup_size+1)*512; |
45a50b16 | 695 | kernel_size -= setup_size; |
642a4f96 | 696 | |
45a50b16 GH |
697 | setup = qemu_malloc(setup_size); |
698 | kernel = qemu_malloc(kernel_size); | |
699 | fseek(f, 0, SEEK_SET); | |
5a41ecc5 KS |
700 | if (fread(setup, 1, setup_size, f) != setup_size) { |
701 | fprintf(stderr, "fread() failed\n"); | |
702 | exit(1); | |
703 | } | |
704 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
705 | fprintf(stderr, "fread() failed\n"); | |
706 | exit(1); | |
707 | } | |
642a4f96 | 708 | fclose(f); |
45a50b16 | 709 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
710 | |
711 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
712 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
713 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
714 | ||
715 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
716 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
717 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
718 | ||
719 | option_rom[nb_option_roms] = "linuxboot.bin"; | |
720 | nb_option_roms++; | |
642a4f96 TS |
721 | } |
722 | ||
b41a2cd1 FB |
723 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
724 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
725 | static const int ide_irq[2] = { 14, 15 }; | |
726 | ||
727 | #define NE2000_NB_MAX 6 | |
728 | ||
675d6f82 BS |
729 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
730 | 0x280, 0x380 }; | |
731 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 732 | |
675d6f82 BS |
733 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
734 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
6508fe59 | 735 | |
6a36d84e | 736 | #ifdef HAS_AUDIO |
d537cf6c | 737 | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
6a36d84e FB |
738 | { |
739 | struct soundhw *c; | |
6a36d84e | 740 | |
3a8bae3e | 741 | for (c = soundhw; c->name; ++c) { |
742 | if (c->enabled) { | |
743 | if (c->isa) { | |
744 | c->init.init_isa(pic); | |
745 | } else { | |
746 | if (pci_bus) { | |
747 | c->init.init_pci(pci_bus); | |
6a36d84e FB |
748 | } |
749 | } | |
750 | } | |
751 | } | |
752 | } | |
753 | #endif | |
754 | ||
3a38d437 | 755 | static void pc_init_ne2k_isa(NICInfo *nd) |
a41b2ff2 PB |
756 | { |
757 | static int nb_ne2k = 0; | |
758 | ||
759 | if (nb_ne2k == NE2000_NB_MAX) | |
760 | return; | |
3a38d437 | 761 | isa_ne2000_init(ne2000_io[nb_ne2k], |
9453c5bc | 762 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
763 | nb_ne2k++; |
764 | } | |
765 | ||
678e12cc GN |
766 | int cpu_is_bsp(CPUState *env) |
767 | { | |
6cb2996c JK |
768 | /* We hard-wire the BSP to the first CPU. */ |
769 | return env->cpu_index == 0; | |
678e12cc GN |
770 | } |
771 | ||
53b67b30 BS |
772 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
773 | BIOS will read it and start S3 resume at POST Entry */ | |
774 | static void cmos_set_s3_resume(void *opaque, int irq, int level) | |
775 | { | |
776 | RTCState *s = opaque; | |
777 | ||
778 | if (level) { | |
779 | rtc_set_memory(s, 0xF, 0xFE); | |
780 | } | |
781 | } | |
782 | ||
783 | static void acpi_smi_interrupt(void *opaque, int irq, int level) | |
784 | { | |
785 | CPUState *s = opaque; | |
786 | ||
787 | if (level) { | |
788 | cpu_interrupt(s, CPU_INTERRUPT_SMI); | |
789 | } | |
790 | } | |
791 | ||
3a31f36a JK |
792 | static CPUState *pc_new_cpu(const char *cpu_model) |
793 | { | |
794 | CPUState *env; | |
795 | ||
796 | env = cpu_init(cpu_model); | |
797 | if (!env) { | |
798 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
799 | exit(1); | |
800 | } | |
801 | if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { | |
802 | env->cpuid_apic_id = env->cpu_index; | |
803 | /* APIC reset callback resets cpu */ | |
804 | apic_init(env); | |
805 | } else { | |
806 | qemu_register_reset((QEMUResetHandler*)cpu_reset, env); | |
807 | } | |
808 | return env; | |
809 | } | |
810 | ||
80cabfad | 811 | /* PC hardware initialisation */ |
c227f099 | 812 | static void pc_init1(ram_addr_t ram_size, |
3023f332 | 813 | const char *boot_device, |
e8b2a1c6 MM |
814 | const char *kernel_filename, |
815 | const char *kernel_cmdline, | |
3dbbdc25 | 816 | const char *initrd_filename, |
e8b2a1c6 | 817 | const char *cpu_model, |
caea79a9 | 818 | int pci_enabled) |
80cabfad | 819 | { |
5cea8590 | 820 | char *filename; |
642a4f96 | 821 | int ret, linux_boot, i; |
c227f099 AL |
822 | ram_addr_t ram_addr, bios_offset, option_rom_offset; |
823 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; | |
45a50b16 | 824 | int bios_size, isa_bios_size; |
46e50e9d | 825 | PCIBus *pci_bus; |
f885f1ea | 826 | PCII440FXState *i440fx_state; |
5c3ff3a7 | 827 | int piix3_devfn = -1; |
d537cf6c | 828 | qemu_irq *cpu_irq; |
1452411b | 829 | qemu_irq *isa_irq; |
d537cf6c | 830 | qemu_irq *i8259; |
53b67b30 BS |
831 | qemu_irq *cmos_s3; |
832 | qemu_irq *smi_irq; | |
1452411b | 833 | IsaIrqState *isa_irq_state; |
f455e98c | 834 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 835 | DriveInfo *fd[MAX_FD]; |
bf483392 | 836 | void *fw_cfg; |
01b9e8c1 | 837 | FDCtrl *floppy_controller; |
57864959 | 838 | PITState *pit; |
d592d303 | 839 | |
00f82b8a AJ |
840 | if (ram_size >= 0xe0000000 ) { |
841 | above_4g_mem_size = ram_size - 0xe0000000; | |
842 | below_4g_mem_size = 0xe0000000; | |
843 | } else { | |
844 | below_4g_mem_size = ram_size; | |
845 | } | |
846 | ||
80cabfad FB |
847 | linux_boot = (kernel_filename != NULL); |
848 | ||
59b8ad81 | 849 | /* init CPUs */ |
a049de61 FB |
850 | if (cpu_model == NULL) { |
851 | #ifdef TARGET_X86_64 | |
852 | cpu_model = "qemu64"; | |
853 | #else | |
854 | cpu_model = "qemu32"; | |
855 | #endif | |
856 | } | |
3a31f36a JK |
857 | |
858 | for (i = 0; i < smp_cpus; i++) { | |
7f5b7d3e | 859 | pc_new_cpu(cpu_model); |
59b8ad81 FB |
860 | } |
861 | ||
26fb5e48 AJ |
862 | vmport_init(); |
863 | ||
80cabfad | 864 | /* allocate RAM */ |
60e4c631 | 865 | ram_addr = qemu_ram_alloc(below_4g_mem_size); |
82b36dc3 | 866 | cpu_register_physical_memory(0, 0xa0000, ram_addr); |
82b36dc3 AL |
867 | cpu_register_physical_memory(0x100000, |
868 | below_4g_mem_size - 0x100000, | |
60e4c631 | 869 | ram_addr + 0x100000); |
00f82b8a AJ |
870 | |
871 | /* above 4giga memory allocation */ | |
872 | if (above_4g_mem_size > 0) { | |
8a637d44 PB |
873 | #if TARGET_PHYS_ADDR_BITS == 32 |
874 | hw_error("To much RAM for 32-bit physical address"); | |
875 | #else | |
82b36dc3 AL |
876 | ram_addr = qemu_ram_alloc(above_4g_mem_size); |
877 | cpu_register_physical_memory(0x100000000ULL, | |
526ccb7a | 878 | above_4g_mem_size, |
82b36dc3 | 879 | ram_addr); |
8a637d44 | 880 | #endif |
00f82b8a | 881 | } |
80cabfad | 882 | |
82b36dc3 | 883 | |
970ac5a3 | 884 | /* BIOS load */ |
1192dad8 JM |
885 | if (bios_name == NULL) |
886 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
887 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
888 | if (filename) { | |
889 | bios_size = get_image_size(filename); | |
890 | } else { | |
891 | bios_size = -1; | |
892 | } | |
5fafdf24 | 893 | if (bios_size <= 0 || |
970ac5a3 | 894 | (bios_size % 65536) != 0) { |
7587cf44 FB |
895 | goto bios_error; |
896 | } | |
970ac5a3 | 897 | bios_offset = qemu_ram_alloc(bios_size); |
51edd4e6 GH |
898 | ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size)); |
899 | if (ret != 0) { | |
7587cf44 | 900 | bios_error: |
5cea8590 | 901 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); |
80cabfad FB |
902 | exit(1); |
903 | } | |
5cea8590 PB |
904 | if (filename) { |
905 | qemu_free(filename); | |
906 | } | |
7587cf44 FB |
907 | /* map the last 128KB of the BIOS in ISA space */ |
908 | isa_bios_size = bios_size; | |
909 | if (isa_bios_size > (128 * 1024)) | |
910 | isa_bios_size = 128 * 1024; | |
5fafdf24 TS |
911 | cpu_register_physical_memory(0x100000 - isa_bios_size, |
912 | isa_bios_size, | |
7587cf44 | 913 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
9ae02555 | 914 | |
45a50b16 GH |
915 | option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE); |
916 | cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); | |
f753ff16 | 917 | |
1d108d97 AG |
918 | /* map all the bios at the top of memory */ |
919 | cpu_register_physical_memory((uint32_t)(-bios_size), | |
920 | bios_size, bios_offset | IO_MEM_ROM); | |
921 | ||
bf483392 | 922 | fw_cfg = bochs_bios_init(); |
8832cb80 | 923 | rom_set_fw(fw_cfg); |
1d108d97 | 924 | |
f753ff16 | 925 | if (linux_boot) { |
45a50b16 | 926 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
f753ff16 PB |
927 | } |
928 | ||
929 | for (i = 0; i < nb_option_roms; i++) { | |
45a50b16 | 930 | rom_add_option(option_rom[i]); |
406c8df3 GC |
931 | } |
932 | ||
a5b38b51 | 933 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
d537cf6c | 934 | i8259 = i8259_init(cpu_irq[0]); |
1452411b AK |
935 | isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state)); |
936 | isa_irq_state->i8259 = i8259; | |
b8d6f539 IY |
937 | if (pci_enabled) { |
938 | isa_irq_state->ioapic = ioapic_init(); | |
939 | } | |
1632dc6a | 940 | isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24); |
d537cf6c | 941 | |
69b91039 | 942 | if (pci_enabled) { |
ec5f92ce | 943 | pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size); |
46e50e9d FB |
944 | } else { |
945 | pci_bus = NULL; | |
2091ba23 | 946 | isa_bus_new(NULL); |
69b91039 | 947 | } |
2091ba23 | 948 | isa_bus_irqs(isa_irq); |
69b91039 | 949 | |
3a38d437 JS |
950 | ferr_irq = isa_reserve_irq(13); |
951 | ||
80cabfad | 952 | /* init basic PC hardware */ |
b41a2cd1 | 953 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
80cabfad | 954 | |
f929aad6 FB |
955 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
956 | ||
1f04275e FB |
957 | if (cirrus_vga_enabled) { |
958 | if (pci_enabled) { | |
fbe1b595 | 959 | pci_cirrus_vga_init(pci_bus); |
1f04275e | 960 | } else { |
fbe1b595 | 961 | isa_cirrus_vga_init(); |
1f04275e | 962 | } |
d34cab9f TS |
963 | } else if (vmsvga_enabled) { |
964 | if (pci_enabled) | |
fbe1b595 | 965 | pci_vmsvga_init(pci_bus); |
d34cab9f TS |
966 | else |
967 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
c2b3b41a | 968 | } else if (std_vga_enabled) { |
89b6b508 | 969 | if (pci_enabled) { |
fbe1b595 | 970 | pci_vga_init(pci_bus, 0, 0); |
89b6b508 | 971 | } else { |
fbe1b595 | 972 | isa_vga_init(); |
89b6b508 | 973 | } |
1f04275e | 974 | } |
80cabfad | 975 | |
32e0c826 | 976 | rtc_state = rtc_init(2000); |
80cabfad | 977 | |
3b4366de BS |
978 | qemu_register_boot_set(pc_boot_set, rtc_state); |
979 | ||
e1a23744 FB |
980 | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
981 | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); | |
982 | ||
3a38d437 | 983 | pit = pit_init(0x40, isa_reserve_irq(0)); |
fd06c375 | 984 | pcspk_init(pit); |
16b29ae1 | 985 | if (!no_hpet) { |
1452411b | 986 | hpet_init(isa_irq); |
16b29ae1 | 987 | } |
b41a2cd1 | 988 | |
8d11df9e FB |
989 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
990 | if (serial_hds[i]) { | |
ac0be998 | 991 | serial_isa_init(i, serial_hds[i]); |
8d11df9e FB |
992 | } |
993 | } | |
b41a2cd1 | 994 | |
6508fe59 FB |
995 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
996 | if (parallel_hds[i]) { | |
021f0674 | 997 | parallel_init(i, parallel_hds[i]); |
6508fe59 FB |
998 | } |
999 | } | |
1000 | ||
a41b2ff2 | 1001 | for(i = 0; i < nb_nics; i++) { |
cb457d76 AL |
1002 | NICInfo *nd = &nd_table[i]; |
1003 | ||
1004 | if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) | |
3a38d437 | 1005 | pc_init_ne2k_isa(nd); |
cb457d76 | 1006 | else |
07caea31 | 1007 | pci_nic_init_nofail(nd, "e1000", NULL); |
a41b2ff2 | 1008 | } |
b41a2cd1 | 1009 | |
e4bcb14c TS |
1010 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
1011 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
1012 | exit(1); | |
1013 | } | |
1014 | ||
1015 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
f455e98c | 1016 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
e4bcb14c TS |
1017 | } |
1018 | ||
a41b2ff2 | 1019 | if (pci_enabled) { |
ae027ad3 | 1020 | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1); |
a41b2ff2 | 1021 | } else { |
e4bcb14c | 1022 | for(i = 0; i < MAX_IDE_BUS; i++) { |
dea21e97 | 1023 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c | 1024 | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); |
69b91039 | 1025 | } |
b41a2cd1 | 1026 | } |
69b91039 | 1027 | |
7f5b7d3e | 1028 | isa_create_simple("i8042"); |
7c29d0c0 | 1029 | DMA_init(0); |
6a36d84e | 1030 | #ifdef HAS_AUDIO |
1452411b | 1031 | audio_init(pci_enabled ? pci_bus : NULL, isa_irq); |
fb065187 | 1032 | #endif |
80cabfad | 1033 | |
e4bcb14c | 1034 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 1035 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 1036 | } |
86c86157 | 1037 | floppy_controller = fdctrl_init_isa(fd); |
b41a2cd1 | 1038 | |
01b9e8c1 IY |
1039 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd, |
1040 | floppy_controller); | |
69b91039 | 1041 | |
bb36d470 | 1042 | if (pci_enabled && usb_enabled) { |
afcc3cdf | 1043 | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); |
bb36d470 FB |
1044 | } |
1045 | ||
6515b203 | 1046 | if (pci_enabled && acpi_enabled) { |
3fffc223 | 1047 | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
0ff596d0 PB |
1048 | i2c_bus *smbus; |
1049 | ||
53b67b30 BS |
1050 | cmos_s3 = qemu_allocate_irqs(cmos_set_s3_resume, rtc_state, 1); |
1051 | smi_irq = qemu_allocate_irqs(acpi_smi_interrupt, first_cpu, 1); | |
0ff596d0 | 1052 | /* TODO: Populate SPD eeprom data. */ |
3a38d437 | 1053 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, |
53b67b30 BS |
1054 | isa_reserve_irq(9), *cmos_s3, *smi_irq, |
1055 | kvm_enabled()); | |
3fffc223 | 1056 | for (i = 0; i < 8; i++) { |
1ea96673 | 1057 | DeviceState *eeprom; |
02e2da45 | 1058 | eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); |
5b7f5327 | 1059 | qdev_prop_set_uint8(eeprom, "address", 0x50 + i); |
ee6847d1 | 1060 | qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); |
e23a1b33 | 1061 | qdev_init_nofail(eeprom); |
3fffc223 | 1062 | } |
3f84865a | 1063 | piix4_acpi_system_hot_add_init(pci_bus); |
6515b203 | 1064 | } |
3b46e624 | 1065 | |
a5954d5c FB |
1066 | if (i440fx_state) { |
1067 | i440fx_init_memory_mappings(i440fx_state); | |
1068 | } | |
e4bcb14c | 1069 | |
7d8406be | 1070 | if (pci_enabled) { |
e4bcb14c | 1071 | int max_bus; |
9be5dafe | 1072 | int bus; |
96d30e48 | 1073 | |
e4bcb14c | 1074 | max_bus = drive_get_max_bus(IF_SCSI); |
e4bcb14c | 1075 | for (bus = 0; bus <= max_bus; bus++) { |
9be5dafe | 1076 | pci_create_simple(pci_bus, -1, "lsi53c895a"); |
e4bcb14c | 1077 | } |
7d8406be | 1078 | } |
80cabfad | 1079 | } |
b5ff2d6e | 1080 | |
c227f099 | 1081 | static void pc_init_pci(ram_addr_t ram_size, |
3023f332 | 1082 | const char *boot_device, |
5fafdf24 | 1083 | const char *kernel_filename, |
3dbbdc25 | 1084 | const char *kernel_cmdline, |
94fc95cd JM |
1085 | const char *initrd_filename, |
1086 | const char *cpu_model) | |
3dbbdc25 | 1087 | { |
fbe1b595 | 1088 | pc_init1(ram_size, boot_device, |
3dbbdc25 | 1089 | kernel_filename, kernel_cmdline, |
caea79a9 | 1090 | initrd_filename, cpu_model, 1); |
3dbbdc25 FB |
1091 | } |
1092 | ||
c227f099 | 1093 | static void pc_init_isa(ram_addr_t ram_size, |
3023f332 | 1094 | const char *boot_device, |
5fafdf24 | 1095 | const char *kernel_filename, |
3dbbdc25 | 1096 | const char *kernel_cmdline, |
94fc95cd JM |
1097 | const char *initrd_filename, |
1098 | const char *cpu_model) | |
3dbbdc25 | 1099 | { |
679a37af GH |
1100 | if (cpu_model == NULL) |
1101 | cpu_model = "486"; | |
fbe1b595 | 1102 | pc_init1(ram_size, boot_device, |
3dbbdc25 | 1103 | kernel_filename, kernel_cmdline, |
caea79a9 | 1104 | initrd_filename, cpu_model, 0); |
3dbbdc25 FB |
1105 | } |
1106 | ||
f80f9ec9 | 1107 | static QEMUMachine pc_machine = { |
d76fa62d | 1108 | .name = "pc-0.13", |
95747581 | 1109 | .alias = "pc", |
a245f2e7 AJ |
1110 | .desc = "Standard PC", |
1111 | .init = pc_init_pci, | |
b2097003 | 1112 | .max_cpus = 255, |
0c257437 | 1113 | .is_default = 1, |
3dbbdc25 FB |
1114 | }; |
1115 | ||
d76fa62d AS |
1116 | static QEMUMachine pc_machine_v0_12 = { |
1117 | .name = "pc-0.12", | |
1118 | .desc = "Standard PC", | |
1119 | .init = pc_init_pci, | |
1120 | .max_cpus = 255, | |
8bfbde6d AS |
1121 | .compat_props = (GlobalProperty[]) { |
1122 | { | |
1123 | .driver = "virtio-serial-pci", | |
1124 | .property = "max_nr_ports", | |
1125 | .value = stringify(1), | |
1126 | },{ | |
1127 | .driver = "virtio-serial-pci", | |
1128 | .property = "vectors", | |
1129 | .value = stringify(0), | |
1130 | }, | |
1131 | { /* end of list */ } | |
1132 | } | |
d76fa62d AS |
1133 | }; |
1134 | ||
2cae6f5e GH |
1135 | static QEMUMachine pc_machine_v0_11 = { |
1136 | .name = "pc-0.11", | |
1137 | .desc = "Standard PC, qemu 0.11", | |
1138 | .init = pc_init_pci, | |
1139 | .max_cpus = 255, | |
1140 | .compat_props = (GlobalProperty[]) { | |
1141 | { | |
1142 | .driver = "virtio-blk-pci", | |
1143 | .property = "vectors", | |
1144 | .value = stringify(0), | |
8bfbde6d AS |
1145 | },{ |
1146 | .driver = "virtio-serial-pci", | |
1147 | .property = "max_nr_ports", | |
1148 | .value = stringify(1), | |
1149 | },{ | |
1150 | .driver = "virtio-serial-pci", | |
1151 | .property = "vectors", | |
1152 | .value = stringify(0), | |
374ef704 GH |
1153 | },{ |
1154 | .driver = "ide-drive", | |
1155 | .property = "ver", | |
1156 | .value = "0.11", | |
1157 | },{ | |
1158 | .driver = "scsi-disk", | |
1159 | .property = "ver", | |
1160 | .value = "0.11", | |
20a86364 GH |
1161 | },{ |
1162 | .driver = "PCI", | |
1163 | .property = "rombar", | |
1164 | .value = stringify(0), | |
2cae6f5e GH |
1165 | }, |
1166 | { /* end of list */ } | |
1167 | } | |
1168 | }; | |
1169 | ||
96cc1810 GH |
1170 | static QEMUMachine pc_machine_v0_10 = { |
1171 | .name = "pc-0.10", | |
1172 | .desc = "Standard PC, qemu 0.10", | |
1173 | .init = pc_init_pci, | |
1174 | .max_cpus = 255, | |
458fb679 | 1175 | .compat_props = (GlobalProperty[]) { |
ab73ff29 GH |
1176 | { |
1177 | .driver = "virtio-blk-pci", | |
1178 | .property = "class", | |
1179 | .value = stringify(PCI_CLASS_STORAGE_OTHER), | |
d6beee99 | 1180 | },{ |
98b19252 | 1181 | .driver = "virtio-serial-pci", |
d6beee99 GH |
1182 | .property = "class", |
1183 | .value = stringify(PCI_CLASS_DISPLAY_OTHER), | |
8bfbde6d AS |
1184 | },{ |
1185 | .driver = "virtio-serial-pci", | |
1186 | .property = "max_nr_ports", | |
1187 | .value = stringify(1), | |
1188 | },{ | |
1189 | .driver = "virtio-serial-pci", | |
1190 | .property = "vectors", | |
1191 | .value = stringify(0), | |
a1e0fea5 GH |
1192 | },{ |
1193 | .driver = "virtio-net-pci", | |
1194 | .property = "vectors", | |
1195 | .value = stringify(0), | |
177539e0 GH |
1196 | },{ |
1197 | .driver = "virtio-blk-pci", | |
1198 | .property = "vectors", | |
1199 | .value = stringify(0), | |
374ef704 GH |
1200 | },{ |
1201 | .driver = "ide-drive", | |
1202 | .property = "ver", | |
1203 | .value = "0.10", | |
1204 | },{ | |
1205 | .driver = "scsi-disk", | |
1206 | .property = "ver", | |
1207 | .value = "0.10", | |
20a86364 GH |
1208 | },{ |
1209 | .driver = "PCI", | |
1210 | .property = "rombar", | |
1211 | .value = stringify(0), | |
ab73ff29 | 1212 | }, |
96cc1810 GH |
1213 | { /* end of list */ } |
1214 | }, | |
1215 | }; | |
1216 | ||
f80f9ec9 | 1217 | static QEMUMachine isapc_machine = { |
a245f2e7 AJ |
1218 | .name = "isapc", |
1219 | .desc = "ISA-only PC", | |
1220 | .init = pc_init_isa, | |
b2097003 | 1221 | .max_cpus = 1, |
b5ff2d6e | 1222 | }; |
f80f9ec9 AL |
1223 | |
1224 | static void pc_machine_init(void) | |
1225 | { | |
1226 | qemu_register_machine(&pc_machine); | |
d76fa62d | 1227 | qemu_register_machine(&pc_machine_v0_12); |
2cae6f5e | 1228 | qemu_register_machine(&pc_machine_v0_11); |
96cc1810 | 1229 | qemu_register_machine(&pc_machine_v0_10); |
f80f9ec9 AL |
1230 | qemu_register_machine(&isapc_machine); |
1231 | } | |
1232 | ||
1233 | machine_init(pc_machine_init); |