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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
aa28b9bf | 26 | #include "apic.h" |
87ecb68b | 27 | #include "fdc.h" |
c0897e0c | 28 | #include "ide.h" |
87ecb68b | 29 | #include "pci.h" |
18e08a55 | 30 | #include "vmware_vga.h" |
376253ec | 31 | #include "monitor.h" |
3cce6243 | 32 | #include "fw_cfg.h" |
16b29ae1 | 33 | #include "hpet_emul.h" |
b6f6e3d3 | 34 | #include "smbios.h" |
ca20cf32 BS |
35 | #include "loader.h" |
36 | #include "elf.h" | |
52001445 | 37 | #include "multiboot.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
b1277b03 | 39 | #include "i8254.h" |
302fe51b | 40 | #include "pcspk.h" |
60ba3cc2 | 41 | #include "msi.h" |
822557eb | 42 | #include "sysbus.h" |
666daa68 | 43 | #include "sysemu.h" |
9b5b76d4 | 44 | #include "kvm.h" |
2446333c | 45 | #include "blockdev.h" |
a19cbfb3 | 46 | #include "ui/qemu-spice.h" |
00cb2a99 | 47 | #include "memory.h" |
be20f9e9 | 48 | #include "exec-memory.h" |
80cabfad | 49 | |
b41a2cd1 FB |
50 | /* output Bochs bios info messages */ |
51 | //#define DEBUG_BIOS | |
52 | ||
471fd342 BS |
53 | /* debug PC/ISA interrupts */ |
54 | //#define DEBUG_IRQ | |
55 | ||
56 | #ifdef DEBUG_IRQ | |
57 | #define DPRINTF(fmt, ...) \ | |
58 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
59 | #else | |
60 | #define DPRINTF(fmt, ...) | |
61 | #endif | |
62 | ||
80cabfad | 63 | #define BIOS_FILENAME "bios.bin" |
80cabfad | 64 | |
7fb4fdcf AZ |
65 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
66 | ||
a80274c3 PB |
67 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
68 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 69 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 70 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 71 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 72 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 73 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 74 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 75 | |
92a16d7a BS |
76 | #define MSI_ADDR_BASE 0xfee00000 |
77 | ||
4c5b10b7 JS |
78 | #define E820_NR_ENTRIES 16 |
79 | ||
80 | struct e820_entry { | |
81 | uint64_t address; | |
82 | uint64_t length; | |
83 | uint32_t type; | |
541dc0d4 | 84 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
85 | |
86 | struct e820_table { | |
87 | uint32_t count; | |
88 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 89 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
90 | |
91 | static struct e820_table e820_table; | |
dd703b99 | 92 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 93 | |
b881fbe9 | 94 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 95 | { |
b881fbe9 | 96 | GSIState *s = opaque; |
1452411b | 97 | |
b881fbe9 JK |
98 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
99 | if (n < ISA_NUM_IRQS) { | |
100 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 101 | } |
b881fbe9 | 102 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 103 | } |
1452411b | 104 | |
b41a2cd1 | 105 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
106 | { |
107 | } | |
108 | ||
f929aad6 | 109 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 110 | static qemu_irq ferr_irq; |
8e78eb28 IY |
111 | |
112 | void pc_register_ferr_irq(qemu_irq irq) | |
113 | { | |
114 | ferr_irq = irq; | |
115 | } | |
116 | ||
f929aad6 FB |
117 | /* XXX: add IGNNE support */ |
118 | void cpu_set_ferr(CPUX86State *s) | |
119 | { | |
d537cf6c | 120 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
121 | } |
122 | ||
123 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
124 | { | |
d537cf6c | 125 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
126 | } |
127 | ||
28ab0e2e | 128 | /* TSC handling */ |
28ab0e2e FB |
129 | uint64_t cpu_get_tsc(CPUX86State *env) |
130 | { | |
4a1418e0 | 131 | return cpu_get_ticks(); |
28ab0e2e FB |
132 | } |
133 | ||
a5954d5c | 134 | /* SMM support */ |
f885f1ea IY |
135 | |
136 | static cpu_set_smm_t smm_set; | |
137 | static void *smm_arg; | |
138 | ||
139 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
140 | { | |
141 | assert(smm_set == NULL); | |
142 | assert(smm_arg == NULL); | |
143 | smm_set = callback; | |
144 | smm_arg = arg; | |
145 | } | |
146 | ||
a5954d5c FB |
147 | void cpu_smm_update(CPUState *env) |
148 | { | |
f885f1ea IY |
149 | if (smm_set && smm_arg && env == first_cpu) |
150 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
a5954d5c FB |
151 | } |
152 | ||
153 | ||
3de388f6 FB |
154 | /* IRQ handling */ |
155 | int cpu_get_pic_interrupt(CPUState *env) | |
156 | { | |
157 | int intno; | |
158 | ||
cf6d64bf | 159 | intno = apic_get_interrupt(env->apic_state); |
3de388f6 | 160 | if (intno >= 0) { |
3de388f6 FB |
161 | return intno; |
162 | } | |
3de388f6 | 163 | /* read the irq from the PIC */ |
cf6d64bf | 164 | if (!apic_accept_pic_intr(env->apic_state)) { |
0e21e12b | 165 | return -1; |
cf6d64bf | 166 | } |
0e21e12b | 167 | |
3de388f6 FB |
168 | intno = pic_read_irq(isa_pic); |
169 | return intno; | |
170 | } | |
171 | ||
d537cf6c | 172 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 173 | { |
a5b38b51 AJ |
174 | CPUState *env = first_cpu; |
175 | ||
471fd342 | 176 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
d5529471 AJ |
177 | if (env->apic_state) { |
178 | while (env) { | |
cf6d64bf BS |
179 | if (apic_accept_pic_intr(env->apic_state)) { |
180 | apic_deliver_pic_intr(env->apic_state, level); | |
181 | } | |
d5529471 AJ |
182 | env = env->next_cpu; |
183 | } | |
184 | } else { | |
b614106a AJ |
185 | if (level) |
186 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
187 | else | |
188 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 189 | } |
3de388f6 FB |
190 | } |
191 | ||
b0a21b53 FB |
192 | /* PC cmos mappings */ |
193 | ||
80cabfad FB |
194 | #define REG_EQUIPMENT_BYTE 0x14 |
195 | ||
d288c7ba | 196 | static int cmos_get_fd_drive_type(FDriveType fd0) |
777428f2 FB |
197 | { |
198 | int val; | |
199 | ||
200 | switch (fd0) { | |
d288c7ba | 201 | case FDRIVE_DRV_144: |
777428f2 FB |
202 | /* 1.44 Mb 3"5 drive */ |
203 | val = 4; | |
204 | break; | |
d288c7ba | 205 | case FDRIVE_DRV_288: |
777428f2 FB |
206 | /* 2.88 Mb 3"5 drive */ |
207 | val = 5; | |
208 | break; | |
d288c7ba | 209 | case FDRIVE_DRV_120: |
777428f2 FB |
210 | /* 1.2 Mb 5"5 drive */ |
211 | val = 2; | |
212 | break; | |
d288c7ba | 213 | case FDRIVE_DRV_NONE: |
777428f2 FB |
214 | default: |
215 | val = 0; | |
216 | break; | |
217 | } | |
218 | return val; | |
219 | } | |
220 | ||
ec2654fb | 221 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd, |
1d914fa0 | 222 | ISADevice *s) |
ba6c2377 | 223 | { |
ba6c2377 FB |
224 | int cylinders, heads, sectors; |
225 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
226 | rtc_set_memory(s, type_ofs, 47); | |
227 | rtc_set_memory(s, info_ofs, cylinders); | |
228 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
229 | rtc_set_memory(s, info_ofs + 2, heads); | |
230 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
231 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
232 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
233 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
234 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
235 | rtc_set_memory(s, info_ofs + 8, sectors); | |
236 | } | |
237 | ||
6ac0e82d AZ |
238 | /* convert boot_device letter to something recognizable by the bios */ |
239 | static int boot_device2nibble(char boot_device) | |
240 | { | |
241 | switch(boot_device) { | |
242 | case 'a': | |
243 | case 'b': | |
244 | return 0x01; /* floppy boot */ | |
245 | case 'c': | |
246 | return 0x02; /* hard drive boot */ | |
247 | case 'd': | |
248 | return 0x03; /* CD-ROM boot */ | |
249 | case 'n': | |
250 | return 0x04; /* Network boot */ | |
251 | } | |
252 | return 0; | |
253 | } | |
254 | ||
1d914fa0 | 255 | static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) |
0ecdffbb AJ |
256 | { |
257 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
258 | int nbds, bds[3] = { 0, }; |
259 | int i; | |
260 | ||
261 | nbds = strlen(boot_device); | |
262 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 263 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
264 | return(1); |
265 | } | |
266 | for (i = 0; i < nbds; i++) { | |
267 | bds[i] = boot_device2nibble(boot_device[i]); | |
268 | if (bds[i] == 0) { | |
1ecda02b MA |
269 | error_report("Invalid boot device for PC: '%c'", |
270 | boot_device[i]); | |
0ecdffbb AJ |
271 | return(1); |
272 | } | |
273 | } | |
274 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 275 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
276 | return(0); |
277 | } | |
278 | ||
d9346e81 MA |
279 | static int pc_boot_set(void *opaque, const char *boot_device) |
280 | { | |
281 | return set_boot_dev(opaque, boot_device, 0); | |
282 | } | |
283 | ||
c0897e0c MA |
284 | typedef struct pc_cmos_init_late_arg { |
285 | ISADevice *rtc_state; | |
286 | BusState *idebus0, *idebus1; | |
287 | } pc_cmos_init_late_arg; | |
288 | ||
289 | static void pc_cmos_init_late(void *opaque) | |
290 | { | |
291 | pc_cmos_init_late_arg *arg = opaque; | |
292 | ISADevice *s = arg->rtc_state; | |
293 | int val; | |
294 | BlockDriverState *hd_table[4]; | |
295 | int i; | |
296 | ||
297 | ide_get_bs(hd_table, arg->idebus0); | |
298 | ide_get_bs(hd_table + 2, arg->idebus1); | |
299 | ||
300 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
301 | if (hd_table[0]) | |
302 | cmos_init_hd(0x19, 0x1b, hd_table[0], s); | |
303 | if (hd_table[1]) | |
304 | cmos_init_hd(0x1a, 0x24, hd_table[1], s); | |
305 | ||
306 | val = 0; | |
307 | for (i = 0; i < 4; i++) { | |
308 | if (hd_table[i]) { | |
309 | int cylinders, heads, sectors, translation; | |
310 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
311 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
312 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
313 | geometry can be different if a translation is done. */ | |
314 | translation = bdrv_get_translation_hint(hd_table[i]); | |
315 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { | |
316 | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); | |
317 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { | |
318 | /* No translation. */ | |
319 | translation = 0; | |
320 | } else { | |
321 | /* LBA translation. */ | |
322 | translation = 1; | |
323 | } | |
324 | } else { | |
325 | translation--; | |
326 | } | |
327 | val |= translation << (i * 2); | |
328 | } | |
329 | } | |
330 | rtc_set_memory(s, 0x39, val); | |
331 | ||
332 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
333 | } | |
334 | ||
845773ab | 335 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
c0897e0c | 336 | const char *boot_device, |
34d4260e | 337 | ISADevice *floppy, BusState *idebus0, BusState *idebus1, |
63ffb564 | 338 | ISADevice *s) |
80cabfad | 339 | { |
63ffb564 | 340 | int val, nb, nb_heads, max_track, last_sect, i; |
980bda8b | 341 | FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; |
34d4260e | 342 | BlockDriverState *fd[MAX_FD]; |
c0897e0c | 343 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 344 | |
b0a21b53 | 345 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
346 | |
347 | /* memory size */ | |
333190eb FB |
348 | val = 640; /* base memory in K */ |
349 | rtc_set_memory(s, 0x15, val); | |
350 | rtc_set_memory(s, 0x16, val >> 8); | |
351 | ||
80cabfad FB |
352 | val = (ram_size / 1024) - 1024; |
353 | if (val > 65535) | |
354 | val = 65535; | |
b0a21b53 FB |
355 | rtc_set_memory(s, 0x17, val); |
356 | rtc_set_memory(s, 0x18, val >> 8); | |
357 | rtc_set_memory(s, 0x30, val); | |
358 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 359 | |
00f82b8a AJ |
360 | if (above_4g_mem_size) { |
361 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
362 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
363 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
364 | } | |
365 | ||
9da98861 FB |
366 | if (ram_size > (16 * 1024 * 1024)) |
367 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
368 | else | |
369 | val = 0; | |
80cabfad FB |
370 | if (val > 65535) |
371 | val = 65535; | |
b0a21b53 FB |
372 | rtc_set_memory(s, 0x34, val); |
373 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 374 | |
298e01b6 AJ |
375 | /* set the number of CPU */ |
376 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
377 | ||
6ac0e82d | 378 | /* set boot devices, and disable floppy signature check if requested */ |
d9346e81 | 379 | if (set_boot_dev(s, boot_device, fd_bootchk)) { |
28c5af54 JM |
380 | exit(1); |
381 | } | |
80cabfad | 382 | |
b41a2cd1 | 383 | /* floppy type */ |
34d4260e KW |
384 | if (floppy) { |
385 | fdc_get_bs(fd, floppy); | |
386 | for (i = 0; i < 2; i++) { | |
387 | if (fd[i] && bdrv_is_inserted(fd[i])) { | |
388 | bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track, | |
389 | &last_sect, FDRIVE_DRV_NONE, | |
390 | &fd_type[i]); | |
34d4260e | 391 | } |
63ffb564 BS |
392 | } |
393 | } | |
394 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
395 | cmos_get_fd_drive_type(fd_type[1]); | |
b0a21b53 | 396 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 397 | |
b0a21b53 | 398 | val = 0; |
b41a2cd1 | 399 | nb = 0; |
63ffb564 | 400 | if (fd_type[0] < FDRIVE_DRV_NONE) { |
80cabfad | 401 | nb++; |
d288c7ba | 402 | } |
63ffb564 | 403 | if (fd_type[1] < FDRIVE_DRV_NONE) { |
80cabfad | 404 | nb++; |
d288c7ba | 405 | } |
80cabfad FB |
406 | switch (nb) { |
407 | case 0: | |
408 | break; | |
409 | case 1: | |
b0a21b53 | 410 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
411 | break; |
412 | case 2: | |
b0a21b53 | 413 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
414 | break; |
415 | } | |
b0a21b53 FB |
416 | val |= 0x02; /* FPU is there */ |
417 | val |= 0x04; /* PS/2 mouse installed */ | |
418 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
419 | ||
ba6c2377 | 420 | /* hard drives */ |
c0897e0c MA |
421 | arg.rtc_state = s; |
422 | arg.idebus0 = idebus0; | |
423 | arg.idebus1 = idebus1; | |
424 | qemu_register_reset(pc_cmos_init_late, &arg); | |
80cabfad FB |
425 | } |
426 | ||
4b78a802 BS |
427 | /* port 92 stuff: could be split off */ |
428 | typedef struct Port92State { | |
429 | ISADevice dev; | |
23af670e | 430 | MemoryRegion io; |
4b78a802 BS |
431 | uint8_t outport; |
432 | qemu_irq *a20_out; | |
433 | } Port92State; | |
434 | ||
435 | static void port92_write(void *opaque, uint32_t addr, uint32_t val) | |
436 | { | |
437 | Port92State *s = opaque; | |
438 | ||
439 | DPRINTF("port92: write 0x%02x\n", val); | |
440 | s->outport = val; | |
441 | qemu_set_irq(*s->a20_out, (val >> 1) & 1); | |
442 | if (val & 1) { | |
443 | qemu_system_reset_request(); | |
444 | } | |
445 | } | |
446 | ||
447 | static uint32_t port92_read(void *opaque, uint32_t addr) | |
448 | { | |
449 | Port92State *s = opaque; | |
450 | uint32_t ret; | |
451 | ||
452 | ret = s->outport; | |
453 | DPRINTF("port92: read 0x%02x\n", ret); | |
454 | return ret; | |
455 | } | |
456 | ||
457 | static void port92_init(ISADevice *dev, qemu_irq *a20_out) | |
458 | { | |
459 | Port92State *s = DO_UPCAST(Port92State, dev, dev); | |
460 | ||
461 | s->a20_out = a20_out; | |
462 | } | |
463 | ||
464 | static const VMStateDescription vmstate_port92_isa = { | |
465 | .name = "port92", | |
466 | .version_id = 1, | |
467 | .minimum_version_id = 1, | |
468 | .minimum_version_id_old = 1, | |
469 | .fields = (VMStateField []) { | |
470 | VMSTATE_UINT8(outport, Port92State), | |
471 | VMSTATE_END_OF_LIST() | |
472 | } | |
473 | }; | |
474 | ||
475 | static void port92_reset(DeviceState *d) | |
476 | { | |
477 | Port92State *s = container_of(d, Port92State, dev.qdev); | |
478 | ||
479 | s->outport &= ~1; | |
480 | } | |
481 | ||
23af670e RH |
482 | static const MemoryRegionPortio port92_portio[] = { |
483 | { 0, 1, 1, .read = port92_read, .write = port92_write }, | |
484 | PORTIO_END_OF_LIST(), | |
485 | }; | |
486 | ||
487 | static const MemoryRegionOps port92_ops = { | |
488 | .old_portio = port92_portio | |
489 | }; | |
490 | ||
4b78a802 BS |
491 | static int port92_initfn(ISADevice *dev) |
492 | { | |
493 | Port92State *s = DO_UPCAST(Port92State, dev, dev); | |
494 | ||
23af670e RH |
495 | memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); |
496 | isa_register_ioport(dev, &s->io, 0x92); | |
497 | ||
4b78a802 BS |
498 | s->outport = 0; |
499 | return 0; | |
500 | } | |
501 | ||
8f04ee08 AL |
502 | static void port92_class_initfn(ObjectClass *klass, void *data) |
503 | { | |
39bffca2 | 504 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
505 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
506 | ic->init = port92_initfn; | |
39bffca2 AL |
507 | dc->no_user = 1; |
508 | dc->reset = port92_reset; | |
509 | dc->vmsd = &vmstate_port92_isa; | |
8f04ee08 AL |
510 | } |
511 | ||
39bffca2 AL |
512 | static TypeInfo port92_info = { |
513 | .name = "port92", | |
514 | .parent = TYPE_ISA_DEVICE, | |
515 | .instance_size = sizeof(Port92State), | |
516 | .class_init = port92_class_initfn, | |
4b78a802 BS |
517 | }; |
518 | ||
83f7d43a | 519 | static void port92_register_types(void) |
4b78a802 | 520 | { |
39bffca2 | 521 | type_register_static(&port92_info); |
4b78a802 | 522 | } |
83f7d43a AF |
523 | |
524 | type_init(port92_register_types) | |
4b78a802 | 525 | |
956a3e6b | 526 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 527 | { |
956a3e6b | 528 | CPUState *cpu = opaque; |
e1a23744 | 529 | |
956a3e6b | 530 | /* XXX: send to all CPUs ? */ |
4b78a802 | 531 | /* XXX: add logic to handle multiple A20 line sources */ |
956a3e6b | 532 | cpu_x86_set_a20(cpu, level); |
e1a23744 FB |
533 | } |
534 | ||
80cabfad FB |
535 | /***********************************************************/ |
536 | /* Bochs BIOS debug ports */ | |
537 | ||
9596ebb7 | 538 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 539 | { |
a2f659ee FB |
540 | static const char shutdown_str[8] = "Shutdown"; |
541 | static int shutdown_index = 0; | |
3b46e624 | 542 | |
80cabfad FB |
543 | switch(addr) { |
544 | /* Bochs BIOS messages */ | |
545 | case 0x400: | |
546 | case 0x401: | |
0550f9c1 BK |
547 | /* used to be panic, now unused */ |
548 | break; | |
80cabfad FB |
549 | case 0x402: |
550 | case 0x403: | |
551 | #ifdef DEBUG_BIOS | |
552 | fprintf(stderr, "%c", val); | |
553 | #endif | |
554 | break; | |
a2f659ee FB |
555 | case 0x8900: |
556 | /* same as Bochs power off */ | |
557 | if (val == shutdown_str[shutdown_index]) { | |
558 | shutdown_index++; | |
559 | if (shutdown_index == 8) { | |
560 | shutdown_index = 0; | |
561 | qemu_system_shutdown_request(); | |
562 | } | |
563 | } else { | |
564 | shutdown_index = 0; | |
565 | } | |
566 | break; | |
80cabfad FB |
567 | |
568 | /* LGPL'ed VGA BIOS messages */ | |
569 | case 0x501: | |
570 | case 0x502: | |
4333979e | 571 | exit((val << 1) | 1); |
80cabfad FB |
572 | case 0x500: |
573 | case 0x503: | |
574 | #ifdef DEBUG_BIOS | |
575 | fprintf(stderr, "%c", val); | |
576 | #endif | |
577 | break; | |
578 | } | |
579 | } | |
580 | ||
4c5b10b7 JS |
581 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
582 | { | |
8ca209ad | 583 | int index = le32_to_cpu(e820_table.count); |
4c5b10b7 JS |
584 | struct e820_entry *entry; |
585 | ||
586 | if (index >= E820_NR_ENTRIES) | |
587 | return -EBUSY; | |
8ca209ad | 588 | entry = &e820_table.entry[index++]; |
4c5b10b7 | 589 | |
8ca209ad AW |
590 | entry->address = cpu_to_le64(address); |
591 | entry->length = cpu_to_le64(length); | |
592 | entry->type = cpu_to_le32(type); | |
4c5b10b7 | 593 | |
8ca209ad AW |
594 | e820_table.count = cpu_to_le32(index); |
595 | return index; | |
4c5b10b7 JS |
596 | } |
597 | ||
bf483392 | 598 | static void *bochs_bios_init(void) |
80cabfad | 599 | { |
3cce6243 | 600 | void *fw_cfg; |
b6f6e3d3 AL |
601 | uint8_t *smbios_table; |
602 | size_t smbios_len; | |
11c2fd3e AL |
603 | uint64_t *numa_fw_cfg; |
604 | int i, j; | |
3cce6243 | 605 | |
b41a2cd1 FB |
606 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
607 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
608 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
609 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 610 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 | 611 | |
4333979e | 612 | register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
613 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
614 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
615 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
616 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
3cce6243 BS |
617 | |
618 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
bf483392 | 619 | |
3cce6243 | 620 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 621 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80deece2 BS |
622 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
623 | acpi_tables_len); | |
9b5b76d4 | 624 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 AL |
625 | |
626 | smbios_table = smbios_get_table(&smbios_len); | |
627 | if (smbios_table) | |
628 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
629 | smbios_table, smbios_len); | |
4c5b10b7 JS |
630 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
631 | sizeof(struct e820_table)); | |
11c2fd3e | 632 | |
40ac17cd GN |
633 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, |
634 | sizeof(struct hpet_fw_config)); | |
11c2fd3e AL |
635 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
636 | * of nodes, one word for each VCPU->node and one word for each node to | |
637 | * hold the amount of memory. | |
638 | */ | |
991dfefd | 639 | numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8); |
11c2fd3e | 640 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 641 | for (i = 0; i < max_cpus; i++) { |
11c2fd3e AL |
642 | for (j = 0; j < nb_numa_nodes; j++) { |
643 | if (node_cpumask[j] & (1 << i)) { | |
644 | numa_fw_cfg[i + 1] = cpu_to_le64(j); | |
645 | break; | |
646 | } | |
647 | } | |
648 | } | |
649 | for (i = 0; i < nb_numa_nodes; i++) { | |
991dfefd | 650 | numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]); |
11c2fd3e AL |
651 | } |
652 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
991dfefd | 653 | (1 + max_cpus + nb_numa_nodes) * 8); |
bf483392 AG |
654 | |
655 | return fw_cfg; | |
80cabfad FB |
656 | } |
657 | ||
642a4f96 TS |
658 | static long get_file_size(FILE *f) |
659 | { | |
660 | long where, size; | |
661 | ||
662 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
663 | ||
664 | where = ftell(f); | |
665 | fseek(f, 0, SEEK_END); | |
666 | size = ftell(f); | |
667 | fseek(f, where, SEEK_SET); | |
668 | ||
669 | return size; | |
670 | } | |
671 | ||
f16408df | 672 | static void load_linux(void *fw_cfg, |
4fc9af53 | 673 | const char *kernel_filename, |
642a4f96 | 674 | const char *initrd_filename, |
e6ade764 | 675 | const char *kernel_cmdline, |
45a50b16 | 676 | target_phys_addr_t max_ram_size) |
642a4f96 TS |
677 | { |
678 | uint16_t protocol; | |
5cea8590 | 679 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 680 | uint32_t initrd_max; |
57a46d05 | 681 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
c227f099 | 682 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 683 | FILE *f; |
bf4e5d92 | 684 | char *vmode; |
642a4f96 TS |
685 | |
686 | /* Align to 16 bytes as a paranoia measure */ | |
687 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
688 | ||
689 | /* load the kernel header */ | |
690 | f = fopen(kernel_filename, "rb"); | |
691 | if (!f || !(kernel_size = get_file_size(f)) || | |
f16408df AG |
692 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
693 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
850810d0 JF |
694 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", |
695 | kernel_filename, strerror(errno)); | |
642a4f96 TS |
696 | exit(1); |
697 | } | |
698 | ||
699 | /* kernel protocol version */ | |
bc4edd79 | 700 | #if 0 |
642a4f96 | 701 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 702 | #endif |
642a4f96 TS |
703 | if (ldl_p(header+0x202) == 0x53726448) |
704 | protocol = lduw_p(header+0x206); | |
f16408df AG |
705 | else { |
706 | /* This looks like a multiboot kernel. If it is, let's stop | |
707 | treating it like a Linux kernel. */ | |
52001445 AL |
708 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
709 | kernel_cmdline, kernel_size, header)) | |
82663ee2 | 710 | return; |
642a4f96 | 711 | protocol = 0; |
f16408df | 712 | } |
642a4f96 TS |
713 | |
714 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
715 | /* Low kernel */ | |
a37af289 BS |
716 | real_addr = 0x90000; |
717 | cmdline_addr = 0x9a000 - cmdline_size; | |
718 | prot_addr = 0x10000; | |
642a4f96 TS |
719 | } else if (protocol < 0x202) { |
720 | /* High but ancient kernel */ | |
a37af289 BS |
721 | real_addr = 0x90000; |
722 | cmdline_addr = 0x9a000 - cmdline_size; | |
723 | prot_addr = 0x100000; | |
642a4f96 TS |
724 | } else { |
725 | /* High and recent kernel */ | |
a37af289 BS |
726 | real_addr = 0x10000; |
727 | cmdline_addr = 0x20000; | |
728 | prot_addr = 0x100000; | |
642a4f96 TS |
729 | } |
730 | ||
bc4edd79 | 731 | #if 0 |
642a4f96 | 732 | fprintf(stderr, |
526ccb7a AZ |
733 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
734 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
735 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
736 | real_addr, |
737 | cmdline_addr, | |
738 | prot_addr); | |
bc4edd79 | 739 | #endif |
642a4f96 TS |
740 | |
741 | /* highest address for loading the initrd */ | |
742 | if (protocol >= 0x203) | |
743 | initrd_max = ldl_p(header+0x22c); | |
744 | else | |
745 | initrd_max = 0x37ffffff; | |
746 | ||
e6ade764 GC |
747 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) |
748 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
642a4f96 | 749 | |
57a46d05 AG |
750 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
751 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
752 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, | |
753 | (uint8_t*)strdup(kernel_cmdline), | |
754 | strlen(kernel_cmdline)+1); | |
642a4f96 TS |
755 | |
756 | if (protocol >= 0x202) { | |
a37af289 | 757 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
758 | } else { |
759 | stw_p(header+0x20, 0xA33F); | |
760 | stw_p(header+0x22, cmdline_addr-real_addr); | |
761 | } | |
762 | ||
bf4e5d92 PT |
763 | /* handle vga= parameter */ |
764 | vmode = strstr(kernel_cmdline, "vga="); | |
765 | if (vmode) { | |
766 | unsigned int video_mode; | |
767 | /* skip "vga=" */ | |
768 | vmode += 4; | |
769 | if (!strncmp(vmode, "normal", 6)) { | |
770 | video_mode = 0xffff; | |
771 | } else if (!strncmp(vmode, "ext", 3)) { | |
772 | video_mode = 0xfffe; | |
773 | } else if (!strncmp(vmode, "ask", 3)) { | |
774 | video_mode = 0xfffd; | |
775 | } else { | |
776 | video_mode = strtol(vmode, NULL, 0); | |
777 | } | |
778 | stw_p(header+0x1fa, video_mode); | |
779 | } | |
780 | ||
642a4f96 TS |
781 | /* loader type */ |
782 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
783 | If this code is substantially changed, you may want to consider | |
784 | incrementing the revision. */ | |
785 | if (protocol >= 0x200) | |
786 | header[0x210] = 0xB0; | |
787 | ||
788 | /* heap */ | |
789 | if (protocol >= 0x201) { | |
790 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
791 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
792 | } | |
793 | ||
794 | /* load initrd */ | |
795 | if (initrd_filename) { | |
796 | if (protocol < 0x200) { | |
797 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
798 | exit(1); | |
799 | } | |
800 | ||
45a50b16 | 801 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 MK |
802 | if (initrd_size < 0) { |
803 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
804 | initrd_filename); | |
805 | exit(1); | |
806 | } | |
807 | ||
45a50b16 | 808 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 809 | |
7267c094 | 810 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
811 | load_image(initrd_filename, initrd_data); |
812 | ||
813 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
814 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
815 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 816 | |
a37af289 | 817 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
818 | stl_p(header+0x21c, initrd_size); |
819 | } | |
820 | ||
45a50b16 | 821 | /* load kernel and setup */ |
642a4f96 TS |
822 | setup_size = header[0x1f1]; |
823 | if (setup_size == 0) | |
824 | setup_size = 4; | |
642a4f96 | 825 | setup_size = (setup_size+1)*512; |
45a50b16 | 826 | kernel_size -= setup_size; |
642a4f96 | 827 | |
7267c094 AL |
828 | setup = g_malloc(setup_size); |
829 | kernel = g_malloc(kernel_size); | |
45a50b16 | 830 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
831 | if (fread(setup, 1, setup_size, f) != setup_size) { |
832 | fprintf(stderr, "fread() failed\n"); | |
833 | exit(1); | |
834 | } | |
835 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
836 | fprintf(stderr, "fread() failed\n"); | |
837 | exit(1); | |
838 | } | |
642a4f96 | 839 | fclose(f); |
45a50b16 | 840 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
841 | |
842 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
843 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
844 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
845 | ||
846 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
847 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
848 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
849 | ||
2e55e842 GN |
850 | option_rom[nb_option_roms].name = "linuxboot.bin"; |
851 | option_rom[nb_option_roms].bootindex = 0; | |
57a46d05 | 852 | nb_option_roms++; |
642a4f96 TS |
853 | } |
854 | ||
b41a2cd1 FB |
855 | #define NE2000_NB_MAX 6 |
856 | ||
675d6f82 BS |
857 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
858 | 0x280, 0x380 }; | |
859 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 860 | |
675d6f82 BS |
861 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
862 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
6508fe59 | 863 | |
48a18b3c | 864 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
865 | { |
866 | static int nb_ne2k = 0; | |
867 | ||
868 | if (nb_ne2k == NE2000_NB_MAX) | |
869 | return; | |
48a18b3c | 870 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 871 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
872 | nb_ne2k++; |
873 | } | |
874 | ||
678e12cc GN |
875 | int cpu_is_bsp(CPUState *env) |
876 | { | |
6cb2996c JK |
877 | /* We hard-wire the BSP to the first CPU. */ |
878 | return env->cpu_index == 0; | |
678e12cc GN |
879 | } |
880 | ||
92a16d7a | 881 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 BS |
882 | { |
883 | if (cpu_single_env) { | |
884 | return cpu_single_env->apic_state; | |
885 | } else { | |
886 | return NULL; | |
887 | } | |
888 | } | |
889 | ||
92a16d7a BS |
890 | static DeviceState *apic_init(void *env, uint8_t apic_id) |
891 | { | |
892 | DeviceState *dev; | |
92a16d7a BS |
893 | static int apic_mapped; |
894 | ||
3d4b2649 | 895 | if (kvm_irqchip_in_kernel()) { |
680c1c6f JK |
896 | dev = qdev_create(NULL, "kvm-apic"); |
897 | } else { | |
898 | dev = qdev_create(NULL, "apic"); | |
899 | } | |
92a16d7a BS |
900 | qdev_prop_set_uint8(dev, "id", apic_id); |
901 | qdev_prop_set_ptr(dev, "cpu_env", env); | |
902 | qdev_init_nofail(dev); | |
92a16d7a BS |
903 | |
904 | /* XXX: mapping more APICs at the same memory location */ | |
905 | if (apic_mapped == 0) { | |
906 | /* NOTE: the APIC is directly connected to the CPU - it is not | |
907 | on the global memory bus. */ | |
908 | /* XXX: what if the base changes? */ | |
680c1c6f | 909 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE); |
92a16d7a BS |
910 | apic_mapped = 1; |
911 | } | |
912 | ||
680c1c6f | 913 | /* KVM does not support MSI yet. */ |
3d4b2649 | 914 | if (!kvm_irqchip_in_kernel()) { |
680c1c6f JK |
915 | msi_supported = true; |
916 | } | |
92a16d7a BS |
917 | |
918 | return dev; | |
919 | } | |
920 | ||
53b67b30 BS |
921 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
922 | BIOS will read it and start S3 resume at POST Entry */ | |
845773ab | 923 | void pc_cmos_set_s3_resume(void *opaque, int irq, int level) |
53b67b30 | 924 | { |
1d914fa0 | 925 | ISADevice *s = opaque; |
53b67b30 BS |
926 | |
927 | if (level) { | |
928 | rtc_set_memory(s, 0xF, 0xFE); | |
929 | } | |
930 | } | |
931 | ||
845773ab | 932 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 BS |
933 | { |
934 | CPUState *s = opaque; | |
935 | ||
936 | if (level) { | |
937 | cpu_interrupt(s, CPU_INTERRUPT_SMI); | |
938 | } | |
939 | } | |
940 | ||
427bd8d6 | 941 | static void pc_cpu_reset(void *opaque) |
0e26b7b8 BS |
942 | { |
943 | CPUState *env = opaque; | |
944 | ||
945 | cpu_reset(env); | |
427bd8d6 | 946 | env->halted = !cpu_is_bsp(env); |
0e26b7b8 BS |
947 | } |
948 | ||
3a31f36a JK |
949 | static CPUState *pc_new_cpu(const char *cpu_model) |
950 | { | |
951 | CPUState *env; | |
952 | ||
953 | env = cpu_init(cpu_model); | |
954 | if (!env) { | |
955 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
956 | exit(1); | |
957 | } | |
958 | if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { | |
0e26b7b8 BS |
959 | env->apic_state = apic_init(env, env->cpuid_apic_id); |
960 | } | |
427bd8d6 JK |
961 | qemu_register_reset(pc_cpu_reset, env); |
962 | pc_cpu_reset(env); | |
3a31f36a JK |
963 | return env; |
964 | } | |
965 | ||
845773ab | 966 | void pc_cpus_init(const char *cpu_model) |
70166477 IY |
967 | { |
968 | int i; | |
969 | ||
970 | /* init CPUs */ | |
971 | if (cpu_model == NULL) { | |
972 | #ifdef TARGET_X86_64 | |
973 | cpu_model = "qemu64"; | |
974 | #else | |
975 | cpu_model = "qemu32"; | |
976 | #endif | |
977 | } | |
978 | ||
979 | for(i = 0; i < smp_cpus; i++) { | |
980 | pc_new_cpu(cpu_model); | |
981 | } | |
982 | } | |
983 | ||
4aa63af1 AK |
984 | void pc_memory_init(MemoryRegion *system_memory, |
985 | const char *kernel_filename, | |
845773ab IY |
986 | const char *kernel_cmdline, |
987 | const char *initrd_filename, | |
e0e7e67b | 988 | ram_addr_t below_4g_mem_size, |
ae0a5466 | 989 | ram_addr_t above_4g_mem_size, |
4463aee6 | 990 | MemoryRegion *rom_memory, |
ae0a5466 | 991 | MemoryRegion **ram_memory) |
80cabfad | 992 | { |
5cea8590 | 993 | char *filename; |
642a4f96 | 994 | int ret, linux_boot, i; |
00cb2a99 AK |
995 | MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr; |
996 | MemoryRegion *ram_below_4g, *ram_above_4g; | |
45a50b16 | 997 | int bios_size, isa_bios_size; |
81a204e4 | 998 | void *fw_cfg; |
d592d303 | 999 | |
80cabfad FB |
1000 | linux_boot = (kernel_filename != NULL); |
1001 | ||
00cb2a99 | 1002 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1003 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1004 | * with older qemus that used qemu_ram_alloc(). |
1005 | */ | |
7267c094 | 1006 | ram = g_malloc(sizeof(*ram)); |
c5705a77 | 1007 | memory_region_init_ram(ram, "pc.ram", |
00cb2a99 | 1008 | below_4g_mem_size + above_4g_mem_size); |
c5705a77 | 1009 | vmstate_register_ram_global(ram); |
ae0a5466 | 1010 | *ram_memory = ram; |
7267c094 | 1011 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
00cb2a99 AK |
1012 | memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, |
1013 | 0, below_4g_mem_size); | |
1014 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
bbe80adf | 1015 | if (above_4g_mem_size > 0) { |
7267c094 | 1016 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
00cb2a99 AK |
1017 | memory_region_init_alias(ram_above_4g, "ram-above-4g", ram, |
1018 | below_4g_mem_size, above_4g_mem_size); | |
1019 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
1020 | ram_above_4g); | |
bbe80adf | 1021 | } |
82b36dc3 | 1022 | |
970ac5a3 | 1023 | /* BIOS load */ |
1192dad8 JM |
1024 | if (bios_name == NULL) |
1025 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
1026 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
1027 | if (filename) { | |
1028 | bios_size = get_image_size(filename); | |
1029 | } else { | |
1030 | bios_size = -1; | |
1031 | } | |
5fafdf24 | 1032 | if (bios_size <= 0 || |
970ac5a3 | 1033 | (bios_size % 65536) != 0) { |
7587cf44 FB |
1034 | goto bios_error; |
1035 | } | |
7267c094 | 1036 | bios = g_malloc(sizeof(*bios)); |
c5705a77 AK |
1037 | memory_region_init_ram(bios, "pc.bios", bios_size); |
1038 | vmstate_register_ram_global(bios); | |
00cb2a99 | 1039 | memory_region_set_readonly(bios, true); |
2e55e842 | 1040 | ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); |
51edd4e6 | 1041 | if (ret != 0) { |
7587cf44 | 1042 | bios_error: |
5cea8590 | 1043 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); |
80cabfad FB |
1044 | exit(1); |
1045 | } | |
5cea8590 | 1046 | if (filename) { |
7267c094 | 1047 | g_free(filename); |
5cea8590 | 1048 | } |
7587cf44 FB |
1049 | /* map the last 128KB of the BIOS in ISA space */ |
1050 | isa_bios_size = bios_size; | |
1051 | if (isa_bios_size > (128 * 1024)) | |
1052 | isa_bios_size = 128 * 1024; | |
7267c094 | 1053 | isa_bios = g_malloc(sizeof(*isa_bios)); |
00cb2a99 AK |
1054 | memory_region_init_alias(isa_bios, "isa-bios", bios, |
1055 | bios_size - isa_bios_size, isa_bios_size); | |
4463aee6 | 1056 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1057 | 0x100000 - isa_bios_size, |
1058 | isa_bios, | |
1059 | 1); | |
1060 | memory_region_set_readonly(isa_bios, true); | |
1061 | ||
7267c094 | 1062 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
c5705a77 AK |
1063 | memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE); |
1064 | vmstate_register_ram_global(option_rom_mr); | |
4463aee6 | 1065 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1066 | PC_ROM_MIN_VGA, |
1067 | option_rom_mr, | |
1068 | 1); | |
f753ff16 | 1069 | |
1d108d97 | 1070 | /* map all the bios at the top of memory */ |
4463aee6 | 1071 | memory_region_add_subregion(rom_memory, |
00cb2a99 AK |
1072 | (uint32_t)(-bios_size), |
1073 | bios); | |
1d108d97 | 1074 | |
bf483392 | 1075 | fw_cfg = bochs_bios_init(); |
8832cb80 | 1076 | rom_set_fw(fw_cfg); |
1d108d97 | 1077 | |
f753ff16 | 1078 | if (linux_boot) { |
81a204e4 | 1079 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
f753ff16 PB |
1080 | } |
1081 | ||
1082 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1083 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1084 | } |
3d53f5c3 IY |
1085 | } |
1086 | ||
845773ab IY |
1087 | qemu_irq *pc_allocate_cpu_irq(void) |
1088 | { | |
1089 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
1090 | } | |
1091 | ||
48a18b3c | 1092 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1093 | { |
ad6d45fa AL |
1094 | DeviceState *dev = NULL; |
1095 | ||
765d7908 IY |
1096 | if (cirrus_vga_enabled) { |
1097 | if (pci_bus) { | |
ad6d45fa | 1098 | dev = pci_cirrus_vga_init(pci_bus); |
765d7908 | 1099 | } else { |
3d402831 | 1100 | dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev; |
765d7908 IY |
1101 | } |
1102 | } else if (vmsvga_enabled) { | |
7ba7e49e | 1103 | if (pci_bus) { |
ad6d45fa | 1104 | dev = pci_vmsvga_init(pci_bus); |
7ba7e49e | 1105 | } else { |
765d7908 | 1106 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); |
7ba7e49e | 1107 | } |
a19cbfb3 GH |
1108 | #ifdef CONFIG_SPICE |
1109 | } else if (qxl_enabled) { | |
ad6d45fa AL |
1110 | if (pci_bus) { |
1111 | dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev; | |
1112 | } else { | |
a19cbfb3 | 1113 | fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__); |
ad6d45fa | 1114 | } |
a19cbfb3 | 1115 | #endif |
765d7908 IY |
1116 | } else if (std_vga_enabled) { |
1117 | if (pci_bus) { | |
ad6d45fa | 1118 | dev = pci_vga_init(pci_bus); |
765d7908 | 1119 | } else { |
48a18b3c | 1120 | dev = isa_vga_init(isa_bus); |
765d7908 IY |
1121 | } |
1122 | } | |
ad6d45fa AL |
1123 | |
1124 | return dev; | |
765d7908 IY |
1125 | } |
1126 | ||
4556bd8b BS |
1127 | static void cpu_request_exit(void *opaque, int irq, int level) |
1128 | { | |
1129 | CPUState *env = cpu_single_env; | |
1130 | ||
1131 | if (env && level) { | |
1132 | cpu_exit(env); | |
1133 | } | |
1134 | } | |
1135 | ||
48a18b3c | 1136 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1137 | ISADevice **rtc_state, |
34d4260e | 1138 | ISADevice **floppy, |
1611977c | 1139 | bool no_vmport) |
ffe513da IY |
1140 | { |
1141 | int i; | |
1142 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1143 | DeviceState *hpet = NULL; |
1144 | int pit_isa_irq = 0; | |
1145 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1146 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1147 | qemu_irq *a20_line; |
64d7e9a4 | 1148 | ISADevice *i8042, *port92, *vmmouse, *pit; |
4556bd8b | 1149 | qemu_irq *cpu_exit_irq; |
ffe513da IY |
1150 | |
1151 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | |
1152 | ||
1153 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); | |
1154 | ||
ffe513da | 1155 | if (!no_hpet) { |
ce967e2f | 1156 | hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); |
822557eb | 1157 | |
dd703b99 | 1158 | if (hpet) { |
b881fbe9 JK |
1159 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1160 | sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]); | |
dd703b99 | 1161 | } |
ce967e2f JK |
1162 | pit_isa_irq = -1; |
1163 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1164 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1165 | } |
ffe513da | 1166 | } |
48a18b3c | 1167 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1168 | |
1169 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1170 | ||
ce967e2f JK |
1171 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
1172 | if (hpet) { | |
1173 | /* connect PIT to output control line of the HPET */ | |
1174 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); | |
1175 | } | |
302fe51b | 1176 | pcspk_init(isa_bus, pit); |
ffe513da IY |
1177 | |
1178 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
1179 | if (serial_hds[i]) { | |
48a18b3c | 1180 | serial_isa_init(isa_bus, i, serial_hds[i]); |
ffe513da IY |
1181 | } |
1182 | } | |
1183 | ||
1184 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
1185 | if (parallel_hds[i]) { | |
48a18b3c | 1186 | parallel_init(isa_bus, i, parallel_hds[i]); |
ffe513da IY |
1187 | } |
1188 | } | |
1189 | ||
4b78a802 | 1190 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1191 | i8042 = isa_create_simple(isa_bus, "i8042"); |
4b78a802 | 1192 | i8042_setup_a20_line(i8042, &a20_line[0]); |
1611977c | 1193 | if (!no_vmport) { |
48a18b3c HP |
1194 | vmport_init(isa_bus); |
1195 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1196 | } else { |
1197 | vmmouse = NULL; | |
1198 | } | |
86d86414 BS |
1199 | if (vmmouse) { |
1200 | qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042); | |
43f20196 | 1201 | qdev_init_nofail(&vmmouse->qdev); |
86d86414 | 1202 | } |
48a18b3c | 1203 | port92 = isa_create_simple(isa_bus, "port92"); |
4b78a802 | 1204 | port92_init(port92, &a20_line[1]); |
956a3e6b | 1205 | |
4556bd8b BS |
1206 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1207 | DMA_init(0, cpu_exit_irq); | |
ffe513da IY |
1208 | |
1209 | for(i = 0; i < MAX_FD; i++) { | |
1210 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1211 | } | |
48a18b3c | 1212 | *floppy = fdctrl_init_isa(isa_bus, fd); |
ffe513da IY |
1213 | } |
1214 | ||
845773ab | 1215 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1216 | { |
1217 | int max_bus; | |
1218 | int bus; | |
1219 | ||
1220 | max_bus = drive_get_max_bus(IF_SCSI); | |
1221 | for (bus = 0; bus <= max_bus; bus++) { | |
1222 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1223 | } | |
1224 | } |